A Turbo code decoding method, system, device and medium based on a memory-computing integrated device

Abstract

The application relates to a Turbo code decoding method, system, device and medium based on a memory-computing integrated device, which comprises the following steps: constructing an extended check matrix and a probability graph model of the Turbo code; configuring a node blocking state of a memory-computing integrated device array; obtaining initial log-likelihood ratios of each variable node as initial input; performing hard decision check on output corresponding to the initial input, outputting a decoding result if a termination condition is met, otherwise, using the memory-computing integrated device array to respectively complete variable node to check node transmission of confidence and calculation of a posteriori log-likelihood ratio of the variable node, and equivalent calculation of check node to variable node transmission of confidence; performing hard decision check on the a posteriori log-likelihood ratio of each variable node after each round of iteration until the iteration is stopped when the termination condition is met, and the decoding result is output. The application can be widely applied in the technical field of signal decoding.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of communication, relates to the field of signal decoding technology, and particularly relates to a Turbo code decoding method, system, device and medium based on a memory-compute integrator. BACKGROUND

[0002] In order to guarantee the transmission reliability of a digital communication system in a complex channel environment, an efficient channel coding scheme is an indispensable technical means. Among numerous coding technologies, Turbo code has become one of the most widely used and most successful technologies in the modern communication field due to its excellent error correction performance approaching the Shannon limit. Since its advent, Turbo code has been widely deployed in global mainstream communication standards, especially in third-generation (3G) and fourth-generation (4G LTE) mobile communication systems. Without the powerful error correction capability provided by Turbo code, high-speed data services and stable connections supported by mobile broadband networks would be difficult to achieve. Similarly, in satellite communication, deep space exploration and other applications with strict requirements for data integrity, Turbo code also plays a core role. Therefore, Turbo code is a basic technology for building a modern high-performance communication system, and its importance and indispensability have been recognized by the industry.

[0003] The core idea of Turbo code is to use two SISO decoders to exchange external information (soft values) through an interleaver for iterative decoding. Through each iteration, the estimated sequence is corrected, thereby continuously improving the decoding performance and ultimately approaching the Shannon limit. However, traditional Turbo decoding is usually implemented based on digital circuits, including FPGA, CMOS application-specific integrated circuits, etc. The decoding process involves a large number of discrete fixed-point number operations, and the energy efficiency of the communication baseband based on traditional digital circuits is severely limited by the power consumption cost of random memory access and the energy overhead of discrete fixed-point number operations in the digital domain. The existing digital circuit processing paradigm cannot fundamentally achieve energy efficiency breakthroughs. SUMMARY

[0004] To solve the above problems, the purpose of the present application is to provide a Turbo code decoding method, system, device and medium based on a memory-compute integrator, which fully utilizes a memory-compute integrator array, converts a probability graph model to a Turbo decoding process, and completes confidence iteration calculation with the memory-compute integrator array to break through the power consumption bottleneck of digital circuits.

[0005] To achieve the above purpose, the present application adopts the following technical solutions:

[0006] In a first aspect, the present application provides a Turbo code decoding method based on a memory-compute integrator, comprising:

[0007] creating an extended check matrix and a corresponding probability graph model according to the received Turbo code;

[0008] Obtain the initial log-likelihood ratio for each variable node, which serves as the initial confidence level for the transfer from the variable node to the validation node in the probabilistic graphical model.

[0009] The Turbo code decoding process is analyzed, and the in-memory computing array is divided into a first in-memory computing array and a second in-memory computing array based on the analysis results. The cross nodes of the first in-memory computing array and the second in-memory computing array are configured with resistive state according to the extended parity-check matrix.

[0010] The initial log-likelihood ratio is loaded into the first in-memory compute array, and the calculation result output by the first in-memory compute array is subjected to hard-decision verification. If the termination condition is met, the decoding result is output; otherwise, iterative calculation is initiated.

[0011] The first in-memory compute array is used to calculate the confidence level and the posterior log-likelihood ratio of the variable node to the verification node. After nonlinear processing of the confidence level from the variable node to the verification node, it is used as the column input of the second in-memory compute array.

[0012] The equivalent calculation of the confidence level is transferred from the verification node to the variable node using the second in-memory computing array. After nonlinear processing of the output of the second in-memory computing array, it is used as the row input of the first in-memory computing array.

[0013] Hard-decision verification is performed on the posterior log-likelihood ratio of each variable node after each iteration until the termination condition is met, at which point the iteration stops and the decoding result is output.

[0014] Secondly, the present invention provides a Turbo code decoding system based on an in-memory computing device, comprising:

[0015] The preprocessing unit is used to create an extended parity-check matrix and a corresponding probabilistic graphical model based on the received Turbo code.

[0016] An initialization unit is used to obtain the initial log-likelihood ratio of each variable node, which serves as the initial confidence level from the variable node to the verification node in the probabilistic graphical model.

[0017] The in-memory computing array configuration unit is used to analyze the Turbo code decoding process, divide the in-memory computing array into a first in-memory computing array and a second in-memory computing array according to the analysis results, and configure the cross nodes of the first in-memory computing array and the second in-memory computing array in a resistive state according to the extended parity check matrix.

[0018] The preliminary verification unit is used to load the initial log-likelihood ratio into the first in-memory compute array and perform hard-decision verification on the calculation results output by the first in-memory compute array. If the termination condition is met, the decoding result is output; otherwise, it proceeds to the first and second computation units for iterative calculation.

[0019] The first computing unit is used to calculate the confidence level and the posterior log-likelihood ratio of the variable node to the verification node using the first in-memory computing array, and to perform nonlinear processing on the confidence level of the variable node to the verification node before using it as the column input of the second in-memory computing array.

[0020] The second computing unit is used to perform the equivalent calculation of the confidence level from the verification node to the variable node using the second in-memory computing array, and to perform nonlinear processing on the output of the second in-memory computing array as the row input of the first in-memory computing array.

[0021] The iterative output unit is used to perform hard-decision verification on the posterior log-likelihood ratio of each variable node after each iteration until the termination condition is met, at which point the iteration stops and the decoding result is output.

[0022] Thirdly, the present invention provides a computer-readable storage medium for storing one or more programs, the one or more programs including instructions that, when executed by a computing device, cause the computing device to perform the Turbo code decoding method based on a memory-computing device.

[0023] Fourthly, the present invention provides a computing device, comprising: one or more processors and a memory, wherein the memory stores one or more programs and is configured to be executed by the one or more processors, the one or more programs including instructions for executing the Turbo code decoding method based on the in-memory computing device.

[0024] The present invention has the following advantages due to the adoption of the above technical solutions: The present invention transforms the decoding process into a confidence transfer process between variable nodes and verification nodes based on the probabilistic graphical model, and performs resistive state configuration on the cross nodes of the in-memory computing array according to the extended parity matrix and the probabilistic graphical model. It utilizes the unique in-memory computing characteristics of in-memory computing devices to store static variables in the calculation process, which can significantly reduce the energy consumption bottleneck of decoding operations in the digital domain, while improving decoding efficiency and increasing decoding throughput.

[0025] Therefore, this invention can be widely applied in the field of signal decoding technology. Attached Figure Description

[0026] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. In the drawings:

[0027] Figure 1 This is a flowchart of a Turbo code decoding method based on a memory computing device provided in this embodiment of the invention;

[0028] Figure 2 This is a schematic diagram of the Turbo code decoding circuit architecture based on a memory computing unit provided in this embodiment of the invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0030] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0031] In some embodiments of the present invention, a Turbo code decoding method based on an in-memory computing unit is provided, comprising: creating an extended parity-check matrix and a corresponding probabilistic graphical model based on the Turbo code; using the probabilistic graphical model to transform the Turbo code decoding process into a confidence transfer process between variable nodes and parity nodes; dividing the in-memory computing unit array into two parts, respectively used to calculate the confidence from variable nodes to parity nodes and the confidence from parity nodes to variable nodes, and configuring the resistance states of the cross nodes of the in-memory computing unit array; using the configured in-memory computing unit array to iteratively update the confidence between variable nodes and parity nodes, and verifying the output results through peripheral circuits until the decoding result is output. The present invention fully utilizes the in-memory computing unit array, loading the static variables in the probabilistic graphical model calculation process into the in-memory computing unit array to overcome the energy overhead caused by memory access during the iteration process, and transforming traditional discrete digital operations into operations on continuous physical variables such as current and voltage, avoiding the energy overhead caused by discrete fixed-point number operations in the digital domain, fundamentally improving energy efficiency.

[0032] Correspondingly, in other embodiments of the present invention, a Turbo code decoding system, device, and medium based on a memory computing device are provided.

[0033] Example 1

[0034] like Figure 1 As shown, this embodiment proposes a Turbo code decoding method based on a memory computing device, which includes the following steps:

[0035] S1. Create an extended parity-check matrix and the corresponding probabilistic graphical model based on the received Turbo code.

[0036] The Turbo code can be the received Turbo code sent by the sender that needs to be decoded. This Turbo code may include... Each code character It is an integer greater than 1.

[0037] The probabilistic graphical model can include multiple variable nodes, multiple check nodes, and multiple undirected edges. Undirected edges connect variable nodes and check nodes that are connected. Each variable node uniquely corresponds to a column vector in the extended check matrix, and each check node uniquely corresponds to a row vector in the extended check matrix. If the row order in the extended check matrix is ​​equal to... Column order equals If the element is 1, then the node number is equal to The variable node and node number are equal to The check nodes have a connection relationship. If the row order in the extended check matrix is ​​equal to... Column order equals If the element is 0, then the node number is equal to The variable node and node number are equal to The verification nodes do not have any connection relationship.

[0038] In practical implementation, this embodiment can establish algebraic constraints based on the two recursive systematic convolutional (RSC) components of the Turbo encoder. Let the input information sequence be... System bits and check bits The check bits are obtained from two generator polynomials. Taking the 8-state RSC component as an example, the corresponding generator polynomials are:

[0039] ;

[0040] in, and These are the feedback polynomial and feedforward polynomial set internally by the RSC encoder, respectively.

[0041] Specifically, in this embodiment, the generator polynomials (including feedback polynomials and feedforward polynomials, set internally by the RSC encoder) described above can be mapped onto the Galois domain GF(2) to binary coefficient vectors [1,0,1,1] and [1,1,0,1], based on the number of encoded information bits. Perform a circular shift (fill the first row with 0s to the length). The second line is padded with zeros to the length. The first row is obtained by circularly shifting one position to the right, and the third row is obtained by circularly shifting one position to the right again based on the second row. Circular shift matrix and For example, when Equals 8, generating polynomial At this time, an 8×8 cyclic shift matrix can be constructed:

[0042] ;

[0043] This embodiment can be used for the construction. and By performing horizontal concatenation, the component verification matrix is ​​obtained. .

[0044] Wherein, the component parity check matrix satisfies . Indicated by system bits and check bits The concatenated vector. The dot product symbol represents the dot product of two row vectors.

[0045] Subsequently, according to the interleaving rules, the interleaving effect of the second RSC component encoder is written as a permutation matrix. The corresponding check relation is right-multiplied. ,get:

[0046] ;

[0047] Similarly, satisfying Based on the above component parity-check matrices, the overall parity-check matrix of the Turbo code (code rate 1 / 3, unchanged), i.e., the initial parity-check matrix, is as follows:

[0048] ;

[0049] The initial check matrix size is ( (where is the number of bits of information encoded) and satisfies the check relationship.

[0050] Subsequently, this embodiment can create a corresponding initial probabilistic graphical model based on the initial parity check matrix, identify and eliminate short loop structures in the initial parity check matrix and the initial probabilistic graphical model, and obtain an extended parity check matrix and a probabilistic graphical model.

[0051] Optional. In this embodiment, after creating the initial parity-check matrix and the initial probabilistic graphical model, the approach of expanding the parity-check matrix is ​​used to systematically eliminate the 4-rings in the initial parity-check matrix and the initial probabilistic graphical model.

[0052] It should be noted that a 4-ring corresponds to a pattern in the check matrix: the elements at the four intersections of two rows (e.g., c_i and c_j) and two columns (e.g., v_p and v_q) are all 1. This indicates that two check equations simultaneously constrain the same pair of variable nodes. Therefore, these 4-rings are eliminated and replaced. First, all four 1s constituting the 4-ring are cleared to zero. Then, a new variable node v_pq is introduced into the initial probabilistic graphical model, and a new check equation (i.e., adding a row to the initial check matrix) is added to define it: v_pq ⊕ v_p ⊕ v_q = 0. The original check equations c_i and c_j are modified so that they are associated through the newly introduced v_pq node, instead of directly connecting v_p and v_q simultaneously. All 4-rings in the initial check matrix are traversed, and the above operation is repeated for all detected 4-rings. The initial check matrix and initial probabilistic graphical model after eliminating all 4-rings are determined as the extended check matrix and probabilistic graphical model, respectively.

[0053] It should be noted that this embodiment fundamentally eliminates the short-ring structure that is most detrimental to decoding performance by replacing each 4-ring in the initial parity-check matrix and the initial probabilistic graphical model with a larger 6-ring. Due to the structural characteristics of Turbo codes, the short rings in their initial parity-check matrix and initial probabilistic graphical model are mainly such 4-rings. Therefore, after this round of expansion optimization, no further processing is usually required. The final result is an expanded parity-check matrix without 4-rings, which is more suitable for high-performance iterative decoding.

[0054] Understandably, the number of variable nodes will increase in the extended parity-check matrix and probabilistic graphical model obtained after the extended optimization, compared to the initial parity-check matrix and probabilistic graphical model.

[0055] S2. Obtain the initial log-likelihood ratio for each variable node, which serves as the initial confidence level for the transfer from the variable node to the verification node in the probabilistic graphical model.

[0056] This embodiment uses Binary Phase Shift Keying (BPSK) as an example to describe the communication between the transmitter and decoder, as well as the decoding target of this embodiment. Specifically, the transmitter can transmit information bits of... The codeword is encoded into indivual Then based on BPSK modulation a symbol And send it to the decoding end. Due to noise interference during transmission, the decoding end will receive a symbol , represented as The decoding task at the decoding end is to... indivual Restore to Thus, based on each Get the original from the sender Each code character.

[0057] Specifically, when obtaining the initial log-likelihood ratio of each variable node in a probabilistic graphical model, there are two methods depending on the type of variable node: For initial variable nodes, the calculation method is as follows:

[0058]

[0059] in, For the first The initial log-likelihood ratio of each variable node. and For the first The set of sub-constellation symbols with bits 0 / 1. These are the symbols received by the decoding end. The symbols sent by the sending end. This represents noise power.

[0060] For the variable nodes introduced by the extension, since they are obtained by the decoder itself and there is no prior information about the channel, their initial log-likelihood ratio is considered to be 0.

[0061] S3. Analyze the Turbo code decoding process, and divide the in-memory computing array into a first in-memory computing array and a second in-memory computing array based on the analysis results. Configure the node resistance state of the two in-memory computing arrays according to the extended parity check matrix.

[0062] Among them, in-memory computing devices are integrated devices that have both storage and computing capabilities, such as resistive random access memory, phase-change memory, magnetic memory, and flash memory.

[0063] This embodiment is based on ( Taking Turbo codes as an example, the code length is... The number of information bits is Assuming the extended parity-check matrix The number of rows and columns is The number of undirected edges is This document introduces the configuration of in-memory compute arrays. Specifically, it includes the following steps:

[0064] S21. Analyze the decoding process of Turbo code, determine the confidence transfer process between variable nodes and verification nodes, and divide the in-memory computing array into the first in-memory computing array and the second in-memory computing array accordingly.

[0065] In this embodiment, based on the analysis of the Turbo code decoding process, it can be roughly divided into two parts: first, based on the confidence level from the check node to the variable node in the previous iteration, the confidence level from the variable node to the check node and the posterior log-likelihood ratio of the variable node are calculated; second, based on the confidence level from the variable node to the check node, the confidence level from the check node to the variable node in the current iteration is calculated.

[0066] like Figure 2 As shown, in order to use the in-memory compute array to calculate the confidence transfer process between variable nodes and verification nodes, this embodiment divides the entire in-memory compute array into two groups. The first in-memory compute array is used to calculate the confidence from variable nodes to verification nodes and the posterior log-likelihood ratio of variable nodes; the second in-memory compute array is used to calculate the confidence from verification nodes to variable nodes.

[0067] S22. Based on the extended verification matrix, combined with the confidence transfer process from variable nodes to verification nodes and the posterior log-likelihood ratio of variable nodes, the cross nodes of the first in-memory computing array are configured in a resistive state.

[0068] Specifically, it includes the following steps:

[0069] S221. Based on the Turbo code extended parity matrix, the first in-memory processor array is divided into regions to obtain the input part, the first iteration part, and the parity output part.

[0070] The first iteration (see) Figure 2 The gray portion in the upper middle of the in-memory compute array is a square array with a size of [missing information]. , This is equal to the number of 1s in the Turbo code extended parity-check matrix; in other words, it's the number of undirected edges in the probabilistic graphical model. (See the parity-check output part...) Figure 2 The yellow portion in the upper middle in-memory array is joined with the first iteration portion along the column dimension, and its size is... That is, the number of columns in the parity check output is equal to the number of columns in the Turbo code extended parity check matrix. Input section (see) Figure 2 The pink portion in the upper middle in-memory array is concatenated with the first iteration portion and the verification output portion along the row dimension, and its size is... That is, the number of rows in the input part is equal to the number of columns in the Turbo code extended parity-check matrix. That is, the number of variable nodes.

[0071] S222. Determine the confidence propagation process of the first iteration part and the verification output part, as well as the posterior log-likelihood ratio of the variable nodes.

[0072] In this embodiment, the rows of the first iteration are used as input and the columns are used as output. Each column is used to calculate the 1 / 2 times decay value of the confidence from the variable node to the verification node in an undirected edge. The calculation formula can be expressed as:

[0073]

[0074] in, For variable nodes To the verification node Confidence level; For verification nodes To variable node Confidence level; For all nodes with variables The set of connected verification nodes, i.e., variable nodes The verification relationship of all the verification equations corresponding to all these verification nodes, verification nodes In the set Except for the check node Other verification nodes besides; For variable nodes The initial log-likelihood ratio.

[0075] The output of the validation section takes rows as input and columns as output, with each column used to calculate the posterior log-likelihood ratio for a variable node. The calculation formula can be expressed as:

[0076]

[0077] in, For variable nodes The posterior log-likelihood ratio.

[0078] S223. Based on the confidence propagation process of the first iteration part and the verification output part, and the posterior log-likelihood ratio of the variable nodes, configure the cross-node resistance states of the first iteration part, the verification output part, and the input part respectively.

[0079] In the first in-memory compute array, each row of input to the first iteration section and the verification output section is: That is, the verification node To variable node The confidence level is reduced by half; each line of the input is... That is, variable nodes The initial log-likelihood ratio. Therefore, when configuring node resistive states:

[0080] For each column in the first iteration, the impedance configuration of its cross nodes is as follows: determine the target variable node number and target verification node number corresponding to the undirected edge of each column; determine the set of verification node numbers connected to the target variable node number based on the target variable node number and the extended verification matrix; determine the input row corresponding to the confidence level of the target variable node to other verification nodes in the verification node number set besides the target verification node based on the set of verification node numbers; set the cross node of each input row with the column to low impedance state 1, and set the cross node of the column with other rows to high impedance state;

[0081] For the input part corresponding to the first iteration part For each column in the column, the impedance configuration of its intersection nodes is as follows: Based on the target variable node number corresponding to the undirected edge, determine the input row corresponding to the input part, set the intersection node of this input row and the column to a 1 / 2 time-attenuated impedance state, and configure the other columns in the same state. All intersection nodes in row -1 are set to a high-impedance state. That is, for the first in-memory compute array... Columns, each column is configured with ( + ) cross nodes (including those in the first iteration) lines and input sections (row), configure all the first in-memory compute arrays in sequence, totaling Each column corresponds to one output. The order of the columns can be changed arbitrarily.

[0082] For each column of the verification output section, the impedance configuration of its cross nodes is as follows: determine the target variable node number corresponding to each column, determine the set of verification node numbers connected to the target variable node number based on the target variable node number and the extended verification matrix; determine the input row corresponding to the confidence level of the target variable node to other verification nodes in the verification node number set besides the target verification node based on the set of verification node numbers, and set the cross node of each input row with the column to a 2x gain impedance state;

[0083] For the input part corresponding to the verification output part For each column, the input row corresponding to the target variable node number is determined, and the intersection node of the input row and the column is set to low resistance state 1; the intersection nodes of other input rows in the same column are set to high resistance state. That is, for the later stages of the first in-memory computing array... Columns, each column is configured with ( + ) cross nodes (including the check output part) lines and input sections (Line); configure sequentially Each column corresponds to one output. .

[0084] For ease of understanding, this embodiment uses variable nodes as an example. To the verification node confidence level Taking the calculation as an example, the configuration of the node's resistive state is introduced. According to the extended parity-check matrix, it can be determined that the node number is... The set of check nodes connected to the variable node is Then we have:

[0085]

[0086] Before the first in-memory computing array When configuring cross nodes for columns, assume that the first column of the first in-memory compute array is used for computation. Then for the first iteration part Okay, based on the set of verification nodes It can be determined that, except for the check node In addition, with variable nodes Other connected verification nodes are ; and thus the variable nodes can be determined. Other verification nodes When passing confidence levels, the corresponding input rows are set to a low-resistance state of 1 at the intersection of each input row and the corresponding column. The first column is then set to a low-resistance state of 1 with the others. The intersection nodes of row -5 are set to high impedance; for the input part... The line will be associated with the variable node. The intersection node of the corresponding input row and the first column is set to 1 / 2 times the attenuation resistance state, and this column is set to other... All intersection nodes in row -1 are set to high-resistance state.

[0087] S23. Based on the confidence transfer process from the verification node to the variable node, perform resistive configuration on the cross nodes of the second in-memory computing array.

[0088] Specifically, in this embodiment, the second in-memory computing array only includes a second iteration part, which is used to calculate the confidence level from the verification node to the variable node.

[0089] Among them, the second in-memory computing array (see Figure 2 The size of the in-memory compute array in the lower middle section is Furthermore, the columns of the second in-memory computing array serve as inputs, and the rows serve as outputs. Each row is used to calculate the verification nodes in an undirected edge. To variable node The equivalent value of the confidence level can be calculated using the following formula:

[0090]

[0091] in, For verification nodes To variable node Confidence level; For all nodes with verification The set of connected variable nodes, For variable nodes To the verification node The confidence level.

[0092] In the second in-memory compute array, the input of each column in the second iteration section is... This corresponds to the output of each column in the first in-memory compute array. It is the output of each column. via the first function The calculation yields the following result. Therefore, when configuring the cross node resistance state:

[0093] For each row of the second in-memory compute array, the impedance configuration of its cross nodes is as follows: Determine the target verification node number and target variable node number corresponding to the undirected edge of each row; determine the set of variable node numbers connected to the target verification node number based on the target verification node number and the extended verification matrix; based on the set of variable node numbers, determine the input column corresponding to the confidence level transmitted from the target verification node to other variable nodes in the variable node number set (excluding the target variable node); set the cross nodes of each input column with the row to low impedance state 1, and set the cross nodes of the row with other columns to high impedance state; configure sequentially. Each line corresponds to one output. .

[0094] S4. Load the initial input into the first in-memory computing array, and use the peripheral circuit to perform hard decision verification on the calculation result output by the verification output part of the first in-memory computing array. If the termination condition is met, output the Turbo code decoding result; otherwise, proceed to step S5.

[0095] Specifically, the initial log-likelihood ratio of the variable nodes The last J rows of the first in-memory compute array, i.e. the input portion, are loaded as input and are always kept there. The initial input of the other rows is 0, and the calculation results are obtained from the verification output portion.

[0096] Hard-decision verification is implemented through the verification output module. The specific process is as follows: First, hard-decision is performed on the initial log-likelihood ratio of each variable node output by the verification output section of the first in-memory array. If the initial log-likelihood ratio of the variable node is <0, it is determined to be 1 (high level); if it is >0, it is determined to be 0 (low level), thus obtaining the codeword corresponding to each variable node. Then, for the code words Perform a check; if it satisfies... , For the modulo operation, stop the iteration and select the bits that were not extended during input. Output the result as the Turbo code decoding result; otherwise, perform the following steps.

[0097] S5. The first in-memory computing array is used to complete the confidence transfer from the variable node to the verification node and the calculation of the log-likelihood ratio of the variable node. The output of the first in-memory computing array is processed by the first nonlinear function implementation module and used as the column input of the second in-memory computing array.

[0098] In this embodiment, the first nonlinear function is: The nonlinear function is calculated based on the output of each column of the first iteration in the first in-memory compute array. And output it to the corresponding column of the second in-memory computing array.

[0099] The first nonlinear function can be implemented by a first nonlinear function implementation module circuit. This module circuit can be implemented using analog or digital circuits. If implemented using digital circuits, an ADC and a DAC module need to be inserted between the first and second in-memory computing arrays.

[0100] S6. The equivalent calculation of confidence transfer from the verification node to the variable node is completed using the second in-memory computing array, and the output of the second in-memory computing array is processed by the second nonlinear function implementation module and used as the row input of the first iteration part in the first in-memory computing array.

[0101] In this embodiment, the second nonlinear function is The nonlinear function is calculated based on the output of each row of the second in-memory compute array. It is then output to the corresponding row of the iteration section in the first in-memory compute array.

[0102] The second nonlinear function can be implemented by a second nonlinear function implementation module circuit. The first nonlinear function implementation module circuit can be implemented by analog circuits or digital circuits. If it is implemented by digital circuits, ADC and DAC modules need to be inserted between the first in-memory processor array and the second in-memory processor array.

[0103] S7. Repeat steps S5 to S6 for iterative calculation, and use the external circuit to perform hard decision verification on the posterior log-likelihood ratio of each variable node after each iteration until the maximum number of iterations is reached or the preset verification condition is met, and stop the iteration to obtain the final Turbo code decoding result.

[0104] Example 2

[0105] Embodiment 1 above provides a Turbo code decoding method based on an in-memory computing device. Correspondingly, this embodiment provides a Turbo code decoding system based on an in-memory computing device. The system provided in this embodiment can implement the Turbo code decoding method based on an in-memory computing device of Embodiment 1. The system can be implemented by software, hardware, or a combination of both. For example, the system may include integrated or separate functional modules or functional units to execute the corresponding steps in the methods of Embodiment 1. Since the system in this embodiment is basically similar to the method embodiment, the description process in this embodiment is relatively simple. For relevant details, please refer to the description of Embodiment 1. The system embodiment provided in this embodiment is merely illustrative.

[0106] The Turbo code decoding system based on an in-memory computing unit provided in this embodiment includes:

[0107] The preprocessing unit is used to create an extended parity-check matrix and a corresponding probabilistic graphical model based on the received Turbo code.

[0108] An initialization unit is used to obtain the initial log-likelihood ratio of each variable node, which serves as the initial confidence level from the variable node to the verification node in the probabilistic graphical model.

[0109] The in-memory computing array configuration unit is used to analyze the Turbo code decoding process, divide the in-memory computing array into a first in-memory computing array and a second in-memory computing array based on the analysis results, and perform resistive state configuration on the cross nodes of the first in-memory computing array and the second in-memory computing array.

[0110] The preliminary verification unit is used to load the initial log-likelihood ratio into the first in-memory compute array and perform hard-decision verification on the calculation results output by the first in-memory compute array. If the termination condition is met, the decoding result is output; otherwise, it proceeds to the first and second computation units for iterative calculation.

[0111] The first computing unit is used to calculate the confidence level and the posterior log-likelihood ratio of the variable node to the verification node using the first in-memory computing array, and to perform nonlinear processing on the confidence level of the variable node to the verification node before using it as the column input of the second in-memory computing array.

[0112] The second computing unit is used to perform the equivalent calculation of the confidence level from the verification node to the variable node using the second in-memory computing array, and to perform nonlinear processing on the output of the second in-memory computing array as the row input of the first in-memory computing array.

[0113] The iterative output unit is used to perform hard-decision verification on the posterior log-likelihood ratio of each variable node after each iteration until the termination condition is met, at which point the iteration stops and the decoding result is output.

[0114] Furthermore, the in-memory computing array configuration unit includes:

[0115] The functional partitioning unit is used to analyze the Turbo code decoding process, determine the confidence transfer process between variable nodes and check nodes and the posterior log-likelihood ratio of variable nodes, and divide the in-memory computing array into the first in-memory computing array and the second in-memory computing array accordingly.

[0116] The first node resistive configuration unit is used to perform resistive configuration on the cross nodes of the first in-memory computing array based on the confidence transfer process from the variable node to the verification node and the posterior log-likelihood ratio of the variable node.

[0117] The second node resistive configuration unit is used to perform resistive configuration on the cross nodes of the second in-memory computing array according to the confidence transfer process from the verification node to the variable node.

[0118] Furthermore, the first node resistive state configuration unit includes:

[0119] The first region partitioning unit is used to partition the first in-memory compute array into regions based on the Turbo code extended parity-check matrix, resulting in an input part, a first iteration part, and a parity-check output part; wherein, the first iteration part is a square matrix with a size of , This is equal to the number of 1s in the expanded parity-check matrix; the parity-check output is concatenated with the first iteration part along the column dimension, and its size is... The input part is concatenated with the first iteration part and the validation output part along the row dimension, and its size is [size missing]. ;

[0120] The first confidence propagation process determination unit is used to determine the confidence propagation process of the first iteration part and the verification output part, as well as the posterior log-likelihood ratio of the variable nodes, respectively.

[0121] The first configuration unit is used to configure the cross-node resistance states of the first iteration part, the verification output part, and the input part respectively, based on the confidence propagation process of the first iteration part and the verification output part and the posterior log-likelihood ratio of the variable nodes.

[0122] Furthermore, in the first configuration unit, based on the confidence propagation process of the first iteration part and the verification output part, and the posterior log-likelihood ratio of the variable nodes, the cross-node resistance states of the first iteration part, the verification output part, and the input part are configured respectively, including:

[0123] For each column in the first iteration, the impedance configuration of its cross nodes is as follows: determine the target variable node number and target verification node number corresponding to the undirected edge of each column; determine the set of verification node numbers connected to the target variable node number based on the target variable node number and the extended verification matrix; determine the input row corresponding to the confidence level of the target variable node to other verification nodes in the verification node number set besides the target verification node based on the set of verification node numbers; set the cross node of each input row with the column to low impedance state 1, and set the cross node of the column with other rows to high impedance state;

[0124] For the input part corresponding to the first iteration part The column's cross-node resistance configuration is as follows: Based on the target variable node number corresponding to the undirected edge, determine the input row corresponding to the input part, set the cross-node of this input row and the column to a 1 / 2 time-attenuated resistance state, and configure the column with other... All intersection nodes in row -1 are set to high-resistance state;

[0125] For each column of the verification output section, the impedance configuration of its cross nodes is as follows: determine the target variable node number corresponding to each column, determine the set of verification node numbers connected to the target variable node number based on the target variable node number and the extended verification matrix; determine the input row corresponding to the confidence level of the target variable node to other verification nodes in the verification node number set besides the target verification node based on the set of verification node numbers, and set the cross node of each input row with the column to a 2x gain impedance state;

[0126] For the input part corresponding to the verification output part For each column, the input row corresponding to the target variable node number is determined, and the intersection node of the input row and the column is set to low resistance state 1; the intersection nodes of other input rows in the column are all set to high resistance state.

[0127] Furthermore, the second node resistive state configuration unit includes:

[0128] The second partitioning unit is used to set the second in-memory compute array as the second iteration part, the size of which is... Furthermore, the columns of the second iteration are used as inputs, and the rows are used as outputs;

[0129] The second confidence propagation process determination unit is used to configure each row to calculate the equivalent value of the confidence propagation from the check node to the variable node in an undirected edge; the input of each column in the second iteration part is This corresponds to the output of each column in the first in-memory compute array. It is the output of each column. Calculated using the first nonlinear function;

[0130] The second configuration unit is used to perform resistive configuration on the cross nodes of the second iteration part according to the determined confidence level transmission process of each column.

[0131] Furthermore, in the second configuration unit, when configuring the cross-node resistance state for the second iteration part:

[0132] For each row of the second in-memory compute array, the impedance configuration of its cross nodes is as follows: Determine the target verification node number and target variable node number corresponding to the undirected edge of each row; determine the set of variable node numbers connected to the target verification node number based on the target verification node number and the extended verification matrix; based on the set of variable node numbers, determine the input column corresponding to the confidence level transmitted from the target verification node to other variable nodes in the variable node number set (excluding the target variable node); set the cross nodes of each input column with the row to low impedance state 1, and set the cross nodes of the row with other columns to high impedance state, and configure them sequentially. OK.

[0133] Example 3

[0134] This embodiment provides a processing device corresponding to the Turbo code decoding method based on in-memory computing provided in Embodiment 1. The processing device can be a client-side processing device, such as a mobile phone, laptop, tablet computer, desktop computer, etc., to execute the method of Embodiment 1.

[0135] The processing device includes a processor, a memory, a communication interface, and a bus. The processor, memory, and communication interface are connected via the bus to enable communication between them. The memory stores a computer program that can run on the processor. When the processor runs the computer program, it executes the Turbo code decoding method based on an in-memory computing device provided in Embodiment 1.

[0136] Preferably, the memory may be high-speed random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage device.

[0137] Preferably, the processor can be any type of general-purpose processor such as a central processing unit (CPU) or a digital signal processor (DSP), and there is no limitation herein.

[0138] Example 4

[0139] The Turbo code decoding method based on an in-memory computing device in Embodiment 1 can be specifically implemented as a computer program product. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing the Turbo code decoding method based on an in-memory computing device described in Embodiment 1 are loaded.

[0140] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any combination thereof.

[0141] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0142] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0143] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0144] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A Turbo code decoding method based on a memory computing device, characterized in that, include: An extended parity-check matrix and a corresponding probabilistic graphical model are created based on the received Turbo code. Obtain the initial log-likelihood ratio for each variable node, which serves as the initial confidence level for the transfer from the variable node to the validation node in the probabilistic graphical model. The Turbo code decoding process is analyzed, and the in-memory computing array is divided into a first in-memory computing array and a second in-memory computing array based on the analysis results. The cross nodes of the first in-memory computing array and the second in-memory computing array are configured with resistive state according to the extended parity-check matrix. The initial log-likelihood ratio is loaded into the first in-memory compute array, and the calculation result output by the first in-memory compute array is subjected to hard-decision verification. If the termination condition is met, the decoding result is output; otherwise, iterative calculation is initiated. The first in-memory compute array is used to calculate the confidence level and the posterior log-likelihood ratio of the variable node to the verification node. After nonlinear processing of the confidence level from the variable node to the verification node, it is used as the column input of the second in-memory compute array. The equivalent calculation of the confidence level is transferred from the verification node to the variable node using the second in-memory computing array. After nonlinear processing of the output of the second in-memory computing array, it is used as the row input of the first in-memory computing array. Hard-decision verification is performed on the posterior log-likelihood ratio of each variable node after each iteration until the termination condition is met, at which point the iteration stops and the decoding result is output.

2. The Turbo code decoding method based on a memory computing device as described in claim 1, characterized in that, The Turbo code decoding process is analyzed, and based on the analysis results, the in-memory computing array is divided into a first in-memory computing array and a second in-memory computing array. Then, based on the extended parity-check matrix, the cross-nodes of the first and second in-memory computing arrays are configured with resistive states, including: The Turbo code decoding process is analyzed to determine the confidence propagation process between variable nodes and check nodes, as well as the posterior log-likelihood ratio of variable nodes. Based on this, the in-memory computing array is divided into the first in-memory computing array and the second in-memory computing array. Based on the extended verification matrix, combined with the confidence transfer process from variable node to verification node and the posterior log-likelihood ratio of variable node, the cross nodes of the first in-memory computing array are configured in a resistive state. Based on the confidence transfer process from the verification node to the variable node, the cross nodes of the second in-memory computing array are configured in a resistive state.

3. The Turbo code decoding method based on a memory computing device as described in claim 2, characterized in that, The process of combining the confidence transfer from the variable node to the verification node and the posterior log-likelihood ratio of the variable node to configure the cross nodes of the first in-memory compute array in a resistive state includes: The first in-memory computing array is divided into regions based on the Turbo code extended parity matrix to obtain the input part, the first iteration part, and the parity output part. The first iteration part is a square matrix with a size of . × , This is equal to the number of 1s in the extended check matrix; the check output portion is concatenated with the first iteration portion along the column dimension, and its size is... × , To expand the number of columns in the verification matrix, the input portion is concatenated with the first iteration portion and the verification output portion from the row dimension, and its size is [size missing]. ×( + ); Determine the confidence propagation process for the first iteration part and the verification output part, as well as the posterior log-likelihood ratio of the variable nodes; Based on the confidence propagation process of the first iteration part and the verification output part, as well as the posterior log-likelihood ratio of the variable nodes, the cross-node resistance states of the first iteration part, the verification output part, and the input part are configured respectively.

4. The Turbo code decoding method based on a memory computing device as described in claim 3, characterized in that, The rows in the first iteration are used as input, and the columns are used as output. Each column is used to calculate the 1 / 2 times decay value of the confidence from the variable node to the check node in an undirected edge. The calculation formula is expressed as: in, For variable nodes To the verification node Confidence level; For verification nodes To variable node The confidence level of transmission; For all nodes with variables The set of connected check nodes, variable nodes The verification relationship of the verification equations corresponding to all verification nodes in the set; verification nodes. In the set Except for the check node Other verification nodes besides; For variable nodes The initial log-likelihood ratio; The rows in the validation output are used as input, and the columns are used as output. Each column is used to calculate the posterior log-likelihood ratio for a variable node. The calculation formula is as follows: in, For variable nodes The posterior log-likelihood ratio.

5. The Turbo code decoding method based on a memory computing device as described in claim 4, characterized in that, The configuration of the cross-node resistance states of the first iteration part, the verification output part, and the input part based on the confidence propagation process of the first iteration part and the verification output part, and the posterior log-likelihood ratio of the variable nodes, includes: For each column in the first iteration, the impedance configuration of its cross nodes is as follows: determine the target variable node number and target verification node number corresponding to the undirected edge of each column; determine the set of verification node numbers connected to the target variable node number based on the target variable node number and the extended verification matrix; determine the input row corresponding to the confidence level of the target variable node to other verification nodes in the verification node number set besides the target verification node based on the set of verification node numbers; set the cross node of each input row with the column to low impedance state 1, and set the cross node of the column with other rows to high impedance state; For each column in the first M columns of the input part corresponding to the first iteration part, the impedance state configuration of its cross nodes is as follows: Based on the target variable node number corresponding to the undirected edge, determine the input row corresponding to the input part, set the cross node of the input row and the column to a 1 / 2 times attenuated impedance state, and set the cross node of the column and the other J-1 rows to a high impedance state. For each column of the verification output section, the impedance configuration of its cross nodes is as follows: determine the target variable node number corresponding to each column, determine the set of verification node numbers connected to the target variable node number based on the target variable node number and the extended verification matrix; determine the input row corresponding to the confidence level of the target variable node to other verification nodes in the verification node number set besides the target verification node based on the set of verification node numbers, and set the cross node of each input row with the column to a 2x gain impedance state; For the last J columns of the input section corresponding to the verification output section, determine the input row corresponding to the input section according to the target variable node number corresponding to each column, and set the intersection node of the input row and the column to low resistance state 1; set the intersection nodes of other input rows in the column to high resistance state.

6. The Turbo code decoding method based on a memory computing device as described in claim 4, characterized in that, The step of configuring the cross nodes of the second in-memory compute array in a resistive state according to the confidence transfer process from the verification node to the variable node includes: The second in-memory computing array includes a second iteration section, the size of which is... × , To expand the number of 1s in the verification matrix, and using the columns of the second iteration as input and the rows as output, each row is used to calculate the equivalent value of the confidence transferred from the verification node to the variable node in an undirected edge. The calculation formula is expressed as: in, For verification nodes To variable node Confidence level; For all nodes with verification The set of connected variable nodes, For another variable node To the verification node Confidence level; The input for each column in the second iteration is This corresponds to the output of each column in the first in-memory compute array. It is the output of each column. Calculated using the first nonlinear function; When configuring the cross-node resistance state in the second iteration: For each row of the second in-memory computing array, the impedance configuration of its cross nodes is as follows: determine the target verification node number and target variable node number corresponding to the undirected edge of each row; determine the set of variable node numbers connected to the target verification node number based on the target verification node number and the extended verification matrix; determine the input column corresponding to the confidence level transmitted from the target verification node to other variable nodes in the variable node number set excluding the target variable node based on the set of variable node numbers; set the cross nodes of each input column with the row to low impedance state 1, and set the cross nodes of the row with other columns to high impedance state.

7. The Turbo code decoding method based on a memory computing device as described in claim 6, characterized in that, The nonlinear processing of the confidence level transmitted from the variable node to the verification node refers to using a nonlinear function. For the output of each column in the first iteration of the first in-memory compute array, the following calculations are performed: And output it to the corresponding column of the second in-memory compute array; The nonlinear processing of the output of the second in-memory computing array refers to using a nonlinear function. The output of each row of the second in-memory compute array is calculated to obtain... It is then output to the corresponding row of the iteration section in the first in-memory compute array.

8. A Turbo code decoding system based on a memory computing device, characterized in that, include: The preprocessing unit is used to create an extended parity-check matrix and a corresponding probabilistic graphical model based on the received Turbo code. An initialization unit is used to obtain the initial log-likelihood ratio of each variable node, which serves as the initial confidence level from the variable node to the verification node in the probabilistic graphical model. The in-memory computing array configuration unit is used to analyze the Turbo code decoding process, divide the in-memory computing array into a first in-memory computing array and a second in-memory computing array according to the analysis results, and configure the cross nodes of the first in-memory computing array and the second in-memory computing array in a resistive state according to the extended parity check matrix. The preliminary verification unit is used to load the initial log-likelihood ratio into the first in-memory compute array and perform hard-decision verification on the calculation results output by the first in-memory compute array. If the termination condition is met, the decoding result is output; otherwise, it proceeds to the first and second computation units for iterative calculation. The first computing unit is used to calculate the confidence level and the posterior log-likelihood ratio of the variable node to the verification node using the first in-memory computing array, and to perform nonlinear processing on the confidence level of the variable node to the verification node before using it as the column input of the second in-memory computing array. The second computing unit is used to perform the equivalent calculation of the confidence level from the verification node to the variable node using the second in-memory computing array, and to perform nonlinear processing on the output of the second in-memory computing array as the row input of the first in-memory computing array. The iterative output unit is used to perform hard-decision verification on the posterior log-likelihood ratio of each variable node after each iteration until the termination condition is met, at which point the iteration stops and the decoding result is output.

9. A computer-readable storage medium for storing one or more programs, characterized in that, The one or more programs include instructions that, when executed by a computing device, cause the computing device to perform any of the Turbo code decoding methods based on in-memory computing as described in claims 1 to 7.

10. A computing device, characterized in that, include: One or more processors and a memory, wherein the memory stores one or more programs and is configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the Turbo code decoding methods based on in-memory computing as described in claims 1 to 7.

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