Ethernet circuit structure with bypass switching function

Abstract

According to the Ethernet circuit structure with the bypass switching function, when the control module outputs the state keeping control signal, the bypass switching module keeps the original connection mode; when the control module outputs a main path connection control signal, the first network device and the switch are connected through the bypass switching module, the second network module and the switch are connected, and a main path connection mode is achieved. When the control module outputs a bypass connection control signal, a bypass connection mode of the first network device 1 and the second network device 2 is realized by means of the bypass switching module. The Bypass function of the Ethernet port is enabled and disabled by means of a simple circuit, the circuit structure is simple, and the design cost of the Bypass is reduced.

Description

Technical Field

[0001] This invention relates to the field of Ethernet communication technology, and in particular to a circuit structure for Ethernet with bypass switching function. Background Technology

[0002] Ethernet bypass functionality is designed for industrial applications, typically used in scenarios with high Ethernet reliability requirements. A simple example application scenario is... Figures 1-2 As shown, when two network devices, namely network device 1A and network device 2A, are connected to a switch 3A, they communicate with each other through the switch. However, in special circumstances, such as when switch 3A loses power, freezes, or restarts, it is necessary to ensure that the communication between the two network devices is not interrupted. In this case, the Bypass function is triggered, allowing the two network devices to physically communicate with each other. Of course, data will no longer be processed through the switch at this time. This is a temporary network interruption prevention function. When the switch returns to normal, the devices return to the previous working mode and communicate with each other again through the switch.

[0003] Bypasses are generally classified according to their control method or triggering method, and can be divided into the following types:

[0004] 1. Power-triggered. In this method, the Bypass function is typically enabled when the switch is not powered on, and immediately switched off once the switch is powered on.

[0005] 2. Controlled by GPIO. After entering the operating system (OS), specific ports can be operated through GPIO to control the bypass switch.

[0006] 3. Controlled by a watchdog timer. This is actually an extension of method 2. The watchdog timer can control the enabling and disabling of the GPIO Bypass program, thus controlling the Bypass state. Using this method, if the platform crashes, the watchdog timer can automatically restart the Bypass.

[0007] The typical application method is as follows: When the power is off, the device is in the bypass open state. After the device is powered on, since the BIOS (Basic Input / Output System) can operate on the bypass, the bypass remains open after the BIOS takes over the device. Then the OS boots up. Once the OS has booted, it typically executes the GPIO bypass program, disabling the bypass, allowing the application to function. In other words, the entire boot process almost never causes network disconnection. Network disconnection is only possible during the brief 2-3 seconds between device power-on and BIOS takeover.

[0008] This functionality typically requires a BIOS, configured via firmware. However, BIOS circuitry is usually complex and costly to design. Furthermore, a battery is often needed to save the boot configuration, which carries the risk of firmware loss. This feature is unsuitable for systems that cannot be configured with a BIOS architecture. Summary of the Invention

[0009] Based on the above, the present invention provides a circuit structure for Ethernet with bypass switching function, which uses a simple analog circuit to enable and disable the bypass function and maintain its state so that it will not be lost due to power failure.

[0010] A circuit structure for Ethernet with bypass switching function includes a bypass switching module and a control module. The bypass switching module includes a switching unit group, which includes a first switching unit and a second switching unit. The first switching unit and the second switching unit are connected through a bypass connection branch.

[0011] When the control signal output by the control module is a state holding control signal, the bypass switching module maintains the original connection mode according to the state holding signal;

[0012] When the control signal output by the control module is the main connection control signal, the first switching unit connects the first connection module corresponding to the first network device and the third connection module corresponding to the switch, and the second switching unit connects the second connection module corresponding to the second network device and the fourth connection module corresponding to the switch, thereby realizing the main connection mode of communication between the first network device and the second network device through the switch.

[0013] When the control signal output by the control module is a bypass connection control signal, the first switching unit connects the first connection module and the bypass connection branch, and the second switching unit connects the second connection module and the bypass connection branch, thereby realizing the bypass connection mode of the first network device and the second network device.

[0014] Furthermore, both the first switching unit and the second switching unit are single-coil magnetic latching relays. A single-coil magnetic latching relay includes a coil, a common terminal pin, a normally open terminal pin, and a normally closed terminal pin.

[0015] The control signal output by the control module consists of a set signal and a reset signal. The set pin of the coil is connected to the set signal, and the reset pin of the coil is connected to the reset signal.

[0016] The normally closed pin of the first switching unit is connected to the normally closed pin of the second switching unit.

[0017] The common terminal pin of the first switching unit is connected to the first connection module, and the normally open terminal pin of the first switching unit is connected to the third connection module.

[0018] The common terminal pin of the second switching unit is connected to the second connection module, and the normally open terminal pin of the second switching unit is connected to the fourth connection module.

[0019] When the reset signal and the set signal are at the same level, the control signal is the state holding control signal;

[0020] When the set signal is high and the reset signal is low, the control signal is the main circuit connection control signal. The normally open pin of the first switching unit is connected to the common pin, and the normally open pin of the second switching unit is connected to the common pin to realize the main circuit connection mode.

[0021] When the set signal is low and the reset signal is high, the control signal is the bypass connection control signal. The normally closed pin of the first switching unit is connected to the common pin, and the normally closed pin of the second switching unit is connected to the common pin to realize the bypass connection mode.

[0022] Furthermore, the control module includes: a main control chip, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor;

[0023] The first end of the third resistor is connected to the working voltage, and the second end of the third resistor is connected to the gate of the first transistor.

[0024] The source of the first transistor is connected to the operating voltage, and the drain of the first transistor is connected to the drain of the second transistor.

[0025] The gate of the second transistor and the gate of the first transistor are connected to the drain of the fifth transistor, and the source of the second transistor is grounded.

[0026] The first end of the fourth resistor is connected to the source of the first transistor, the second end of the fourth resistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the source of the second transistor.

[0027] The first end of the fifth resistor is also connected to the drain of the second transistor, and the drain of the second transistor serves as the set signal output terminal to output the set signal.

[0028] The first terminal of the sixth resistor is connected to the operating voltage, and the second terminal of the sixth resistor is connected to the gate of the third transistor.

[0029] The source of the third transistor is connected to the operating voltage, and the drain of the third transistor is connected to the drain of the fourth transistor.

[0030] The gate of the fourth transistor and the gate of the third transistor are connected to the reset control terminal of the main control chip, and the source of the fourth transistor is grounded.

[0031] The first end of the second resistor is connected to the source of the third transistor, the second end of the second resistor is connected to the first end of the eighth resistor, and the second end of the eighth resistor is connected to the source of the fourth transistor.

[0032] The first end of the eighth resistor is also connected to the drain of the fourth transistor, and the drain of the fourth transistor serves as the reset signal output terminal to output the reset signal.

[0033] The first end of the seventh resistor is connected to the working voltage, the second end of the seventh resistor is connected to the gate of the fifth transistor, and the source of the fifth transistor is connected to the set control terminal of the main control chip.

[0034] The main control chip's reset control terminal outputs a reset control signal, and the main control chip's set control terminal outputs a set control signal.

[0035] Furthermore, the control module also includes a fourth diode, a fifth diode, and a sixth diode;

[0036] The anodes of the fourth diode, the fifth diode, and the sixth diode are all connected to the gate of the fifth transistor;

[0037] The cathode of the fourth diode is connected to the watchdog signal;

[0038] The cathode of the fifth diode is connected to the switch system restart signal;

[0039] The cathode of the sixth diode is connected to the power-on signal of the switch.

[0040] Furthermore, the bypass switching module includes multiple switching unit groups, and the first connection module, the second connection module, the third connection module and the fourth connection module have multiple differential signal line pairs;

[0041] In each switching unit group, the first switching unit corresponds to a differential signal line pair connected to the first connection module and the third connection module, respectively, and the second switching unit corresponds to a differential signal line pair connected to the second connection module and the fourth connection module, respectively.

[0042] Differential signal lines consist of positive signal lines and negative signal lines.

[0043] Furthermore, the common terminal pins of a single-coil magnetic latching relay are divided into a positive common terminal pin and a negative common terminal pin;

[0044] Normally open pins are divided into positive normally open pins and negative normally open pins;

[0045] Normally closed pins are divided into positive normally closed pins and negative normally closed pins;

[0046] The normally closed positive terminal pin of the first switching unit is connected to the normally closed positive terminal pin of the second switching unit.

[0047] The normally closed negative terminal pin of the first switching unit is connected to the normally closed negative terminal pin of the second switching unit.

[0048] The positive common terminal pin of the first switching unit is connected to the positive signal line of the first connection module, and the positive normally open terminal pin of the first switching unit is connected to the positive signal line of the third connection module.

[0049] The negative common terminal pin of the first switching unit is connected to the negative signal line of the first connection module, and the negative normally open terminal pin of the first switching unit is connected to the negative signal line of the third connection module.

[0050] The positive common terminal pin of the second switching unit is connected to the positive signal line of the second connection module, and the positive normally open terminal pin of the second switching unit is connected to the positive signal line of the fourth connection module.

[0051] The negative common terminal pin of the second switching unit is connected to the negative signal line of the second connection module, and the negative normally open terminal pin of the second switching unit is connected to the negative signal line of the fourth connection module.

[0052] Furthermore, the control module also includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0053] The first capacitor is connected in series between the second end of the fourth resistor and the first end of the fifth resistor;

[0054] The second end of the fifth resistor is connected in series with the second capacitor and then grounded;

[0055] The third capacitor is connected in series between the second end of the second resistor and the first end of the eighth resistor.

[0056] The second end of the eighth resistor is connected in series with the fourth capacitor and then grounded.

[0057] Furthermore, the control module also includes a first fuse and a second fuse;

[0058] The source of the third transistor is connected in series with the first fuse and then connected to the operating voltage;

[0059] The source of the first transistor is connected in series with the second fuse and then connected to the operating voltage.

[0060] Furthermore, both the third and fourth connection modules include interconnected network port transformers and common mode inductors;

[0061] The network port transformer of the third connection module is also connected to the first switching unit, and the common mode inductor of the third connection module is connected to the first physical layer chip of the switch.

[0062] The network port transformer of the fourth connection module is also connected to the second switching unit, and the common mode inductor of the fourth connection module is connected to the second physical layer chip of the switch.

[0063] Furthermore, the main control chip is a GPIO expansion chip.

[0064] The beneficial technical effects of this invention are as follows: By using a simple analog circuit, the bypass function can be turned on and off, and the state can be maintained without being lost due to power failure. Because the circuit structure is simple, the bypass design cost is reduced. Attached Figure Description

[0065] Figure 1 This is a topology diagram of existing Ethernet communication via switches;

[0066] Figure 2 This is a topology diagram of existing Ethernet communication via bypass.

[0067] Figure 3 The schematic diagram of a single-coil holding relay used in the circuit structure of an Ethernet circuit with bypass switching function according to the present invention;

[0068] Figures 4-5 This is a schematic diagram of the control module in a circuit structure with Ethernet bypass switching function according to the present invention;

[0069] Figure 6 and Figure 15 These are schematic diagrams of the third and fourth connection modules in a circuit structure with Ethernet bypass switching function according to the present invention.

[0070] Figures 7-14 This is a schematic diagram of the first and second switching units in a switching unit group corresponding to multiple differential signal line pairs in the circuit structure of an Ethernet circuit with bypass switching function according to the present invention.

[0071] Figure 16 This is a schematic diagram of the first connection module in a circuit structure with Ethernet bypass switching function according to the present invention;

[0072] Figure 17This is a schematic diagram of the second connection module of the Ethernet circuit structure with bypass switching function according to the present invention;

[0073] Figure 18 This is a schematic diagram of the specific structure of the switching unit group in the circuit structure with Ethernet bypass switching function of the present invention;

[0074] Figure 19 This is a schematic diagram of the circuit structure of the present invention, which provides an Ethernet circuit with bypass switching function, in which two network devices are connected by bypass due to magnetic holding when the switch is not powered on.

[0075] Figure 20 This is a schematic diagram of the circuit structure of the present invention, which realizes the main connection mode of communication through the switch when the switch system is in the set state after initialization.

[0076] Figure 21 This is a schematic diagram of the main connection mode of the Ethernet circuit structure with bypass switching function of the present invention, which continues to communicate through the switch when the switch system is locked in the holding state.

[0077] Figure 22 This is a schematic diagram of the circuit structure of an Ethernet circuit with bypass switching function of the present invention, which switches from a reset state to a bypass connection mode due to reasons such as watchdog restart / switch restart / switch power failure. Detailed Implementation

[0078] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0079] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0080] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0081] Combination Figures 16-18 The present invention provides a circuit structure for Ethernet with bypass switching function, including a bypass switching module and a control module. The bypass switching module includes a switching unit group, which includes a first switching unit and a second switching unit. The first switching unit and the second switching unit are connected through a bypass connection branch.

[0082] When the control signal output by the control module is a state holding control signal, the bypass switching module maintains the original connection mode according to the state holding signal;

[0083] When the control signal output by the control module is the main connection control signal, the first switching unit connects the first connection module U20 corresponding to the first network device 1A and the third connection module corresponding to the switch 3A, and the second switching unit connects the second connection module U21 corresponding to the second network device 2A and the fourth connection module corresponding to the switch 3A, so as to realize the main connection mode of communication between the first network device 1A and the second network device 2A through the switch 3A.

[0084] When the control signal output by the control module is a bypass connection control signal, the first switching unit connects the first connection module U20 and the bypass connection branch, and the second switching unit connects the second connection module U21 and the bypass connection branch, thereby realizing the bypass connection mode of the first network device 1A and the second network device 2A.

[0085] The bypass function can be turned on and off using a simple analog circuit, and the state is maintained so that it will not be lost due to power failure. Because of the simple circuit structure, the bypass design cost is reduced.

[0086] Furthermore, both the first switching unit and the second switching unit are single-coil magnetic latching relays. A single-coil latching relay includes a coil, a common terminal pin, a normally open terminal pin, and a normally closed terminal pin.

[0087] The control signal output by the control module consists of a set signal and a reset signal. The set pin of the coil is connected to the set signal, and the reset pin of the coil is connected to the reset signal.

[0088] The normally closed pin of the first switching unit is connected to the normally closed pin of the second switching unit.

[0089] The common terminal pin of the first switching unit is connected to the first connection module, and the normally open terminal pin of the first switching unit is connected to the third connection module.

[0090] The common terminal pin of the second switching unit is connected to the second connection module, and the normally open terminal pin of the second switching unit is connected to the fourth connection module.

[0091] When the reset signal and the set signal are at the same level, the control signal is the state holding control signal;

[0092] When the set signal is high and the reset signal is low, the control signal is the main circuit connection control signal. The normally open pin of the first switching unit is connected to the common pin, and the normally open pin of the second switching unit is connected to the common pin to realize the main circuit connection mode.

[0093] When the set signal is low and the reset signal is high, the control signal is the bypass connection control signal. The normally closed pin of the first switching unit is connected to the common pin, and the normally closed pin of the second switching unit is connected to the common pin to realize the bypass connection mode.

[0094] See Figure 3 The core component mainly used in the circuit of this invention is a single-coil magnetic latching relay. As the core component of the first and second switching units, the single-coil magnetic latching relay includes two sets of pins and a coil. Pins 5, 6, and 7 form the first set, and pins 2, 3, and 4 form the second set. Pin 2 corresponds to pin 7 as a normally closed terminal, pin 3 corresponds to pin 6 as a common terminal, and pin 4 corresponds to pin 5 as a normally open terminal. The two pins 1 and 8 corresponding to the coil are the set and reset terminals, respectively. The direction indication of the single-coil magnetic latching relay typically refers to the polarity of the coil.

[0095] Default state: Pin 6 and pin 7 are directly connected, and pin 2 and pin 3 are directly connected.

[0096] In the powered-on state:

[0097] Taking the first group as an example, if the set pin 1 and the reset pin 8 are in the same direction, the magnetic state remains the same as the previous connection state. For example, if pin 6 and pin 7 were directly connected in the previous state, then this state will be maintained. If pin 1 and pin 8 are in opposite directions, for example, pin 8 is positive and pin 1 is negative, then the switch state is reset, and pin 6 and pin 7 are directly connected. Then, if pin 8 is negative and pin 1 is positive, then the switch state is set, and pin 6 is directly connected to pin 5 and disconnected from pin 7. The pin situation for the second group is similar to that of the first group, and will not be described in detail here.

[0098] like Figure 4 and Figure 5 As shown, the control module further includes: a main control chip U1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8.

[0099] The first end of the third resistor R3 is connected to the working voltage V1, and the second end of the third resistor R3 is connected to the gate G of the first transistor Q1.

[0100] The source S of the first transistor Q1 is connected to the operating voltage V1, and the drain D of the first transistor Q1 is connected to the drain D of the second transistor Q2.

[0101] The gate G of the second transistor Q2 and the gate G of the first transistor Q1 are connected to the drain D of the fifth transistor Q5, and the source S of the second transistor Q2 is grounded.

[0102] The first end of the fourth resistor R4 is connected to the source S of the first transistor Q1, the second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the source S of the second transistor Q2.

[0103] The first end of the fifth resistor R5 is also connected to the drain D of the second transistor Q2. The drain D of the second transistor Q2 serves as the set signal output terminal, outputting the set signal SET_P.

[0104] The first terminal of the sixth resistor R6 is connected to the working voltage V1, and the second terminal of the sixth resistor R6 is connected to the gate G of the third transistor Q3.

[0105] The source S of the third transistor Q3 is connected to the operating voltage V1, and the drain D of the third transistor Q3 is connected to the drain D of the fourth transistor Q4.

[0106] The gate G of the fourth transistor Q4 and the gate G of the third transistor Q3 are connected to the reset control terminal of the main control chip U1, and the source S of the fourth transistor Q4 is grounded.

[0107] The first end of the second resistor R2 is connected to the source S of the third transistor Q3, the second end of the second resistor R2 is connected to the first end of the eighth resistor R8, and the second end of the eighth resistor R8 is connected to the source S of the fourth transistor Q4.

[0108] The first end of the eighth resistor R8 is also connected to the drain D of the fourth transistor Q4. The drain D of the fourth transistor Q4 serves as the reset signal output terminal, outputting the reset signal RSET_P.

[0109] The first end of the seventh resistor R7 is connected to the working voltage V1, the second end of the seventh resistor R7 is connected to the gate G of the fifth transistor Q5, and the source S of the fifth transistor Q5 is connected to the set control terminal of the main control chip U1.

[0110] The reset control terminal of the main control chip U1 outputs the reset control signal BYRSET_CTL, and the set control terminal of the main control chip U1 outputs the set control signal SET_CTL.

[0111] Furthermore, the main control chip U1 is a GPIO expansion chip that communicates via the I2C interface to expand the GPIO ports, and AD0~2 are the I2C address bits.

[0112] VDD is the positive power supply, providing power to the chip's internal logic, and is connected to the operating voltage V1. VSS is the ground. The first terminal of the fifth capacitor C5 is connected to the VDD pin, and the second terminal of the fifth capacitor C5 is grounded.

[0113] SDA is the I2C data line (data signal LED_I2C_SDA), used to transmit data and instructions between the master device and the GPIO chip. SCL is the I2C clock line (clock signal LED_I2C_CLK). It is generated by the master device (MCU) and used to synchronize data communication on the SDA line. AD0~AD2 are I2C address selection pins. The AD2 pin is grounded, and the AD0-AD1 pins are connected to the operating voltage V1 and are connected in series with the ninth resistor R9. INT is the interrupt output pin. When the state of a GPIO input port changes, this pin can generate an interrupt signal to notify the master controller. P0~P7 are extended general-purpose GPIO pins.

[0114] Furthermore, the control module also includes a fourth diode D4, a fifth diode D5, and a sixth diode D6;

[0115] The anodes of the fourth diode D4, the fifth diode D5, and the sixth diode D6 are all connected to the gate of the fifth transistor Q5.

[0116] The cathode of the fourth diode D4 is connected to the watchdog signal BY_WDT;

[0117] The cathode of the fifth diode D5 is connected to the switch system restart signal BY_REBOOT;

[0118] The cathode of the sixth diode D6 is connected to the power-on signal BY_PG of the switch.

[0119] Specifically, the first transistor Q1 and the third transistor Q3 are P-channel enhancement-mode MOSFETs, which require a voltage lower than their source to drive. The second transistor Q2, the fourth transistor Q4, and the fifth transistor Q5 are N-channel enhancement-mode MOSFETs, which require a voltage higher than their source to drive.

[0120] The high and low levels of SET_P are associated with SET_CTL, the fifth transistor Q5, the watchdog signal BY_WDT, the system restart signal BY_REBOOT, and the power-on signal BY_PG.

[0121] When the watchdog signal BY_WDT, the system restart signal BY_REBOOT, and the power-on signal BY_PG are all at a high level (H), diodes D4, D5, and D6 are not conducting.

[0122] When diodes D4, D5, and D6 are not conducting, the set control signal SET_CTL is high (H), and the reset control signal BYRSET_CTL is high (H). Q5 is not conducting, causing SET_CTL_C to be high. Q1 is not conducting, and Q2 is conducting, therefore SET_P is low (L). When BYRSET_CTL is high (H), Q3 is not conducting, and Q4 is conducting, therefore RSET_P is low (L).

[0123] When diodes D4, D5, and D6 are not conducting, SET_CTL is low (L), and BYRSET_CTL is high (H), then Q3 is not conducting, Q4 is conducting, and RSET_P becomes low (L). When SET_CTL is low, Q5 conducts, SET_CTL_C is low (L), Q1 conducts, and Q2 is not conducting; therefore, SET_P is high (H), forming a set signal.

[0124] When diodes D4, D5, and D6 are not conducting, SET_CTL is low (L), BYRSET_CTL is low (L), SET_CTL is low (L), SET_P is high (H), BYRSET_CTL is low (L), Q3 is conducting, Q4 is not conducting, and RSET_P is high (H).

[0125] When any of the watchdog signal BY_WDT, system restart signal BY_REBOOT, or power-on signal BY_PG is low (L), one of diodes D4, D5, or D6 conducts, SET_CTL is low (L), Q5 is not conducting, SET_CTL_C is pulled up to high (L), Q1 is not conducting, Q2 is conducting, and SET_P is low (L). When BYRSET_CTL is low (L), Q3 conducts, Q4 is not conducting, and RSET_P is high (H).

[0126] The truth table for the control module is shown below.

[0127]

[0128] BY_REBOOT is triggered by a soft reboot of the system, causing this signal to go low. The watchdog signal BY_WDT goes low during a watchdog reboot, and the power-on signal BY_PG goes low when the switch is powered off. BY_REBOOT is output by U1.

[0129] Furthermore, the bypass switching module includes multiple switching unit groups, and the first connection module, the second connection module, the third connection module and the fourth connection module have multiple differential signal line pairs;

[0130] In each switching unit group, the first switching unit corresponds to a differential signal line pair corresponding to the first connection module and the third connection module respectively, and the second switching unit corresponds to a differential signal line pair corresponding to the second connection module and the fourth connection module respectively;

[0131] Differential signal lines consist of positive signal lines and negative signal lines.

[0132] like Figure 16 As shown, U20 is the first connection module, as... Figure 17 U21 is the second connection module. The first connection module is physically connected to the first network device, and the second connection module is physically connected to the second network device. U20 and U21 are external M12 interfaces. U20 has four differential signal pairs: M12_P4X0+ and M12_P4X0-, M12_P4X1+ and M12_P4X1-, M12_P4X2+ and M12_P4X2-, and M12_P4X3+ and M12_P4X3-. U21 has four differential signal pairs: M12_P3X0+ and M12_P3X0-, M12_P3X1+ and M12_P3X1-, M12_P3X2+ and M12_P3X2-, and M12_P3X3+ and M12_P3X3-.

[0133] Furthermore, the common terminal pins of a single-coil magnetic latching relay are divided into a positive common terminal pin and a negative common terminal pin;

[0134] Normally open pins are divided into positive normally open pins and negative normally open pins;

[0135] Normally closed pins are divided into positive normally closed pins and negative normally closed pins;

[0136] The normally closed positive terminal pin of the first switching unit is connected to the normally closed positive terminal pin of the second switching unit.

[0137] The normally closed negative terminal pin of the first switching unit is connected to the normally closed negative terminal pin of the second switching unit.

[0138] The positive common terminal pin of the first switching unit is connected to the positive signal line of the first connection module, and the positive normally open terminal pin of the first switching unit is connected to the positive signal line of the third connection module.

[0139] The negative common terminal pin of the first switching unit is connected to the negative signal line of the first connection module, and the negative normally open terminal pin of the first switching unit is connected to the negative signal line of the third connection module.

[0140] The positive common terminal pin of the second switching unit is connected to the positive signal line of the second connection module, and the positive normally open terminal pin of the second switching unit is connected to the positive signal line of the fourth connection module.

[0141] The negative common terminal pin of the second switching unit is connected to the negative signal line of the second connection module, and the negative normally open terminal pin of the second switching unit is connected to the negative signal line of the fourth connection module.

[0142] like Figures 7-14 As shown, U7 and U11, U8 and U12, U9 and U13, U10 and U14 constitute the first, second, third and fourth switching unit groups, respectively.

[0143] The set pin 1 of the coils of all the first and second switching units is connected to the SET_P signal, and the reset pin 8 is connected to the RSET_P signal.

[0144] U10 and U14 are the first and second switching units of the first switching unit group, respectively. U10 is used to connect the differential signal lines M12_P4X0+ and M12_P4X0-. U14 is used to connect the differential signal lines M12_P3X0+ and M12_P3X0-.

[0145] U9 and U13 are the first and second switching units of the second switching unit group, respectively. U9 is used to connect the differential signal lines M12_P4X1+ and M12_P4X1-. U13 is used to connect the differential signal lines M12_P3X1+ and M12_P3X1-.

[0146] U8 and U12 are the first and second switching units of the second switching unit group, respectively. U8 is used to connect the differential signal lines M12_P4X2+ and M12_P4X2-. U12 is used to connect the differential signal lines M12_P3X2+ and M12_P3X2-.

[0147] U7 and U11 are the first and second switching units of the second switching unit group, respectively. U7 is used to connect the differential signal lines M12_P4X3+ and M12_P4X3-. U11 is used to connect the differential signal lines M12_P3X3+ and M12_P3X3-. Figure 18 As shown.

[0148] In U7 and U11, U8 and U12, U9 and U13, U10 and U14, BY_P3+, BY_P3-, BY_P2+, BY_P2-, BY_P1+, BY_P1-, BY_P0+, and BY_P0- represent the signal lines of normally closed pins.

[0149] Furthermore, the control module also includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4;

[0150] The first capacitor C1 is connected in series between the second end of the fourth resistor R4 and the first end of the fifth resistor R5.

[0151] The second terminal of the fifth resistor R5 is connected in series with the second capacitor C2 and then grounded;

[0152] The third capacitor C3 is connected in series between the second end of the second resistor R2 and the first end of the eighth resistor R8.

[0153] The second end of the eighth resistor R8 is connected in series with the fourth capacitor C4 and then grounded.

[0154] The purpose of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 is to perform filtering.

[0155] Furthermore, the control module also includes a first fuse RF1 and a second fuse RF2;

[0156] The source of the third transistor Q3 is connected in series with the first fuse RF1 and then connected to the operating voltage V1.

[0157] The source of the first transistor Q1 is connected in series with the second fuse RF2 and then connected to the operating voltage V1.

[0158] Both the first fuse RF1 and the second fuse RF2 are self-resetting fuses with current-limiting design to prevent excessive impact.

[0159] Furthermore, it also includes a first diode D1, the anode of the first diode D1 is connected to a voltage of V1, and the cathode of the first diode D1 is connected to the first terminal of the first fuse RF1, the first terminal of the second fuse RF2, the first terminal of the seventh resistor R7, the first terminal of the sixth resistor R6, and the first terminal of the third resistor R3.

[0160] The second terminal of the first fuse RF1 is connected to the source S of the third transistor Q3, and the second terminal of the second fuse RF2 is connected to the source S of the first diode Q1.

[0161] Specifically, it also includes a second diode D2, a third diode D3, and a first resistor R1. The anode of the second diode D2 is connected to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to a voltage of V1. The cathode of the second diode D2 is connected to the cathode of the first diode D1, the first terminal of the first fuse RF1, the first terminal of the second fuse RF2, the first terminal of the seventh resistor R7, the first terminal of the sixth resistor R6, and the first terminal of the third resistor R3.

[0162] Specifically, the resistance values ​​of the third resistor R3, the sixth resistor R6, and the seventh resistor R7 are much greater than the resistance values ​​of the second resistor R2, the fourth resistor R4, the fifth resistor R5, and the eighth resistor R8. For example, the resistance values ​​of the third resistor R3, the sixth resistor R6, and the seventh resistor R7 are chosen to be 10K ohms, while the resistance values ​​of the second resistor R2, the fourth resistor R4, the fifth resistor R5, and the eighth resistor R8 are chosen to be 1 ohm.

[0163] Specifically, the control module also includes an electrolytic capacitor SC1. The first terminal (positive end) of the electrolytic capacitor SC1 is connected to the anode of the second diode D2, and the second terminal (negative end) of the electrolytic capacitor SC1 is grounded.

[0164] Furthermore, both the third and fourth connection modules include interconnected network port transformers and common mode inductors;

[0165] The network port transformer of the third connection module is also connected to the first switching unit, and the common mode inductor of the third connection module is connected to the first physical layer chip of the switch 3A.

[0166] The network port transformer of the fourth connection module is also connected to the second switching unit, and the common mode inductor of the fourth connection module is connected to the second physical layer chip of the switch 3A.

[0167] See Figure 6 and Figure 15 The system includes a third connection module with a first network port transformer U2 and a fourth connection module with a second network port transformer U15, used for network port signal isolation. The third connection module also includes common-mode inductors: a first common-mode inductor U3, a second common-mode inductor U4, a third common-mode inductor U5, and a fourth common-mode inductor U6. The fourth connection module also includes a fifth common-mode inductor U16, a sixth common-mode inductor U17, a seventh common-mode inductor U18, and an eighth common-mode inductor U19. The common-mode inductors of the third connection module are connected to the first physical layer chip (PHY chip). The first common-mode inductor U3 is connected to the P4_TRX3- and P4_TRX3+ terminals of the first physical layer chip. The second common-mode inductor U4 is connected to the P4_TRX2- and P4_TRX2+ terminals of the first physical layer chip. The third common-mode inductor U5 is connected to the P4_TRX1- and P4_TRX1+ terminals of the first physical layer chip. The fourth common-mode inductor U6 is connected to the P4_TRX0- and P4_TRX0+ terminals of the first physical layer chip. It passes through the first network transformer U2, which includes multiple transformer units. The first transformer unit is connected to U3, the second to U4, the third to U5, and the fourth to U6. P4X3+ and P4X3- of the first transformer unit are connected to U7, P4X2+ and P4X2- of the second transformer unit are connected to U8, P4X1+ and P4X1- of the third transformer unit are connected to U9, and P4X0+ and P4X0- of the fourth transformer unit are connected to U10.

[0168] The common-mode inductor of the fourth connection module is connected to the second physical layer chip (PHY chip). The fifth common-mode inductor U16 is connected to the P3_TRX3- and P3_TRX3+ terminals of the second physical layer chip. The sixth common-mode inductor U17 is connected to the P3_TRX2- and P3_TRX2+ terminals of the second physical layer chip. The seventh common-mode inductor U18 is connected to the P3_TRX1- and P3_TRX1+ terminals of the second physical layer chip. The eighth common-mode inductor U19 is connected to the P3_TRX0- and P3_TRX0+ terminals of the second physical layer chip. The second network transformer U15 includes multiple transformer units; the first transformer unit is connected to U16, the second to U17, the third to U18, and the fourth to U19. P3X3+ and P3X3- of the first transformer unit are connected to U11, P3X2+ and P3X2- of the second transformer unit are connected to U12, P3X1+ and P3X1- of the third transformer unit are connected to U13, and P3X0+ and P3X0- of the fourth transformer unit are connected to U14.

[0169] For each common-mode inductor, Zener diodes are provided between the differential signal pairs connected to the physical layer chip and between the differential signal pairs connected to the corresponding transformer unit. For example, Zener diodes DZ1 and DZ5 are provided between the differential signal pairs connected to U3; Zener diodes DZ2 and DZ56 are provided between the differential signal pairs connected to U4; Zener diodes DZ3 and DZ7 are provided between the differential signal pairs connected to U5; Zener diodes DZ4 and DZ8 are provided between the differential signal pairs connected to U6; Zener diodes DZ9 and DZ13 are provided between the differential signal pairs connected to U16; Zener diodes DZ10 and DZ14 are provided between the differential signal pairs connected to U17; Zener diodes DZ11 and DZ15 are provided between the differential signal pairs connected to U18; and Zener diodes DZ12 and DZ16 are provided between the differential signal pairs connected to U19.

[0170] As a specific application scenario of the present invention, such as Figure 19-22 As shown. In Figure 19 In the current state, the switch is not yet powered on, and both SET_P and RSET_P are low (L). At this time, the first network device 1A and the second network device 2A are in a direct bypass connection mode and do not communicate with the switch 3A. Figure 20 After the system completes initialization, SET_P and RSET_P are set to high and low levels respectively, activating the relays. This connects the third connection module of the first network device 1A and the switch 3A, and the fourth connection module of the second network device 2A and the switch 3A. The third and fourth connection modules of switch 3A are also connected, achieving the main connection mode, meaning the two network devices communicate through switch 3A. Figure 21In this state, both SET_P and RSET_P are high (H), indicating a hold state and maintaining the main connection mode. Figure 22 In the middle, after the watchdog restarts, the system restarts, or the device is powered off, the control SET_P and RSET_P are at low level (L) and high level (H) respectively, the relay is reset, and the bypass connection mode is used.

[0171] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit structure for Ethernet with bypass switching function, characterized in that, It includes a bypass switching module and a control module. The bypass switching module includes a switching unit group, which includes a first switching unit and a second switching unit. The first switching unit and the second switching unit are connected through a bypass connection branch. When the control signal output by the control module is a state holding control signal, the bypass switching module maintains the original connection mode according to the state holding signal. When the control signal output by the control module is the main path connection control signal, the first switching unit connects the first connection module corresponding to the first network device and the third connection module corresponding to the switch, and the second switching unit connects the second connection module corresponding to the second network device and the fourth connection module corresponding to the switch, thereby realizing the main path connection mode through which the first network device and the second network device communicate via the switch. When the control signal output by the control module is a bypass connection control signal, the first switching unit connects the first connection module and the bypass connection branch, and the second switching unit connects the second connection module and the bypass connection branch, thereby realizing the bypass connection mode of the first network device and the second network device.

2. The circuit structure with Ethernet bypass switching function as described in claim 1, characterized in that, Both the first switching unit and the second switching unit are single-coil magnetic latching relays, and the single-coil magnetic latching relay includes a coil, a common terminal pin, a normally open terminal pin, and a normally closed terminal pin; The control signal output by the control module consists of a set signal and a reset signal. The set pin of the coil is connected to the set signal, and the reset pin of the coil is connected to the reset signal. The normally closed pin of the first switching unit is connected to the normally closed pin of the second switching unit; The common terminal pin of the first switching unit is connected to the first connection module, and the normally open terminal pin of the first switching unit is connected to the third connection module. The common terminal pin of the second switching unit is connected to the second connection module, and the normally open terminal pin of the second switching unit is connected to the fourth connection module; When the reset signal and the set signal are at the same level, the control signal is the state holding control signal; When the set signal is high and the reset signal is low, the control signal is the main circuit connection control signal. The normally open pin of the first switching unit and the common pin are connected, and the normally open pin of the second switching unit and the common pin are connected to realize the main circuit connection mode. When the set signal is low and the reset signal is high, the control signal is a bypass connection control signal. The normally closed pin and the common pin of the first switching unit are connected, and the normally closed pin and the common pin of the second switching unit are connected to realize the bypass connection mode.

3. The circuit structure with Ethernet bypass switching function as described in claim 2, characterized in that, The control module includes: a main control chip, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; The first terminal of the third resistor is connected to the operating voltage, and the second terminal of the third resistor is connected to the gate of the first transistor. The source of the first transistor is connected to the operating voltage, and the drain of the first transistor is connected to the drain of the second transistor; The gate of the second transistor and the gate of the first transistor are connected to the drain of the fifth transistor, and the source of the second transistor is grounded; The first end of the fourth resistor is connected to the source of the first transistor, the second end of the fourth resistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the source of the second transistor. The first end of the fifth resistor is also connected to the drain of the second transistor, and the drain of the second transistor serves as the set signal output terminal to output the set signal. The first end of the sixth resistor is connected to the operating voltage, and the second end of the sixth resistor is connected to the gate of the third transistor; The source of the third transistor is connected to the operating voltage, and the drain of the third transistor is connected to the drain of the fourth transistor. The gate of the fourth transistor and the gate of the third transistor are connected to the reset control terminal of the main control chip, and the source of the fourth transistor is grounded. The first end of the second resistor is connected to the source of the third transistor, the second end of the second resistor is connected to the first end of the eighth resistor, and the second end of the eighth resistor is connected to the source of the fourth transistor. The first end of the eighth resistor is also connected to the drain of the fourth transistor, and the drain of the fourth transistor serves as the reset signal output terminal to output the reset signal. The first end of the seventh resistor is connected to the operating voltage, the second end of the seventh resistor is connected to the gate of the fifth transistor, and the source of the fifth transistor is connected to the set control terminal of the main control chip. The main control chip's reset control terminal outputs a reset control signal, and the main control chip's set control terminal outputs a set control signal.

4. The circuit structure with Ethernet bypass switching function as described in claim 3, characterized in that, The control module also includes a fourth diode, a fifth diode, and a sixth diode; The anodes of the fourth diode, the fifth diode, and the sixth diode are all connected to the gate of the fifth transistor; The cathode of the fourth diode is connected to the watchdog signal; The cathode of the fifth diode is connected to the switch system restart signal; The cathode of the sixth diode is connected to the power-on signal of the switch.

5. The circuit structure with Ethernet bypass switching function as described in claim 2, characterized in that, The bypass switching module includes multiple switching unit groups, and the first connection module, the second connection module, the third connection module and the fourth connection module have multiple differential signal line pairs; In each of the switching unit groups, the first switching unit is respectively connected to a differential signal line pair of the first connection module and the third connection module, and the second switching unit is respectively connected to a differential signal line pair of the second connection module and the fourth connection module; The differential signal line consists of a positive signal line and a negative signal line.

6. The circuit structure with Ethernet bypass switching function as described in claim 5, characterized in that, The common terminal pins of the single-coil magnetic latching relay are divided into positive common terminal pins and negative common terminal pins; Normally open pins are divided into positive normally open pins and negative normally open pins; Normally closed pins are divided into positive normally closed pins and negative normally closed pins; The normally closed positive terminal pin of the first switching unit is connected to the normally closed positive terminal pin of the second switching unit; The normally closed negative terminal pin of the first switching unit is connected to the normally closed negative terminal pin of the second switching unit; The positive common terminal pin of the first switching unit is connected to the positive signal line of the first connection module, and the positive normally open terminal pin of the first switching unit is connected to the positive signal line of the third connection module. The negative common terminal pin of the first switching unit is connected to the negative signal line of the first connection module, and the negative normally open terminal pin of the first switching unit is connected to the negative signal line of the third connection module. The positive common terminal pin of the second switching unit is connected to the positive signal line of the second connection module, and the positive normally open terminal pin of the second switching unit is connected to the positive signal line of the fourth connection module. The negative common terminal pin of the second switching unit is connected to the negative signal line of the second connection module, and the negative normally open terminal pin of the second switching unit is connected to the negative signal line of the fourth connection module.

7. The circuit structure with Ethernet bypass switching function as described in claim 3, characterized in that, The control module also includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The first capacitor is connected in series between the second end of the fourth resistor and the first end of the fifth resistor; The second end of the fifth resistor is connected in series with the second capacitor and then grounded. The third capacitor is connected in series between the second end of the second resistor and the first end of the eighth resistor; The second end of the eighth resistor is connected in series with the fourth capacitor and then grounded.

8. The circuit structure with Ethernet bypass switching function as described in claim 3, characterized in that, The control module also includes a first fuse and a second fuse; The source of the third transistor is connected in series with the first fuse and then connected to the operating voltage; The source of the first transistor is connected in series with the second fuse and then connected to the operating voltage.

9. The circuit structure with Ethernet bypass switching function as described in claim 1, characterized in that, Both the third connection module and the fourth connection module include interconnected network port transformers and common mode inductors; The network port transformer of the third connection module is also connected to the first switching unit, and the common mode inductor of the third connection module is connected to the first physical layer chip of the switch. The network port transformer of the fourth connection module is also connected to the second switching unit, and the common mode inductor of the fourth connection module is connected to the second physical layer chip of the switch.

10. The circuit structure with Ethernet bypass switching function as described in claim 3, characterized in that, The main control chip is a GPIO expansion chip.

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