Modulation decoder supporting multiple modulation systems

Abstract

The invention provides a modulation decoder supporting multiple modulation systems. An input buffer module receives and caches input soft bit data; the control state machine module generates a data request signal and controls the reading time sequence of the soft bit data; the branch metric calculation module selects a corresponding multiplication matrix according to a preset modulation mode and performs operation with the soft bit data to obtain a branch metric value; the addition, comparison and selection module is used for generating survivor paths and current path metrics; the path metric calculation module obtains the maximum path metric and the corresponding state index; the surviving path storage module stores surviving paths; the backtracking module generates a decoded bitstream. The decoder supports multiple modulation systems such as binary phase shift keying modulation, binary phase shift keying-pulse position modulation and mapping modulation, the processing bandwidth is larger than or equal to the input data bandwidth by configuring the depth of the input buffer module and the sliding window technology, new data can be continuously received in the backtracking process, and the decoding efficiency is improved. And the decoding efficiency and the system adaptability are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication signal processing, and in particular to a modulation decoder supporting multiple modulation modes. BACKGROUND

[0002] With the rapid development of communication technology, modulation and demodulation technology plays a vital role in digital communication systems. As an implementation of the optimal sequence detection algorithm, the Viterbi decoder is widely used in satellite communication, mobile communication, deep space communication and other fields, for correcting the error codes generated in the channel transmission process and improving the reliability of the communication system.

[0003] However, the existing Viterbi decoder is usually designed for a single modulation mode only, and cannot process signals modulated by multiple modulation modes such as binary phase shift keying modulation (BPSK), binary phase shift keying-pulse position modulation (BPSK-BPM) and mapping modulation at the same time. This results in the need to configure multiple different decoders in a communication system that needs to process multiple modulation modes, increasing the system complexity and reducing the adaptability and flexibility of the system. SUMMARY

[0004] The present application provides a modulation decoder supporting multiple modulation modes to solve the defect that multiple different decoders must be configured in a communication system that needs to process multiple modulation modes in the prior art, increasing the system complexity and reducing the adaptability and flexibility of the system.

[0005] In one aspect, the present application provides a modulation decoder supporting multiple modulation modes, comprising:

[0006] An input buffer module for receiving and buffering the input soft bit data;

[0007] A control state machine module for generating a data request signal and controlling the reading timing of the soft bit data in the non-empty state of the data of the input buffer module;

[0008] A branch metric calculation module for selecting a corresponding multiplication matrix according to a preset modulation mode and performing operation on the soft bit data and the multiplication matrix to obtain a branch metric value;

[0009] An add-compare-select module for generating a survivor path and a current path metric of the survivor path through an add-compare-select process based on the branch metric value;

[0010] a path metric calculation module, configured to compare the current path metrics to obtain a maximum path metric and a state index corresponding to the maximum path metric;

[0011] a surviving path storage module, configured to store the surviving paths;

[0012] a backtracking module, configured to extract surviving path bits from the surviving path storage module according to the maximum path metric and the state index, and generate a decoded bit stream.

[0013] According to the modulation decoder supporting multiple modulation modes provided by the application, the input buffer module is a deep configurable FIFO memory, and the input buffer module continues to receive and buffer new soft bit data when the backtracking module works.

[0014] According to the modulation decoder supporting multiple modulation modes provided by the application, the input buffer module has a depth of N, is configured to buffer M groups of accumulated soft bit data in the backtracking process, and is configured to process N groups of soft bit data through a sliding window technology.

[0015] The sliding window technology matches the FIFO depth at the entrance of the decoding module with the external input data rate, and ensures that the decoding module completes the processing of N groups of input soft bit data in each sliding window time.

[0016] According to the modulation decoder supporting multiple modulation modes provided by the application, the input buffer module is further configured to output a valid signal if the data request signal is received, and output an invalid signal if the data request signal is not received.

[0017] The control state machine module is further configured to control the branch metric calculation module, the add-compare-select module and the path metric calculation module to work if the valid signal is received, and control the branch metric calculation module, the add-compare-select module and the path metric calculation module to stop working and maintain the data state before stopping working if the invalid signal is received.

[0018] According to the modulation decoder supporting multiple modulation modes provided by the application, the branch metric calculation module is further configured to:

[0019] generate corresponding code words according to different modulation modes;

[0020] convert the code words into multiplication matrices corresponding to respective modulation modes.

[0021] According to the modulation decoder supporting multiple modulation modes provided by the application, the modulation mode is a binary phase shift keying modulation mode.

[0022] The branch metric calculation module is further configured to:

[0023] obtaining a 2-bit code word of convolutional encoding output;

[0024] converting the code word bit value into a pulse polarity to obtain a multiplication matrix of the binary phase shift keying modulation mode;

[0025] wherein 1 in the 2-bit code word is converted into -1, and 0 is converted into 1; and the multiplication matrix of the BPSK modulation mode is [1, 1; 1, -1; -1, 1; -1, -1].

[0026] According to the application, a modulation decoder supporting multiple modulation modes is provided, and the modulation mode is a binary phase shift keying-pulse position modulation mode.

[0027] The branch metric calculation module is further configured to:

[0028] obtaining a 2-bit code word of convolutional encoding output; wherein a high-bit in the 2-bit code word represents pulse position information, and a low-bit represents binary phase shift keying information;

[0029] generating a pulse position vector according to the high-bit; wherein when the high-bit is 0, a vector [1, 0] representing that a pulse exists in a first time period is generated, and when the high-bit is 1, a vector [0, 1] representing that a pulse exists in a second time period is generated;

[0030] generating a polarity multiplier according to the low-bit; wherein when the low-bit is 0, a multiplier 1 representing a positive pulse is generated, and when the low-bit is 1, a multiplier -1 representing a negative pulse is generated;

[0031] performing scalar multiplication operation on the pulse position vector and the polarity multiplier to obtain a multiplication matrix of the binary phase shift keying-pulse position modulation mode;

[0032] The multiplication matrix of the binary phase shift keying-pulse position modulation mode is [1, 0; -1, 0; 0, 1; 0, -1].

[0033] According to the application, a modulation decoder supporting multiple modulation modes is provided, and the modulation mode is a mapping modulation mode.

[0034] The branch metric calculation module is further configured to:

[0035] obtaining a 2-bit code word of convolutional encoding output;

[0036] converting the 2-bit code word into a final bit according to a preset mapping table;

[0037] Map the final bit to a symbol vector, and obtain a multiplication matrix of the mapping modulation mode; wherein 0 in the final bit is mapped to a symbol vector of 1, and 1 in the final bit is mapped to a symbol vector of -1; the multiplication matrix of the mapping modulation mode is [1, 1; -1, -1; -1, 1; 1, -1].

[0038] According to the application, the input buffer module is further used to realize a processing bandwidth greater than or equal to an input data bandwidth by configuring a depth and a processing capacity of a sliding window.

[0039] According to the application, the control state machine module comprises:

[0040] A decoding flow control unit is used to manage initialization, iterative processing, state updating and error detection.

[0041] A decoding interrupt control unit is used to suspend decoding and reserve states of each module when input data is invalid, and continue decoding when input data is valid.

[0042] A backtracking triggering unit is used to trigger a backtracking operation when a path metric buffer is full or decoding is completed.

[0043] The application provides a modulation decoder supporting multiple modulation modes, which receives and buffers input soft bit data through the input buffer module; generates a data request signal and controls a reading timing of the soft bit data under a non-empty state of the input buffer module through the control state machine module, selects a corresponding multiplication matrix according to a preset modulation mode through the branch metric calculation module, and obtains a branch metric value by operating the soft bit data and the multiplication matrix; generates a survivor path and a current path metric of the survivor path through an adding, comparing and selecting process based on the branch metric value through the selection module, compares the current path metric through the path metric calculation module to obtain a maximum path metric and a state index corresponding to the maximum path metric, stores the survivor path through the survivor path storage module, and extracts a survivor path bit from the survivor path storage module according to the maximum path metric and the state index through the backtracking module to generate a decoded bit stream, so that signals modulated by multiple modulation modes such as BPSK-BPM, BPSK and mapping modulation can be decoded under the same hardware module, the adaptability and flexibility of the system are improved, real-time decoding can be realized even if the input decoded data is discontinuous, the timeliness of decoding is ensured, and the robustness of the system is improved. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0045] Figure 1 is a structural schematic diagram of a modulation decoder supporting multiple modulation modes provided by an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the objects, technical solutions and advantages of the present application clearer, the following will clearly and completely describe the technical solutions in the present application with reference to the drawings in the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0047] Viterbi decoding is a common error correction technique based on dynamic programming algorithm, which plays an important role in communication systems. Its main function is to convert the received signal into original bit information, especially in digital communication systems, Viterbi decoder is usually used to correct or solve the error problem caused in the channel. Specifically, Viterbi decoder finds the most likely transmission path by comparing the similarity of the received signal sequence with the known signal sequence, thereby correcting the error. Its working principle mainly includes the following steps:

[0048] (1) Establish a state diagram: according to the characteristics of the coding scheme, a directed acyclic state diagram is established, in which each node represents a state and each edge represents the transition from one state to another state.

[0049] (2) Calculate the maximum probability of reaching each state: starting from the initial state, the probability of reaching each state is calculated step by step according to the input sequence of the code. For each state, the maximum probability of reaching the state can be calculated by considering the probability of all states at the previous time and the transition probability.

[0050] (3) Backtracking path: after finding the path with the maximum probability, Viterbi decoder will backtrack this path, thereby obtaining the most likely original signal sequence.

[0051] Viterbi decoder has the following advantages:

[0052] First, superior performance: Viterbi decoding is a maximum likelihood sequence estimation algorithm that can achieve a low bit error rate in noisy and interference-prone channels, thereby improving the reliability and performance of the system.

[0053] Second, it is applicable to various channel conditions: the Viterbi decoding algorithm has a strong adaptability to changes in channel conditions and can be applied to different types of channels.

[0054] Third, it can be used in combination with other technologies: Viterbi decoding can be used in combination with other error correction coding techniques, modulation techniques, etc., to further improve the performance of communication systems.

[0055] Currently, with technological advancements, the use of Viterbi in conjunction with other modulation techniques requires not only integration with BPSK modulation but also, with further technological developments, with BPSK-BPM and mapping modulation (hereinafter referred to as mapping modulation). To reduce decoder resource consumption, the receiver's Viterbi decoder needs the ability to simultaneously process signals processed by multiple modulation methods, including the aforementioned convolutionally encoded BPSK-BPM, BPSK, and mapping modulation, and must achieve real-time decoding even when the input decoding data is discontinuous. However, existing Viterbi decoders cannot meet these technical requirements and suffer from drawbacks such as high storage resource requirements and significant decoding delays. Therefore, this invention proposes a modulation decoder supporting multiple modulation schemes. This decoder can decode signals modulated by multiple modulation methods, such as BPSK-BPM, BPSK, and mapping modulation, within the same hardware module. Even when the input decoding data is discontinuous, this novel decoder can achieve real-time decoding.

[0056] Specifically, Figure 1 This is a schematic diagram of the structure of a modulation decoder that supports multiple modulation systems, provided in an embodiment of the present invention.

[0057] like Figure 1 As shown, the modulation decoder supporting multiple modulation standards provided in this embodiment of the invention may include an input buffer module and a control state machine module. Figure 1 (denoted as PM), branch metric calculation module (which has multiple, Figure 1 Taking 64 as an example, denoted as BMU0 to BMU63), plus a selection module (which has multiple modules), Figure 1 Taking 64 as an example, denoted as ACS0 to ACS63), the path metric calculation module ( Figure 1 (referred to as PM), Survival path storage module ( Figure 1 (referred to as PMBuffer) and backtracking module ( Figure 1 (Note: This is referred to as Traceback).

[0058] In one specific implementation, the input buffer module is configured to receive and buffer the input soft bits. The input buffer module is a deep configurable FIFO memory, and continues to receive and buffer new soft bits while the traceback module is working. The depth of the input buffer module is N, which is configured to buffer the accumulated M groups of soft bits during the traceback process, and process N groups of soft bits by using the sliding window technique. The sliding window technique is configured to match the FIFO depth at the decoder input with the external input data rate, to ensure that the decoder completes the processing of N groups of soft bits within each sliding window time. The input buffer module is further configured to output a valid signal if a data request signal is received, and output an invalid signal if no data request signal is received. The input buffer module is further configured to achieve a processing bandwidth greater than or equal to the input data bandwidth by configuring the depth and the processing capability of the sliding window.

[0059] The control state machine module is configured to generate a data request signal and control the read timing of the soft bits when the input buffer module is not empty. The control state machine module is further configured to control the branch metric calculation module, the add-compare-select module, and the path metric calculation module to work if a valid signal is received, and to control the branch metric calculation module, the add-compare-select module, and the path metric calculation module to stop working and maintain the data state before stopping if an invalid signal is received. The control state machine module includes a decoding flow control unit, a decoding interrupt control unit, and a traceback trigger unit. The decoding flow control unit is configured to manage initialization, iterative processing, state update, and error detection. The decoding interrupt control unit is configured to pause decoding when the input data is invalid and to preserve the state of each module, and to continue decoding when the input data is valid. The traceback trigger unit is configured to trigger a traceback operation when the path metric buffer is full or decoding is complete.

[0060] The branch metric calculation module is configured to select a corresponding multiplication matrix according to a preset modulation mode, and to perform an operation on the soft bits and the multiplication matrix to obtain a branch metric value. The branch metric calculation module is further configured to generate a corresponding code word according to different modulation modes, and to convert the code word into a multiplication matrix corresponding to the respective modulation mode.

[0061] When the modulation mode is a binary phase shift keying modulation mode, the branch metric calculation module is further configured to obtain a 2-bit code word output by convolutional encoding, to convert the bit values of the code word into pulse polarity, and to obtain a multiplication matrix of the binary phase shift keying modulation mode. In this case, 1 in the 2-bit code word is converted into -1, and 0 is converted into 1. For the possible combinations of the code word, there are "00", "01", "10", and "11", and the multiplication matrix of the BPSK modulation mode is [1, 1; 1, -1; -1, 1; -1, -1].

[0062] When the modulation mode is a binary phase shift keying-pulse position modulation mode, the branch metric calculation module is further configured to obtain a 2-bit code word output by the convolutional encoding, wherein a high-bit in the 2-bit code word represents information of a pulse position, and a low-bit represents information of a binary phase shift keying; generate a pulse position vector according to the high-bit, wherein when the high-bit is 1, a vector [1, 0] representing that a pulse exists in a first time period is generated, and when the high-bit is 0, a vector [0, 1] representing that a pulse exists in a second time period is generated; generate a polarity multiplier according to the low-bit, wherein when the low-bit is 0, the multiplier 1 representing a positive pulse is generated, and when the low-bit is 1, the multiplier -1 representing a negative pulse is generated; and perform scalar multiplication operation on the pulse position vector and the polarity multiplier to obtain a multiplication matrix of the binary phase shift keying-pulse position modulation mode. For the possible combinations of the code word, the multiplication matrix of the binary phase shift keying-pulse position modulation mode is [1, 0; -1, 0; 0, 1; 0, -1].

[0063] When the modulation mode is a mapping modulation mode, the branch metric calculation module is further configured to obtain a 2-bit code word output by the convolutional encoding; convert the 2-bit code word into a final bit according to a preset mapping table; map the final bit into a symbol vector to obtain a multiplication matrix of the mapping modulation mode. Wherein 0 in the final bit is mapped into a symbol vector of 1, and 1 in the final bit is mapped into a symbol vector of -1.

[0064] In a specific implementation process, the preset mapping table can be as shown in Table 1:

[0065] Table 1

[0066] Original bit (high) Original bit (low) Final bit (high) Final bit (low) 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1

[0067] In this way, the original-final-matrix is as follows: [0, 0]-[0, 0]-[1, 1]; [0, 1]-[1, 1]-[-1, -1]; [1, 0]-[1, 0]-[-1, 1]; [1, 1]-[0, 1]-[1, -1]. The multiplication matrix of the overall mapping modulation mode is [1, 1; -1, -1; -1, 1; 1, -1].

[0068] The add-compare-select module is configured to generate a survivor path and a current path metric of the survivor path through an add-compare-select process based on the branch metric values. The working process of the add-compare-select module includes: first, for each possible state transition, adding the path metric of the previous state to the corresponding branch metric value to obtain a new path metric candidate value; then, for each target state, comparing all path metric candidate values that can reach the state to select the maximum value as the new path metric of the state; finally, recording the previous state corresponding to the selected path as part of the survivor path.

[0069] The path metric calculation module is used to compare the current path metrics, obtain the maximum path metric and the state index corresponding to the maximum path metric. The path metric calculation module finds the maximum value and the state index corresponding to the maximum value by comparing the path metric values of all states. The maximum path metric value represents the most likely decoding path, and the corresponding state index indicates the starting point of backtracking.

[0070] The surviving path storage module is used to store the surviving paths. The surviving path storage module uses a matrix structure to store the surviving path information of each decoding depth, and the number of rows of the matrix is equal to the number of states and the number of columns is equal to the backtracking depth. After each add-compare-select operation, the new surviving path bits are written to the current column of the storage matrix, and the column pointer is updated.

[0071] The backtracking module is used to extract the surviving path bits from the surviving path storage module according to the maximum path metric and the state index, and generate the decoding bit stream. The backtracking module starts from the state corresponding to the maximum path metric, traces the entire decoding path in reverse according to the stored surviving path information, and extracts the corresponding decoding bits. The backtracking process starts from the latest surviving path information and traces back step by step until the predetermined backtracking depth is reached, and finally generates a complete decoding bit stream.

[0072] In this embodiment, the working process of the modulation decoder is as follows:

[0073] First, the input buffer module receives and buffers the soft bit data from the communication channel. These soft bit data are usually signals processed by the demodulator, which contain noise and interference information introduced during the channel transmission process.

[0074] When there is data in the input buffer module, the control state machine module detects the non-empty state of the data, generates a data request signal, and starts to control the reading timing of the soft bit data. The control state machine ensures that the data is read and processed in the correct timing to maintain the continuity and correctness of the decoding process.

[0075] The branch metric calculation module selects the corresponding multiplication matrix according to the preset modulation mode (such as BPSK, BPSK-PPM or mapping modulation mode). Then, the read soft bit data is operated with the selected multiplication matrix to calculate the branch metric value. The branch metric value represents the similarity between the received signal and the possible transmitted signal, and is the basis for subsequent Viterbi decoding.

[0076] The add-compare-select module receives the branch metric value and performs the core operation of the Viterbi algorithm. It generates the surviving path and the current path metric through the addition (adding the path metric of the previous state and the branch metric), comparison (comparing the metric values of different paths reaching the same state) and selection (selecting the path with the maximum metric value) processes.

[0077] The path metric calculation module compares the path metrics of all current states and finds the maximum path metric and its corresponding state index. The state corresponding to the maximum path metric is the most likely encoding state and will be used as the starting point for backtracking.

[0078] The surviving path storage module continuously stores the surviving path information generated by each add-compare-select operation. This information records the optimal predecessor state of each state at each time, forming the data structure required for backtracking.

[0079] When sufficient surviving path information has been accumulated, the backtracking module begins to work. It starts from the state with the maximum path metric and traces the entire decoding path in reverse direction according to the stored surviving path information, extracts the corresponding decoding bits, and finally generates a complete decoding bit stream.

[0080] During the entire decoding process, the input buffer module continuously receives and buffers new soft bit data, and does not stop even when the backtracking module is working. This design ensures that the decoder can continuously process the input data stream, improving the system's throughput.

[0081] Through the sliding window technique, the decoder can complete the processing of N groups of soft bit data within each sliding window time. By configuring the depth and processing capacity of the input buffer module, it is ensured that the processing bandwidth is greater than or equal to the input data bandwidth, avoiding data overflow or processing delay.

[0082] When the input data is temporarily invalid, the control state machine module will suspend the decoding process and preserve the current state of each module. Once the input data resumes to be valid, the decoding process will continue from the suspended point, ensuring the continuity and correctness of the decoding.

[0083] The modulation decoder supporting multiple modulation modes of the embodiment receives and buffers the input soft bit data through the input buffer module; the control state machine module generates a data request signal in the non-empty state of the data of the input buffer module, controls the reading timing of the soft bit data, the branch metric calculation module selects the corresponding multiplication matrix according to the preset modulation mode, and obtains the branch metric value by operating the soft bit data and the multiplication matrix; then, the comparison module generates the survivor path and the current path metric of the survivor path through the addition, comparison and selection process based on the branch metric value, the path metric calculation module compares the current path metric to obtain the maximum path metric and the state index corresponding to the maximum path metric, the survivor path storage module stores the survivor path, and the backtracking module extracts the survivor path bit from the survivor path storage module according to the maximum path metric and the state index to generate a decoded bit stream, so that the signals modulated by multiple modulation modes such as BPSK-BPM, BPSK and mapping modulation can be decoded under the same hardware module, the adaptability and flexibility of the system are improved, real-time decoding can be realized even if the input decoding data is discontinuous, the timeliness of decoding is ensured, and the robustness of the system is improved.

[0084] In a specific implementation process, the embodiment provides a specific implementation mode of a modulation decoder supporting multiple modulation modes, and particularly relates to the detailed process of branch metric calculation under different modulation modes.

[0085] When the modulation mode is a binary phase shift keying modulation mode, the working process of the branch metric calculation module is as follows:

[0086] Firstly, the branch metric calculation module obtains 2-bit code words output by the convolutional encoder. These code words are the direct output of the convolutional encoding process, and each code word contains 2 bits.

[0087] Then, the branch metric calculation module converts each bit value in the code word into a corresponding pulse polarity. Specifically, 1 in the code word is converted into -1, and 0 is converted into 1. For example, the code word “10” will be converted into [-1, 1].

[0088] Through this conversion, the branch metric calculation module generates the multiplication matrix of the binary phase shift keying modulation mode. For 2-bit code words, the possible combinations are “00”, “01”, “10” and “11”, and the corresponding multiplication matrices are [1, 1], [1, -1], [-1, 1] and [-1, -1].

[0089] Finally, the branch metric calculation module performs an inner product operation between the received soft bit data and the multiplication matrix to obtain a branch metric value. This value represents the similarity between the received signal and the possible transmitted signal, and the larger the value, the more likely it is the correct transmitted signal.

[0090] When the modulation mode is binary phase shift keying-pulse position modulation, the working process of the branch metric calculation module is more complex:

[0091] First, the branch metric calculation module also obtains the 2-bit code word output by the convolutional encoder. However, in this modulation mode, the high-bit of the code word is used to represent the pulse position information, and the low-bit is used to represent the binary phase shift keying information.

[0092] According to the value of the high-bit, the branch metric calculation module generates a pulse position vector. When the high-bit is 1, the vector [1, 0] is generated, indicating that the pulse is in the first time period; when the high-bit is 0, the vector [0, 1] is generated, indicating that the pulse is in the second time period.

[0093] According to the value of the low-bit, the branch metric calculation module generates a polarity multiplier. When the low-bit is 0, the multiplier -1 is generated, indicating a positive pulse; when the low-bit is 1, the multiplier +1 is generated, indicating a negative pulse.

[0094] Then, the branch metric calculation module performs a scalar multiplication operation between the pulse position vector and the polarity multiplier to obtain the multiplication matrix of the binary phase shift keying-pulse position modulation mode. For a 2-bit code word, the possible combinations are "00", "01", "10" and "11", and the corresponding multiplication matrices are [1, 0], [-1, 0], [0, 1] and [0, -1].

[0095] Finally, the branch metric calculation module performs an inner product operation between the received soft bit data and the multiplication matrix to obtain a branch metric value.

[0096] When the modulation mode is mapping modulation, the working process of the branch metric calculation module is as follows:

[0097] First, the branch metric calculation module obtains the 2-bit code word output by the convolutional encoder.

[0098] Then, according to the pre-set mapping table (see Table 1 described above), the 2-bit code word is converted into the final bit. This mapping process can be any mapping relationship, depending on the system design requirements.

[0099] Then, the branch metric calculation module maps the final bits to a symbol vector, where 0 is mapped to symbol vector 1 and 1 is mapped to symbol vector -1. Through this mapping, a multiplication matrix of the mapping modulation mode is generated. For a 2-bit code word, the possible multiplication matrices are [1, 1], [-1, -1], [-1, 1] and [1, -1].

[0100] Finally, the branch metric calculation module performs an inner product operation on the received soft bit data and the multiplication matrix to obtain the branch metric value.

[0101] By supporting multiple modulation modes, the modulation decoder of the embodiment can adapt to different communication scenarios and needs. For example, the BPSK modulation mode is suitable for scenarios that require high reliability, the BPSK-PPM modulation mode is suitable for scenarios that require energy saving, and the mapping modulation mode provides greater flexibility and can customize the mapping relationship according to specific needs.

[0102] In one specific implementation process, the embodiment provides a detailed implementation of a control state machine module of a modulation decoder supporting multiple modulation modes.

[0103] The control state machine module includes a decoding flow control unit, a decoding interrupt control unit and a backtracking trigger unit. These three units work together to ensure the correct execution and efficient operation of the decoding process.

[0104] The decoding flow control unit is responsible for managing the flow of the entire decoding process, including initialization, iterative processing, state updating and error detection.

[0105] In the initialization phase, the decoding flow control unit initializes the path metric value to a preset value. Typically, the path metric of the initial state is set to 0, and the path metrics of other states are set to a very small negative value, indicating that these states are initially unreachable. At the same time, it also initializes the survivor path storage matrix and clears all historical data.

[0106] In the iterative processing phase, the decoding flow control unit controls the working rhythm of each module according to the predetermined timing. It first checks whether the input buffer module has data, and if so, generates a data request signal to trigger data reading. Then it controls the branch metric calculation module to calculate the branch metric value. Next, it controls the add-compare-select module to perform the core operation of the Viterbi algorithm. Finally, it controls the path metric calculation module to find the maximum path metric and its state index.

[0107] In the state updating phase, the decoding flow control unit updates the state information of each module, including the current processing data position, the accumulated path metric value, the survivor path information, etc. These updates prepare for the next iteration.

[0108] In the error detection phase, the decoding flow control unit monitors the decoding process for possible abnormal conditions, such as path metric overflow, data inconsistency, etc. Once an error is detected, it triggers the corresponding error handling mechanism to ensure the system can resume normal operation.

[0109] The decoding interrupt control unit is responsible for handling interruptions during the decoding process. When the input data is temporarily invalid (e.g., due to deteriorating channel conditions or temporary unavailability of the data source), the decoding interrupt control unit suspends the decoding process and preserves the current state of each module, including path metric values, surviving path information, processing position, etc.

[0110] When the input data resumes being valid, the decoding interrupt control unit resumes the decoding process from the suspension point without the need to reinitialize or discard processed data. This design ensures that the decoder can maintain efficient operation and minimize data loss even when the data stream is discontinuous.

[0111] The backtracking trigger unit is responsible for deciding when to start the backtracking process. It monitors two conditions: whether the path metric buffer is full and whether the decoding process has ended. When either condition is met, the backtracking trigger unit triggers the backtracking operation.

[0112] When the path metric buffer is full, it indicates that enough surviving path information has been accumulated to start backtracking decoding. The backtracking trigger unit sends a start signal to the backtracking module and provides the maximum path metric and its state index as the starting point for backtracking.

[0113] When the decoding process ends (e.g., all input data has been processed), the backtracking trigger unit also triggers the backtracking operation to decode the last batch of data.

[0114] Through the coordinated work of these three functional units, the control state machine module can effectively manage the entire decoding process, ensuring data processing continuity, correctness, and efficiency. Especially when dealing with large continuous data streams or facing unstable data sources, this design can provide better adaptability and robustness.

[0115] The apparatus embodiment described above is merely illustrative, and the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e., they can be located in one place or distributed on multiple network units. Some or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. Those skilled in the art can understand and implement it without creative labor.

[0116] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A modulation decoder supporting multiple modulation standards, characterized in that, include: The input buffer module is used to receive and buffer the input soft bit data; A control state machine module is used to generate a data request signal when the data in the input buffer module is not empty, and to control the timing of reading the soft bit data; The branch metric calculation module is used to select the corresponding multiplication matrix according to the preset modulation method, and to perform operations on the soft bit data and the multiplication matrix to obtain the branch metric value; The addition, comparison, and selection module is used to generate the surviving path and the current path metric of the surviving path based on the branch metric value through an addition, comparison, and selection process; The path metric calculation module is used to compare the current path metric to obtain the maximum path metric and the state index corresponding to the maximum path metric. A survival path storage module is used to store the survival paths; The backtracking module is used to extract the surviving path bits from the surviving path storage module based on the maximum path metric and the state index, and generate a decoded bit stream.

2. The modulation decoder supporting multiple modulation standards according to claim 1, characterized in that, The input buffer module is a depth-configurable FIFO memory, and continues to receive and buffer new soft bit data while the backtracking module is working.

3. The modulation decoder supporting multiple modulation schemes according to claim 1, characterized in that, The input buffer module has a depth of N and is used to cache the accumulated M sets of soft bit data during the backtracking process, and to process the N sets of soft bit data through the sliding window technique. The sliding window technique ensures that the decoder completes the processing of N sets of soft bit data within each sliding window by configuring the FIFO depth at the decoder entry point to match the external input data rate.

4. The modulation decoder supporting multiple modulation schemes according to claim 1, characterized in that, The input buffer module is also used to output a valid signal if the data request signal is received, and to output an invalid signal if the data request signal is not received. The control state machine module is also used to control the branch metric calculation module, the addition and comparison module, and the path metric calculation module to work if the valid signal is received, and to control the branch metric calculation module, the addition and comparison module, and the path metric calculation module to stop working if the invalid signal is received, while maintaining the data state before the work was stopped.

5. The modulation decoder supporting multiple modulation schemes according to claim 1, characterized in that, The branch metric calculation module is also used for: Generate corresponding codewords based on different modulation methods; The codewords are converted into multiplication matrices corresponding to their respective modulation schemes.

6. The modulation decoder supporting multiple modulation standards according to claim 5, characterized in that, The modulation scheme is binary phase shift keying modulation. The branch metric calculation module is also used for: Obtain the 2-bit codeword output by the convolutional coding; Convert the codeword bit values ​​into pulse polarity to obtain the multiplication matrix of the binary phase shift keying modulation scheme; In the 2-bit codeword, 1 is converted to -1 and 0 is converted to 1; the multiplication matrix of the binary phase shift keying modulation method is [1,1; 1,-1; -1,1; -1,-1].

7. The modulation decoder supporting multiple modulation schemes according to claim 5, characterized in that, The modulation scheme is binary phase shift keying-pulse position modulation. The branch metric calculation module is also used for: Obtain the 2-bit codeword output by the convolutional coding; wherein: the high-order bits of the 2-bit codeword represent pulse position information, and the low-order bits represent binary phase shift keying information; A pulse position vector is generated based on the high-order bits; where, when the high-order bits are 0, a vector [1,0] is generated to indicate the presence of a pulse in the first time period, and when the high-order bits are 1, a vector [0,1] is generated to indicate the presence of a pulse in the second time period. The polarity multiplier is generated based on the least significant bit; where, when the least significant bit is 0, multiplier 1 representing a positive pulse is generated; when the least significant bit is 1, multiplier -1 representing a negative pulse is generated. Perform a scalar multiplication operation between the pulse position vector and the polarity multiplier to obtain the multiplication matrix of the binary phase shift keying-pulse position modulation method; The multiplication matrix of the binary phase shift keying-pulse position modulation method is [1,0;-1,0;0,1;0,-1].

8. The modulation decoder supporting multiple modulation standards according to claim 5, characterized in that, The modulation scheme is a mapping modulation scheme; The branch metric calculation module is also used for: Obtain the 2-bit codeword output by the convolutional coding; The 2-bit codeword is converted into the final bits according to the preset mapping table; The final bits are mapped to symbol vectors to obtain the multiplication matrix of the mapping modulation method; wherein, the 0 in the final bits is mapped to the symbol vector 1, and the 1 in the final bits is mapped to the symbol vector -1; the multiplication matrix of the mapping modulation method is [1,1; -1,-1; -1,1; 1,-1].

9. The modulation decoder supporting multiple modulation schemes according to any one of claims 1-8, characterized in that, The input buffer module is also used to achieve a processing bandwidth greater than or equal to the input data bandwidth by configuring the depth and sliding window processing capabilities.

10. A modulation decoder supporting multiple modulation schemes according to any one of claims 1-8, characterized in that, The control state machine module includes: The decoding process control unit is used to manage initialization, iterative processing, status updates, and error detection; The decoding interrupt control unit is used to pause decoding and retain the state of each module when the input data is invalid, and to resume decoding when the input data becomes valid again; The backtracking trigger unit is used to trigger a backtracking operation when the path metric buffer is full or when decoding is finished.

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