Semiconductor device and data storage system including same

Abstract

The invention provides a semiconductor device and a data storage system including the same. The semiconductor device includes: a conductive layer; a stacked structure including gate electrodes stacked in a first direction, and stacked in the first direction in a first region and a second region adjacent to the first region; a channel structure penetrating the stack structure in the first direction; a contact structure including a first portion penetrating the stacked structures and a second portion extending from the first portion to a different length, penetrating the gate electrode and contacting the gate electrode, the first portion including a sub-member penetrating one of the stacked structures, the sub-member having an upper surface having a width greater than a lower surface having a width greater than a width of the lower surface, the sub-component comprises an inclined side surface between the upper surface and the lower surface, and the width of the lower surface of the first part is the same as the width of the upper surface of the second part.

Description

[0001] This application claims the benefit and priority of Korean Patent Application No. 10-2024-0075838, filed on June 11, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of this disclosure relate to semiconductor devices and data storage systems including semiconductor devices. Background Technology

[0003] Semiconductor devices can be advantageous for storing high-capacity data in data storage systems where data storage is required. Therefore, methods for increasing the data storage capacity of semiconductor devices have been investigated. For example, as a method for increasing the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensional memory cells instead of two-dimensional memory cells have been proposed. Summary of the Invention

[0004] Some exemplary embodiments of this disclosure provide semiconductor devices with improved reliability by reducing the etching depth of contact plugs in contact structures with relatively long lengths and high integration density, while simplifying the manufacturing process.

[0005] Some example embodiments of this disclosure provide data storage systems comprising semiconductor devices with improved reliability by reducing the etching depth of contact plugs in contact structures with relatively long lengths and / or high integration densities, while simplifying the manufacturing process. According to some example embodiments of this disclosure, a semiconductor device may include: a conductive layer; a plurality of stacked structures, each of the plurality of stacked structures including a plurality of gate electrodes sequentially stacked in a first direction perpendicular to the upper surface of the conductive layer, the plurality of stacked structures being sequentially stacked in a first direction in a first region and a second region adjacent to the first region; a channel structure including a plurality of channel portions respectively penetrating the plurality of stacked structures, and the plurality of channel portions being connected to each other in a first direction in the first region; a plurality of first-type contact structures penetrating at least one of the gate electrodes of the uppermost stacked structure of the plurality of stacked structures, the plurality of first-type contact structures extending to different lengths in a second region and being electrically connected to the gate electrode of the uppermost stacked structure respectively; and a plurality of second-type contact structures. The plurality of second-type contact structures extend from the top of the topmost stacked structure to completely penetrate at least one of the plurality of stacked structures, and extend to different lengths in the second region and are electrically connected to the topmost gate electrode of the stacked structure below the topmost stacked structure, respectively; and a plurality of third-type contact structures, each third-type contact structure comprising a first portion and a second portion, the first portion extending from the top of the topmost stacked structure to completely penetrate at least one of the plurality of stacked structures, the second portion extending from the bottom of the first portion in the second region to different lengths, penetrating at least one of the gate electrodes and electrically connected to the assigned gate electrode, wherein the boundary surface between the first portion and the second portion of each of the plurality of third-type contact structures is at the same height as the boundary surface between the plurality of channel portions of the channel structure.

[0006] According to some example embodiments of this disclosure, a semiconductor device may include: a conductive layer; a plurality of stacked structures, each of the plurality of stacked structures including gate electrodes stacked sequentially in a first direction perpendicular to the upper surface of the conductive layer, the plurality of stacked structures being stacked sequentially in the first direction in a first region and a second region adjacent to the first region; a channel structure penetrating the plurality of stacked structures in the first region and extending in the first direction; and contact structures, each including a first portion and a second portion, the first portion completely penetrating at least one of the plurality of stacked structures from the upper part of the uppermost stacked structure, the second portion extending from the lower part of the first portion to a different length, penetrating at least one of the gate electrodes and contacting the assigned gate electrode, wherein the first portion includes at least one sub-component completely penetrating one of the plurality of stacked structures, the width of the upper surface of each of the at least one sub-component is greater than the width of the lower surface of the at least one sub-component, and the at least one sub-component includes a continuously inclined side surface between the upper and lower surfaces, and the width of the lower surface of the first portion is the same as the width of the upper surface of the second portion.

[0007] According to some example embodiments of this disclosure, a data storage system may include: a semiconductor memory device including a first semiconductor structure comprising circuit elements, a second semiconductor structure on one surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit elements; and a controller electrically connected to the semiconductor memory device via the input / output pad and controlling the semiconductor memory device, wherein the second semiconductor structure includes a conductive layer; a plurality of stacked structures, each of the plurality of stacked structures including gate electrodes sequentially stacked in a first direction perpendicular to the upper surface of the conductive layer, the plurality of stacked structures being sequentially stacked in a first direction in a first region and a second region adjacent to the first region; and a channel structure penetrating the plurality of stacked structures in the first region. The stacked structure extends in a first direction; and the contact structure includes a first portion and a second portion, the first portion extending completely through at least one of the plurality of stacked structures from the top of the uppermost stacked structure, the second portion extending from the bottom of the first portion to a different length in a second region, penetrating at least one of the gate electrodes and contacting the assigned gate electrode, wherein the first portion includes at least one sub-component that completely penetrates one of the plurality of stacked structures, the width of the upper surface of each of the at least one sub-component is greater than the width of the lower surface of the at least one sub-component, and the at least one sub-component includes a continuously inclined side surface between the upper and lower surfaces, and the width of the lower surface of the first portion is the same as the width of the upper surface of the second portion. Attached Figure Description

[0008] The above and other aspects, features and / or advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0010] Figures 2A to 2D This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0011] Figures 3A to 3D yes Figures 2A to 2D An enlarged view of a portion of the area shown.

[0012] Figures 4 to 7 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0013] Figures 8 to 11 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0014] Figure 12 This is a diagram illustrating an etching process for forming contact holes in a semiconductor device according to some example embodiments of the present disclosure.

[0015] Figures 13A to 13L This is a cross-sectional view illustrating a method for manufacturing a semiconductor device.

[0016] Figure 14 This is a diagram illustrating a data storage system including a semiconductor device according to some example embodiments of the present disclosure.

[0017] Figure 15 This is a perspective view illustrating a data storage system including a semiconductor device according to some example embodiments of the present disclosure. Detailed Implementation

[0018] In the following description, some exemplary embodiments of this disclosure will be described with reference to the accompanying drawings.

[0019] Figure 1 This is a plan view illustrating a semiconductor device according to some example embodiments. Figures 2A to 2D This is a cross-sectional view showing a semiconductor device according to some example embodiments. Figure 2A It shows along Figure 1 A cross-sectional view of the region of the semiconductor device cut off by line I-I'. Figure 2B It shows along Figure 1 A cross-sectional view of the region of the semiconductor device taken by line II-II'. Figure 2C It shows along Figure 1 A cross-sectional view of the region of the semiconductor device taken by line III-III'. Figure 2D It shows along Figure 1 A cross-sectional view of the region of the semiconductor device taken by line IV-IV'. Figure 3A It is shown Figure 2A A magnified view of region "A" in the image. Figure 3B It is shown Figure 2A A magnified view of region "B" in the image. Figure 3C It is shown Figure 2D An enlarged view of region "C" in the image, and Figure 3D It is shown Figure 2A A magnified view of region "D" in the image. Figure 2B In the diagram, the first direction D1 and the second direction D2 are directions obtained by rotating the X and Y directions by a certain angle.

[0020] Reference Figures 1 to 3D The semiconductor device 100 may include a memory region R1 and an extension region R2 on one side of the memory region R1 in the X direction.

[0021] Memory region R1 may be a memory cell region containing memory cell strings CSTRs, and a channel structure CH may be disposed within memory region R1. Extension region R2 may be configured to electrically connect the channel structure CH to peripheral circuitry, and for this purpose, multiple word line contact plugs MC2 connected to the gate electrode 130 at different heights may be disposed within extension region R2, although some example embodiments are not limited thereto. When multiple groups (mats) are configured, memory region R1 may be defined for each group, but some example embodiments are not limited thereto.

[0022] The string selection region R3 can be located between the memory region R1 and the extension region R2. The string selection region R3 can be defined as the region where a string selection contact plug MC1 is provided to select each of the gate electrodes 130, which serve as string selection lines.

[0023] The semiconductor device 100 may have a structure in which a memory region R1, a string select region R3, and an extension region R2 are continuously arranged in the X direction. The memory region R1 and the string select region R3 may be defined as a first region by means of the isolation gate electrode 130, and the extension region R2 may be defined as a second region.

[0024] The semiconductor device 100 may include a conductive layer 101 in a memory region R1, a string select region R3, and an extension region R2; a stacked structure GS (GS1 to GSk, where k is a positive integer) in which gate electrodes 130 and interlayer insulating layers 120 are alternately stacked on the upper surface of the conductive layer 101; a channel structure CH in the memory region R1 that penetrates the stacked structures GS1 to GSk; an isolation region MS that penetrates the stacked structures GS1 to GSk and extends in the X direction; and an insulating region SS that penetrates a portion of the gate electrodes 130. Interconnect structures and passivation layers may also be included below the lower portion of the conductive layer 101.

[0025] The support structure DH and word line contact plug MC2 can be located in the extension area R2, and the support structure DH and string selection contact plug MC1 can be located in the string selection area R3.

[0026] exist Figures 2A to 3D In this embodiment, contact plugs MC1 and MC2 may extend to different lengths to connect between each gate electrode 130 and contact plugs MC1 and MC2, but some example embodiments are not limited thereto.

[0027] The memory region R1 and the extended region R2 may include a cell region insulating layer 150 on the stacked structures GS1 to GSK, a stud 185 that penetrates the cell region insulating layer 150 and is configured to be electrically connected to the channel structure CH and the contact plugs MC1 and MC2, and a cell interconnect 180 on the cell region insulating layer 150.

[0028] The conductive layer 101 may serve as a common source electrode and includes at least one of conductive materials such as doped silicon and conductive materials such as metals or metal nitrides. For example, the conductive layer 101 may include a silicon layer having N-type conductivity that can serve as a common source electrode.

[0029] The gate electrode 130 can be vertically stacked on the upper surface of the conductive layer 101 and can form a stacked structure GS (GS1 to GSk) together with the interlayer insulating layer 120. The gate electrode 130 can extend from the extension region R2 to the memory region R1 on one side, but the upper gate electrode 130U can be physically and electrically isolated between the string select region R3 and the extension region R2.

[0030] The stacked structures GS1 to GSk can include stacked structures GS1 to GSk that have multiple stages and are stacked vertically. Figures 2A to 2D The first to fifth stacking structures GS1, GS2, GS3, GS4, and GS5 are included, but some example embodiments are not limited thereto, and stacking structures GS1 to GS6 and GS1 to GS8 with six to eight levels may be included. In some example embodiments, stacking structures GS1 to GSk may include two stacking structures GS1 to GS2.

[0031] The stacked structures GS1 to GSK can be divided by the height of the stacked structure in which a process is performed to form channel holes with a predetermined or (optionally) desired depth for the channel structure CH, and can also be divided by the channel portion of the channel structure CH.

[0032] The lower stacked structure disposed on the upper surface of the conductive layer 101 can be referred to as the first stacked structure GS1. The stacked structures GS2 to GSK disposed on the first stacked structure GS1 can be referred to as the second stacked structure GS2, the third stacked structure GS3, and the fourth stacked structure GS4 to the kth stacked structure (GSk, k=5) in sequence. The second stacked structures GS2 to the fifth stacked structure GS5 can be referred to as the upper stacked structure. In addition, the kth stacked structure (GSk, k=5) disposed in the uppermost region and furthest from the conductive layer 101 in the Z direction can be referred to as the uppermost stacked structure.

[0033] In the stacked structures GS1 to GSk, the gate electrode 130 and the interlayer insulating layer 120 may be stacked alternately in the Z direction, and the boundary surface S between the stacked structures GS1 to GSk can be defined as the interface surface between the uppermost gate electrode 130 of the lower stacked structures GS1 to GS4 and the lowermost interlayer insulating layer 120 of the upper stacked structures GS2 to GS5. The thickness of the lowermost interlayer insulating layer 120 and the uppermost gate electrode 130 disposed at the boundary surface S may be substantially the same as the thickness of the other interlayer insulating layers 120 and the gate electrode 130. The length in the Z direction of each of the stacked structures GS1 to GS5 (or the number of gate electrodes 130 in each of the stacked structures GS1 to GS5) may be substantially the same, but some example embodiments are not limited thereto.

[0034] Relative to the entire stacked structure GS1 to GS5, gate electrode 130 may include at least one lower gate electrode 130L forming the gate of a ground selection transistor, a memory gate electrode 130M forming the gate of a plurality of memory cells, and an upper gate electrode 130U forming the string select line of the gate of a string selection transistor. Here, the lower gate electrode 130L and the upper gate electrode 130U may be referred to as “lower” and “upper” relative to the direction during the manufacturing process. The number of memory gate electrodes 130M forming memory cells may be determined according to the capacity of the semiconductor device 100. In some example embodiments, the number of each of the upper gate electrode 130U and the lower gate electrode 130L may be one to two or more, and may have the same or different structure as the memory gate electrode 130M. In some example embodiments, the number of upper gate electrodes 130U may be three. The erase gate electrode 130 may be further disposed below the upper gate electrode 130U. Furthermore, a portion of the gate electrode 130 (e.g., the memory gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L) may be a dummy gate electrode 130, but some example embodiments are not limited thereto.

[0035] Reference Figures 1 to 2D The gate electrodes 130 can be isolated from each other in the Y direction by isolation regions MS that extend continuously from memory region R1 to extension region R2. The gate electrodes 130 between the pairs of isolation regions MS can form a memory block BLK, but some example embodiments of the memory block BLK are not limited thereto. A portion of the gate electrodes 130 (e.g., memory gate electrode 130M) can be formed into a layer within the memory block BLK.

[0036] The gate electrodes 130 can be vertically stacked within the memory region R1, the string select region R3, and the extension region R2, and can maintain a continuous plate shape without forming a stepped structure in the extension region R2. The contact area of ​​each of the gate electrodes 130 can be defined as the area that contacts the contact plugs MC1 and MC2 in the string select region R3 and the extension region R2.

[0037] The gate electrode 130 may be formed of, for example, W, Ru, Mo, Nb, Ni, Co, Ti, Ta, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof, but some exemplary embodiments are not limited thereto. In some exemplary embodiments, the gate electrode 130 may also include a diffusion barrier 131, for example, the diffusion barrier 131 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0038] Interlayer insulating layer 120 may be disposed between gate electrodes 130 and may form stacked structures GS1, GS2, GS3, GS4, and GS5. Similar to gate electrodes 130, interlayer insulating layer 120 may also be stacked perpendicularly to the upper surface of conductive layer 101 and may extend in the X direction. Interlayer insulating layer 120 may include an insulating material (such as silicon oxide or silicon nitride).

[0039] In some example embodiments, the thickness of the interlayer insulating layers 120 may be substantially the same, but the thickness of some of the interlayer insulating layers 120 may be different. For example, the uppermost interlayer insulating layer 121 of the interlayer insulating layers 120 may have a thickness greater than the thickness of the other interlayer insulating layers 120, but some example embodiments are not limited to this.

[0040] The isolation region MS can be configured to penetrate at least a portion of the gate electrode 130 and extend in the X direction. The isolation region MS can continuously intersect the memory region R1, the string select region R3, and the extension region R2, and can extend in the X direction. The isolation region MS can penetrate the entire stacked gate electrode 130 and can be connected to the conductive layer 101. The isolation region MS can extend in the X direction as an integrated region, or it can extend discontinuously along its portion, or it can be disposed only in a portion of the region. The isolation region MS can be linear in the XY plane, or it can have a shape with continuously curved surfaces on its side surfaces and extend in the X direction.

[0041] The isolation region MS may have an isolation insulating layer 164 disposed therein. The isolation insulating layer 164 may have a shape in which its width decreases toward the conductive layer 101 due to a high aspect ratio (or height-to-width ratio or depth-to-width ratio), but some exemplary embodiments are not limited thereto. The upper surface of the isolation insulating layer 164 may contact the cell region insulating layer 150, and the lower surface of the isolation insulating layer 164 may contact the upper surface of the conductive layer 101.

[0042] The insulating region SS may include a first insulating region SS1 extending in the X direction and a second insulating region SS2 extending in the Y direction between adjacent insulating regions MS. The insulating region SS may selectively penetrate only the upper gate electrodes 130U1 to 130U3 (i.e., the series select line SSL), and may divide the upper gate electrodes 130U1 to 130U3 of the stacked structure GS5 among the stacked structures GS1 to GS5 into multiple sub-regions.

[0043] Reference Figure 1 The second insulating region SS2 may intersect with the extension region R2 and the series selection region R3 in the Y direction, and may isolate the upper gate electrodes 130U1 to 130U3. When at least three upper gate electrodes 130U1 to 130U3 are assigned to the series selection line, the three upper gate electrodes 130U1 to 130U3 may be simultaneously penetrated by the second insulating region SS2, and may be physically / electrically separated from each other in the plane.

[0044] The first insulating region SS1 may extend across memory region R1 and string select region R3 in the X direction. The first insulating region SS1 may include a plurality of first insulating regions SS1 that are parallel to each other between isolation regions MS and stacked in the Y direction, and may selectively isolate only the upper gate electrodes 130U1 to 130U3.

[0045] The first insulating region SS1 and the second insulating region SS2 can be configured to have the same length (e.g., depth) in the Z direction from the top, and the lower surfaces of the first insulating region SS1 and the second insulating region SS2 can be located at a height lower than the height of the lower surface of the lowest upper gate electrode 130U1 among the upper gate electrodes 130U1 to 130U3, and at a height higher than the height of the lower surface of the interlayer insulating layer 120 below the lowest upper gate electrode 130U1. Therefore, the first insulating region SS1 and the second insulating region SS2 can completely penetrate all the upper gate electrodes 130U1 to 130U3, so that the upper gate electrodes 130U1 to 130U3 can form multiple sub-regions that are physically / electrically completely separated.

[0046] Insulating regions SS1 and SS2 may not be located within the extension region R2, and may isolate the extension region R2 and the string selection region R3. The upper gate electrodes 130U1 to 130U3 may be isolated into multiple sub-regions in the Y direction within the memory region R1 and the string selection region R3, and may not be isolated within the extension region R2 and may form a single plate shape. In this case, insulating regions SS1 and SS2 may selectively penetrate only the upper gate electrodes 130U1 to 130U3, and may not extend to the memory gate electrode 130M, such that the memory gate electrode 130M and the lower gate electrode 130L may not be isolated from each other by insulating regions SS1 and SS2, and may be stacked in a plate shape within the memory region R1, the string selection region R3, and the extension region R2.

[0047] The end of the first insulating region SS1 may intersect with the second insulating region SS2 and may extend into the extension region R2, but some example embodiments are not limited thereto, and the first insulating region SS1 may be connected to the second insulating region SS2.

[0048] The first insulating region SS1 may span a portion of the channel structure CH within the memory region R1. The first insulating region SS1 may have a predetermined or (optionally) desired width in the Y direction and may extend in the X direction across multiple channel structures CH arranged in a zigzag pattern. Therefore, when multiple channel structures CH are arranged with the same spacing, the first insulating region SS1 may extend across a row of channel structures CH simultaneously. The first insulating region SS1 may be recessed into the upper portion of the channel structure CH (e.g., the upper end of the channel structure CH facing the three upper gate electrodes 130U), and thus, a portion of the channel structure CH may be removed. In this case, the channel structure CH may be recessed to a length smaller than the radius of the channel structure CH from the channel central axis to the inner wall of the channel hole. Therefore, the first insulating region SS1 may not pass through the channel central axis of the channel structure CH, and more than half of the upper surface of the channel structure CH may remain, although some example embodiments are not limited to this. The channel structure CH into which the first insulating region SS1 is recessed may be an effective channel structure actually used as a memory cell, rather than a dummy channel structure. Each of the insulating regions SS1 and SS2 may include an upper insulating layer 168. The upper insulating layer 168 may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0049] The channel structure CH can be stacked on the conductive layer 101 of the memory region R1, forming both rows and columns. Within the memory region R1, the channel structure CH can be arranged in a zigzag pattern along one direction in the XY plane. The channel structure CH can penetrate the gate electrode 130, can extend in a vertical direction perpendicular to the upper surface of the conductive layer 101 (e.g., in the Z direction), can have a columnar shape, and can have sloping side surfaces depending on the aspect ratio and a width that decreases towards the conductive layer 101.

[0050] Each of the channel structures CH may have k channel portions CH1 to CHk (k is a positive integer (such as 1, 2, 3, 4, ...)) connected to each other. Each channel structure CH penetrates the k stacked structures GS1 to GSk of the gate electrode 130, and in some example embodiments, the five channel portions (first channel portion CH1 to fifth channel portion CH5) that penetrate the five stacked structures GS1 to GS5 respectively may be connected to each other. The connection portion between the first channel portion CH1 to the fifth channel portion CH5 may have a bend BP due to differences or changes in width.

[0051] like Figure 3A As shown in the enlarged view, the upper end (e.g., upper surface) of each of the first channel portions CH1 to the fifth channel portions CH5 may have a width Wt greater than the width Wb of the lower end (e.g., lower surface), and due to the width difference between the upper and lower ends, the inclined side surface between the upper and lower surfaces may have a slope in which its width decreases toward the conductive layer 101. The lower ends of the upper channel portions CH1 to CH5 and the upper ends of the lower channel portions CH1 to CH5 may be connected to each other and may form a bend BP. The bending portion BP can be disposed on the boundary surface S of the first stacked structure GS1 to the fifth stacked structure GS5, and the upper surface of each of the first channel portion CH1 to the fifth channel portion CH5 can be coplanar with the upper surface of the first stacked structure GS1 to the fifth stacked structure GS5. When viewed in cross section, the side surface of the channel structure CH can be bent along the boundary surface S at the lower end of the upper channel portion CH1 to CH5 along the slope of the side surface of each of the channel portions CH1 to CH5, and can form a bending portion BP extending to the upper end of the lower channel portion CH1 to CH5, and the bending portion BP can have a discontinuous shape with corners.

[0052] Each of the channel structures CH may include a first portion within the stacked structures GS1 to GS5 and a second portion protruding below the stacked structures GS1 to GS5 and in contact with the conductive layer 101.

[0053] The channel layer 140 may be entirely disposed on the first and second portions of the channel structure CH, and may extend to the upper end of the second portion. The channel layer 140 may include protrusions disposed in the second portion of the channel structure CH and projecting and exposed below the stacked structures GS1 to GS5, and non-protrusions disposed in the first portion of the channel structure CH. The protrusions in the second portion of the channel structure CH and the protrusions of the channel layer 140 may have the same length, but some example embodiments are not limited thereto. The channel layer 140 may be formed in an annular shape having a buried insulating layer 147 surrounding its side surfaces, but in some example embodiments, the channel layer 140 may have a columnar shape (such as a cylinder or prism) without a buried insulating layer 147. The protrusions of the channel layer 140 may extend into the conductive layer 101 and may contact (e.g., directly contact) the conductive layer 101. The protrusions may be formed with a gentle slope compared to the non-protrusions, such that the annular shape may be as follows: Figure 3A The channel layer 140 may include a semiconductor material (such as polycrystalline silicon or monocrystalline silicon), and the semiconductor material may be an undoped material or a material including P-type impurities or N-type impurities.

[0054] In the channel structure CH, a channel pad 149 may be disposed on the upper part of the channel layer 140. The channel pad 149 may be configured to cover the upper surface of the buried insulating layer 147 and may be electrically connected to the channel layer 140. The channel pad 149 may include, for example, doped polysilicon.

[0055] A channel dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. The channel dielectric layer 145 may include a tunneling layer 141, a charge storage layer 142, and a barrier layer 143 sequentially stacked from the channel layer 140. The tunneling layer 141 can tunnel charge into the charge storage layer 142 and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer 142 may be a charge trapping layer or a floating gate conductive layer. The barrier layer 143 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. According to some example embodiments, at least a portion of the channel dielectric layer 145 may be formed as a channel dielectric layer extending horizontally along the gate electrode 130.

[0056] The channel dielectric layer 145 may be removed in the second portion from the region below the stacked structure GS1 to GS5, so that the protrusions of the channel layer 140 may be exposed to the outside. Therefore, the lower end of the channel dielectric layer 145 may contact the conductive layer 101, and the side surface of the channel dielectric layer 145 may be configured as non-protrusions surrounding the channel layer 140 in the first portion.

[0057] The channel layer 140, the channel dielectric layer 145, and the buried insulating layer 147 can be connected to each other between the first channel section CH1 to the fifth channel section CH5.

[0058] The support structure DH may be disposed in the string select region R3 and the extension region R2, and may have the same or similar structure as the channel structure CH, and may not perform any actual function within the semiconductor device 100. The support structure DH may be regularly arranged in columns and rows in the string select region R3 and the extension region R2. The support structure DH may have a diameter that is the same as or greater than the diameter of the channel structure CH (e.g., the maximum diameter), and a diameter that is the same as or smaller than the diameters of the contact plugs MC1 and MC2 (e.g., the maximum diameter). The shape of the support structure DH, the number of support structures DH, and / or the spacing between the support structures DH may vary. The channel structure CH and the support structure DH may have circular or nearly circular shapes, but some example embodiments are not limited to this, and the channel structure CH and the support structure DH may have elliptical shapes. The support structure DH may be similar to the channel structure CH penetrating the stacked structures GS1 to GS5, and may include a vertical portion extending in the Z direction and a horizontal portion protruding from the vertical portion toward each of the gate electrodes 130, but some example embodiments are not limited thereto. The support structure DH may also have a structure including a plurality of bends corresponding to the bends BP of the first channel portion CH1 to the fifth channel portion CH5 of the channel structure CH. The support structure DH may be a support member that can prevent or reduce possible deformation (such as warping) of the stacked structures GS1 to GS5.

[0059] The semiconductor device 100 may include contact plugs MC1 and MC2 connected to the gate electrode 130 in the string select region R3 and the extension region R2, respectively. Contact plugs MC1 and MC2 may penetrate at least a portion of the uppermost interlayer insulating layer 121, may extend downward in the Z direction, and may be connected to the upper surface of the assigned gate electrode 130. Contact plugs MC1 and MC2 may be as follows: Figure 1 The contacts shown have circular or elliptical shapes in the XY plane and can be stacked in both the X and Y directions. The contact plugs MC1 and MC2 can be arranged in a lattice shape or a zigzag pattern.

[0060] Each of the contact plugs MC1 and MC2 may include a plug conductive layer 175 and a contact blocking layer 172 surrounding the side and bottom surfaces of the plug conductive layer 175, and a side insulating layer 160 may further be disposed on the side surface of the contact blocking layer 172 of the contact plugs MC1 and MC2. The contact plugs MC1 and MC2 and the side insulating layer 160 surrounding the side surfaces of the contact plugs MC1 and MC2 may be referred to as contact structures MCa, MCb, and MCc.

[0061] In each of the contact plugs MC1 and MC2, the lower surface of the contact blocking layer 172 may be connected to and contact a contact area of ​​one of the gate electrodes 130, and the side insulating layer 160 may electrically insulate the plug conductive layer 175 from the gate electrode 130 adjacent to the side surface of the plug conductive layer 175. The plug conductive layer 175 may extend continuously from the lower surface of the contact plugs MC1 and MC2 that contacts the contact area of ​​the gate electrode 130 to the upper surface of the contact plugs MC1 and MC2.

[0062] In some example embodiments, each of the stacked structures GS1 to GS5 may include eight gate electrodes 130, and at least one contact plug MC1 and MC2 in physical / electrical contact with each gate electrode 130 may be provided. The number of gate electrodes 130 in the first stacked structures GS1 to the fifth stacked structures GS5 may be example, but some example embodiments are not limited thereto.

[0063] Contact plugs MC1 and MC2 may include a string select contact plug MC1 and a word line contact plug MC2.

[0064] The string selection contact plug MC1 can be disposed in the string selection area R3 and can be connected to a predetermined or (optionally) desired number of upper gate electrodes 130U1 to 130U3, which serve as string selection lines, respectively, in the upper part of the upper gate electrode 130U.

[0065] Figures 1 to 2BThe diagram shows three string select lines included, and therefore, three string select contact plugs MC1 connected to the upper gate electrodes 130U1 to 130U3, which serve as string select lines, can be disposed in each sub-region. That is, the string select contact plugs MC1 connected to the string select lines can be disposed in the sub-regions of the upper gate electrode 130U, divided by a first insulating region SS1 and a second insulating region SS2. In some example embodiments, each of the upper gate electrodes 130U1 to 130U3 can be connected to a string select contact plug MC1, or alternatively, multiple string select contact plugs MC1 can be connected to one of the upper gate electrodes 130U1 to 130U3. Therefore, the number of string select contact plugs MC1 assigned to each sub-region can be the same, and the number of string select contact plugs MC1 assigned to each sub-region can satisfy an integer multiple of the number of gate electrodes used as string select lines.

[0066] In each sub-region, the first upper gate electrode 130U3 to the third upper gate electrode 130U1 can be individually connected to the three string selection contact plugs MC1 through the three string selection contact plugs MC1, which can transmit electrical signals and select the channel structure CH of the corresponding sub-region.

[0067] The string select contact plug MC1 may not protrude beyond the sub-regions formed by cutting off the first upper gate electrode 130U3 to the third upper gate electrode 130U1. The lower end of the first string select contact plug MC1 may contact (e.g., directly contact) the upper surface of the first upper gate electrode 130U3. The lower end of the second string select contact plug MC1 may contact (e.g., directly contact) the upper surface of the second upper gate electrode 130U2. Subsequently, the lower end of the third string select contact plug MC1 may contact (e.g., directly contact) the upper surface of the third upper gate electrode 130U1. Therefore, the string select contact plug MC1 may not extend beyond the exterior of each sub-region formed by cutting off the first upper gate electrode 130U3 to the third upper gate electrode 130U1 (i.e., the string select contact plug MC1 may not extend below the third upper gate electrode 130U1).

[0068] In the extended region R2, when word line contact plugs MC2, which are respectively connected to the memory gate electrode 130M and the lower gate electrode 130L, are allocated one by one, the word line contact plugs MC2 can be configured to have different lengths to connect to the gate electrodes 130M and 130L, which have different heights.

[0069] exist Figures 2A to 3DIn some example embodiments, each of the first stack structure GS1 to the fifth stack structure GS5 may include eight gate electrodes 130, and since the upper three gate electrodes 130U serve as string select lines, 37 gate electrodes 130M and 130L may remain. Word line contact plugs MC2, whose lengths are differently adjusted to contact the upper surfaces of the 37 gate electrodes 130M and 130L respectively, may be disposed in the extension region R2.

[0070] The arrangement of the word line contact plug MC2 can vary, and in some example embodiments, such as Figures 1 to 2D As shown, in column 1, the word line contact plug MC2 can be arranged such that the word line contact plug MC2 can be lowered one layer at a time in the Z direction in the Y direction, and can contact the assigned gate electrode 130 respectively. Therefore, as Figure 2C As shown, in column 1, the word line contact plug MC2 arranged in the Y direction may have a length that increases in the Z direction, such that when the uppermost gate electrode 130 is referred to as the first gate electrode 130U3, the word line contact plug MC2 may contact the fourth to seventh gate electrodes 130 respectively. In column 2, the word line contact plug MC2 may extend to contact each of the eighth to eleventh gate electrodes 130, and in column 3, the word line contact plug MC2 may extend to contact each of the twelfth to fifteenth gate electrodes 130. Furthermore, as... Figure 2D As shown, in column 4, the word line contact plugs MC2 arranged in the Y direction have an increased length in the Z direction to contact the 16th to 19th gate electrodes 130, respectively. Therefore, the word line contact plugs MC2 can be arranged to have a length that increases in the X direction away from the memory region R1, and the word line contact plugs MC2 can be arranged to have a length that decreases downwards in the Y direction, but some example embodiments are not limited to this. For example, the word line contact plugs MC2 can be arranged in a single row, and can also be arranged symmetrically such that the length of the word line contact plugs MC2 in the Z direction increases towards the center of the word line contact plugs MC2. The word line contact plugs MC2 located in the last column may include dummy word line contact plugs MC2 and can be used as a support structure DH without performing the function of selecting actual word lines.

[0071] In contact structures MCa, MCb, and MCc, the side insulating layer 160 may be disposed only on the side surfaces of contact plugs MC1 and MC2, such that the lower portion of the gate electrode 130 and the lower surface of the contact barrier layer 172 can contact each other (e.g., in direct contact). In some example embodiments, a portion of contact plugs MC1 and MC2 may be configured to extend to a height lower than the upper surface of the assigned gate electrode 130, but may not extend to a height lower than the lower surface of the assigned gate electrode 130. Therefore, the lower surfaces of contact plugs MC1 and MC2 may be disposed at the same height as or lower than the upper surface of the gate electrode 130 in contact with contact plugs MC1 and MC2, and at a height higher than the lower surface of the gate electrode 130 in contact with contact plugs MC1 and MC2.

[0072] The plug conductive layer 175 of the contact structures MCa, MCb, and MCc may include a conductive material (e.g., at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof). For example, the plug conductive layer 175 may include tungsten (W). The contact barrier layer 172 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0073] The side insulating layer 160 may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0074] The contact structures MCa, MCb, and MCc may have different shapes depending on the shape of the contact plugs MC1 and MC2 included therein. The contact structures MCa, MCb, and MCc may have different lengths and different shapes to contact the gate electrode 130 disposed at different heights, respectively.

[0075] Specifically, contact structures MCa, MCb, and MCc may include a first type contact structure MCa, a second type contact structure MCb, and a third type contact structure MCc. The classification of contact structures MCa, MCb, and MCc may be based on their shape rather than on the type of contact plug (string select contact plug, word line contact plug). Each of the first type contact structure MCa, the second type contact structure MCb, and the third type contact structure MCc may have a symmetrical structure based on a centerline passing through the center of the width (e.g., maximum width) of the upper surface of each of the first type contact structure MCa, the second type contact structure MCb, and the third type contact structure MCc, but some example embodiments are not limited thereto.

[0076] However, the contact structure including the string select contact plug MC1 that contacts the uppermost gate electrode 130U3 may not be a structure that penetrates the gate electrode 130, and may only penetrate the uppermost interlayer insulating layer 121. Therefore, the contact structure that contacts the uppermost gate electrode 130U3 may include a string select contact plug MC1 having a plug shape and a side insulating layer 160 surrounding the side surface of the string select contact plug MC1, and may have a structure in which the width of the upper surface is greater than the width of the lower surface and an inclined side surface is formed between the upper surface and the lower surface.

[0077] The first type of contact structure MCa can be a contact structure MCa for contacting the gate electrode 130 in the uppermost stack structure GS5 other than the uppermost gate electrode 130U3, and can be a contact structure MCa that includes a portion of the string select contact plug MC1 to the word line contact plug MC2 connected to the eighth gate electrode 130.

[0078] Reference Figure 2A , Figure 2B , Figure 2C and Figure 3B The first type of contact structure MCa may have a continuous side surface from the upper surface of the first type of contact structure MCa, which is coplanar with the upper surface of the uppermost interlayer insulating layer 121, to the lower surface of the first type of contact structure MCa, and the width of the first type of contact structure MCa may increase toward the lower surface of the first type of contact structure MCa. The first type of contact structure MCa may include a reduced portion in which its width decreases inward from a portion near the lower surface of the first type of contact structure MCa, but some example embodiments are not limited thereto, and the first type of contact structure MCa may be configured such that the lower surface of the first type of contact structure MCa may have a maximum width. For example, the first type of contact structure MCa may have a maximum width in a portion near the lower surface of the first type of contact structure MCa, in which the width of the first type of contact structure MCa decreases inward toward the bottom surface of the first type of contact structure MCa. The first type of contact structure MCa may not include a bend BP in which its width decreases and increases from the upper surface to the lower surface of the first type of contact structure MCa, and the width of the first type of contact structure MCa may increase uniformly. Therefore, the first type of contact structure MCa may have a first type of contact structure MCa having the longest word line contact plug MC2 that contacts the lowest gate electrode 130 within the uppermost stacked structure GS5 (e.g. Figure 2A As shown in the image).

[0079] The upper surface of the first type of contact structure MCa may have a first width W1, and the first width W1 may have a width greater than the width (e.g., the maximum width) of the support structure DH.

[0080] The second type of contact structure MCb can be a contact structure MCb for contacting the uppermost gate electrode 130 in each of the stack structures GS1 to GS4 other than the uppermost stack structure GS5, and when each of the stack structures GS1 to GS4 may include eight gate electrodes 130, the second type of contact structure MCb may be a contact structure MCb including word line contact plugs MC2 that are respectively connected to the 9th gate electrode 130, the 17th gate electrode 130, the 25th gate electrode 130 and the 33rd gate electrode 130 from the top of the uppermost stack structure GS5.

[0081] Reference Figure 2B , Figure 2D and Figure 3C The second type of contact structure MCb may include a side surface having a slope whose width decreases from the upper surface to the lower surface, the upper surface being coplanar with the upper surface of the uppermost interlayer insulating layer 121. The upper surface of the second type of contact structure MCb may be disposed at the same height as the upper surface of the uppermost interlayer insulating layer 121. The second type of contact structure MCb may completely penetrate the stacked structures GS2 to GS5 from the upper surface to the lower surface of the assigned gate electrode 130, and may extend in the Z direction. The length of the second type of contact structure MCb may be determined according to the number of stacked structures GS penetrated by the second type of contact structure MCb, and the second type of contact structure MCb in contact with the 9th gate electrode 130 may have a length equal to the sum of the length of the uppermost stacked structure GS5 in the Z direction and the length of the uppermost surface of the uppermost stacked structure GS5 from the upper surface of the uppermost interlayer insulating layer 121. The second type of contact structure MCb, which contacts the 17th gate electrode 130, may have a length equal to the sum of the length of the stacked structures GS4 to GS5 in the Z direction and the length of the uppermost surface of the uppermost stacked structure GS5 from the uppermost surface of the uppermost interlayer insulating layer 121. Each sub-component of the second type of contact structure MCb that penetrates each of the stacked structures GS2 to GS5 may have a side surface with a continuous slope (e.g., a continuously inclined side surface), such that the second width W2 of the upper surface of each sub-component may be greater than the width W4 of the lower surface of each sub-component, and the side surface (e.g., the inclined side surface) of each sub-component may have a continuous slope, such that the width of each sub-component may decrease toward the lower surface of each sub-component. In this case, when the second type of contact structure MCb includes multiple sub-components, the bend BP may be formed by the difference between the second width W2 of the upper surface and the width W4 of the lower surface, and the bend BP may be located at the same height as the bend BP of the channel structure CH at the boundary surface S between the stacked structures GS1 to GS4. In other words, each sub-component with a shape having a second width W2 on the upper surface that is greater than the width W4 on the lower surface can be connected to each other in the Z direction for each of the stacked structures GS2 to GS5, and can form a second type of contact structure MCb.

[0082] In one example, when the second type contact structure MCb includes at least two sub-components, the second type contact structure MCb may include a bend BP. Therefore, the second type contact structure MCb connected to the 9th gate electrode 130 may include a sub-component that penetrates only the fifth stack structure GS5 without a bend BP, and the second type contact structure MCb connected to the 17th gate electrode 130 may include, for example... Figure 3C The bending portion BP shown is located on the boundary surface S between the fifth stacked structure GS5 and the fourth stacked structure GS4, according to the difference between the widths W2 and W4 of the upper and lower surfaces of each sub-component. Similar to the channel structure CH, the bending portion BP can connect and contact with the upper sub-component of the second type contact structure MCb and the lower sub-component of the second type contact structure MCb, and can be achieved through discontinuous side surfaces with corners.

[0083] The second type of contact structure MCb can have an upper surface with the same width W2 regardless of its length. In this case, the second width W2 of the upper surface of the second type of contact structure MCb can be smaller than the first width W1 of the upper surface of the first type of contact structure MCa.

[0084] The third type of contact structure MCc may include contact structures MCb and MCc other than the second type of contact structure MCb, which are used to contact the gate electrode 130 in the stacked structures GS1 to GS4 other than the topmost stacked structure GS5.

[0085] Reference Figure 2A , Figure 2B , Figure 2D and Figure 3D The third type of contact structure MCc can have a structure in which the second type of contact structure MCb and the first type of contact structure MCa are combined with each other.

[0086] The third type of contact structure MCc may have a length longer than that of one of the stacked structures GS1 to GS5. When at least one of the stacked structures GS2 to GS5 is disposed above the assigned gate electrode 130, a first portion MCc1 corresponding to the length of at least one of the stacked structures GS2 to GS5 that is completely penetrated by the third type of contact structure MCc, and a second portion MCc2 extending from the lower surface of the first portion MCc1 to the height of the assigned gate electrode 130 disposed below the first portion MCc1, may be included.

[0087] The shape of the first part MCc1 may be similar to or correspond to the second type of contact structure MCb, and the shape of the second part MCc2 may be similar to or correspond to the first type of contact structure MCa. In this case, the configuration in which the components are similar or corresponding to each other may indicate that the components may be the same as each other, and may also indicate that the shapes of the components may be similar, and the directions of width increase may be similar.

[0088] Referring to Figure 2A and Figure 3D , the gate electrode 130 assigned to contact the third type of contact structure MCc may be disposed within the m-th stacked structure (GSm, m < k, m = 1, 2,..., k - 1) among the k stacked structures GS1 to GSk. In this case, in the first part MCc1 of the third type of contact structure MCc that penetrates k - m stacked structures GS from above, similar to the second type of contact structure MCb, sub-components having a width decreasing from the upper surface to the lower surface may be disposed in each stage of the stacked structures GSm+1 to GSk on the m-th stacked structure GSm, and may have a bent portion BP on the boundary surface S between the stacked structures GSm+1 to GSk on the m-th stacked structure GSm.

[0089] As an example, as Figure 2A shown, when the gate electrode 130 contacting the third type of contact structure MCc is disposed from above in the third stacked structure GS3, in the first part MCc1 of the third type of contact structure MCc that penetrates two stacked structures GS4 and GS5 from above, two sub-components (such as the second type of contact structure MCb) whose widths decrease from the upper surface to the lower surface may be sequentially disposed in the stacked structures GS4 and GS5, and may have a bent portion BP on the boundary surface S between the stacked structures GS4 and GS5.

[0090] The bent portion BP may be disposed such that the upper surface of the upper stacked structure GS5 may be parallel to the upper surface of the lower stacked structure GS4, such that the side surface may indicate a discontinuous side surface having a corner, and each bent portion BP may be disposed at the same height as one of the bent portions BP in the channel structure CH.

[0091] The second part MCc2 may be disposed such that the second part MCc2 may extend from the lower surface of the first part MCc1 to the region contacting the upper surface of the assigned gate electrode 130 below the first part MCc1.

[0092] The second portion MCc2 may have a shape similar to the first type of contact structure MCa, and may include a reduced portion whose width increases from the upper surface to the lower surface of the second portion MCc2 and decreases towards the lower surface of the second portion MCc2, but some example embodiments are not limited thereto. The width of the second portion MCc2 (e.g., the maximum width W6) may be set within the thickness of the penetrating lowermost gate electrode 130, but some example embodiments are not limited thereto. That is, the second portion MCc2 may include a reduced portion whose width increases downward and decreases as it passes through the penetrating lowermost gate electrode 130, and the width W7 of the lower surface of the second portion MCc2 may have a value smaller than the width (e.g., the maximum width W6). However, even when the width W7 of the lower surface of the second portion MCc2 decreases due to the reduced portion, this value may be the same as or greater than the width W5 of the lower surface of the first portion MCc1.

[0093] The boundary between the first part MCc1 and the second part MCc2 may include a bend CP on the boundary surface S of the stacked structures GS1 to GS5. In other words, the boundary between the first part MCc1 and the second part MCc2 may be at the same height as the boundary surface S of the stacked structures GS1 to GS5. Unlike the bend BP, the bend CP may not have a corner, and the lower surface of the first part MCc1 and the upper surface of the second part MCc2 may coincide with each other, so that the first part MCc1 and the second part MCc2 can continuously form a bend surface and the slope can be changed.

[0094] like Figure 3D As shown, the third type contact structure MCc in the second-level stacked structure GS4, starting from the top of the stacked structure GS, may include only the bent portion CP without the bent portion BP. Furthermore, the third type contact structure MCc in the stacked structures GS3 to GS1 below the second level, which contacts the gate electrode 130, may include both the bent portion BP and the bent portion CP. Depending on the height of the gate electrode 130 in contact with the third type contact structure MCc, multiple bent portions BP may be included together with the bent portions CP.

[0095] Therefore, the third type of contact structure MCc may include a first portion MCc1 having different lengths comprising a different number of sub-components and a second portion MCc2 having the same length. Thus, the second portion MCc2 may contact the gate electrode 130 at the same height from the upper part within the stacked structure GS in each stage.

[0096] When the first part MCc1 includes multiple sub-components, the width W3 of the upper surface of the sub-components may be the same. The upper surface of the third type contact structure MCc may have a third width W3, and the third width W3 may have a width greater than the width (e.g., the maximum width) of the support structure DH, and may be the same as or greater than the first width W1 of the first type contact structure MCa.

[0097] Therefore, among the contact structures MCa, MCb and MCc, the second width W2 of the upper surface of the second type contact structure MCb can be the smallest, and the third width W3 of the third type contact structure MCc can be the same as or greater than the first width W1 of the first type contact structure MCa.

[0098] In the contact structures MCa, MCb, and MCc, the second type contact structure MCb and the third type contact structure MCc, which extend through the stacked structure GS having multiple levels, can have a bend BP at the same height as the bend BP of the channel structure CH. This can be achieved by forming the contact holes of the second type contact structure MCb and the third type contact structure MCc together with the channel holes of the channel structure CH up to the boundary surface S between the levels of the stacked structure GS.

[0099] In the string selection region R3 and the extension region R2, the support structure DH can be arranged in a regular pattern with the contact structures MCa, MCb, and MCc. For example, as... Figure 1 As shown, the support structure DH and contact structures MCa, MCb and MCc can be arranged alternately, but some example embodiments are not limited to this.

[0100] The cell region insulating layer 150 may be configured to cover the stacked structure GS. In some example embodiments, the cell region insulating layer 150 may include multiple insulating layers. The cell region insulating layer 150 may be formed of an insulating material and may include at least one of, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0101] The spike 185 and cell interconnect 180 can form a cell interconnect structure electrically connected to the memory cell. The spike 185 can penetrate a portion of the cell region insulating layer 150 and can be connected to the channel structure CH and contact structures MCa, MCb and / or MCc, and can be electrically connected to the channel layer 140 and the gate electrode 130. The spike 185 can have a plug shape, and the cell interconnect 180 can have a line shape, but some example embodiments are not limited thereto. The spike 185 and cell interconnect 180 can include metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.).

[0102] The upper insulating layer 190 may be provided to cover the cell interconnects 180 on the cell region insulating layer 150. The upper insulating layer 190 may be formed of an insulating material and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON and / or SiOCN.

[0103] Figures 4 to 7 This is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0104] In addition to the shapes of the first type of contact structure MCa and the third type of contact structure MCc Figure 4 The semiconductor device 100a in the middle can be with Figures 1 to 3D The semiconductor device 100 in it is the same.

[0105] The third type of contact structure MCc can have a structure in which the second type of contact structure MCb and the first type of contact structure MCa are connected to each other.

[0106] The third type of contact structure MCc may have a length longer than the length of a stage of the stacked structure GS. When at least one stage of the stacked structure GS is disposed above the gate electrode 130, the third type of contact structure MCc may include a first portion MCc1 corresponding to the length of at least one stage of the fully penetrated stacked structure GS, and a second portion MCc2 connected to the lower surface of the first portion MCc1 and extending below the first portion MCc1 to the height at which the corresponding gate electrode 130 is disposed.

[0107] The shape of the first part MCc1 can be similar to the shape of the second type of contact structure MCb, and the shape of the second part MCc2 can be similar to the shape of the first type of contact structure MCa. Because the first part MCc1 of the third type of contact structure MCc is similar to... Figure 3D The first part MCc1 of the third type contact structure MCc is the same, therefore its description will not be provided, and the second part MCc2 will be the main description. Furthermore, the description of the second part MCc2 can replace the description of the first type contact structure MCa.

[0108] The second part MCc2 can be configured such that the second part MCc2 can extend from the upper surface of the m-th stacked structure (GSm, m=1, 2, 3, 4) below the first part MCc1 to the upper surface of the corresponding gate electrode 130.

[0109] The second part MCc2 may have a width that increases from the upper surface (e.g., upper part) to the lower surface (e.g., lower part) of the second part MCc2.

[0110] The first portion MCc1 and the second portion MCc2 may include a first bend CP1 at the boundary surface S between the stages of the stacked structure GS. Unlike the bend BP, the first bend CP1 may not have a corner and may be defined as having an inflection point (e.g., an inflection point) that forms a gently curved surface and has a changing slope.

[0111] Depending on the length, in addition to the first curved portion CP1, the second portion MCc2 may also include at least one curved portion CP below the first curved portion CP1. Specifically, as... Figure 4 As shown, whenever the second part MCc2 penetrates the second part MCc1 below the second... N (N=0, 1, 2, 3, ...) When the gate electrode is 130, an additional bending portion CP can be set.

[0112] exist Figure 4 In this process, the second portion MCc2 can penetrate seven gate electrodes 130, and may include a second bend CP2 on the interlayer insulating layer 120 below the upper surface of the fourth gate electrode 130 starting from the lower surface of the first portion MCc1, and a third bend CP3 on the interlayer insulating layer 120 below the upper surface of the sixth gate electrode 130 (i.e., the second gate electrode 130 starting from the fourth gate electrode 130) starting from the lower surface of the first portion MCc1. That is, depending on the number of gate electrodes 130 penetrated by the second portion MCc2, additional bends CP may be provided on the second portion MCc2. N On the upper surface of the gate electrode 130, the bend CP may include an inflection point formed due to the width of the lower part of the bend CP increasing more rapidly than the width of the upper part of the bend CP, and when the slope of the side surface of the upper part of the bend CP is different from the slope of the side surface of the lower part of the bend CP, the bend CP may be defined as a region that continuously connects the two side surfaces to each other.

[0113] When the second portion MCc2 penetrates one, two, or four gate electrodes 130, the second portion may include only the first bend CP1 without the additional bend CP. When the second portion MCc2 penetrates three gate electrodes 130, the additional bend CP may be included on the upper surface of the second gate electrode 130 extending downwards from the first portion MCc1. When the second portion MCc2 penetrates five or six gate electrodes 130, the additional bend CP may be included on the upper surface of the fourth gate electrode 130 extending downwards from the first portion MCc1, and as... Figure 4 As shown, when the second portion MCc2 penetrates the seven gate electrodes 130, the additional second bend CP2 and third bend CP3 may be included on the upper surfaces of the fourth gate electrode 130 and the sixth gate electrode 130 extending downward from the first portion MCc1.

[0114] In some example embodiments, a stage of the stacked structure GS (e.g., each of the stacked structures GS1, GS2, GS3, GS4 and GS5) may include eight gate electrodes 130, and when a greater number of gate electrodes 130 are included, a greater number of bends CP may be included.

[0115] exist Figure 4 In the middle, when the additional curved portion CP is set in the second part according to the number of gate electrodes 130 penetrated by the second part MCc2, N When the gate electrode 130 is on the upper surface, the bent portion CP can be arranged in the order of 4th, 2nd and 1st, or the bent portion CP can be arranged in the reverse order (in the order of 1st, 2nd and 4th).

[0116] When multiple curved portions CP are provided in the second portion MCc2, the width of the curved portions CP can increase rapidly from the upper end to the lower end of the second portion MCc2, and the curved portions CP can have a width that increases towards the lower end of the second portion MCc2. For example, in Figure 4 In this case, the width W8 of the second curved portion CP2 can be greater than the width W5 of the upper end of the second portion MCc2, the width W9 of the third curved portion CP3 can be greater than the width W8 of the second curved portion CP2, and the width W10 of the lower end of the second portion MCc2 can be the largest. In this case, the width W10 of the lower end of the second portion MCc2 can be greater than when extending from the upper end of the second portion MCc2 to the lower end of the second portion MCc2 with a slope from the upper end of the second portion MCc2 to the lower end of the second portion MCc2 (…). Figure 3D The width of the lower end of the second part MCc2. The lower end of the second part MCc2 may include, for example: Figure 3D It is a portion of the reduced portion, but some example embodiments are not limited thereto.

[0117] The curved portions CP1 to CP3 can be formed by multiple wet etching processes on the second portion MCc2, and by using binary (2 n The symbol represents the height of each gate electrode 130. When contact holes are formed at different depths by etching at the same number of etches as the number of binary digits to contact the gate electrodes 130 at different heights, holes can be formed at different depths depending on the number of etches. In this case, the first portion MCc1 of the second type contact structure MCb and the third type contact structure MCc can be etched together with the channel holes of the channel structure CH, so that the number of additional etches to the contact structures MCb and MCc by wet etching can be (e.g., significantly) reduced, and the etch depth of a single etch can also be (e.g., significantly) reduced.

[0118] The second width W2 of the upper surface of the second type contact structure MCb without repeated wet etching can be the smallest, and the third width W3 of the third type contact structure MCc with repeated wet etching can be the same as or greater than the first width W1 of the first type contact structure MCa.

[0119] Furthermore, the contact structures MCb and MCc, which extend by penetrating multiple stacked structures GS, may have a bend BP at the same height as a portion of the bend BP in the channel structure CH.

[0120] In addition to the shapes of the first type of contact structure MCa and the third type of contact structure MCc Figure 5 The semiconductor device 100b in the middle can be connected with Figures 1 to 3D The semiconductor device 100 in it is the same.

[0121] Figure 5 The third type of contact structure MCc can have a structure in which a first part MCc1, identical to the second type of contact structure MCb, and a second part MCc2, identical to the first type of contact structure MCA, are combined with each other, and because the combined structure and Figure 4 The third type of contact structure MCc is the same, therefore a description of the first part MCc1 will not be provided.

[0122] Figure 5 The width of the second portion MCc2 of the third type of contact structure MCc can increase downwards from the upper surface of the second portion MCc2 and can decrease in the bend CP. The boundary between the first portion MCc1 and the second portion MCc2 may include a first bend CP1 at the boundary surface S of the stacked structure GS. Unlike the bend BP, the first bend CP1 may not have a corner and may have an inflection point where the bend surface is gently formed and the slope changes.

[0123] The second part MCc2 of the third type of contact structure MCc may also include an additional bend CP below the first bend CP1, depending on the length.

[0124] Specifically, such as Figure 5 As shown, when the second part MCc2 penetrates the first part MCc1 below 2 N When there are (N=0, 1, 2, 3, ...) gate electrodes 130, the bent portion CP can be included below the second portion MCc1. N At the gate electrode 130.

[0125] The bend CP can be defined as the region including the inflection point formed because the width of the lower part of the bend CP decreases more rapidly than the width of the upper part of the bend CP, and an additional bend CP can be set in the second... N On the upper surface of the gate electrode 130.

[0126] When the second portion MCc2 penetrates one, two, and four gate electrodes 130, the second portion MCc2 may only include the first bend CP1, without the additional bend CP. For example, when the second portion MCc2 penetrates three gate electrodes 130, the second portion MCc2 may include an additional bend CP on the upper surface of the second gate electrode 130 extending downward from the first portion MCc1. When the second portion MCc2 penetrates five and six gate electrodes 130, the second portion MCc2 may include an additional bend CP on the upper surface of the fourth gate electrode 130 extending downward from the first portion MCc1. Figure 4 As shown, when the second portion MCc2 penetrates the seven gate electrodes 130, the second portion MCc2 may include additional second bends CP2 and third bends CP3 on the upper surfaces of the fourth gate electrode 130 and the sixth gate electrode 130 extending downward from the first portion MCc1.

[0127] In some example embodiments, a stage of the stacked structure GS may include eight gate electrodes 130, and when the stage includes a greater number of gate electrodes 130, a greater number of bends CP may be included.

[0128] When multiple curved portions CP are provided in the second part MCc2, the width of the curved portions CP decreases rapidly from the upper end to the lower end of the second part MCc2, and the lower end of the second part MCc2 may have a minimum width W13. For example, in Figure 5 In this configuration, the width W11 of the second curved portion CP2 can be greater than the width W5 of the upper end of the second portion MCc2, and the width W11 can decrease rapidly when passing through the second curved portion CP2. Similarly, the width W12 of the third curved portion CP3 can be less than the width W11 of the second curved portion CP2, and the width W12 can decrease rapidly when passing through the third curved portion CP3, so that the width W13 of the lower end of the second portion MCc2 can be minimized. In this case, the width W13 of the lower end of the second portion MCc2 can be much smaller than when extending from the upper end of the second portion MCc2 to the lower end of the second portion MCc2 with a slope from the upper end of the second portion MCc2 to the second curved portion CP2 (e.g., ...). Figure 3D The width of the lower end of the second portion MCc2 (as shown in the diagram). The lower end of the second portion MCc2 may include, for example, the width of the lower end of the second portion MCc2. Figure 3D It is a portion of the reduced portion, but some example embodiments are not limited thereto.

[0129] The bend CP can be formed by repeatedly etching the second part MCc2 to extend the contact hole downwards.

[0130] In addition to the shapes of the first type of contact structure MCa and the third type of contact structure MCc Figure 6 The semiconductor device 100c in the middle can be with Figures 1 to 3D The semiconductor device 100 in it is the same.

[0131] Figure 6 The third type of contact structure MCc can have a structure in which a first part MCc1, identical to the second type of contact structure MCb, and a second part MCc2, identical to the first type of contact structure MCA, are combined with each other, and because the combined structure and Figure 5 The third type of contact structure MCc is the same, therefore a description of the first part MCc1 will not be provided.

[0132] Figure 6 The second portion MCc2 of the third type of contact structure MCc can be formed such that the width W14 is substantially consistent from the upper to the lower part of the second portion MCc2. The first portion MCc1 and the second portion MCc2 may include a bend CP on the boundary surface S of the stacked structure GS. The lower surface of the first portion MCc1 and the upper surface of the second portion MCc2 may be continuously connected to each other and may have the same width W5. In the upper part of the second portion MCc2, the width of the upper surface of the bend surface portion may extend to meet a predetermined or (optionally) desired width W14. When the second portion MCc2 meets the predetermined or (optionally) desired width W14, the second portion MCc2 may extend to the lower end of the second portion MCc2 while maintaining the predetermined or (optionally) desired width W14.

[0133] Therefore, the second part MCc2 of the third type of contact structure MCc can have a similar shape regardless of its length, by using binary (2 n The symbol 130 represents the height of each gate electrode. When contact holes of various depths contacting the gate electrodes at different heights are formed by performing an etching process equal to the number of etches as the number of binary numbers, the contact holes can be formed by multiple etching processes to maintain a predetermined or (optionally) desired width W14. Furthermore, in the first type of contact structure MCa, when contact holes of various depths contacting the gate electrodes at different heights within the uppermost stacked structure GS5 are formed by performing an etching process equal to the number of etches as the number of digits in the binary system, the contact holes can be formed by multiple etching processes to maintain a predetermined or (optionally) desired width.

[0134] In addition to the shapes of the first type of contact structure MCa and the third type of contact structure MCc Figure 7 The semiconductor device 100d in the middle can be with Figure 4 The semiconductor device 100a is the same.

[0135] The third type of contact structure MCc can have a structure in which the second type of contact structure MCb and the first type of contact structure MCa are combined with each other.

[0136] The third type of contact structure MCc may have a length longer than the length of one stage of the stacked structure GS. When multiple stacked structures GS are disposed above the assigned gate electrode 130, a first portion MCc1 corresponding to the length of the multiple stacked structures GS that are completely penetrated may be included, and a second portion MCc2 extending below the first portion MCc1 to the height of the assigned gate electrode 130 may be included.

[0137] The shape of the first part MCc1 may be similar to that of the second type contact structure MCb, and the shape of the second part MCc2 may be similar to that of the first type contact structure MCa. Since the shape of the first part MCc1 is the same as that described above, no description will be provided, and since the shape of the second part MCc2 is the same as that of the first type contact structure MCa, the description of the first type contact structure MCa can be replaced by the description of the second part MCc2.

[0138] The second portion MCc2 can be configured such that it extends from the upper surface of the stacked structure GS, which has the assigned gate electrode 130 disposed below the first portion MCc1, to the upper surface of the assigned gate electrode 130. The second portion MCc2 can have a width that increases from the upper surface to the lower surface of the second portion MCc2.

[0139] The first portion MCc1 and the second portion MCc2 may include a first bend CP1 on the interface surface of the stacked structure GS. Unlike the bend BP, the first bend CP1 may not have a corner and may be defined as having an inflection point forming a gently curved surface and having a changing slope. In addition to the first bend CP1, the second portion MCc2 may also include an additional bend CP below the first bend CP1. Specifically, as Figure 7 As shown, when the second part MCc2 penetrates the second part MCc1 below the second... N (N=0, 1, 2, 3, ...) When the gate electrode is 130, the second one below the first part MCc1 N The gate electrode 130 may have a bend CP.

[0140] Figure 7An example is shown where the second portion MCc2 penetrates the seven gate electrodes 130, and thus, the second bend CP2 and the third bend CP3 may be included on the upper surface of the fourth gate electrode 130, which is the lower surface of the first portion MCc1, and the sixth gate electrode 130, which is the second gate electrode 130, which is the fourth gate electrode 130.

[0141] Depending on the number of gate electrodes penetrated by the second part MCc2, an additional bend CP can be set in the second... N On the upper surface of the gate electrode, the bend CP may include an inflection point formed due to the rapid increase in the width of the lower part of the bend CP compared to the width of the upper part of the bend CP.

[0142] In some example embodiments, one stage of the stacked structure may include eight gate electrodes 130, and when a greater number of gate electrodes are included, a greater number of bends CP may be included.

[0143] When multiple curved portions CP are provided in the second portion MCc2, the curved portions CP can rapidly extend from the upper surface of the second portion MCc2 to the lower end of the second portion MCc2, and can have a width that increases towards the lower end of the second portion MCc2. For example... Figure 3D As shown, the lower end of the second part MCc2 may include a portion of the reduced portion, but some example embodiments are not limited thereto.

[0144] The curved portion CP can be formed by extending the contact hole downwards through continuous wet etching of the second portion MCc2. In this case, when the center line extending in the Z direction through the center of the width of the first portion MCc1 (e.g., the upper surface of the first portion MCc1) and the first curved portion CP1 is defined as the first virtual line l0, the center line extending in the Z direction through the center of the width of the second curved portion CP2 is defined as the second virtual line l1, and the center line extending in the Z direction through the center of the width of the third curved portion CP3 is defined as the third virtual line l2, the second virtual line l1 can be offset without being coaxial with the first virtual line l0, and the third virtual line l2 can be offset without being coaxial with the second virtual line l1. Therefore, the second portion MCc2 can be asymmetrically arranged with respect to the first virtual line l0. For example, as Figure 7 As shown, one side surface of the second portion MCc2 can maintain a vertical straight line in the Z direction from the first curved portion CP1 to the lower end of the second portion MCc2, and the second curved portion CP2 and the third curved portion CP3 can be sequentially arranged on the other side surface. In this case, the third virtual line l2 can be set to be farther away from the first virtual line l0 than the second virtual line l1, and the third virtual line l2 can satisfy a predetermined or (optionally) desired width in the Z direction by being set within the width W5 of the lower end of the first portion MCc1.

[0145] In the contact hole process that forms the second part MCc2, by using binary (2 n The height of each gate electrode 130 is represented by the number of etching operations equal to the number of digits in the binary system, which forms contact holes that contact all gate electrodes 130. In this case, because the predetermined or (optionally) desired value is met in the continuous region in the Z direction, the third type of contact structure MCc can be formed by multiple etching processes even if misalignment occurs while each bend CP is formed by etching once.

[0146] In the following text, reference will be made to Figures 8 to 11 Describes a semiconductor device according to some example embodiments.

[0147] Figure 8 It is shown that... Figure 2B A cross-sectional view of the corresponding semiconductor device 100e, and excluding the dimensions of the contact structures MCa, MCb, and MCc. Figure 8 The semiconductor device 100e in the middle can be connected with Figures 1 to 3D The semiconductor device 100 in it is the same.

[0148] Reference Figure 8 The contact structures MCa, MCb and MCc may include a first type of contact structure MCa, a second type of contact structure MCb and a third type of contact structure MCc, and the upper surface width WT of the first type of contact structure MCa may be the same as the upper surface width WT of the second type of contact structure MCb, and the upper surface width WT of the second type of contact structure MCb may be substantially the same as the upper surface width WT of the third type of contact structure MCc.

[0149] The first type of contact structure MCa, the second type of contact structure MCb, and the third type of contact structure MCc can be formed by different types of etching processes performed in different sequences, and these processes can be performed a different number of times. Even in this case, the upper surface width WT of the first type of contact structure MCa, the second type of contact structure MCb, and the third type of contact structure MCc can be substantially the same as the final structure.

[0150] Therefore, in the high aspect ratio contact (HARC) etching process for forming the first portion MCc1 of the second type contact structure MCb and the third type contact structure MCc, the mask opening width of the first portion MCc1 forming the third type contact structure MCc can be smaller than the mask opening width forming the second type contact structure MCb. The upper surface width WT of the first type contact structure MCa and the third type contact structure MCc, which employ multiple or different etching processes, and the second type contact structure MCb, which employs only the HARC etching process, can be formed to be the same, thereby preventing or reducing possible misalignment with the pins 185 provided on the contact structures MCa, MCb, and MCc.

[0151] Figure 9 It is shown that... Figure 2A A cross-sectional view of the corresponding semiconductor device 100f, and in addition to the third type contact structure MCc, Figure 9 The semiconductor device 100f in the middle can be connected with Figures 1 to 3D The semiconductor device 100 in it is the same.

[0152] Reference Figure 9 The second part MCc2, which is the lowest level of the third type contact structure MCc (i.e., the third type contact structure MCc that contacts the gate electrode 130 of the first stacked structure GS1), may have a length greater than the length of a level of the stacked structure GS.

[0153] Specifically, the second portion MCc2 of the third type contact structure MCc, which is located at a height higher than the lowest level and contacts the gate electrodes 130 of the second stacked structures GS2 to the fourth stacked structures GS4, may have a length smaller than the length of one level of the stacked structure GS (e.g., the maximum length). The third type contact structure MCc, which is configured to contact the gate electrode 130 of the first stacked structure GS1, which is the lowest level, may have a second portion MCc2 connected from the lower end of the first portion MCc1, and the length of the second portion MCc2 may be greater than the entire length of the second stacked structure GS2.

[0154] In other words, the first part MCc1 of the third type contact structure MCc can be set with a length that penetrates the stacked structure GS3 to GS5, and the second part MCc2 can be set as the gate electrode 130 distributed from the upper surface of the second stacked structure GS2, which is the second level, to the first stacked structure GS1 from the bottom.

[0155] As described above, the contact holes of the contact structure MCc, which are formed simultaneously with the channel holes of the channel structure CH, may not be formed in the two lower stacked structures GS1 and GS2, but may only be formed in the upper stacked structures GS3 to GS5. By reducing the number of bends BP, the possibility of physical / electrical short circuits caused by abrupt differences in width can be prevented or reduced.

[0156] Reference Figure 10 Apart from the structure of the series select contact plug MC1 and the upper gate electrode 130U of the series select line, the semiconductor device 100g can be used with Figures 1 to 3D The semiconductor device 100g is the same as that in the semiconductor device 100g. The semiconductor device 100g may have string select contact plugs MC1 and word line contact plugs MC2 with different shapes.

[0157] The upper gate electrode 130U may include a contact area for contacting the string selection contact plug MC1 in the string selection region R3, and may include a stepped structure GP with a stepped shape such that the contact area can be exposed.

[0158] When the three upper gate electrodes 130U1 to 130U3 are assigned as series select lines, the three upper gate electrodes 130U1 to 130U3 may have a stepped structure GP with a stepped shape whose length can increase downwards. Therefore, the stepped dummy step structure GP may also be formed in the extended region R2 on opposite sides, and the step width of the dummy step structure GP in the extended region R2 and the step width of the stepped structure GP in the series select region R3 may be different from each other. For example, the step width of the dummy step structure GP in the extended region R2 may be narrower than the step width of the stepped structure GP in the series select region R3, but some exemplary embodiments are not limited to this. According to the stepped structure GP, the series select contact plug MC1 may be configured to contact each of the exposed contact areas of the series select line.

[0159] The string select contact plug MC1 may only have a conductive layer 177 formed. That is, only the conductive layer 177 may be provided in the form of a plug without a side surface insulating layer, and may be configured to contact the upper surface of the exposed contact area of ​​the upper gate electrode 130U. In this case, a contact blocking layer may be further provided around the conductive layer 177, but some example embodiments are not limited thereto.

[0160] A stepped structure GP with a stepped shape can be formed between the string selection region R3 and the extension region R2, so that the upper gate electrodes 130U1 to 130U3 can be cut, and the second insulating region SS2 does not need to be set separately.

[0161] In the extended region R2, the word line contact plug MC2 can be configured to contact the gate electrodes 130M and 130L respectively (the gate electrodes 130M and 130L are at a height lower than the upper gate electrodes 130U1 to 130U3), and the word line contact plug MC2 can satisfy the shapes of the first type of contact structure MCa, the second type of contact structure MCb, and the third type of contact structure MCc described above. That is, the shape of the word line contact plug MC2 can be consistent with... Figures 2A to 3D The plug conductive layer 175 and the side insulating layer 160 have the same shape.

[0162] Figure 11 The semiconductor device 100h may include Figures 1 to 3D The semiconductor device 100 serves as a first semiconductor structure S1, and the second semiconductor structure S2 can be configured as a peripheral circuit structure on the first semiconductor structure S1. The first semiconductor structure S1 can be stacked in the Z direction perpendicular to the second semiconductor structure S2. Specifically, the first semiconductor structure S1 can be disposed below the second semiconductor structure S2 in the Z direction. In some example embodiments, conversely, the second semiconductor structure S2 can be disposed below the first semiconductor structure S1.

[0163] The first semiconductor structure S1 may further include a bonding structure. Specifically, a first bonding via 195, a first bonding metal layer 198, and a first bonding insulating layer may form a first bonding structure for the first semiconductor structure S1. The first bonding via 195 may be disposed on the cell interconnect 180, and the first bonding metal layer 198 may be connected to the first bonding via 195. The first bonding metal layer 198 may have an upper surface exposed to the upper surface of the first semiconductor structure S1. The first bonding metal layer 198 may be bonded to and connected to a second bonding metal layer 298 of the second semiconductor structure S2. The first bonding via 195 and the first bonding metal layer 198 may include a conductive material (e.g., copper (Cu)). The first bonding insulating layer may form a dielectric-dielectric bond with the second bonding insulating layer of the second semiconductor structure S2.

[0164] The second semiconductor structure S2 may include a substrate 201, a source / drain region 205 and a device isolation layer 210 within the substrate 201, a circuit element 220 disposed on the substrate 201, a peripheral region insulating layer 290, a circuit contact plug 270, a circuit interconnect 280, a second bonding via 295 and a second bonding metal layer 298.

[0165] The substrate 201 may have a lower surface extending in the X and Y directions. An active region may be defined within the substrate 201 by a device isolation layer 210. Source / drain regions 205, including impurities, may be disposed within a portion of the active region. The substrate 201 may include a semiconductor material (e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). The substrate 201 may be a bulk wafer or may be configured as an epitaxial layer.

[0166] Circuit element 220 may include planar transistors. Each of circuit elements 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be formed on both sides of the circuit gate electrode 225 within the substrate 201.

[0167] The peripheral region insulating layer 290 may be configured to cover circuit elements 220 on the lower surface of the substrate 201. The peripheral region insulating layer 290 may include multiple insulating layers formed using different processes. The peripheral region insulating layer 290 may be formed of an insulating material. A portion of the peripheral region insulating layer 290 may be used as a second bonding insulating layer.

[0168] Circuit contact plug 270 and circuit interconnect 280 can form a circuit interconnect structure electrically connected to circuit element 220 and source / drain region 205. Circuit contact plug 270 may have a cylindrical shape, and circuit interconnect 280 may have a line shape. Electrical signals can be applied to circuit element 220 through circuit contact plug 270 and circuit interconnect 280. In areas not shown, circuit contact plug 270 may also be connected to circuit gate electrode 225. Circuit interconnect 280 may be connected to circuit contact plug 270 and may be arranged in multiple layers. Circuit contact plug 270 and circuit interconnect 280 may include conductive materials (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), and each of the components may also include a diffusion barrier. In some example embodiments, the number of layers of circuit contact plug 270 and circuit interconnect 280 may vary.

[0169] A second bonding via 295, a second bonding metal layer 298, and a second bonding insulating layer may be included in the second bonding structure and may be disposed below a lowermost portion of the circuit interconnect 280. The second bonding via 295 may have a cylindrical shape, and the second bonding metal layer 298 may have a pad shape having a circular shape or a relatively short line shape in a plane. The lower surface of the second bonding metal layer 298 may be exposed to the lower surface of the second semiconductor structure S2. The second bonding via 295 and the second bonding metal layer 298 may provide an electrical connection path to the first semiconductor structure S1. In some example embodiments, a portion of the second bonding metal layer 298 may not be connected to the circuit interconnect 280 and may be configured solely for bonding. The second bonding via 295 and the second bonding metal layer 298 may include a conductive material (e.g., copper (Cu)).

[0170] The second bonding insulating layer may be defined from the lower surface of the peripheral region insulating layer 290 to a predetermined or (optionally) desired thickness, but may also be implemented as an insulating layer on the lower surface of the peripheral region insulating layer 290. The second bonding insulating layer may be configured for dielectric-dielectric bonding with the first bonding insulating layer of the first semiconductor structure S1. The second bonding insulating layer may also serve as a diffusion barrier for the second bonding metal layer 298 and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0171] The first semiconductor structure S1 and the second semiconductor structure S2 can be joined together by a bonding between the first bonding metal layer 198 and the second bonding metal layer 298, and by a bonding between the first bonding insulating layer and the second bonding insulating layer. The bonding between the first bonding metal layer 198 and the second bonding metal layer 298 can be, for example, a copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer and the second bonding insulating layer can be, for example, a dielectric-dielectric bonding (such as a SiCN-SiCN bonding). The first semiconductor structure S1 and the second semiconductor structure S2 can be joined together by a hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0172] like Figure 11 As shown, the first semiconductor structure S1 and the second semiconductor structure S2 can be packaged with the first semiconductor structure S1 disposed below the second semiconductor structure S2, or they can be packaged with the second semiconductor structure S2 disposed invertedly below the first semiconductor structure S1.

[0173] Figure 12 and Figures 13A to 13L A method for manufacturing a semiconductor device according to some example embodiments is shown.

[0174] Figure 12This is a diagram illustrating an etching process for forming contact holes in a semiconductor device according to some example embodiments. Figures 13A to 13L This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some example embodiments, thereby showing the relationship with... Figure 2A The corresponding cross-section.

[0175] Figure 12 The diagram illustrates a contact hole forming process for forming contact structures MCa, MCb, and MCc within a process of manufacturing a semiconductor device according to some example embodiments.

[0176] exist Figure 12 In the diagram, each column can represent the number of stages of the molded structure replaced by the stacked structure GS, each row can represent the etching process, and each diagram can represent the shape of the contact hole for each stage that is subjected to the corresponding etching process.

[0177] like Figures 1 to 3D As described above, the contact structures MCa, MCb, and MCc of the semiconductor device 100 can have different lengths depending on the height of the gate electrode 130 that contacts each other. To form contact structures MCa, MCb, and MCc with different lengths, contact holes with corresponding depths can be formed in the regions corresponding to the contact structures MCa, MCb, and MCc, respectively. The contact holes can be processed according to their depths. Figure 12 The corresponding etching process shown in the etching process diagram.

[0178] Etching processes used for contact holes can be classified into HARC etching process E1 and contact hole partial etching process E2.

[0179] Specifically, when forming a stacked structure of five levels GS1 to GS5, in each of the corresponding molding structures MS1 to MS5, if the contact structures MCb and MCc penetrate all molding structures MS1 to MS5 within each level of the molding structures MS1 to MS5, when forming the channel hole of the channel structure CH, the first part P1 of the contact hole penetrating all molding structures MS1 to MS5 can be formed by simultaneously performing the HARC etching process.

[0180] For the first portion P1 of the contact hole formed by the HARC etching process E1, after the first molding structure MS1 is formed, a first HARC etching process that penetrates the first molding structure MS1 is performed, and when a channel hole corresponding to the first channel portion CH1 of the channel structure CH is formed, the first portion P1 of the contact hole may not be formed.

[0181] After the second molding structure MS2 is formed during the HARC etching process E1, a second HARC etching process that penetrates the second molding structure MS2 can be performed, and when a channel hole corresponding to the second channel portion CH2 of the channel structure CH is formed, the first portion P1 of the contact hole can also be formed together.

[0182] When performing each repeated HARC etching process E1 for each of the molded structures MS2 to MS5, the first portion P1 of the contact hole corresponding to the fifth molded structure MS5 can be formed.

[0183] When the contact structures MCb and MCc penetrate the entire stacked structure GS through repeated HARC etching process E1, a first portion P1 of the contact hole penetrating the stacked structure GS can be formed, and multiple HARC etching processes can be applied according to the length of the contact structures MCb and MCc, so that a bend BP can be formed between the first portions P1 of multiple contact holes.

[0184] In the subsequent process, a contact hole etching process E2 can be performed on the third type contact structure MCc, which has a length exceeding one level of the stacked structure GS, and the first type contact structure MCa, which contacts the gate electrode 130 of the fifth stacked structure GS5.

[0185] When each gate electrode 130 is represented in binary, the contact hole etching process E2 can form contact holes of varying depths with the full height of the gate electrode 130 exposed by performing additional etching the same number of times as the binary digits.

[0186] exist Figure 12 In the stacked structure GS, the gate electrode 130 can be etched six times to form contact holes that expose all of the gate electrode 130.

[0187] Specifically, in the first etching step E21, etching of the gate electrode 130 penetrating one layer can be performed; in the second etching step E22, etching of the gate electrode 130 penetrating two layers simultaneously can be performed; in the third etching step E23, etching of the gate electrode 130 penetrating four layers simultaneously can be performed; in the fourth etching step E24, etching of the gate electrode 130 penetrating eight layers simultaneously can be performed; in the fifth etching step E25, etching of the gate electrode 130 penetrating 16 layers simultaneously can be performed; and in the sixth etching step E26, etching of the gate electrode 130 penetrating 32 layers simultaneously can be performed.

[0188] A stacked structure GS can be configured with 64 gate electrodes 130, and contact holes exposing the gate electrodes 130 can be formed in the stacked structure GS through 6 etching processes.

[0189] For example, opening the contact hole of the 48th gate electrode 130 from the top of the stacked structure GS of each level may require penetrating 47 (32+8+4+2+1) layers of gate electrode 130, which can be formed by applying an etching process other than the fifth etching process that penetrates 16 layers of gate electrode 130, one of the six etching processes.

[0190] In some example embodiments, a stage may include eight layers of gate electrodes 130, such that the etching process can be partially performed three times.

[0191] Therefore, the contact structures MCb and MCc penetrating at least one stage of the stacked structures GS2 to GS5 can ensure depth by forming the first portion P1 of the contact hole simultaneously with the formation of the channel hole of the channel structure CH via HARC etching process E1, thereby reducing the number of etching processes and / or etching depth during the contact hole partial etching process E2, and / or ensuring device reliability. The second portion P2 of the contact hole can be formed during the first portion etching E21 to the sixth portion etching E26.

[0192] Specifically, refer to Figure 13A The sacrificial insulating layer 118 and the interlayer insulating layer 120 can be alternately stacked on the substrate SUB, and the sacrificial insulating layer 118 and the interlayer insulating layer 120 can be formed up to the uppermost interlayer insulating layer 121. A vertical sacrificial structure 116 can be formed that penetrates the molded structures MS1 to MS5.

[0193] The substrate SUB can be removed by subsequent processes, and the substrate SUB can be a semiconductor substrate (such as a silicon (Si) wafer). First, a first molding structure MS1, consisting of molding structures MS1 to MS5, can be formed, and a HARC etch E1 can be performed to penetrate the first molding structure MS1. After forming a portion of the vertical sacrificial structure 116, a second molding structure MS2 can be formed, and a HARC etch E1 can be performed to penetrate the second molding structure MS2, forming a portion of the vertical sacrificial structure 116 and a portion of the contact sacrificial structure 117. Third molding structures MS3 to MS5, a portion of the vertical sacrificial structure 116, and a portion of the contact sacrificial structure 117 can be formed in the same manner as described above.

[0194] Gate electrode 130 can be used in subsequent processes (see...) Figure 2AThe sacrificial insulating layer 118 is replaced. The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material that has etch selectivity relative to the interlayer insulating layer 120 under specific etch conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some example embodiments, the thickness of the interlayer insulating layers 120 may be different, and the uppermost interlayer insulating layer 121 may have a greater thickness than the other interlayer insulating layers 120. The thickness and number of films included in the interlayer insulating layers 120 and the sacrificial insulating layer 118 may differ from the examples shown.

[0195] Vertical sacrificial structure 116 can be formed in conjunction with Figure 2A The vertical sacrificial structure 116 is located at the corresponding positions of the channel structure CH and the support structure DH. The vertical sacrificial structure 116 may be formed, for example, having the same dimensions as the channel structure CH and the support structure DH. The vertical sacrificial structure 116 may include, for example, carbon (C), but some example embodiments are not limited thereto.

[0196] Contact sacrificial structure 117 can be formed in conjunction with Figure 2A The contact sacrificial structure 117 is located at the position corresponding to the first portion MCc1 of the second type contact structure MCb and the third type contact structure MCc in the contact structure. The upper surface of the contact sacrificial structure 117 may be formed to have an initial width Wa, and the contact sacrificial structure 117 may be formed to have, for example, the same dimensions as the second type contact structure MCb. The contact sacrificial structure 117 may include, for example, carbon (C), but some example embodiments are not limited thereto.

[0197] Reference Figure 13B A mask layer ML can be formed on the uppermost interlayer insulating layer 121, and a first opening OP1 can be formed by passing through the mask layer ML.

[0198] The mask layer ML may include a photoresist layer. It can be used in conjunction with... Figure 2A The first opening OP1 is formed in a circular, elliptical, or similar shape in the regions corresponding to the contact structures MCa, MCb, and MCc. This allows the mask layer ML to be patterned, and thus the uppermost interlayer insulating layer 121 can be removed, thereby forming the first opening OP1.

[0199] In this configuration, when the contact sacrificial structure 117 of the first opening OP1 is opened, the first opening OP1 can be extended by removing all of the contact sacrificial structure 117. Therefore, the upper surface of each of the molded structures MS1 to MS5 can be exposed in the area where the contact sacrificial structure 117 is removed through the first opening OP1.

[0200] Reference Figure 13C The second opening OP2 can be formed by etching the molded structures MS1 to MS5 to penetrate an additional layer of the sacrificial insulating layer 118 in the portion of the first opening OP1.

[0201] The second opening OP2 may extend from the first opening OP1 to a first depth h1. For example, contact structures MCa and MCc of some gate electrodes 130 in each stage of the through-molded structures MS1 to MS5 may be formed by etching a pair of sacrificial insulating layers 118 and interlayer insulating layers 120 below the first opening OP1 to a first depth h1.

[0202] Reference Figure 13D The third opening can be formed by etching the molded structures MS1 to MS5OP3 to penetrate two pairs of sacrificial insulating layers 118 and interlayer insulating layers 120 in a portion of the first opening OP1 or the second opening OP2.

[0203] The third opening OP3 may extend to a second depth h2 from either the first opening OP1 or the second opening OP2. In this case, when the third opening OP3 is formed below the second opening OP2, the via can have a downwardly increasing width through a repeatable identical etching process, and a reduced portion with a decreasing width at the lowest level can be formed.

[0204] Reference Figure 13E The fourth opening OP4 is formed by etching the molded structures MS1 to MS5 to penetrate four pairs of sacrificial insulating layers 118 and interlayer insulating layers 120 in a portion of the first opening OP1 to the third opening OP3.

[0205] The fourth opening OP4 can extend to a third depth h3 from the first opening OP1 to the third opening OP3. In this case, when the fourth opening OP4 is formed below the second opening OP2 or the third opening OP3, the through-hole can have a downwardly increasing width through a repeatable identical etching process, and a reduced width portion with a decreasing width at the lowest level can be formed, such that respectively forming... Figure 2A Contact holes of the shapes of contact structures MCa, MCb, and MCc can be formed.

[0206] Reference Figure 13F A preliminary contact insulation layer 160P and a contact sacrificial layer 161 can be formed on the first opening OP1 to the fourth opening OP4.

[0207] The initial contact insulation layer 160P can be conformally formed to cover the sidewalls and bottom surface of the first opening OP1 to the fourth opening OP4. For example, atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes can be used to form the initial contact insulation layer 160P.

[0208] The contact sacrificial layer 161 may be formed to fill the first opening OP1 to the fourth opening OP4 on the initial contact insulation layer 160P. The contact sacrificial layer 161 may include a material different from the material of the initial contact insulation layer 160P, and may include, for example, carbon (C).

[0209] Reference Figure 13G By removing a portion of the vertical sacrificial structure 116, a channel structure CH can be formed.

[0210] A mask layer can be formed to expose only the region corresponding to the channel structure CH in the memory region R1, and a channel via can be formed by removing the exposed vertical sacrificial structure 116. At least a portion of the channel dielectric layer 145, the channel layer 140, the channel buried insulating layer 147, and the channel pad 149 can be deposited sequentially within the channel via to form the channel structure CH.

[0211] The channel dielectric layer 145 can be formed to have a uniform thickness using either an ALD or CVD process. In this process, all or a portion of the channel dielectric layer 145 can be formed, and a portion extending vertically along the channel structure CH to the conductive layer 101 can also be formed. The channel layer 140 can be formed within a channel via on the channel dielectric layer 145. The channel buried insulating layer 147 can be formed to fill the channel via and can be an insulating material. The channel pad 149 can be formed of a conductive material (e.g., polysilicon).

[0212] In addition, a portion of the vertical sacrificial structure 116 can be removed, and a supporting structure DH can be formed.

[0213] A mask layer can be formed to expose the regions corresponding to the support structure DH in the string selection region R3 and the extension region R2, and a dummy via can be formed by removing the exposed vertical sacrificial structure 116. A process can be performed to expand the dummy via by removing a portion of the molded structure around it. The expanded dummy via can be filled with an insulating material to form the support structure DH.

[0214] Reference Figure 13H The sacrificial insulating layer 118 can be removed and the gate electrode 130 can be formed.

[0215] Can be formed for use with Figure 1 and Figure 2D The isolation opening corresponds to the region opening of the isolation region MS. The isolation opening can be formed by forming multiple vertical holes in the region where the isolation region MS is formed, and can also be formed by expanding the vertical holes via a cleaning process and connecting the vertical holes to adjacent vertical holes. When the isolation opening is formed by expanding multiple vertical holes, the side surface of the isolation opening may continuously include a convex curved surface, but some example embodiments are not limited to this.

[0216] The sacrificial insulating layer 118 exposed through the isolation opening can be removed. The sacrificial insulating layer 118 can be selectively removed relative to the interlayer insulating layer 120, the channel structure CH, the support structure DH, and the initial contact insulating layer 160P, for example, using wet etching.

[0217] The gate electrode 130 can be formed by depositing a conductive material on the region where the sacrificial insulating layer 118 has been removed. The conductive material may include a metal, polysilicon, or a metal silicide. A diffusion barrier 131 (see [link to documentation]) may be formed in the gate electrode 130. Figure 3A The gate electrode 130 can be formed by depositing conductive material. In some example embodiments, a portion of the channel dielectric layer 145 may be formed prior to the formation of the gate electrode 130. Therefore, a stacked structure GS comprising a first stacked structure GS1 to a fifth stacked structure GS5 can be formed. After the gate electrode 130 is formed, insulating material may be deposited within the isolation opening to form a structure such as... Figure 1 The isolation region MS extends in the X direction as shown.

[0218] Reference Figure 13I This can form a first insulating region SS1 and a second insulating region SS2 that penetrate the upper gate electrodes 130U1 to 130U3.

[0219] like Figure 1 as well as Figure 2A and Figure 2B As shown, trenches can be formed for removing the upper gate electrodes 130U1 to 130U3 and the interlayer insulating layer 120 in the regions corresponding to the first insulating region SS1 and the second insulating region SS2.

[0220] Between two adjacent isolation regions MS, as a horizontal trench corresponding to the first insulating region SS1, the first trench can penetrate from the upper part of the uppermost interlayer insulating layer 121 through the third upper gate electrode 130U1 to the first upper gate electrode 130U3, extending in the X direction within the memory region R1 and the string select region R3, and the upper part of the fifth stack structure GS5 can be selectively cut. The first trench can be formed to extend and cut a portion of the channel structure CH in the memory region R1.

[0221] Furthermore, a second trench may be formed in the region corresponding to the second insulating region SS2. The second trench may extend in the Y direction to isolate the extended region R2 from the string select region R3, and may selectively cut the upper portion of the fifth stack structure GS5 to penetrate from the uppermost interlayer insulating layer 121 through the first upper gate electrode 130U1 to the third upper gate electrode 130U3. Therefore, the first and second trenches may not extend to the memory gate electrode 130M corresponding to the word line. Insulating material may be deposited in the first and second trenches to form the first insulating region SS1 and the second insulating region SS2.

[0222] like Figure 13J As shown, contact structures MCa, MCb, and MCc can be formed. Specifically, the contact sacrificial layer 161 can be selectively removed relative to the initial contact insulation layer 160P, and a portion of the exposed initial contact insulation layer 160P can be removed to form the contact insulation layer 160.

[0223] In other words, after removing the contact sacrificial layer 161, the exposed preliminary contact insulating layer 160P can be partially removed from the bottom surface. When the preliminary contact insulating layer 160P is removed, the exposed gate electrode 130 can also be partially recessed from the upper surface. Therefore, a contact insulating layer 160 can be formed only on the sidewalls of the first opening OP1 to the fourth opening OP4. Contact plugs MC1 and MC2 can be formed by depositing conductive material within the first opening OP1 to the fourth opening OP4. Contact plugs MC1 and MC2 can be physically connected to the downwardly distributed gate electrode 130, respectively.

[0224] Reference Figure 13K The spike head 185 and the cell interconnect line 180 can be formed on the stacked structure GS1 to GS5.

[0225] After forming the unit area insulation layer 150, the nail head 185 and the unit interconnect line 180 can be formed.

[0226] The spike head 185 can be formed by forming a penetrating cell region insulating layer 150 to expose the channel structure CH and the spike head holes of the contact plugs MC1 and MC2, and filling the spike head holes with a conductive material. Cell interconnects 180 can be formed on the spike head 185. An upper insulating layer 190 can also be formed on the cell interconnects 180, and a layer for connecting with... Figure 11 The first bonding structure is bonded to the second semiconductor structure S2 in the process.

[0227] Reference Figure 13L It can remove the substrate SUB and expose the channel layer 140.

[0228] By removing a portion of the substrate SUB and the exposed channel dielectric layer 145 (see...) Figure 3A This allows the channel layer 140 to be exposed.

[0229] Subsequently, refer to Figure 2A A conductive layer 101 can be formed that is connected to the channel layer 140, and it can be manufactured Figure 2A The semiconductor device 100 is described. In some example embodiments, the conductive layer 101 may be formed as a conformal layer along the upper layer of the channel structure CH and the upper layer of the support structure DH.

[0230] Figure 14This is a diagram illustrating a data storage system including a semiconductor device according to some example embodiments.

[0231] Reference Figure 14 The data storage system 1000 may include a semiconductor device (or semiconductor memory device) 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a memory device including one or more semiconductor devices 1100 or as an electronic device including a memory device. For example, the data storage system 1000 may be implemented as a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0232] Semiconductor device 1100 can be implemented as a non-volatile memory device (such as, in reference to...) Figures 1 to 12 (Taking the NAND flash memory device described in the foregoing example embodiments as an example). Semiconductor device 1100 may include a first structure (or first semiconductor structure) 1100F and a second structure (or second semiconductor structure) 1100S on the first structure 1100F. In some example embodiments, the first structure 1100F may be disposed on the side of the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1, a second gate upper line UL2, a first gate lower line LL1, a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL. In some embodiments, the second structure 1100S may be related to a reference... Figures 1 to 2D The semiconductor device 100 described is the same.

[0233] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In some example embodiments, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0234] In some example embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be configured as gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be configured as gate electrode of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be configured as gate electrodes of upper transistors UT1 and UT2, respectively.

[0235] In some example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 can be used for an erase operation to erase data stored in the memory cell transistor MCT by using the gate-induced drain leakage current (GIDL) phenomenon.

[0236] The common-source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, the first upper gate line UL1, and the second upper gate line UL2 are electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0237] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0238] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0239] Processor 1210 controls the overall operation of data storage system 1000, including controller 1200. Processor 1210 operates according to predetermined or (optionally) desired firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include controller interface 1221 for handling communication with semiconductor device 1100. Through controller interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be sent. Host interface 1230 provides communication functionality between data storage system 1000 and an external host. When receiving control commands from an external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0240] Figure 15 This is a perspective view illustrating a data storage system including a semiconductor device according to some example embodiments.

[0241] Reference Figure 15 In some example embodiments, the data storage system 2000 may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0242] The motherboard 2001 may include a connector 2006 comprising a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some example embodiments, the data storage system 2000 may communicate with the external host via one of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI Fast), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In some example embodiments, the data storage system 2000 may be operated by power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0243] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0244] DRAM 2004 can be configured as a buffer memory to mitigate speed differences between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can operate as a cache memory and can provide space for temporary data storage during control operations on the semiconductor package 2003. When the data storage system 2000 may include DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003, controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0245] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0246] The package substrate 2100 may be configured as a printed circuit board including package pads 2130. Each of the semiconductor chips 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to... Figure 14 The input / output pad 1101 is included. Each of the semiconductor chips 2200 may include the input / output pads as shown above. Figures 1 to 11 The semiconductor device described.

[0247] In some example embodiments, the connection structure 2400 may be configured to electrically connect the input / output pad 2210 to a bonding wire of the package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chip 2200 may be electrically connected to each other via a bonding wire method and may be electrically connected to the package pad 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chip 2200 may be electrically connected to each other via a connection structure 2400 that includes a through-electrode (TSV) instead of a bonding wire method.

[0248] In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a different intermediate substrate than the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other via interconnects formed on the intermediate substrate.

[0249] Any or all of the elements described with reference to the accompanying drawings may communicate with any or all other elements described with reference to the respective drawings. For example, any element may communicate with any or all other elements in a one-way and / or two-way and / or broadcast manner, such as serial and / or parallel, via a bus (such as a wireless bus and / or a wired bus) (not shown), to transmit and / or exchange and / or receive information (such as, but not limited to, data and / or commands). The information may be in various encoded formats (such as analog and / or digital formats).

[0250] Any of the elements and / or functional blocks disclosed above may include processing circuitry systems (such as hardware including logic circuitry; hardware / software combinations (such as a processor executing software); or combinations thereof) or be implemented as processing circuitry systems (such as hardware including logic circuitry; hardware / software combinations (such as a processor executing software); or combinations thereof). For example, processing circuitry systems may more specifically include, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc. Processing circuitry systems may include electronic components (such as at least one of transistors, resistors, capacitors, etc.). Processing circuitry systems may include electronic components (such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.).

[0251] According to some of the foregoing example embodiments, a contact structure that contacts the contact region of the gate electrode can be formed by a process for forming the contact structure, without the need for a step process for forming the contact region of the gate electrode in a step shape. In this case, in a semiconductor device having a stacked structure with multiple levels, a contact structure having a bend at the same height as the bend of the channel structure corresponding to each level can be formed. That is, in the process for forming the channel hole of the channel structure, the contact hole of the contact structure can be formed simultaneously, so that the depth of the contact hole etched in one step can be (e.g., significantly) reduced. Therefore, the possibility of defects (such as short circuits) caused by the expansion of the contact hole due to the formation of a relatively deep contact hole can be prevented or reduced.

[0252] Therefore, with the simplification of the process and the specification of the contact hole locations, a semiconductor device with improved reliability and a data storage system including the semiconductor device can be provided.

[0253] While some exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Conductive layer; Multiple stacked structures, each of the multiple stacked structures including multiple gate electrodes stacked sequentially in a first direction perpendicular to the upper surface of the conductive layer, the multiple stacked structures being stacked sequentially in the first direction in a first region and a second region adjacent to the first region; The channel structure includes a plurality of channel portions that penetrate the plurality of stacked structures respectively, and the plurality of channel portions are connected to each other in a first region and in a first direction; A plurality of first-type contact structures penetrate at least one of the gate electrodes of the uppermost stacked structure among the plurality of stacked structures, the plurality of first-type contact structures extending to different lengths in the second region and respectively electrically connected to the gate electrodes of the uppermost stacked structure other than the uppermost gate electrode of the uppermost stacked structure; Multiple second-type contact structures completely penetrate at least one of the multiple stacked structures from the top of the topmost stacked structure, and the multiple second-type contact structures extend to different lengths in the second region and are respectively electrically connected to the topmost gate electrode of each of the stacked structures below the topmost stacked structure; as well as Multiple third-type contact structures, each third-type contact structure including a first portion and a second portion, wherein the first portion completely penetrates at least one of the multiple stacked structures from the top of the uppermost stacked structure, and the second portion extends from the bottom of the first portion in a second region and is electrically connected to the assigned gate electrode. Wherein, the boundary surface between the first and second portions of each of the plurality of third-type contact structures is at the same height as the boundary surface between the plurality of channel portions of the channel structure.

2. The semiconductor device according to claim 1, wherein, Each of the plurality of channel portions of the channel structure includes an upper surface, a lower surface having a width smaller than the width of the upper surface, and an inclined side surface between the upper and lower surfaces. The channel structure includes a bend such that on the boundary surface between the plurality of channel portions, the width of the lower surface of the upper channel portion is smaller than the width of the upper surface of the lower channel portion.

3. The semiconductor device according to claim 1, wherein, In each of the plurality of third-type contact structures, the first portion includes at least one sub-component that completely penetrates one of the plurality of stacked structures.

4. The semiconductor device according to claim 3, wherein, Each of the at least one sub-component includes an upper surface, a lower surface having a width smaller than that of the upper surface, and an inclined side surface between the upper and lower surfaces. The upper surface of the second part has the same width as the lower surface of the lowest sub-component of the at least one sub-component of the first part.

5. The semiconductor device according to claim 1, wherein, The first portion of each of the plurality of third-type contact structures has the same or corresponding shape as at least one of the plurality of second-type contact structures.

6. The semiconductor device according to claim 1, wherein, Each of the plurality of third-type contact structures is symmetrical about the center line of the width of the upper surface of each of the plurality of third-type contact structures.

7. The semiconductor device according to claim 1, wherein, The side surface of the second portion of each of the plurality of third-type contact structures includes at least one inflection point, such that the slope of the side surface changes.

8. The semiconductor device according to claim 1, wherein, Each of the plurality of first-type contact structures includes a region having a width that increases from the upper to the lower portion of each of the plurality of first-type contact structures, and The second portion of each of the plurality of third-type contact structures includes a region having a width that increases from the upper to the lower part of the second portion.

9. The semiconductor device according to claim 1, wherein, Each of the plurality of first-type contact structures includes a region that increases downward in width and a region that decreases downward in width, and The second part of each of the plurality of third-type contact structures includes a region that increases downward in width and a region that decreases downward in width.

10. The semiconductor device according to claim 1, wherein, Each of the plurality of first-type contact structures includes a region with a constant width, and The second part of each of the plurality of third-type contact structures includes a region with a constant width.

11. The semiconductor device according to claim 1, wherein, The second portion of each of the plurality of third-type contact structures is asymmetrical about the center line of the width of the upper surface of each of the plurality of third-type contact structures.

12. The semiconductor device according to claim 1, wherein, Each of the plurality of first-type contact structures, the plurality of second-type contact structures, and the plurality of third-type contact structures includes: A contact plug, including a plug conductive layer and contact blocking layers on the side and lower surfaces of the plug conductive layer; and Side insulation layer, surrounding the side surface of the contact plug. The lower surface of the contact barrier layer is in contact with the upper surface of the assigned gate electrode.

13. The semiconductor device according to claim 1, further comprising: Interlayer insulating layers are alternately stacked with the plurality of gate electrodes; The uppermost interlayer insulating layer is located on the uppermost gate electrode of the uppermost stacked structure. as well as The fourth type of contact structure penetrates the uppermost interlayer insulation layer and contacts the uppermost gate electrode of the uppermost stacked structure.

14. A semiconductor device, comprising: Conductive layer; Multiple stacked structures, each of the multiple stacked structures including gate electrodes stacked sequentially in a first direction perpendicular to the upper surface of the conductive layer, the multiple stacked structures being stacked sequentially in the first direction in a first region and a second region adjacent to the first region; A channel structure that penetrates the plurality of stacked structures in a first region and extends in a first direction; as well as Each contact structure includes a first portion and a second portion. The first portion extends completely through at least one of the plurality of stacked structures from the top of the uppermost stacked structure, and the second portion extends from the bottom of the first portion and contacts the assigned gate electrode. The first part includes at least one sub-component that completely penetrates one of the plurality of stacked structures. The width of the upper surface of each of the at least one sub-component is greater than the width of the lower surface of each of the at least one sub-component, and each of the at least one sub-component includes a continuously inclined side surface between the upper and lower surfaces of each of the at least one sub-component. The width of the lower surface of the first part is the same as the width of the upper surface of the second part.

15. The semiconductor device according to claim 14, wherein, In response to the first part comprising at least two sub-components, the first part including a bend such that at the boundary surface between the at least two sub-components, the width of the upper surface of the lower sub-component is greater than the width of the lower surface of the upper sub-component.

16. The semiconductor device according to claim 14, wherein, Each of the at least one sub-component in the first part has a width that decreases toward the conductive layer, and The second part includes a region with a width that increases toward the conductive layer.

17. The semiconductor device according to claim 14, wherein, The second part includes a reduction portion, in which the width of the second part decreases toward the conductive layer in the portion near the lower surface of the second part.

18. The semiconductor device according to claim 14, wherein, The contact structure includes a first part with a different length and a second part with the same length.

19. A data storage system, comprising: A semiconductor memory device includes a first semiconductor structure containing circuit elements, a second semiconductor structure on one surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit elements. as well as The controller is electrically connected to the semiconductor memory device via input / output pads and controls the semiconductor memory device. The second semiconductor structure includes, Conductive layer; Multiple stacked structures, each of the multiple stacked structures including gate electrodes stacked sequentially in a first direction perpendicular to the upper surface of the conductive layer, the multiple stacked structures being stacked sequentially in the first direction in a first region and a second region adjacent to the first region; A channel structure, penetrating the plurality of stacked structures in a first region and extending in a first direction; and The contact structure includes a first portion and a second portion, wherein the first portion completely penetrates at least one of the plurality of stacked structures from the top of the uppermost stacked structure, and the second portion extends from the bottom of the first portion in a second region and contacts the assigned gate electrode. The first part includes at least one sub-component that completely penetrates one of the plurality of stacked structures. The width of the upper surface of each of the at least one sub-component is greater than the width of the lower surface of each of the at least one sub-component, and each of the at least one sub-component includes a continuously inclined side surface between the upper and lower surfaces of each of the at least one sub-component. The width of the lower surface of the first part is the same as the width of the upper surface of the second part.

20. The data storage system according to claim 19, wherein, The channel structure includes multiple channel portions that penetrate the plurality of stacked structures, and the plurality of channel portions are connected to each other in a first direction. The boundary surface between the first and second parts of the contact structure is at the same height as one of the boundary surfaces between the plurality of channel portions of the channel structure.

Images