Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: taking a first mask layer as a mask, carrying out the etching of a gate material layer, forming a gate structure pair, enabling one side, in a first direction, of the gate structure pair and a substrate to form a first opening, and enabling the gate structure pair to comprise two gate structures which are sequentially arranged in the first direction, a second opening is formed between the two gate structures of one gate structure pair; forming a filling layer in the first opening and the second opening; the filling layer is etched with the second mask layer as a mask to form a word line located on the substrate, the word line comprises a first part, and the first part is located between the two gate structures of the gate structure pair. The first mask layer defines the position and the size of the gate structure, so that the process precision is improved, and a process window is expanded; in addition, the process complexity of forming the floating gate and the control gate located on the floating gate is reduced, and the processing time is shortened; in addition, the first mask layer defines the positions and the sizes of the first opening and the second opening, so that the position and the size of the first part of the word line are defined, and the technological process is simplified.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As an important branch of non-volatile flash memory technology, NOR memory holds a unique position and has a unique development history in the semiconductor memory field. NOR memory uses floating-gate transistor technology to store data. Data is stored in the form of electric charge in the floating gate. The state (0 or 1) of the memory cell is determined by controlling the electric field between the floating gate and the control gate. When writing data, charge is injected or removed from the floating gate using methods such as hot electron injection; when reading data, the data state is determined by detecting changes in the current or voltage of the memory cell. This storage mechanism gives NOR memory byte-level access capabilities, enabling fast random access to data, meeting the stringent read speed requirements of applications such as code storage and firmware updates.

[0003] However, current NORD memory still has shortcomings. Summary of the Invention

[0004] The problem addressed by this invention is how to expand the process window and reduce process complexity while continuously shrinking the structure of NORD memory cells.

[0005] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a substrate, the substrate including a base and a gate material layer located on the base; forming a first mask layer on the gate material layer; using the first mask layer as a mask, etching the gate material layer to form a gate structure pair, wherein one side of the gate structure pair along a first direction forms a first opening with the substrate, the gate structure pair including two gate structures arranged sequentially along the first direction, a second opening being formed between the two gate structures of the gate structure pair, the gate structure including a floating gate and a control gate located on the floating gate, the first direction being parallel to the surface of the substrate; forming a filling layer within the first opening and the second opening; forming a second mask layer on the gate structure pair and the filling layer; using the second mask layer as a mask, etching the filling layer to form a word line located on the substrate, the word line including a first portion located between the two gate structures of the gate structure pair.

[0006] Optionally, the substrate includes an active region and an isolation region, both of which extend along a first direction, and the active region and the isolation region are alternately distributed along a second direction, which is parallel to the surface of the substrate and perpendicular to the first direction.

[0007] Optionally, the step of etching the gate material layer using the first mask layer as a mask to form a gate structure pair includes: using the first mask layer as a mask to etch a portion of the gate material layer to form a control gate pair located on the active region and a third pre-fabricated opening located within the gate material layer of the isolation region, the third pre-fabricated opening exposing a portion of the gate material layer of the isolation region, the control gate pair forming a first pre-fabricated opening with the gate material layer along one side of the first direction, a control gate pair including two control gates arranged sequentially along the first direction, a second pre-fabricated opening formed between the two control gates of a control gate pair; forming a protective sidewall on the sidewall of the control gate in the active region; and using the first mask layer as a mask to continue etching the remaining thickness of the gate material layer to form a floating gate located on the active region.

[0008] Optionally, during the process of etching the filling layer using the second mask layer as a mask to form word lines on the substrate, the method further includes: thinning the mask material layer on the gate structure of at least a portion of the isolation region.

[0009] Optionally, the substrate includes a functional region and a logic region, the functional region including the active region and the isolation region; the method of forming the semiconductor structure further includes: after forming a filling layer in the first opening and the second opening, before etching the filling layer with the second mask layer as a mask to form a word line on the substrate, forming a pseudo gate in the logic region.

[0010] Optionally, it further includes: after forming a filling layer in the first opening and the second opening, and before forming a pseudo-gate in the logic region, performing ion implantation on the filling layer; and performing oxidation repair on the filling layer.

[0011] Optionally, during the process of etching the gate material layer using the first mask layer as a mask to form the gate structure pair, the process further includes: forming a third opening, wherein the third opening exposes a portion of the gate material layer of the isolation region, the third opening extends along the first direction, and the third opening connects the first opening and the second opening adjacent to each other along the first direction.

[0012] Optionally, one of the second openings has two third openings connected thereto, the two third openings being arranged along the first direction and connected to each other.

[0013] Optionally, the first opening has two third openings connected to it, the two third openings are arranged along the second direction, and the positions of the two third openings correspond to the two ends of the first opening along the second direction.

[0014] Optionally, the first opening has two third openings communicating with it, the two third openings being located on different sides of the first opening along the first direction.

[0015] Optionally, the process of forming a filling layer in the first opening and the second opening further includes forming a filling layer in the third opening.

[0016] Optionally, during the process of etching the filling layer to form a word line on the substrate using the second mask layer as a mask, the process further includes: etching the filling layer within the third opening to form a second part of the word line, wherein one end of the second part along the first direction is connected to the first part.

[0017] Optionally, it also includes forming a word line lead-out structure on the second part.

[0018] Optionally, the step of forming a word line lead-out structure on the second part includes: removing the oxide layer located on the word line; forming a metal silicide layer on at least the second part; and forming a word line lead-out structure on the second part.

[0019] Optionally, during the process of forming the word line lead-out structure on the second part, the method further includes: forming a bit line lead-out structure on the substrate on one side of the gate structure; and forming a control gate lead-out structure on the control gate of the isolation region.

[0020] Accordingly, the present invention provides a semiconductor structure, comprising: a substrate; a device structure layer, the device structure layer comprising: a pair of gate structures located on the substrate, the pair of gate structures being arranged sequentially along a first direction, each pair of gate structures comprising two gate structures arranged sequentially along the first direction, each gate structure comprising a floating gate and a control gate located on the floating gate, the gate structure extending along a second direction, the first direction intersecting the second direction; a word line located on the substrate, the word line comprising a first portion and a second portion, the first portion extending along the second direction, the second portion extending along the first direction, one end of the second portion along the first direction being connected to the first portion, the first portion being located between the two gate structures of a pair of gate structures; and a word line lead-out structure located on the second portion of the word line in the device structure layer.

[0021] Optionally, the device structure layer includes: a bit line region extending along the second direction, and a pair of gate structures located on the same side of the bit line region along the first direction.

[0022] Optionally, the second part extends from the other end along the first direction to the corresponding position of the bit line region.

[0023] Optionally, the bit line region of the device structure layer includes a bit line lead-out structure.

[0024] Optionally, one first part has two second parts connected to it.

[0025] Optionally, the two second parts are located on opposite sides of the first part along the first direction, and the positions of the two second parts correspond to each other.

[0026] Optionally, the word line lead-out structure is located on at least one of the two second parts.

[0027] Optionally, two adjacent bit line regions of the device structure layer are arranged along a first direction, and a gate structure pair is located between the two adjacent bit line regions.

[0028] Optionally, two adjacent first portions along the first direction, a second portion connected to one first portion, and a second portion connected to another first portion are located on opposite sides of the bit line region along the second direction.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the semiconductor structure formation method of the present invention, the first mask layer defines the position and size of the gate structure. The gate material layer is etched using the first mask layer as a mask to form the gate structure, which improves process accuracy and expands the process window. Furthermore, using the first mask layer as a mask to etch the gate material layer to form the floating gate and the control gate located on the floating gate reduces the process complexity of forming the floating gate and the control gate located on the floating gate, and shortens the processing time. In addition, the first mask layer also defines the position and size of the first opening and the second opening, thereby defining the position and size of the first part of the word line, simplifying the process flow.

[0031] In an optional embodiment of the present invention, a word line lead-out structure is further included: forming a word line lead-out structure on the second part. One end of the second part along the first direction is connected to the first part. The dimension of the word line at the location where the first part and the second part are connected in the first direction is equal to the sum of the dimensions of the first part and the second part in the first direction. The dimension of the word line at the location where the first part and the second part are connected in the first direction is relatively large. When it is necessary to form a word line lead-out structure on the word line, forming the word line lead-out structure at the location where the second part and the first part are connected can increase the process window of the word line lead-out structure, improve process stability, increase product yield, and ensure the reliability of semiconductor devices. Attached Figure Description

[0032] Figure 1 It is a schematic diagram of a semiconductor structure;

[0033] Figure 2 yes Figure 1 A partial schematic diagram of the central region;

[0034] Figure 3 Is it a semiconductor structure in Figure 2 Schematic diagram of the cross-sectional structure at positions A1A2, B1B2, C1C2, D1D2, and E1E2;

[0035] Figure 4 , Figures 7 to 10 ,as well as Figures 13 to 15 This is a cross-sectional structural schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0037] Figure 6 yes Figure 5 A partial schematic diagram of the central region;

[0038] Figure 11 This is another schematic diagram of the semiconductor structure according to an embodiment of the present invention;

[0039] Figure 12 yes Figure 11 A partial schematic diagram of the central region. Detailed Implementation

[0040] As can be seen from the background technology, existing NORD memories still have shortcomings. The reasons for these problems are analyzed below:

[0041] Please refer to the reference. Figures 1 to 3 A method for forming a semiconductor structure includes: forming a substrate, the substrate including a substrate 100, a first gate material layer on the substrate 100, an isolation layer on the first gate material layer, a second gate material layer on the isolation layer, and a mask layer on the second gate material layer, the mask layer exposing at least a portion of the surface of the second gate material layer;

[0042] A first sidewall is formed on the sidewall of the mask layer;

[0043] Using the first sidewall as a mask, the second gate material layer is etched to form the control gate 102;

[0044] A second sidewall is formed on the sidewall of the control gate 102;

[0045] Using the first sidewall and the second sidewall as masks, the first gate material layer is etched to form a floating gate 101.

[0046] In the method for forming the semiconductor structure, the position of the flash memory cell is first defined by the mask layer, then the first sidewall and the second sidewall are deposited, and the first gate material layer and the second gate material layer are etched by self-alignment to form the control gate 102 and the floating gate 101.

[0047] This self-aligned etching method has low etching precision and a small process window. As NORD memory cells continue to shrink, it leads to reliability issues in semiconductor devices. Furthermore, the process steps for forming the control gate 102 and floating gate 101 using this method are relatively complex, which prolongs the process time.

[0048] Furthermore, the semiconductor structure formed by the semiconductor forming method includes: a substrate 100; a device structure layer, the device structure layer including: a gate structure pair, the gate structure pair being located on the substrate 100, the gate structure pair being arranged sequentially along a first direction, one gate structure pair including two gate structures arranged sequentially along the first direction, the gate structure including a floating gate 101 and a control gate 102 located on the floating gate 101, the gate structure extending along a second direction X, the first direction Y intersecting the second direction X; a word line 103, the word line 103 being located on the substrate 100, the word line 103 extending along the second direction X, the word line 103 being located between the two gate structures of a gate structure pair; and a word line lead-out structure 104, the word line lead-out structure 104 being located on the word line 103 in the device structure layer.

[0049] The device structure layer further includes a bit line region 105, which extends along the second direction X, and the gate structure pair is located on one side of the bit line region 105 along the first direction Y.

[0050] The bit line region of the device structure layer includes: bit line lead-out structure 106.

[0051] The character line 103 extends only along the second direction X, and the character line 103 has a smaller size along the first direction Y. The character line lead-out structure 104 is located on the character line 103, resulting in a smaller process window for the character line lead-out structure 104.

[0052] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising: forming a substrate, the substrate including a base and a gate material layer located on the base; forming a first mask layer on the gate material layer; using the first mask layer as a mask, etching the gate material layer to form a gate structure pair, wherein one side of the gate structure pair along a first direction forms a first opening with the substrate, the gate structure pair including two gate structures arranged sequentially along the first direction, a second opening being formed between the two gate structures of the gate structure pair, the gate structure including a floating gate and a control gate located on the floating gate, the first direction being parallel to the surface of the substrate; forming a filling layer within the first opening and the second opening; forming a second mask layer on the gate structure pair and the filling layer; using the second mask layer as a mask, etching the filling layer to form a word line located on the substrate, the word line including a first portion located between the two gate structures of the gate structure pair.

[0053] In the semiconductor structure formation method of the present invention, the first mask layer defines the position and size of the gate structure. The gate material layer is etched using the first mask layer as a mask to form the gate structure, which improves process accuracy and expands the process window. Furthermore, using the first mask layer as a mask to etch the gate material layer to form the floating gate and the control gate located on the floating gate reduces the process complexity of forming the floating gate and the control gate located on the floating gate, and shortens the processing time. In addition, the first mask layer also defines the position and size of the first opening and the second opening, thereby defining the position and size of the first part of the word line, simplifying the process flow.

[0054] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0055] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 6 for Figure 5 A partial schematic diagram, Figure 11 This is another schematic diagram of the semiconductor structure according to an embodiment of the present invention. Figure 12 for Figure 11 A partial schematic diagram, Figure 4 , Figures 7 to 10 ,as well as Figures 13 to 15 This is a cross-sectional schematic diagram of the semiconductor structure according to an embodiment of the present invention. Figure 5 The middle layout defines the locations of word lines, bit line regions, and gate structures; Figure 11The middle layout defines the location of the word line material layer of the bit line region to be etched away, and the location of the mask material layer on the gate structure of the isolation region II to be etched away.

[0056] Please refer to Figures 4 to 7 A substrate is provided, the substrate including a substrate 200 and a gate material layer 201 located on the substrate 200; a first mask layer (not shown) is formed on the gate material layer 201.

[0057] For example, in some embodiments of the present invention, the step of forming the first mask layer includes:

[0058] like Figure 4 As shown, a mask material layer (not shown) is formed on the gate material layer 201.

[0059] like Figure 7 As shown, the mask material layer is patterned to form the first mask layer (not shown).

[0060] The first mask layer defines the location and size of the subsequently formed gate structure. Specifically, in some embodiments of the present invention, the material of the first mask layer is silicon oxide.

[0061] The substrate 200 includes an active region I and an isolation region II, both of which extend along a first direction Y. The active region I and the isolation region II are alternately distributed along a second direction X, and the first direction Y intersects with the second direction X.

[0062] The substrate 200 includes a functional region 2001 and a logic region 2002, wherein the functional region 2001 includes the active region I and the isolation region II.

[0063] The substrate 200 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. Specifically, in some embodiments of the present invention, the substrate 200 is made of silicon.

[0064] The gate material layer 201 provides the structural basis for the subsequent formation of the gate structure 202. The material of the gate material layer 201 includes polysilicon.

[0065] The method for forming the gate material layer 201 includes deposition, and the thickness of the deposited gate material layer 201 is calculated by back-calculation based on the etching amount of each step in etching to form the gate structure 202.

[0066] Please refer to Figure 8 Using the first mask layer as a mask, the gate material layer 201 (e.g.) is subjected to... Figure 7Etching is performed to form a gate structure pair 216. The gate structure pair 216 forms a first opening 205 with the substrate along one side of the first direction Y. The gate structure pair includes two gate structures 202 arranged sequentially along the first direction Y. A second opening 206 is formed between the two gate structures 202 of the gate structure pair 216. The gate structure 202 includes a floating gate 204 and a control gate 203 located on the floating gate 204. The first direction Y is parallel to the surface of the substrate 200.

[0067] The first mask layer defines the position and size of the gate structure 202. The gate material layer 201 is etched using the first mask layer as a mask to form the gate structure, which improves the process accuracy and expands the process window. Furthermore, the process of etching the gate material layer 201 using the first mask layer as a mask to form the floating gate 204 and the control gate 203 located on the floating gate 204 reduces the process complexity of forming the floating gate 204 and the control gate 203 located on the floating gate 204 and shortens the processing time.

[0068] The first opening 205 provides a structural basis for the subsequent formation of the bit line lead-out structure, and the second opening 206 provides a structural basis for the subsequent formation of the word line 210. The first mask layer defines the position and size of the first opening 205 and the second opening 206, thereby defining the position of the bit line lead-out structure and the position and size of the first part of the word line, simplifying the process flow.

[0069] For example, the step of etching the gate material layer 201 to form the gate structure pair 216 using the first mask layer as a mask includes:

[0070] Using the first mask layer as a mask, a portion of the gate material layer 201 is etched to form a control gate pair located on the active region I and a third pre-fabricated opening located in the gate material layer 201 of the isolation region II. The third pre-fabricated opening exposes a portion of the gate material layer 201 of the isolation region II. The control gate pair and the gate material layer 201 together form a first pre-fabricated opening along one side of the first direction Y. A control gate pair includes two control gates 203 arranged sequentially along the first direction Y. A second pre-fabricated opening is formed between the two control gates 203 of a control gate pair.

[0071] A protective sidewall is formed on the sidewall of the control gate 203 in the active region I;

[0072] Using the first mask layer as a mask, the remaining thickness of the gate material layer 201 is etched to form a floating gate 204 located on the active region I.

[0073] The floating gate 204 and the control gate 203 located on the floating gate 204 are used as the gate structure 202.

[0074] Please refer to the reference. Figure 6 and Figure 8 In the process of etching the gate material layer 201 using the first mask layer as a mask to form the gate structure pair 216, the process further includes: forming a third opening 207, the third opening 207 exposing a portion of the gate material layer 201 of the isolation region II, the third opening 207 extending along the first direction Y, and the third opening 207 connecting the first opening 205 and the second opening 206 adjacent along the first direction Y.

[0075] The third opening 207 provides a structural basis for the second part of the subsequent formation of the character line 210.

[0076] The second opening 206 has two third openings 207 connected thereto, the two third openings 207 are arranged along the first direction Y and are connected to each other.

[0077] Specifically, in some embodiments of the present invention, the two third openings 207 are connected through the second opening 206.

[0078] The first opening 205 has two third openings 207 connected to it. The two third openings 207 are arranged along the second direction X, and the positions of the two third openings 207 correspond to the two ends of the first opening 205 along the second direction X.

[0079] The first opening 205 extends along the second direction X, one end of the first opening 205 along the second direction X is connected to a third opening 207, and the other end of the first opening 205 along the second direction X is connected to another third opening 207.

[0080] The first opening 205 has two third openings 207 connected thereto, and the two third openings 207 are located on different sides of the first opening 205 along the first direction Y.

[0081] The first opening 205 has two opposite sides along the first direction Y, one of the third openings 207 is connected to one side of the first opening 205, and the other of the third openings 207 is connected to the other side of the first opening 205.

[0082] Please refer to Figure 9 A filling layer 208 is formed in the first opening 205 and the second opening 206.

[0083] The process of forming a filling layer 208 in the first opening 205 and the second opening 206 also includes forming a filling layer 208 in the third opening 207.

[0084] For example, in some embodiments of the present invention, the step of forming the filling layer 208 includes:

[0085] An initial filling layer is deposited in the first opening 205, the second opening 206 and the third opening 207;

[0086] The initial fill layer is planarized to form the fill layer 208.

[0087] The filler layer 208 provides a material and structural basis for the subsequent formation of the word lines 210. Specifically, in some embodiments of the present invention, the material of the filler layer 208 is polycrystalline silicon.

[0088] Please refer to Figure 10 After forming a filling layer 208 in the first opening 205, the second opening 206 and the third opening 207, the filling layer 208 is ion implanted.

[0089] After ion implantation, the filling layer 208 is subjected to oxidation repair.

[0090] Please continue to refer to this. Figure 10 A pseudo-gate 209 is formed in the logic region 2002.

[0091] After the filling layer 208 is formed, a second mask layer is formed on the gate structure pair 216 and the filling layer 208.

[0092] The second mask layer defines the location of the fill layer to be etched away and the location of the mask material layer on the gate structure 202 of the isolation region II to be etched away.

[0093] Please refer to Figure 13 Using the second mask layer as a mask, the filling layer 208 is etched to form a word line 210 on the substrate 200. The word line 210 includes a first part 2101, which is located between the two gate structures 202 of the gate structure pair 216.

[0094] Specifically, in some embodiments of the present invention, etching removes the portion located at the first opening 205 (e.g., Figure 8 The filling layer 208 within the second opening 206 (as shown) retains the filling layer 208 within the second opening 206 (as shown). Figure 8 The filling layer 208 (as shown) is used to form the first part 2101 of the word line 210.

[0095] Please refer to the reference. Figure 12 and Figure 13 During the process of etching the filling layer 208 using the second mask layer as a mask to form the word line 210 on the substrate 200, the process also includes: etching the third opening 207 (e.g., Figure 8 The filling layer 208 (as shown) forms the second part of the word line 210, and one end of the second part 2102 along the first direction Y is connected to the first part 2101.

[0096] Specifically, in some embodiments of the present invention, the filling layer 208 located in the third opening 207 has two opposite ends along the first direction Y, one end of which is connected to the filling layer 208 located in the second opening 206, and the other end is connected to the filling layer 208 located in the first opening 205. The portion of the filling layer 208 at the other end is etched away to form the second part 2102.

[0097] The filler layer 208 at the other end is etched away to form the second part 2102, avoiding the risk of increased leakage current and reduced yield caused by the second part 2102 being too close to the bit line region 213 between the adjacent gate structure pair 216.

[0098] In the process of etching the filling layer 208 using the second mask layer as a mask to form the word line 210 on the substrate 200, the process further includes thinning the mask material layer on at least a portion of the gate structure 202 of the isolation region II.

[0099] The mask material layer on at least a portion of the gate structure 202 of the isolation region II is thinned so that the thickness of the mask material layer on the gate structure 202 of the isolation region II is not greater than the thickness of the mask material layer on the gate structure 202 of the active region I, the thickness of the mask material layer on the first part 2101, and the thickness of the mask material layer on the second part 2102, so as to provide a structural basis for the subsequent formation of the metal silicide layer 215.

[0100] like Figure 14 and Figure 15 As shown, a word line lead-out structure 211 is formed on the second part 2102.

[0101] A word line lead-out structure 211 is formed on the second part 2102. One end of the second part 2102 along the first direction Y is connected to the first part 2101. The size of the word line 210 at the position where the first part 2101 and the second part 2102 are connected in the first direction Y is equal to the sum of the size of the first part 2101 and the size of the second part 2102 in the first direction Y. The size of the word line 210 at the position where the first part 2101 and the second part 2102 are connected in the first direction Y is relatively large. When it is necessary to form a word line lead-out structure 211 on the word line 210, forming the word line lead-out structure 211 at the position where the second part 2102 and the first part 2101 are connected can increase the process window of the word line lead-out structure 211, improve the stability of the process, increase the yield of the product, and ensure the reliability of the semiconductor device.

[0102] For example, the steps of forming the word line lead-out structure 211 on the second part 2102 include:

[0103] Remove the oxide layer located on the word line 211;

[0104] A metal silicide layer 215 is formed on at least the second part 2102;

[0105] A sidewall is formed on the sidewall of the gate structure 202;

[0106] A word line lead-out structure 211 is formed on the second part 2102.

[0107] Remove the oxide layer located on the word line 211 to provide a basis for the formation of the metal silicide layer 215 and prevent the metal silicide layer 215 from forming on the silicon oxide layer.

[0108] The metal silicide layer 215 improves signal transmission efficiency by reducing contact resistance, while stabilizing the interface structure to enhance device reliability. Word lines 210 are critical connections in memory devices used to select specific memory cells; their resistance directly affects signal transmission speed and power consumption. The metal silicide layer 215, located on the word lines 210, utilizes its low resistivity to significantly reduce the overall resistance of the word lines 210, minimizing signal attenuation and delay during transmission, and ensuring fast and accurate transmission of memory cell selection signals.

[0109] In the process of forming the word line lead-out structure 211 on the second part 2102, the following is also included:

[0110] A bit line lead-out structure 214 is formed on the substrate 200 on one side of the gate structure pair 216; a control gate lead-out structure 212 is formed on the control gate 203 of the isolation region II.

[0111] The bit line lead-out structure 214 is electrically connected to the bit line region 213 located between adjacent gate structure pairs 216.

[0112] Accordingly, embodiments of the present invention also provide a semiconductor structure. Please refer to the references. Figure 12 and Figure 15 , Figure 15 They are respectively Figure 12 Cross-sectional structural diagrams at positions AA1, BB1, CC1, DD1, and EE1. The semiconductor structure includes: a substrate; a device structure layer, the device structure layer including: a pair of gate structures located on the substrate, the pair of gate structures arranged sequentially along a first direction, each pair of gate structures including two gate structures arranged sequentially along the first direction, each gate structure including a floating gate and a control gate located on the floating gate, the gate structure extending along a second direction, the first direction intersecting the second direction; a word line located on the substrate, the word line including a first portion and a second portion, the first portion extending along the second direction, the second portion extending along the first direction, one end of the second portion along the first direction being connected to the first portion, the first portion being located between the two gate structures of a pair of gate structures; and a word line lead-out structure located on the second portion of the word line in the device structure layer.

[0113] The semiconductor structure includes: substrate 200.

[0114] Specifically, the substrate 200 includes an active region I and an isolation region II, both extending along a first direction Y. The active region I and the isolation region II are alternately distributed along a second direction X, and the first direction Y intersects with the second direction X. Specifically, in some embodiments of the present invention, the first direction Y is perpendicular to the second direction X.

[0115] Please continue to refer to this. Figure 15 The isolation zone II includes: an isolation structure (not shown).

[0116] The substrate 200 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. Specifically, in some embodiments of the present invention, the substrate 200 is made of silicon.

[0117] Please continue to refer to this. Figure 15The semiconductor structure includes a device structure layer, which includes a gate structure pair 216 located on the substrate 200. The gate structure pair 216 is arranged sequentially along a first direction Y. Each gate structure pair 216 includes two gate structures 202 arranged sequentially along the first direction Y. The gate structures 202 are located on the substrate 200. Each gate structure 202 includes a floating gate 204 and a control gate 203 located on the floating gate 204. The gate structures 202 extend along a second direction X, where the first direction Y intersects with the second direction X.

[0118] The floating gate 204 plays a core role in data storage within the NORD memory. The number and state of electrons stored in the floating gate 204 directly determine whether the data represented by that memory cell is "0" or "1". When electrons are present in the floating gate 204, they change the threshold voltage of the transistor, hindering current flow; at this time, the memory cell state corresponds to "0". If there are no electrons in the floating gate 204, the transistor threshold voltage is lower, current can flow normally, and the memory cell state is "1".

[0119] The main function of the control gate 203 is to precisely control the charge state of the floating gate 204 by applying different voltages. During Fowler-Nordheim tunneling write, the voltage of the control gate 203 changes the electric field distribution between the floating gate 204 and the substrate 200, causing electrons to enter the floating gate 204 through tunneling. During the erase operation, applying a specific reverse voltage to the control gate 203 reverses the electric field, allowing electrons in the floating gate 204 to return to the substrate 200 through tunneling, thus erasing the data. When reading data from the NORD memory, the control gate 203 applies a specific read voltage, which puts the memory cell in a detectable state. By detecting the magnitude of the current flowing through the memory cell, it is determined whether electrons are stored in the floating gate 204, thereby determining the data state of the memory cell.

[0120] Specifically, the floating gate 204 is located on the active region I of the substrate 200; the control gate 203 is located on the floating gate 204, and the control gate 203 also extends to the isolation structure.

[0121] Please continue to refer to this. Figure 12 and Figure 15 The semiconductor structure further includes a control gate lead-out structure 212, which is located on the control gate 203 of the isolation region II of a portion of the device structure layers.

[0122] Please continue to refer to this. Figure 12 and Figure 15The device structure layer further includes a word line 210, which is located on the substrate 200. The word line 210 includes a first part 2101 and a second part 2102. The first part 2101 extends along the second direction X, and the second part 2102 extends along the first direction Y. One end of the second part 2102 along the first direction Y is connected to the first part 2101. The first part 2101 is located between two gate structures 202 in a gate structure pair 216.

[0123] The character line 210 includes a first part 2101 and a second part 2102. The first part 2101 extends along the second direction X, and the second part 2102 extends along the first direction Y. One end of the second part 2102 along the first direction Y is connected to the first part 2101. The character line 210 includes two parts: the first part 2101 and the second part 2102. The size of the character line 210 at the position where the first part 2101 and the second part 2102 are connected in the first direction Y is equal to the size of the first part 2101 in the first direction Y. The sum of the dimension in the Y direction and the dimension of the second part 2102 in the first direction Y is large at the position where the first part 2101 and the second part 2102 are connected. When it is necessary to form a word line lead-out structure 211 on the word line 210, forming the word line lead-out structure 211 at the position where the second part 2102 and the first part 2101 are connected can increase the process window of the word line lead-out structure 211, improve the stability of the process, increase the yield of the product, and ensure the reliability of the semiconductor device.

[0124] For details, please continue to refer to [the website / information]. Figure 12 The first part 2101 is located on the active region I and the isolation region II; the second part 2102 is located on a portion of the isolation regions II.

[0125] For details, please continue to refer to [the website / information]. Figure 12 In some embodiments of the present invention, one first part 2101 has two second parts 2102 connected thereto.

[0126] The second part 2102, which is connected to the first part 2101, increases the area of ​​the word line 210. Furthermore, the word line 210 at the position where the first part 2101 and the second part 2102 are connected has a larger size in the first direction Y, which increases the process window of the word line lead-out structure 211 formed on the word line 210.

[0127] For details, please refer to Figure 12 The two second parts 2102 are located on opposite sides of the first part 2101 along the first direction Y, and the positions of the two second parts 2102 correspond to each other.

[0128] The two second parts 2102 are located on opposite sides of the first part 2101 along the first direction Y, that is, the first part 2101 has opposite sides along the first direction Y. Of the two second parts 2102, one second part 2102 is connected to one side of the first part 2101, and the other second part 2102 is connected to the other side of the first part 2101. The two second parts 2102 connected to the first part 2101 extend in opposite directions.

[0129] The positions of the two second parts 2102 correspond to each other, that is, the projections of the two second parts 2102 in the plane perpendicular to the first direction Y at least partially overlap.

[0130] Specifically, in some embodiments of the present invention, two second parts 2102 connected to one first part 2101 are collinear, and the two second parts 2102 connected to one first part 2101 have the same size in the second direction X.

[0131] Each first part 2101 has two second parts 2102 connected to it, and the positions of the two second parts 2102 are corresponding. The size of the word line 210 at the position where the first part 2101 and the second part 2102 are connected in the first direction Y is equal to the sum of the size of the first part 2101 in the first direction Y and the size of the two second parts 2102 in the first direction Y. The size of the position in the first direction Y is large. When a word line lead-out structure 211 is formed on the word line 210, the word line lead-out structure 211 is formed at the position of the two second parts 2102 connected to the first part 2101, so that the process window of the word line lead-out structure 211 is larger, which is beneficial to improving the reliability of the semiconductor device.

[0132] Please refer to the reference. Figure 12 and Figure 15 The device structure layer includes a bit line region 213, which extends along the second direction X, and the gate structure pair 216 is located on the same side of the bit line region 213 along the first direction Y.

[0133] Specifically, in some embodiments of the present invention, the second part 2102 extends along the other end of the first direction Y to the corresponding position of the bit line region 213.

[0134] The bit line region 213 has two opposing sides along the first direction Y. The distance between one side of the bit line region 213 and the first portion 2101 adjacent to the bit line region 213 is less than the distance between the other side of the bit line region 213 and the first portion 2101 adjacent to the bit line region 213. The second portion 2102 extends along the other end of the first direction Y to the corresponding position of the bit line region 213, that is, one end of the second portion 2102 along the first direction Y is connected to the first portion, and the other end of the second portion 2102 along the first direction does not extend beyond one side of the bit line region 213 adjacent to the first portion.

[0135] Please continue to refer to the reference. Figure 12 and Figure 15 The two adjacent bit line regions 213 of the device structure layer are arranged along the first direction Y, and the gate structure pair 216 is located between the two adjacent bit line regions 213.

[0136] For details, please continue to refer to [the website / information]. Figure 12 and Figure 15 The bit line region 213 of the device structure layer is located on the active region I and the isolation region II.

[0137] Please continue to refer to the reference. Figure 12 and Figure 15 The bit line region 213 of the device structure layer includes a bit line lead-out structure 214.

[0138] The bit line lead-out structure 214 of the bit line region 213 in the device structure layer is located at the overlapping position of the active region I and the bit line region 213.

[0139] Please continue to refer to the reference. Figure 12 and Figure 15 The semiconductor structure includes a word line lead-out structure 211, which is located on the second part 2102 of the word line 210 in the device structure layer.

[0140] The word line 210 includes a first part 2101 and a second part 2102. The first part 2101 extends along the second direction X, and the second part 2102 extends along the first direction Y. One end of the second part 2102 along the first direction Y is connected to the first part 2101. At the position where the first part 2101 and the second part 2102 are connected, the word line 210 has a larger dimension along the first direction Y. The structure of the word line 210 is located on the second part 2102. The process window of the word line lead-out structure 211 is larger, which improves the stability of the process, increases the yield of the product, and ensures the reliability of the semiconductor device.

[0141] For specific details, please refer to the following: Figure 12and Figure 15 In some embodiments of the present invention, a first part 2101 has two second parts 2102 connected thereto, the two second parts 2102 are located on opposite sides of the first part 2101 along the first direction Y and the positions of the two second parts 2102 correspond to each other, and the word line lead-out structure 211 is located on at least one of the two second parts 2102.

[0142] Each first part 2101 has two second parts 2102 connected to it, and the positions of the two second parts 2102 are corresponding. The size of the word line 210 at the position where the first part 2101 and the second part 2102 are connected in the first direction Y is equal to the sum of the size of the first part 2101 in the first direction Y and the size of the two second parts 2102 in the first direction Y. The size of the word line 210 at the position in the first direction Y is larger. When a word line lead-out structure 211 is formed on the word line 210, the word line lead-out structure 211 is located on at least one of the two second parts 2102, so that the process window of the word line lead-out structure 211 is larger, which is beneficial to improving the reliability of the semiconductor device.

[0143] Please continue to refer to this. Figure 12 Two adjacent first portions 2101 along the first direction Y, a second portion 2102 connected to one first portion 2101, and a second portion 2102 connected to another first portion 2101 are respectively located on opposite sides of the bit line region 213 along the second direction X.

[0144] Two second parts 2102 connected to the first part 2101 and another second part 2102 connected to the first part 2101 are located on opposite sides of the bit line region 213 along the second direction X. This distribution makes the current path of the word lines 210 more balanced, avoiding the problem of large parasitic inductance caused by the concentrated distribution of word lines 210 on the same side of the bit line region 213. This results in a small parasitic inductance of the memory cell; furthermore, this distribution avoids the situation of crowded wiring on one side and idle space on the other side, which can reduce the area occupied by the memory array in the chip, thereby improving the integration density.

[0145] Please continue to refer to this. Figure 15 The device structure layer further includes: a metal silicide layer 215, which is located on the word line 210; the metal silicide layer 215 is also located between the bit line region 213 and the bit line lead-out structure 214 of the device structure layer; the metal silicide layer 215 is also located between the control gate lead-out structure 212 and the control gate 203.

[0146] The metal silicide layer 215 improves signal transmission efficiency by reducing contact resistance, while stabilizing the interface structure to enhance device reliability. Word lines 210 are critical connections in memory devices used to select specific memory cells; their resistance directly affects signal transmission speed and power consumption. The metal silicide layer 215, located on the word lines 210, utilizes its low resistivity to significantly reduce the overall resistance of the word lines 210, minimizing signal attenuation and delay during transmission, and ensuring fast and accurate transmission of memory cell selection signals.

[0147] In summary, in the semiconductor structure formation method of the present invention, the first mask layer defines the position and size of the gate structure. Etching the gate material layer using the first mask layer as a mask to form the gate structure improves process accuracy and expands the process window. Furthermore, etching the gate material layer using the first mask layer as a mask to form the floating gate and the control gate located on the floating gate reduces the process complexity of forming the floating gate and the control gate located on the floating gate, shortening the processing time. In addition, the first mask layer also defines the position and size of the first opening and the second opening, thereby defining the position and size of the first part of the word line, simplifying the process flow. Furthermore, a word line lead-out structure is formed on the second part. One end of the second part along the first direction is connected to the first part. The size of the word line at the position where the first part and the second part are connected in the first direction is equal to the sum of the size of the first part and the size of the second part in the first direction. The size of the word line at the position where the first part and the second part are connected in the first direction is larger. When it is necessary to form a word line lead-out structure on the word line, forming the word line lead-out structure at the position where the second part and the first part are connected can increase the process window of the word line lead-out structure, improve the stability of the process, increase the yield of the product, and ensure the reliability of the semiconductor device.

[0148] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is formed, the substrate comprising a substrate and a gate material layer located on the substrate; A first mask layer is formed on the gate material layer; Using the first mask layer as a mask, the gate material layer is etched to form a gate structure pair. One side of the gate structure pair along the first direction forms a first opening with the substrate. The gate structure pair includes two gate structures arranged sequentially along the first direction. A second opening is formed between the two gate structures of the gate structure pair. The gate structure includes a floating gate and a control gate located on the floating gate. The first direction is parallel to the surface of the substrate. A filling layer is formed within the first opening and the second opening; A second mask layer is formed on the gate structure pair and the fill layer; Using the second mask layer as a mask, the filling layer is etched to form a word line on the substrate. The word line includes a first portion located between the two gate structures of the gate structure pair.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes an active region and an isolation region, both of which extend along a first direction. The active region and the isolation region are alternately distributed along a second direction, which is parallel to the surface of the substrate and perpendicular to the first direction.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The step of etching the gate material layer using the first mask layer as a mask to form a gate structure pair includes: Using the first mask layer as a mask, a portion of the gate material layer is etched to form a control gate pair located on the active region and a third pre-fabricated opening located within the gate material layer of the isolation region. The third pre-fabricated opening exposes a portion of the gate material layer of the isolation region. The control gate pair forms a first pre-fabricated opening with the gate material layer along one side of the first direction. A control gate pair includes two control gates arranged sequentially along the first direction. A second pre-fabricated opening is formed between the two control gates of a control gate pair. A protective sidewall is formed on the sidewall of the control gate in the active region; Using the first mask layer as a mask, the remaining thickness of the gate material layer is etched to form a floating gate located on the active region.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the process of etching the filling layer using the second mask layer as a mask to form word lines on the substrate, the method further includes: thinning the mask material layer on the gate structure of at least a portion of the isolation region.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The substrate includes a functional region and a logic region, wherein the functional region includes the active region and the isolation region; The method for forming the semiconductor structure further includes: after forming a filling layer in the first opening and the second opening, before etching the filling layer using the second mask layer as a mask to form word lines on the substrate, forming a pseudo gate in the logic region.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, Also includes: After forming a filling layer in the first opening and the second opening, and before forming a pseudo-gate in the logic region, the filling layer is ion implanted. The filling layer is then subjected to oxidative repair.

7. The method for forming a semiconductor structure as described in claim 2, characterized in that, During the process of etching the gate material layer using the first mask layer as a mask to form a gate structure pair, the method further includes: forming a third opening, wherein the third opening exposes a portion of the gate material layer of the isolation region, the third opening extends along the first direction, and the third opening connects the first opening and the second opening adjacent to each other along the first direction.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The second opening has two third openings connected to it, the two third openings being arranged along the first direction and connected to each other.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first opening has two third openings connected to it, the two third openings are arranged along the second direction, and the positions of the two third openings correspond to the two ends of the first opening along the second direction.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first opening has two third openings connected to it, and the two third openings are located on different sides of the first opening along the first direction.

11. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process of forming a filling layer in the first opening and the second opening also includes forming a filling layer in the third opening.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the process of etching the filling layer to form word lines on the substrate using the second mask layer as a mask, the process further includes: etching the filling layer located in the third opening to form a second part of the word line, wherein one end of the second part along the first direction is connected to the first part.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, Also includes: A word line leader structure is formed on the second part.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The steps for forming the word line leader structure on the second part include: Remove the oxide layer located on the word lines; A metal silicide layer is formed on at least the second part; A word line leader structure is formed on the second part.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the process of forming the word line lead-out structure in the second part, the method further includes: forming a bit line lead-out structure on the substrate on one side of the gate structure; A control gate lead-out structure is formed on the control gate of the isolation zone.

16. A semiconductor structure, characterized in that, include: Substrate; A device structure layer, the device structure layer comprising: a pair of gate structures, the pair of gate structures being located on the substrate, the pair of gate structures being arranged sequentially along a first direction, each pair of gate structures comprising two gate structures arranged sequentially along the first direction, each gate structure comprising a floating gate and a control gate located on the floating gate, the gate structure extending along a second direction, the first direction intersecting the second direction; A word line, the word line being located on the substrate, the word line comprising a first part and a second part, the first part extending along a second direction, the second part extending along a first direction, one end of the second part along the first direction being connected to the first part, the first part being located between two gate structures of a gate structure pair; A word line lead-out structure is located on the second part of the word line in the device structure layer.

17. The semiconductor structure as claimed in claim 16, characterized in that, The device structure layer includes: a bit line region extending along the second direction, and a pair of gate structures located on the same side of the bit line region along the first direction.

18. The semiconductor structure as claimed in claim 17, characterized in that, The second part extends along the other end of the first direction to the corresponding position of the bit line region.

19. The semiconductor structure as claimed in claim 17, characterized in that, The bit line region of the device structure layer includes: a bit line lead-out structure.

20. The semiconductor structure as claimed in claim 17, characterized in that, The first part has two second parts connected to it.

21. The semiconductor structure as claimed in claim 20, characterized in that, The two second parts are located on opposite sides of the first part along the first direction, and the positions of the two second parts correspond to each other.

22. The semiconductor structure as claimed in claim 21, characterized in that, The word line lead-out structure is located on at least one of the two second parts.

23. The semiconductor structure as claimed in claim 21, characterized in that, The two adjacent bit line regions of the device structure layer are arranged along a first direction, and the gate structure pair is located between the two adjacent bit line regions.

24. The semiconductor structure as claimed in claim 23, characterized in that, Two adjacent first portions along the first direction, a second portion connected to one first portion, and a second portion connected to another first portion are respectively located on opposite sides of the bit line region along the second direction.

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