Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The method comprises the following steps: providing a substrate; forming a sacrificial layer on the substrate; forming a first opening, wherein the first opening penetrates through the sacrificial layer and is located in a part of thickness of the substrate; forming a collector region in the first opening; forming a base region in the first opening on the collector region; forming an emitter region on the base region; removing the sacrificial layer to expose the side wall of the base region; and forming an outer base region on the substrate at two sides of the base region, wherein the outer base region is connected with the side wall of the base region. After the sacrificial layer is formed, directly forming a base region on the collector region; after the base region is formed, the sacrificial layer is removed, and the outer base regions connected with the side walls of the base region are formed on the substrate on the two sides of the base region, so that the base region is formed in the single direction, holes and defects in the base region can be effectively avoided, the contact resistance between the outer base regions and the base region is reduced, and the performance of the device is improved. And the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor device and a method for forming the same. Background Technology

[0002] RF front-end modules typically include power amplifiers (PAs), low-noise amplifiers (LNAs), switches, and filters. Power amplifiers often include heterojunction bipolar transistors (HBTs). An HBT is a transistor composed of an emitter, a base, and a collector. The emitter uses a lightly doped, wide bandgap, while the base uses a heavily doped, narrow bandgap. The emitter efficiency is determined by the bandgap difference. Its primary function is current gain, such as increasing the collector current or the base current. HBT devices are characterized by stable performance, high speed, and high frequency. With the widespread application of SiGeBiCMOS (Silicon-Geobium Bipolar Complementary Metal-Oxide-Semiconductor) technology, the performance requirements for HBTs have increased.

[0003] Currently, the performance of silicon-germanium bipolar complementary metal-oxide-semiconductor devices needs to be improved. Summary of the Invention

[0004] The technical problem solved by this invention is how to improve the performance of semiconductor devices.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor device, comprising: providing a substrate; forming a sacrificial layer on the substrate; forming a first opening, the first opening penetrating the sacrificial layer and located within a portion of the thickness of the substrate; forming a collector region within the first opening; forming a base region within the first opening on the collector region; forming an emitter region on the base region; removing the sacrificial layer to expose the sidewalls of the base region; and forming outer base regions on the substrate on both sides of the base region, the outer base regions being connected to the sidewalls of the base region.

[0006] Optionally, the step of forming a base region within the first opening on the collector region includes: forming the base region within the first opening on the collector region by selective epitaxy.

[0007] Optionally, the step of forming an outer base region on the substrate on both sides of the base region includes: growing the outer base region on the substrate on both sides of the base region by selective epitaxy.

[0008] Optionally, the method for forming the semiconductor device further includes: after providing a substrate, before forming a sacrificial layer on the substrate, forming a first seed layer on the substrate; the step of removing the sacrificial layer includes: removing the sacrificial layer to expose the sidewalls of the base region and the surface of the first seed layer; the step of growing an outer base region on the substrate on both sides of the base region by selective epitaxy includes: growing the outer base region on the sidewalls of the base region and the surface of the first seed layer by selective epitaxy.

[0009] Optionally, the step of forming an outer base region on the substrate on both sides of the base region includes: forming an outer base layer on the substrate on both sides of the base region; removing a portion of the outer base layer away from the base region to form the outer base region.

[0010] Optionally, the method for forming the semiconductor device further includes: after forming an emitter region on the base region and before removing the sacrificial layer, forming sacrificial sidewalls on the sacrificial layer on both sides of the emitter region; the step of removing the sacrificial layer includes: removing the sacrificial layer to expose the sidewalls of the base region, and forming a lateral opening between the sacrificial sidewalls and the substrate; the step of forming an outer base layer on the substrates on both sides of the base region includes: forming an outer base layer on the substrates on both sides of the base region that fills the lateral opening; after forming the outer base layer on the substrates on both sides of the base region that fills the lateral opening, removing a portion of the outer base layer away from the base region, and removing the sacrificial sidewalls before forming the outer base region.

[0011] Optionally, in the step of forming an outer base layer on the substrate on both sides of the base region, the thickness of the outer base layer on the side away from the base region is greater than the thickness of the outer base layer on the side closer to the base region.

[0012] Optionally, the method for forming the semiconductor device further includes: after providing a substrate, before forming a sacrificial layer on the substrate, forming a first isolation structure within the substrate; in the step of forming a first opening, the first opening is located within the first isolation structure, and the bottom of the first opening exposes the substrate below the first isolation structure.

[0013] Optionally, in the step of providing a substrate, the substrate has a second isolation structure; the step of forming a first isolation structure in the substrate includes: forming a first isolation structure in the substrate between adjacent second isolation structures.

[0014] Optionally, the step of forming the first isolation structure in the substrate includes: forming a first isolation structure in the substrate with a depth less than that of the second isolation structure.

[0015] Optionally, the method further includes: forming a base region within a first opening on the collector region, and forming a second opening on the base region; the step of forming an emitter region on the base region includes: forming a first sidewall material layer on the surface of the sacrificial layer away from the substrate, the sidewall of the second opening, and the surface of the base region away from the collector region; forming a second seed material layer on the sidewall layer; removing the second seed material layer and the first sidewall material layer on the sacrificial layer to form a second seed layer and a first sidewall; forming an emitter layer on the sacrificial layer, the second seed layer, and the first sidewall; and removing the emitter layer on the sacrificial layer to form an emitter region.

[0016] Optionally, it further includes: forming a second sidewall material layer on the sacrificial layer during the formation of the sacrificial layer on the substrate; and after forming the second seed layer and the first sidewall layer, removing a portion of the second sidewall material layer away from the first sidewall to form the second sidewall.

[0017] Optionally, the base region is made of germanium silicon, the outer base region is made of polycrystalline silicon, and the sacrificial layer is made of silicon nitride.

[0018] Accordingly, the present invention also provides a semiconductor device, comprising: a substrate; a collector region located within the substrate; a base region located on the collector region; an emitter region located on the base region; and an outer base region located on the substrate on both sides of the base region, the outer base region being connected to the sidewalls of the base region.

[0019] Optionally, it further includes: a first isolation structure located within the substrate, the current collector region located within the first isolation structure, and the current collector region penetrating the first isolation structure along its thickness; and a second isolation structure located within the substrate on the side of the first isolation structure away from the current collector region.

[0020] Optionally, the depth of the first isolation structure is less than the depth of the second isolation structure.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] The semiconductor device formation method provided by the present invention involves forming the sacrificial layer, then directly forming a base region on the collector region; after forming the base region, removing the sacrificial layer, and forming an outer base region connected to the sidewalls of the base region on the substrate on both sides of the base region, so that the base region is formed in a single direction, which can effectively avoid the generation of holes and defects in the base region, reduce the contact resistance between the outer base region and the base region, and improve the performance of the semiconductor device.

[0023] In an optional embodiment of the present invention, by selectively epitaxially growing an outer base region, the outer base region can grow along the lattice of the base region, so that the lattice of the outer base region matches the lattice of the base region, thereby improving the connectivity between the outer base region and the base region, thereby reducing the contact resistance between the outer base region and the base region, and improving the performance of the semiconductor device.

[0024] In an optional embodiment of the present invention, by forming the first isolation structure on both sides of the collector region, the first isolation structure can isolate the collector region and the outer base region, reduce the parasitic capacitance between the collector region and the outer base region, increase the maximum cutoff frequency of the heterojunction bipolar transistor, and improve the performance of the semiconductor device. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a semiconductor device;

[0026] Figures 2 to 14 This is a schematic diagram of the semiconductor device formation process in one embodiment of the present invention. Detailed Implementation

[0027] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0028] As described in the background section, the fabrication process of heterojunction bipolar transistors in the prior art still has shortcomings. The reasons for these shortcomings are analyzed below:

[0029] Figure 1 This is a schematic diagram of a semiconductor structure.

[0030] like Figure 1 As shown, the semiconductor structure includes: a substrate 100; an oxide layer 101 located within the substrate 100 and on the surface of the substrate 100; and an outer base region 102 located on the side of the oxide layer 101 away from the substrate 100.

[0031] Along the first direction X, the width of the oxide layer 101 is smaller than that of the outer base region 102, and along the direction perpendicular to the substrate 100, a lateral opening 103 is formed between the bottom of the outer base region 102 and the substrate 100.

[0032] The semiconductor structure further includes a base region (not shown in the figure), which is located between the bottom of the outer base region 102 and the substrate 100.

[0033] The step of forming the base region includes: using an epitaxial growth process, filling germanium-silicon along the bottom surface of the outer base region 102 and along two growth directions along the surface of the substrate 100 until the lateral opening is filled to form the base region.

[0034] It is evident that currently, a base region needs to be formed between the outer base region and the substrate in two directions, which increases the difficulty of the epitaxial process and easily leads to the generation of holes and defects in the base region, increasing the contact resistance between the base region and the outer base region and affecting the performance of the semiconductor device.

[0035] To address the aforementioned technical problems, the present invention provides a semiconductor device and a method for forming the same. After forming the sacrificial layer, a base region is directly formed on the collector region. After forming the base region, the sacrificial layer is removed, and an outer base region connected to the sidewalls of the base region is formed on the substrates on both sides of the base region. This ensures that the base region is formed in a single direction, effectively preventing the generation of holes and defects within the base region, reducing the contact resistance between the outer base region and the base region, and improving the performance of the semiconductor device.

[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] refer to Figures 2 to 14 The diagram shows structural schematics of various steps in some embodiments of the method for forming a semiconductor device according to the present invention.

[0038] The forming method may include: providing a substrate; forming a sacrificial layer on the substrate; forming a first opening that penetrates the sacrificial layer and is located within a portion of the thickness of the substrate; forming a collector region within the first opening; forming a base region within the first opening on the collector region; forming an emitter region on the base region; removing the sacrificial layer to expose the sidewalls of the base region; and forming outer base regions on the substrate on both sides of the base region, the outer base regions being connected to the sidewalls of the base region.

[0039] After forming the sacrificial layer, a base region is directly formed on the collector region; after forming the base region, the sacrificial layer is removed, and an outer base region connected to the sidewall of the base region is formed on the substrate on both sides of the base region, so that the base region is formed in a single direction, thereby reducing the contact resistance between the outer base region and the base region and improving the performance of the semiconductor device.

[0040] refer to Figure 2 The forming method includes: providing a substrate 200.

[0041] In some embodiments of the present invention, the substrate 200 is made of silicon.

[0042] In other embodiments, the substrate 200 may be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate 200 may be a silicon substrate on an insulator or a germanium substrate on an insulator.

[0043] In some of the example embodiments, during the step of providing substrate 200, a second isolation structure 201 is formed within the substrate 200.

[0044] The second isolation structure 201 is used to form electrical isolation between adjacent semiconductor devices.

[0045] Specifically, the steps for forming the second isolation structure 201 include: forming a first mask material layer on the substrate 200; forming a first pattern layer (not shown in the figure) on the first mask material layer; etching the first mask material layer using the first pattern layer as a mask to expose the substrate 200, thereby forming the first mask layer (not shown in the figure); etching the substrate 200 using the first mask layer as a mask to form an isolation trench (not shown in the figure) within the substrate 200; and forming the second isolation structure 201 within the isolation trench.

[0046] For example, in the step of forming the second isolation structure 201, an oxide layer 2011 is formed on the surface of the substrate 200.

[0047] The first patterning layer is used to pattern the first mask material layer to define the size and position of the second isolation structure 201.

[0048] In some examples of embodiments, after the substrate 200 is provided, a first isolation structure 202 is formed within the substrate 200.

[0049] The first isolation structure 202 is used to form electrical isolation between the subsequently formed collector region 2001 and the outer base region 2012.

[0050] Specifically, the steps for forming the first isolation structure 202 include: forming a second mask material layer on the substrate 200; forming a second pattern layer (not shown in the figure) on the second mask material layer; etching the second mask material layer using the second pattern layer as a mask to expose the substrate 200, thereby forming the second mask layer (not shown in the figure); and etching the substrate 200 using the second mask layer as a mask to form an isolation opening 2021 in the substrate 200.

[0051] The second patterning layer is used to pattern the second mask material layer to define the depth and position of the first isolation structure 202.

[0052] In some embodiments of the present invention, the etching process of the substrate 200 is a dry etching process.

[0053] In some embodiments of the present invention, the second isolation structure 201 is formed by chemical vapor deposition or physical vapor deposition; the material of the second isolation structure 201 includes silicon oxide, silicon nitride, and silicon oxynitride.

[0054] refer to Figure 3 The first isolation layer 2022 is formed within the isolation opening 2021.

[0055] The first isolation layer 2022 is used to provide a structural basis for the subsequent formation of the first isolation structure 202.

[0056] In some embodiments of the present invention, the first isolation layer 2022 is formed by chemical vapor deposition or physical vapor deposition; the material of the first isolation layer 2022 includes silicon oxide, silicon nitride, and silicon oxynitride.

[0057] refer to Figure 4 The first isolation layer 2022 is etched to form the first isolation structure 202.

[0058] The first isolation structure 202 is used to isolate the subsequent collector region and the outer base region.

[0059] By forming the first isolation structure on both sides of the collector region, the first isolation structure can isolate the collector region and the outer base region, reduce the parasitic capacitance between the collector region and the outer base region, increase the maximum cutoff frequency of the heterojunction bipolar transistor, and improve the performance of the semiconductor device.

[0060] In a specific embodiment, after forming the first isolation layer 2022 and before forming the first isolation structure 202, a first seed material layer (not shown in the figure) is formed on the oxide layer 2011; a sacrificial material layer (not shown in the figure) is formed on the first seed layer 203; and a second sidewall material layer 205 is formed on the sacrificial material layer.

[0061] The first seed material layer is used to provide a structural basis for the subsequent formation of the first seed layer 203.

[0062] The sacrificial material layer is used to provide a structural basis for the subsequent formation of sacrificial layer 204.

[0063] The second sidewall material layer 205 is used to provide a structural foundation for the subsequent formation of the second sidewall.

[0064] In some embodiments of the present invention, the first seed material layer, the sacrificial material layer, and the second sidewall material layer 205 are formed by chemical vapor deposition or physical vapor deposition.

[0065] The first seed material layer is made of polycrystalline silicon, and the sacrificial material layer and the second sidewall material layer 205 are made of silicon oxide, silicon nitride, and silicon oxynitride.

[0066] In a specific embodiment, the step of forming the first isolation structure 202 includes: forming a third mask material layer on the substrate 200; forming a third pattern layer on the third mask material layer; using the third pattern layer as a mask, etching the third mask material layer to expose the second sidewall material layer 205 to form the third mask layer (not shown in the figure); using the third mask layer as a mask, etching the second sidewall material layer 205, the sacrificial material layer, the first seed material layer, and the first isolation layer 2022 to form a first opening 2031, the first isolation structure 202, the first seed layer 203, the sacrificial layer 204, the second sidewall material layer 205, and the oxide layer 2011.

[0067] The first seed layer 203 provides an attachment point and growth base for the subsequent outer base region, preventing the outer base region from growing directly on the first isolation structure 202 and ensuring the quality of the forming material of the outer base region.

[0068] The second patterning layer is used to pattern the second mask material layer to define the depth and position of the first isolation structure 202.

[0069] The first opening 2031 penetrates the sacrificial layer 204 and is located within a portion of the thickness of the substrate 200, and the first opening 2031 is located between adjacent first isolation structures 202.

[0070] In the step of forming the first opening 2031, the first opening 2031 is located inside the first isolation structure 202, and the bottom of the first opening 2031 exposes the substrate 200 below the first isolation structure 202.

[0071] The first opening 2031 is used to accommodate the subsequently formed collector area.

[0072] Along a direction perpendicular to the substrate 200, the depth of the first isolation structure 202 is less than that of the second isolation structure 201.

[0073] Specifically, the depth of the first isolation structure 202 ranges from 900 angstroms to 1000 angstroms.

[0074] In some embodiments, a portion of the first isolation layer 2022 is removed by wet etching.

[0075] refer to Figure 5A current collection area 2001 is formed within the first opening 2031.

[0076] The top of the current collection area 2001 is flush with the top of the first isolation structure 202.

[0077] The steps for forming the current collector region 2001 include: forming a current collector layer (not shown in the figure) in the first opening 2031 using a selective epitaxial process; and doping the current collector layer to form the current collector region 2001.

[0078] The collector region 2001 is used to collect electrons and form a collector current. Specifically, electrons are injected from the emitter region into the base region, some electrons recombine in the base region, and the remaining electrons diffuse to the collector junction and are pulled into the collector region 2001 under the action of the collector junction electric field to form a collector current.

[0079] The material of the current collector 2001 includes silicon or germanium-silicon.

[0080] refer to Figure 6 A base region 206 is formed within the first opening on the current collector region 2001.

[0081] The step of forming a base region 206 within a first opening on the collector region 2001 includes: forming a base region 206 within a first opening on the collector region 2001 by selective epitaxy.

[0082] The top of the base region 206 is flush with the top of the sacrificial layer 204.

[0083] The base region 206 affects the current amplification and switching characteristics of the device by controlling the injection and transport of charge carriers.

[0084] The base region 206 is made of germanium-silicon.

[0085] After forming the sacrificial layer, a base region is directly formed on the collector region; after forming the base region, the sacrificial layer is removed, and an outer base region connected to the sidewall of the base region is formed on the substrate on both sides of the base region, so that the base region is formed in a single direction, which can effectively avoid the generation of holes and defects in the base region, reduce the contact resistance between the outer base region and the base region, and improve the performance of the semiconductor device.

[0086] In some embodiments, a base region 206 is formed within a first opening 2031 on the current collector region 2001, and a second opening 2052 is formed on the base region 206.

[0087] The second opening 2052 is used to accommodate the subsequently formed launch area 209.

[0088] For example, a launch region 209 is formed on base region 206.

[0089] refer to Figure 7 The step of forming the emitter region 209 on the base region 206 includes: forming a first sidewall material layer 2071 on the surface of the sacrificial layer 204 away from the substrate 200, the sidewall of the second opening 2052, and the surface of the base region 206 away from the collector region 2001; and forming a second seed material layer 2081 on the first sidewall material layer 2071.

[0090] The second seed material layer 2081 is used to provide a structural basis for the subsequent formation of the second seed layer.

[0091] The first sidewall material layer 2071 is used to provide a structural foundation for the subsequent formation of the first sidewall.

[0092] In some embodiments of the present invention, the second seed material layer 2081 and the first sidewall material layer 2071 are formed by chemical vapor deposition or physical vapor deposition.

[0093] refer to Figure 8 Remove the second seed material layer 2081 and the first sidewall material layer 2071 on the sacrificial layer 204 to form the second seed layer 208 and the first sidewall 207.

[0094] The second seed layer 208 provides an attachment point and growth base for the subsequent launch zone 209, preventing the launch zone 209 from growing directly on the first sidewall 207 and ensuring the quality of the materials forming the launch zone 209.

[0095] In some embodiments, the second seed material layer 2081 and the first sidewall material layer 2071 on the sacrificial layer 204 are removed by wet etching until the surface of the second sidewall material layer 205 is exposed, thereby forming the first sidewall 207 and the second seed layer 208.

[0096] The first sidewall 207 is located on the sidewall of the second opening 2052 and part of the top surface of the base region 206, and the first sidewall 207 is L-shaped.

[0097] The second seed layer 208 is located within the L-shaped notch of the first sidewall 207.

[0098] The second seed layer 208 is made of polycrystalline silicon, and the first sidewall 207 is made of silicon oxide, silicon nitride, and silicon oxynitride.

[0099] refer to Figure 9An emission layer is formed on the sacrificial layer 204, the second seed layer 208, and the first sidewall 207; the emission layer on the sacrificial layer 204 and a portion of the second sidewall material layer 205 away from the first sidewall 207 are removed to form an emission area 209 and a second sidewall 2051.

[0100] The steps of forming the emission layer include: forming the emission layer on the second sidewall material layer 205, the top of the first sidewall 207, the top of the second seed layer 208, and the top of the base region 206 by selective epitaxy; and forming a first protective material layer on the emission layer.

[0101] The emission layer is used to provide a structural basis for the subsequent formation of the emission region 209.

[0102] The emitter region 209 is made of a wide bandgap semiconductor material. The bandgap of the emitter region 209 is greater than the bandgap of the base region 206 material, which forms a built-in barrier at the emitter junction, effectively suppressing the injection of holes from the base region 206 into the emitter region 209, thereby improving the emission efficiency.

[0103] In some embodiments, the emission layer, a portion of the second sidewall material layer 205 away from the first sidewall 207, and the first protective material layer (not shown) on the sacrificial layer 204 are removed by wet etching until the surface of the sacrificial layer 204 is exposed, forming the emission region 209, the second sidewall 2051, and the first protective layer 2091.

[0104] The wet etching process can also use potassium hydroxide solution or ammonia solution.

[0105] The material of the emission region 209 is polycrystalline silicon, and the materials of the second sidewall 2051 and the first protective layer 2091 include silicon oxide, silicon nitride, and silicon oxynitride.

[0106] refer to Figure 10 Sacrificial sidewalls 210 are formed on the sacrificial layers 204 on both sides of the launch area 209.

[0107] In some embodiments of the present invention, the sacrificial sidewall 210 is formed using a chemical vapor deposition process or a physical vapor deposition process.

[0108] The sacrificial sidewall 210 is located on the sidewall of the first protective layer 2091, the sidewall of the emission area 209, the sidewall of the second sidewall 2051, and the top of part of the sacrificial layer 204, and the sacrificial sidewall 210 is L-shaped.

[0109] The material of the sacrificial sidewall 210 includes silicon oxide, silicon nitride, and silicon oxynitride.

[0110] refer to Figure 11 Remove the sacrificial layer 204 to expose the sidewall of the base region 206, and form a lateral opening 211 between the sacrificial sidewall 210 and the substrate 200.

[0111] The lateral opening 211 is used to accommodate the subsequently formed outer base region 2012.

[0112] The step of removing the sacrificial layer 204 includes: removing the sacrificial layer 204 to expose the sidewall of the base region 206 and the surface of the first seed layer 203.

[0113] In some embodiments, the sacrificial layer 204 is removed by wet etching until the surface of the first seed layer 203 and the sidewall of the base region 206 are exposed, forming a lateral opening 211 between the sacrificial sidewall 210 and the seed layer.

[0114] The wet etching process can also use potassium hydroxide solution or ammonia solution.

[0115] refer to Figure 12 An outer base layer 20121 is formed on the substrate 200 on both sides of the base region 206, filling the lateral opening 211.

[0116] The step of forming an outer base region 2012 on the substrate 200 on both sides of the base region 206 includes: growing an outer base layer 20121 on the substrate 200 on both sides of the base region 206 by selective epitaxy.

[0117] By selectively epitaxially growing the outer base region 2012, the outer base region 2012 can grow along the lattice of the base region 206, so that the lattice of the outer base region 2012 matches the lattice of the base region 206, thereby improving the connectivity between the outer base region 2012 and the base region 206, thereby reducing the contact resistance between the outer base region 2012 and the base region 206, and improving the performance of the semiconductor device.

[0118] Specifically, an outer base layer 20121 is grown on the sidewall of the base region 206 and the surface of the first seed layer 203 by selective epitaxy.

[0119] The thickness of the outer base layer 20121 on the side away from the base region 206 is greater than the thickness of the outer base layer 20121 on the side closer to the base region 206, that is, the thickness of the outer base layer 20121 outside the lateral opening 211 is greater than the thickness of the outer base layer 20121 inside the lateral opening 211.

[0120] The top of the portion of the outer base layer 20121 outside the lateral opening 211 is flush with the top of the first sidewall 207, and the top of the portion of the outer base layer 20121 inside the lateral opening 211 is flush with the base area 206.

[0121] The material of the outer base layer 20121 is polycrystalline silicon.

[0122] refer to Figure 13 Remove the sacrificial sidewall 210.

[0123] In some embodiments, the sacrificial sidewall 210 is removed by wet etching to form an opening between the emitter region 209 and the outer base layer 20121.

[0124] refer to Figure 14 Remove a portion of the outer base layer 20121 that is far from the base region 206 to form the outer base region 2012.

[0125] In some embodiments, a portion of the outer substrate 20121 is removed by wet etching to expose the surface of the oxide layer 2011, forming the outer base region 2012.

[0126] The wet etching process can also use potassium hydroxide solution or ammonia solution.

[0127] The outer base region 2012 is used to connect with the base region 206 to realize the connection between the base region 206 and the external circuit, and the outer base region 2012 can reduce the parasitic capacitance between the emitter region 209 and the collector region 2001.

[0128] Before forming the outer base region 2012, the method further includes forming a second protective layer 2013 on the outer base layer 20121, the sidewall of the second sidewall 2051, and the surface of the emission region 209.

[0129] Accordingly, please continue to refer to Figure 14 The present invention also provides a semiconductor device, comprising: a substrate 200; a collector region 2001 located within the substrate 200; a base region 206 located on the collector region 2001; an emitter region 209 located on the base region 206; and an outer base region 2012 located on the substrate 200 on both sides of the base region 206, the outer base region 2012 being connected to the sidewalls of the base region 206.

[0130] The collector region 2001 is used to collect electrons and form a collector current. Specifically, electrons are injected from the emitter region 209 into the base region 206. Some electrons recombine in the base region 206, and the remaining electrons diffuse to the collector junction and are pulled into the collector region 2001 under the action of the collector junction electric field to form a collector current.

[0131] The base region 206 affects the current amplification and switching characteristics of the device by controlling the injection and transport of charge carriers.

[0132] The emitter region 209 is made of a wide bandgap semiconductor material. The bandgap of the emitter region 209 is greater than the bandgap of the base region 206 material, which forms a built-in barrier at the emitter junction, effectively suppressing the injection of holes from the base region 206 into the emitter region 209, thereby improving the emission efficiency.

[0133] The outer base region 2012 is used to connect with the base region 206 to realize the connection between the base region 206 and the external circuit, and the outer base region 2012 can reduce the parasitic capacitance between the emitter region 209 and the collector region 2001.

[0134] In some embodiments, the semiconductor device further includes: a first isolation structure 202 located within the substrate 200, a collector region 2001 located within the first isolation structure 202 and the collector region 2001 extending through the first isolation structure 202 along its thickness; and a second isolation structure 201 located within the substrate 200 on the side of the first isolation structure 202 away from the collector region 2001.

[0135] The first isolation structure 202 is used to isolate the collector region 2001 and the outer base region 2012, and the second isolation structure 201 is used to form electrical isolation between adjacent semiconductor devices.

[0136] In some embodiments, the depth of the first isolation structure 202 is less than the depth of the second isolation structure 201.

[0137] The first isolation structure 202 can isolate the collector region 2001 and the outer base region 2012, reduce the parasitic capacitance between the collector region 2001 and the outer base region 2012, increase the maximum cutoff frequency of the heterojunction bipolar transistor, and improve the performance of the semiconductor device.

[0138] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: Provide substrate; A sacrificial layer is formed on the substrate; A first opening is formed, the first opening penetrating the sacrificial layer and located within a portion of the thickness of the substrate; A current-collecting region is formed within the first opening; A base region is formed within the first opening on the current collector region; A launch region is formed on the base region; Remove the sacrificial layer to expose the sidewalls of the base region; An outer base region is formed on the substrate on both sides of the base region, and the outer base region is connected to the sidewall of the base region.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, The step of forming a base region within a first opening in the collector region includes: forming a base region within a first opening in the collector region by selective epitaxy.

3. The method for forming a semiconductor device as described in claim 1, characterized in that, The step of forming outer base regions on the substrates on both sides of the base region includes: The outer base region is grown on the substrate on both sides of the base region by selective epitaxy.

4. The method for forming a semiconductor device as described in claim 1 or 3, characterized in that, Also includes: After providing the substrate, and before forming the sacrificial layer on the substrate, a first seed layer is formed on the substrate; The step of removing the sacrificial layer includes: removing the sacrificial layer to expose the sidewalls of the base region and the surface of the first seed layer; The step of growing an outer base region on the substrate on both sides of the base region by selective epitaxy includes: growing the outer base region on the sidewall of the base region and the surface of the first seed layer by selective epitaxy.

5. The method for forming a semiconductor device as described in claim 1, characterized in that, The step of forming outer base regions on the substrates on both sides of the base region includes: An outer base layer is formed on the substrate on both sides of the base region; The outer base layer, which is far from the base region, is removed to form the outer base region.

6. The method for forming a semiconductor device as described in claim 5, characterized in that, Also includes: After the emitter region is formed on the base region and before the sacrificial layer is removed, sacrificial sidewalls are formed on the sacrificial layers on both sides of the emitter region. The step of removing the sacrificial layer includes: removing the sacrificial layer to expose the sidewalls of the base region, and forming a lateral opening between the sacrificial sidewalls and the substrate; The step of forming an outer base layer on the substrates on both sides of the base region includes: forming an outer base layer on the substrates on both sides of the base region that fills the lateral opening; After forming an outer base layer that fills the lateral opening on the substrate on both sides of the base region, a portion of the outer base layer away from the base region is removed. Before forming the outer base region, the sacrificial sidewall is removed.

7. The method for forming a semiconductor device as described in claim 5, characterized in that, In the step of forming an outer base layer on the substrate on both sides of the base region, the thickness of the outer base layer on the side away from the base region is greater than the thickness of the outer base layer on the side closer to the base region.

8. The method for forming a semiconductor device as described in claim 1, characterized in that, Also includes: After the substrate is provided, and before the sacrificial layer is formed on the substrate, a first isolation structure is formed within the substrate; In the step of forming the first opening, the first opening is located within the first isolation structure, and the bottom of the first opening exposes the substrate below the first isolation structure.

9. The method for forming a semiconductor device as described in claim 8, characterized in that, In the step of providing a substrate, the substrate has a second isolation structure; The step of forming a first isolation structure in the substrate includes: forming a first isolation structure in the substrate between adjacent second isolation structures.

10. The method for forming a semiconductor device as described in claim 9, characterized in that, The step of forming a first isolation structure in the substrate includes: forming a first isolation structure in the substrate with a depth less than that of the second isolation structure.

11. The method for forming a semiconductor device as claimed in claim 1, characterized in that, Also includes: A base region is formed within the first opening in the current collector region, and a second opening is formed in the base region; The steps for forming a emitter region on the base region include: A first sidewall material layer is formed on the surface of the sacrificial layer away from the substrate, the sidewall of the second opening, and the surface of the base region away from the collector region; A second seed material layer is formed on the sidewall layer; Remove the second seed material layer and the first sidewall material layer from the sacrificial layer to form the second seed layer and the first sidewall. An emission layer is formed on the sacrificial layer, the second seed layer, and the first sidewall; Remove the emission layer on the sacrificial layer to form the emission region.

12. The method for forming a semiconductor device as claimed in claim 11, characterized in that, Also includes: In forming a sacrificial layer on the substrate, a second sidewall material layer is formed on the sacrificial layer; After forming the second seed layer and the first sidewall layer, the portion of the second sidewall material layer away from the first sidewall is removed to form the second sidewall.

13. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The base region is made of germanium silicon, the outer base region is made of polycrystalline silicon, and the sacrificial layer is made of silicon nitride.

14. A semiconductor device, characterized in that, include: Substrate; A current collector region, wherein the current collector region is located within the substrate; The base region is located on the collector region; A transmission region, which is located on the base region; An outer base region is located on the substrate on both sides of the base region, and the outer base region is connected to the sidewall of the base region.

15. The semiconductor device as claimed in claim 14, characterized in that, Also includes: A first isolation structure is located within the substrate, and a current collector region is located within the first isolation structure, with the current collector region extending through the first isolation structure along its thickness. The second isolation structure is located in the substrate on the side of the first isolation structure away from the collector region.

16. The semiconductor device as claimed in claim 15, characterized in that, The depth of the first isolation structure is less than the depth of the second isolation structure.

Images