Gallium oxide IGBT device and manufacturing method thereof

Abstract

The invention provides a gallium oxide IGBT (Insulated Gate Bipolar Translator) device and a manufacturing method thereof, and relates to the technical field of semiconductors, the gallium oxide IGBT device comprises a heavily doped P-type substrate, an N-type gallium oxide buffer layer, an N-type gallium oxide drift region, a P-type layer, an N-type carrier storage layer, a P-type well region and a doped contact region which are sequentially laminated; the doped contact region comprises a heavily doped N-type region and a heavily doped P-type region; the P-type layer, the N-type carrier storage layer and the P-type well region form a P-type body region; a gate groove is formed in the middle of the P-type body region; in the P-type body region, emitter deep trenches are symmetrically arranged on two sides with the gate trench as a symmetry axis. P-type layers are arranged at the bottoms of the grid electrode deep groove and the emitter electrode deep groove; the doped contact regions are located in the N-type carrier storage layer and symmetrically arranged on the two sides of the gate trench. Sacrificial breakdown voltage is avoided, and high conductive efficiency and stability of the device are ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gallium oxide IGBT device and its manufacturing method. Background Technology

[0002] Gallium oxide IGBTs (Ga2O3 IGBTs) are insulated-gate bipolar transistors (IGBTs) made of gallium oxide (Ga2O3). They combine the advantages of MOSFETs and bipolar junction transistors (BJTs), featuring high voltage, high efficiency, and low conduction losses. Gallium oxide's wide bandgap allows it to withstand higher voltages than silicon and maintain stable operation at high temperatures and high frequencies, making it suitable for high-voltage power electronic equipment, inverters, and high-efficiency power supplies.

[0003] Because gallium oxide (GaO) materials have higher breakdown voltage and lower conduction losses, they can operate at higher voltages and in smaller sizes, greatly improving the energy efficiency of power systems and reducing heat dissipation requirements. This makes GaO IGBTs an ideal choice for high-efficiency power supplies, high-voltage DC transmission, rail transportation, electric vehicles, and other fields, driving technological advancements in clean energy and electrification.

[0004] Currently, IGBT designs often employ high carrier injection into the N-type carrier storage layer to achieve low on-state voltage. While a lower on-state voltage is generally better, current IGBT devices primarily rely on the junction formed by the P-type well region and the N-type carrier storage layer for voltage withstand. A low on-state voltage requires high carrier injection into the N-type carrier storage layer, which necessitates increasing the doping concentration of the N-type carrier storage layer. However, high doping concentration significantly reduces the breakdown voltage of the IGBT device, leading to insufficient voltage withstand capability, susceptibility to breakdown, and inadequate stability. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a gallium oxide IGBT device that can solve the technical problems of the present invention. The current IGBT devices mainly rely on the junction formed by the P-type well region and the N-type carrier storage layer for voltage bearing. The low conduction voltage requires high carrier injection of the N-type carrier storage layer, that is, increasing the doping concentration of the N-type carrier storage layer. The high doping concentration will greatly reduce the breakdown voltage of the IGBT device, resulting in insufficient voltage bearing capacity, easy breakdown, and insufficient stability of the IGBT device.

[0006] A first aspect of this invention provides a gallium oxide IGBT device, comprising:

[0007] The heavily doped P-type substrate, N-type gallium oxide buffer layer, N-type gallium oxide drift region, P-type layer, N-type carrier storage layer, P-type well region and doped contact region are stacked sequentially.

[0008] The doped contact region includes heavily doped N-type regions and heavily doped P-type regions;

[0009] The P-type body region is composed of a P-type layer, an N-type carrier storage layer, and a P-type well region.

[0010] A gate trench is provided in the middle of the P-type body region, wherein the gate trench penetrates the P-type body region and contacts the N-type gallium oxide drift region;

[0011] In the P-type body region, emitter deep trenches are symmetrically arranged on both sides with the gate trench as the axis of symmetry, wherein the depth of the emitter deep trench is greater than the depth of the gate trench in the first direction.

[0012] A P-type layer is provided at the bottom of both the gate trench and the emitter deep trench;

[0013] The doped contact regions are located in the N-type carrier storage layer and are symmetrically arranged on both sides of the gate trench.

[0014] A second aspect of this invention provides a method for manufacturing a gallium oxide IGBT device, comprising:

[0015] S1: An N-type gallium oxide buffer layer, an N-type gallium oxide drift region, and a P-type bulk region are sequentially grown on a heavily doped P-type substrate;

[0016] S2: Combine a feedback control algorithm based on tunneling current to create gate trenches and emitter deep trenches in the P-type body region.

[0017] S3: A P-type layer is generated at the bottom of the gate trench and the bottom of the emitter deep trench by ion implantation;

[0018] S4: At a preset time interval, polysilicon deposition is performed in the gate trench and emitter deep trench to generate the emitter and gate.

[0019] S5: A doped contact region, namely a heavily doped N-type layer and a heavily doped P-type layer, is generated above the P-type well region by ion implantation.

[0020] S6: Deposit gate metal and emitter metal to obtain gallium oxide IGBT device.

[0021] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0022] In this embodiment of the invention, the gallium oxide IGBT device has emitter deep trenches symmetrically arranged on both sides of the gate trench as the axis of symmetry, wherein the depth of the emitter deep trenches is greater than the depth of the gate trench in a first direction. Furthermore, a P-type layer is disposed at the bottom of the gate trench and the emitter deep trench, thereby forming a self-controlled PMOS device composed of a P-type layer, an N-type carrier storage layer, and a P-type well region. When the potential rises to the self-controlled PMOS threshold voltage, a hole channel is formed in the N-type carrier storage layer near the emitter trench, causing the self-controlled PMOS to automatically conduct. This hole channel connects the P-type layer and the emitter to form a voltage clamping path for the N-type carrier storage layer, ensuring that the clamped N-type carrier storage layer has a consistently low potential, allowing for the use of higher doping concentrations. Additionally, the voltage-bearing region can be led from the near end of the gate to a voltage-bearing junction formed by the P-type layer and the N-type gallium oxide drift region, away from the gate. This prevents a high electric field from appearing in the region near the gate, thereby protecting the N-type carrier storage layer and ensuring that its breakdown performance is not compromised even with a high doping concentration. Furthermore, the transfer of the voltage-bearing junction can also protect against gate oxide damage caused by a strong electric field accumulating near the gate, thus improving device lifetime. Consequently, even with high carrier injection, it maintains low on-resistance while avoiding sacrificing breakdown voltage, thereby ensuring high conductivity and stability of the device. Attached Figure Description

[0023] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a gallium oxide IGBT device provided in an embodiment of the present invention;

[0025] Figure 2 This is an equivalent circuit diagram of a gallium oxide IGBT device provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic flowchart of a gallium oxide IGBT device manufacturing method provided in an embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] The gallium oxide IGBT device provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0029] Reference manual attached Figure 1 The diagram shows a schematic representation of a gallium oxide IGBT device according to an embodiment of the present invention.

[0030] Reference manual attached Figure 2 The diagram shows an equivalent circuit diagram of a gallium oxide IGBT device provided in an embodiment of the present invention.

[0031] This invention provides a gallium oxide IGBT device, comprising: a heavily doped P-type substrate, an N-type gallium oxide buffer layer, an N-type gallium oxide drift region, a P-type layer, an N-type carrier storage layer, a P-type well region, and a doped contact region stacked sequentially. The doped contact region includes a heavily doped N-type region and a heavily doped P-type region. The P-type layer, the N-type carrier storage layer, and the P-type well region constitute a P-type body region. A gate trench is disposed in the middle of the P-type body region, wherein the gate trench penetrates the P-type body region and contacts the N-type gallium oxide drift region. Emitter deep trenches are symmetrically disposed on both sides of the gate trench in the P-type body region, wherein the depth of the emitter deep trenches is greater than the depth of the gate trench in a first direction. A P-type layer is disposed at the bottom of both the gate trench and the emitter deep trenches. The doped contact region is located in the N-type carrier storage layer and is symmetrically disposed on both sides of the gate trench.

[0032] The heavily doped P-type substrate serves as the base of the entire device, providing fundamental support for the semiconductor and the main structure for current flow. The heavily doped P-type substrate has low resistance, ensuring low loss and high efficiency in the conductive state. The N-type gallium oxide buffer layer connects the gallium oxide drift region and the P-type substrate, providing a suitable electric field distribution and effectively reducing the reverse interface current between the P-type substrate and the N-type gallium oxide drift region. The N-type gallium oxide drift region is the main current-carrying region of the device, determining its breakdown voltage (BV). The use of N-type gallium oxide improves the conductivity of this region, and the larger band gap of gallium oxide helps enhance the breakdown voltage, enabling the IGBT device to operate at higher voltages. The P-type layer is a key component of the device, forming a self-controlled pMOS element together with the N-type carrier storage layer and the P-type well region. This structure provides current control and clamping. The N-type carrier storage layer stores carriers and regulates the current. The P-type well region forms the reverse blocking region of the device, which, together with the N-type gallium oxide drift region, ensures that current is blocked in the off-state. This guarantees low leakage current when the device is off, improving its turn-off performance. The doped contact region, comprising heavily doped N-type and P-type regions, provides low-resistance contact, allowing for efficient current flow. It also helps guide current to the emitter and collector contact layers, ensuring good conductivity during operation. The gate trench forms the gate control region, penetrating the P-type body region and contacting the N-type gallium oxide drift region. After depositing a metal gate in the gate trench, the gate voltage controls the electric field under the gate, thereby controlling the on / off state of the MOS structure. The gate trench not only controls conduction but also, in conjunction with the emitter deep trench, further enhances current extraction capability and switching efficiency. The emitter deep trench, located on both sides of the gate trench and with a depth greater than the gate trench, ensures more efficient current extraction. These deep trenches provide low-resistance current paths, enhancing the device's current carrying capacity. At the bottom of the emitter trench, the P-type layer helps regulate current flow and forms a clamping path with the N-type carrier storage layer.

[0033] Specifically, this gallium oxide IGBT device introduces a deep emitter trench and a P-type layer, thereby forming a self-controlled PMOS device consisting of a P-type layer, an N-type carrier storage layer, and a P-type well region. This allows the equivalent circuit diagram of the entire gallium oxide IGBT device to integrate NMOS, PMOS, and PNP elements.

[0034] In both on and off states, when the collector potential increases, the potentials of the N-type carrier storage layer and the N-type gallium oxide drift region also increase. When the potential rises above the PMOS threshold, a hole channel is formed in the N-type carrier storage layer near the emitter trench, turning on the PMOS. At this point, the hole channel connects the P-type layer and the emitter, effectively maintaining the P-type layer and the N-type carrier storage layer at a lower potential.

[0035] Specifically, when the device is off, the pressure-bearing region mainly relies on the pressure-bearing junction J2 formed by the P-type layer and the N-type gallium oxide drift region, instead of the gate near-end pressure-bearing junction J1 formed by the P-well region and the N-type carrier storage layer. The resulting self-controlled pmos ensures that a high electric field does not appear in the gate near-end region of the device, thereby protecting the N-type carrier storage layer. Even with high doping concentration, the breakdown performance will not be damaged.

[0036] Specifically, when the device is turned on, the PMOS transistor automatically turns on as the collector potential increases, and the clamping of the N-type carrier storage layer depends on the PMOS threshold voltage. Since the N-type carrier storage layer is the intrinsic drain of the PMOS transistor, maintaining a low potential allows the device to operate at a low saturation current, improving short-circuit characteristics. In other words, based on the protective effect of this structure, it is possible to maintain a highly doped N-type carrier storage layer while effectively reducing the turn-on voltage and improving the device's conductivity.

[0037] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0038] In this embodiment of the invention, the gallium oxide IGBT device has emitter deep trenches symmetrically arranged on both sides of the gate trench as the axis of symmetry, wherein the depth of the emitter deep trenches is greater than the depth of the gate trench in a first direction. Furthermore, a P-type layer is disposed at the bottom of the gate trench and the emitter deep trench, thereby forming a self-controlled PMOS device composed of a P-type layer, an N-type carrier storage layer, and a P-type well region. When the potential rises to the self-controlled PMOS threshold voltage, a hole channel is formed in the N-type carrier storage layer near the emitter trench, causing the self-controlled PMOS to automatically conduct. This hole channel connects the P-type layer and the emitter to form a voltage clamping path for the N-type carrier storage layer, ensuring that the clamped N-type carrier storage layer has a consistently low potential, allowing for the use of higher doping concentrations. Additionally, the voltage-bearing region can be led from the near end of the gate to a voltage-bearing junction formed by the P-type layer and the N-type gallium oxide drift region, away from the gate. This prevents a high electric field from appearing in the region near the gate, thereby protecting the N-type carrier storage layer and ensuring that its breakdown performance is not compromised even with a high doping concentration. Furthermore, the transfer of the voltage-bearing junction can also protect against gate oxide damage caused by a strong electric field accumulating near the gate, thus improving device lifetime. Consequently, even with high carrier injection, it maintains low on-resistance while avoiding sacrificing breakdown voltage, thereby ensuring high conductivity and stability of the device.

[0039] In one possible implementation, the doped contact region includes a heavily doped N-type layer and a heavily doped P-type layer. Both the heavily doped N-type layer and the heavily doped P-type layer are disposed above the P-type well region. The distance between the heavily doped N-type layer and the gate trench is smaller than the distance between the heavily doped P-type layer and the gate trench.

[0040] It should be noted that the doped contact region includes heavily doped N-type and P-type layers, which are located above the P-type well region. The smaller distance between the heavily doped N-type layer and the gate trench means that the current path in this region is closer to the gate, enhancing current controllability. Conversely, the larger distance between the heavily doped P-type layer and the gate trench allows for a more extensive distribution of the P-type layer's control region. This structure helps optimize current flow and device conduction performance.

[0041] In one possible implementation, both the emitter trench and the gate trench are filled with polysilicon to form the emitter and the gate.

[0042] Understandably, both the emitter trench and the gate trench are filled with polysilicon, which effectively forms the emitter and gate. As a conductive material, polysilicon not only ensures good electrical contact but also improves the device's conductivity and switching efficiency. By filling with polysilicon, the gate and emitter can more stably control current flow, enhancing the overall performance and reliability of the device.

[0043] In one possible implementation, the P-type layer, the N-type carrier storage layer, the P-type well region, and the emitter constitute a self-controlled PMOS device, wherein the source of the self-controlled PMOS device is connected to the collector of the gallium oxide IGBT device, and the drain of the self-controlled PMOS device is connected to the emitter of the gallium oxide IGBT device.

[0044] The N-type gallium oxide drift region, P-type well region, gate, and emitter constitute a gate-controlled NMOS device. The source of the gate-controlled NMOS device is connected to the emitter of the gallium oxide IGBT device, and the drain of the gate-controlled NMOS device is connected to the collector of the gallium oxide IGBT device.

[0045] A PNP device consists of a P-type well region, an N-type carrier storage layer, and an N-type gallium oxide drift region. The P-type well region is the emitter of the PNP device, the N-type carrier storage layer is the base of the PNP device, and the N-type gallium oxide drift region is the collector of the PNP device.

[0046] The equivalent circuit of a gallium oxide IGBT device is formed by the combination of a self-controlled PMOS element, a gate-controlled NMOS element, and a PNP element.

[0047] The self-controlled pMOS device consists of a P-type layer, an N-type carrier storage layer, a P-type well region, and an emitter. The source and collector of the self-controlled pMOS device are connected, and the drain is connected to the emitter of the IGBT. Its main function is to control current clamping through gate voltage, automatically turning on at high voltages to ensure low saturation current and improve conductivity. The gate-controlled nMOS device consists of an N-type gallium oxide drift region, a P-type well region, a gate, and an emitter. The source and emitter of the gate-controlled nMOS device are connected, and the drain and collector are connected. The gate voltage controls the on / off state of the nMOS device, acting as a current switch and enhancing the switching speed and efficiency of the device. The PNP device consists of a P-type well region, an N-type carrier storage layer, and an N-type gallium oxide drift region. The P-type well region is the emitter, the N-type carrier storage layer is the base, and the N-type gallium oxide drift region is the collector. The PNP device provides current gain, allowing current to flow more efficiently from the emitter to the collector, enhancing the device's short-circuit withstand capability and stability.

[0048] It should be noted that this structure combines a self-controlled pMOS, a gate-controlled nMOS, and a PNP element to form an optimized equivalent circuit. This achieves low saturation current, high current carrying capacity, fast switching, and improved thermal stability. The complementary characteristics of the self-controlled pMOS and the gate-controlled nMOS effectively improve conductivity and turn-off losses, while the current gain of the PNP element enhances the device's short-circuit tolerance and reliability. This design gives the gallium oxide IGBT device excellent performance and long-term stability, making it suitable for high-power, high-frequency applications.

[0049] In one possible implementation, it further includes: gate metal disposed above the gate and emitter metal disposed above the emitter.

[0050] It should be noted that the gate metal is disposed above the gate and is responsible for providing the control voltage to regulate the switching state. The emitter metal is disposed above the emitter to ensure that current flows in from the emitter, forming a low-resistance current path. Together, these two elements improve the device's conductivity, switching speed, and overall performance.

[0051] In one possible implementation, the heavily doped P-type substrate is specifically a heavily doped P-type nickel oxide substrate or a heavily doped P-type copper oxide substrate.

[0052] It should be noted that heavily doped P-type substrates use nickel oxide or copper oxide as substrate materials. These materials have good conductivity and stability, which can improve the current carrying capacity and thermal management efficiency of the device, while also enhancing the device's breakdown resistance.

[0053] Specifically, this gallium oxide IGBT device employs a precise stacked structure design, including a heavily doped P-type substrate, an N-type gallium oxide buffer layer, an N-type gallium oxide drift region, a P-type layer, an N-type carrier storage layer, a P-type well region, and doped contact regions, forming a combination of a self-controlled pMOS, a gate-controlled nMOS, and a PNP element. This structure provides low saturation current, high current carrying capacity, and good switching efficiency. The complementary effects of the self-controlled pMOS and the gate-controlled nMOS optimize current clamping and switching performance, while the current gain of the PNP element improves short-circuit tolerance and device stability. Furthermore, the high breakdown voltage of gallium oxide material enables the device to operate stably at high voltages, comprehensively improving the device's efficiency, thermal stability, and long-term reliability, making it suitable for high-power and high-frequency applications.

[0054] Reference manual attached Figure 3 The diagram shows a flow chart of a gallium oxide IGBT device manufacturing method provided by an embodiment of the present invention.

[0055] S1: An N-type gallium oxide buffer layer, an N-type gallium oxide drift region, and a P-type body region are sequentially grown on a heavily doped P-type substrate.

[0056] It should be noted that, firstly, an N-type gallium oxide buffer layer is grown on the P-type substrate, providing an interface with good electrical performance. Subsequently, an N-type gallium oxide drift region is grown, serving as the primary current-carrying region. Finally, a P-type body region is grown to form a self-controlled pMOS device, providing current control and clamping functions. This process ensures the device's high voltage tolerance and high efficiency.

[0057] S2: Combine a feedback control algorithm based on tunneling current to create gate trenches and emitter deep trenches on the P-type body region.

[0058] Tunneling current refers to the current generated when electrons or holes pass through a potential barrier (such as an oxide layer). Even when electrons or holes lack sufficient energy to overcome the barrier, they still have a certain probability of passing through; this phenomenon is called tunneling. In semiconductor devices, tunneling current often occurs in regions such as the gate oxide layer or pn junction, affecting the device's leakage current and performance.

[0059] It should be noted that, by combining a feedback control algorithm based on tunneling current, gate trenches and emitter deep trenches are formed in the P-type body region. Through the feedback mechanism of tunneling current, the etching depth and rate of the trenches can be accurately calculated. The core of this step is to dynamically adjust the etching process by changing the tunneling current, ensuring precise etching of the gate trenches and emitter deep trenches, thereby optimizing the trench geometry and improving the switching performance and reliability of the device. This control algorithm avoids the problems of over-etching or uneven etching.

[0060] In one possible implementation, S2 specifically includes:

[0061] S201: Etching trenches of a predetermined depth in the P-type body region, wherein the trenches include gate trenches and emitter deep trenches.

[0062] It should be noted that those skilled in the art can set the preset depth according to actual needs, and this invention does not limit it. It is understood that this preset depth is much smaller than the target etching depth of the gate trench and emitter deep trench.

[0063] S202: Calculate the tunneling current of the trench sidewall under the preset voltage.

[0064] The specific formula for calculating tunneling current is as follows:

[0065]

[0066] Where d represents the trench etching depth, φ represents the material barrier height, and m * I0 represents the effective mass of the material, I0 represents the initial value of the tunneling current associated with the material, and exp represents the natural exponential function. t (d) represents the tunneling current at time t when the trench etching depth is d. This represents the reduced Planck constant.

[0067] For example, gallium nitride has a material barrier height of approximately 4.0 eV and an effective material mass of approximately 0.34 m. e m e It represents the mass of free electrons.

[0068] It should be noted that those skilled in the art can set the preset voltage according to actual needs, and this invention does not limit this. For example, for gallium nitride, a small voltage in the range of 0.1-0.5V can be applied.

[0069] It should be noted that by calculating the tunneling current, the current characteristics of the trench sidewalls at different etching depths can be accurately evaluated, thereby optimizing the etching process. Utilizing the relationship between tunneling current and etching depth, the etching rate can be effectively controlled, over-etching can be avoided, and the accuracy of the trench can be improved. Furthermore, the flexible setting of the preset voltage allows this method to adapt to different materials (such as gallium nitride), improving the accuracy and consistency of etching control and ensuring the efficiency and reliability of the device fabrication process.

[0070] S203: Calculate the etching rate and trench sidewall inclination angle based on the tunneling current.

[0071] The specific formula for calculating the etching rate is as follows.

[0072]

[0073] Among them, Re The etching rate is represented by k, and the process constant related to the etching machine is represented by d. target Let d(t) represent the target etching depth of the trench, d(t) represent the trench etching depth at time t, and || represent taking the absolute value.

[0074] Specifically, when the etching depth approaches the target depth, the etching rate automatically decreases to avoid over-etching. For deep emitter trenches (requiring deeper etching), the algorithm automatically extends the high etching rate phase.

[0075] The specific formula for calculating the trench sidewall inclination angle is as follows:

[0076]

[0077] Where θ represents the trench sidewall inclination angle, arctan represents the arctangent function, and ΔI t Δx represents the tunneling current difference corresponding to different etching depths, Δy represents the lateral distance between points at different etching depths, and Δy represents the longitudinal distance between points at different etching depths.

[0078] It should be noted that this process calculates the etching rate and trench sidewall tilt angle to optimize the etching process. First, the etching rate is calculated based on the tunneling current variation. The formula takes into account the difference between the target depth and the actual etching depth, automatically adjusting the etching rate to prevent over-etching. For deep trenches, the algorithm extends the high-speed etching stage to ensure accurate etching. Second, by calculating the sidewall tilt angle, the shape of the trench sidewall is determined using the variation of the tunneling current at different etching depths. Etching parameters such as ion energy and passivation gas ratio are adjusted to obtain a uniform trench shape, ensuring the stability and performance of the device.

[0079] S204: Adjust the etching parameters according to the trench sidewall inclination angle. The etching parameters include ion bombardment energy and passivation gas ratio.

[0080] In one possible implementation, S204 specifically includes:

[0081] If the trench sidewall inclination angle is less than the preset trench sidewall inclination angle, increase the ion bombardment energy; otherwise, reduce the ion bombardment energy and increase the passivation gas ratio until the trench sidewall inclination angle is consistent with the preset trench sidewall inclination angle.

[0082] It should be noted that those skilled in the art can set the size of the preset trench sidewall inclination angle according to actual needs, and the present invention does not limit this.

[0083] S205: Etch according to the etching rate and etching parameters to obtain the gate trench and emitter deep trench.

[0084] Specifically, firstly, by calculating the tunneling current and considering the relationship between voltage and etching depth, the current variation on the trench sidewalls is determined. Then, by analyzing the relationship between the tunneling current and etching rate, the etching rate and the trench sidewall tilt angle are calculated to ensure uniform etching and avoid over-etching. In adjusting etching parameters, the ion bombardment energy and passivation gas ratio are adjusted based on the sidewall tilt angle to optimize the etching effect. Finally, through precise etching, the gate and emitter trenches are ensured to reach the predetermined depth and shape. A feedback control algorithm dynamically adjusts the etching process to avoid errors, ensuring the stability and efficiency of device performance, while simultaneously optimizing the current control path and trench structure to improve the device's switching speed and conductivity.

[0085] S3: A P-type layer is generated at the bottom of the gate trench and the bottom of the emitter deep trench by ion implantation.

[0086] It should be noted that a P-type layer is generated at the bottom of the gate trench and the emitter deep trench via ion implantation. In this process, specific P-type ions (such as boron ions) are implanted into the bottom of the gate trench and emitter deep trench to alter the conductivity of that region, forming a P-type layer. This P-type layer acts as a current regulator and clamping agent in the device, ensuring its conductivity, switching performance, and stability. The depth of ion implantation and the doping concentration determine the electrical characteristics of the P-type layer, directly affecting the device's efficiency and reliability.

[0087] S4: At a preset time interval, polysilicon deposition is performed in the gate trench and emitter deep trench to generate the emitter and gate.

[0088] It should be noted that those skilled in the art can set the preset duration according to actual needs, and this invention does not impose any limitations on it. The preset duration is set to ensure sufficient formation of the oxide layer.

[0089] S5: A doped contact region, namely a heavily doped N-type layer and a heavily doped P-type layer, is generated above the P-type well region by ion implantation.

[0090] Understandably, above the P-type well region, a doped contact region, namely a heavily doped N-type layer and a heavily doped P-type layer, is generated through ion implantation. This process creates a highly conductive contact region above the P-type well region by implanting a high concentration of N-type and P-type ions. The heavily doped N-type and P-type layers provide a low-resistance current path for the device, ensuring efficient current flow and contributing to the electrical contact and stability of the device. This step is crucial for improving the device's conductivity, reducing contact resistance, and enhancing operating efficiency.

[0091] S6: Deposit gate metal and emitter metal to obtain gallium oxide IGBT device.

[0092] It should be noted that above the P-type well region, a doped contact region, namely a heavily doped N-type layer and a heavily doped P-type layer, is generated through ion implantation. This process, by implanting high concentrations of N-type and P-type ions, forms a highly conductive contact region above the P-type well region. The heavily doped N-type and P-type layers provide a low-resistance current path for the device, ensuring efficient current flow and contributing to the electrical contact and stability of the device. This step is crucial for improving the device's conductivity, reducing contact resistance, and enhancing operating efficiency.

[0093] In one possible implementation, after S6, the following is also included:

[0094] Pretreatment of the gate metal and emitter metal includes chemical polishing and mechanical polishing.

[0095] Understandably, pretreatment with chemical and mechanical polishing is necessary for both the gate and emitter metals. This process removes irregularities and excess material from the metal surfaces, ensuring the smoothness and conductivity of the metal layer. Polishing improves the quality of metal contacts, enhancing the device's current transport efficiency and long-term stability.

[0096] In practical applications, each step, from substrate growth and trench etching to metal deposition, is precisely controlled to optimize device performance. First, a heavily doped P-type substrate and an N-type gallium oxide buffer layer provide stable electrical support and high voltage tolerance for the device. Next, a feedback control algorithm based on tunneling current is used to precisely etch the gate trench and emitter deep trench, ensuring that the trench shape and depth meet requirements. Ion implantation generates a P-type layer to further regulate current flow. Subsequently, polysilicon is deposited to form the gate and emitter, providing good electrical contact and high conductivity. Finally, metal deposition and polishing ensure the stability of the current path and the long-term reliability of the device. This entire process optimizes the current control path, improves switching performance and conductivity, enabling the gallium oxide IGBT device to achieve high-power, high-frequency applications.

[0097] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0098] In this embodiment of the invention, the gallium oxide IGBT device has emitter deep trenches symmetrically arranged on both sides of the gate trench as the axis of symmetry, wherein the depth of the emitter deep trenches is greater than the depth of the gate trench in a first direction. Furthermore, a P-type layer is disposed at the bottom of the gate trench and the emitter deep trench, thereby forming a self-controlled PMOS device composed of a P-type layer, an N-type carrier storage layer, and a P-type well region. When the potential rises to the self-controlled PMOS threshold voltage, a hole channel is formed in the N-type carrier storage layer near the emitter trench, causing the self-controlled PMOS to automatically conduct. This hole channel connects the P-type layer and the emitter to form a voltage clamping path for the N-type carrier storage layer, ensuring that the clamped N-type carrier storage layer has a consistently low potential, allowing for the use of higher doping concentrations. Additionally, the voltage-bearing region can be led from the near end of the gate to a voltage-bearing junction formed by the P-type layer and the N-type gallium oxide drift region, away from the gate. This prevents a high electric field from appearing in the region near the gate, thereby protecting the N-type carrier storage layer and ensuring that its breakdown performance is not compromised even with a high doping concentration. Furthermore, the transfer of the voltage-bearing junction can also protect against gate oxide damage caused by a strong electric field accumulating near the gate, thus improving device lifetime. Consequently, even with high carrier injection, it maintains low on-resistance while avoiding sacrificing breakdown voltage, thereby ensuring high conductivity and stability of the device.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A gallium oxide IGBT device, characterized in that, include: The heavily doped P-type substrate, N-type gallium oxide buffer layer, N-type gallium oxide drift region, P-type layer, N-type carrier storage layer, P-type well region and doped contact region are stacked sequentially. The doped contact region includes a heavily doped N-type region and a heavily doped P-type region; The P-type layer, the N-type carrier storage layer, and the P-type well region constitute a P-type body region; A gate trench is provided at the middle position of the P-type body region, wherein the gate trench penetrates the P-type body region and contacts the N-type gallium oxide drift region; In the P-type body region, emitter deep trenches are symmetrically arranged on both sides with the gate trench as the axis of symmetry, wherein the depth of the emitter deep trench is greater than the depth of the gate trench in the first direction. The bottom of both the gate trench and the emitter trench is provided with the P-type layer; The doped contact region is located in the N-type carrier storage layer and is symmetrically arranged on both sides of the gate trench.

2. The gallium oxide IGBT device according to claim 1, characterized in that, The doped contact region includes a heavily doped N-type layer and a heavily doped P-type layer; Both the heavily doped N-type layer and the heavily doped P-type layer are disposed above the P-type well region; The distance between the heavily doped N-type layer and the gate trench is less than the distance between the heavily doped P-type layer and the gate trench.

3. The gallium oxide IGBT device according to claim 1, characterized in that, Both the emitter trench and the gate trench are filled with polysilicon to form the emitter and the gate.

4. The gallium oxide IGBT device according to claim 3, characterized in that, The P-type layer, the N-type carrier storage layer, the P-type well region, and the emitter constitute a self-controlled PMOS element, wherein the source of the self-controlled PMOS element is connected to the collector of the gallium oxide IGBT device, and the drain of the self-controlled PMOS element is connected to the emitter of the gallium oxide IGBT device. The N-type gallium oxide drift region, the P-type well region, the gate, and the emitter constitute a gate-controlled NMOS device. The source of the gate-controlled NMOS device is connected to the emitter of the gallium oxide IGBT device, and the drain of the gate-controlled NMOS device is connected to the collector of the gallium oxide IGBT device. The P-type well region, the N-type carrier storage layer, and the N-type gallium oxide drift region constitute a PNP element, wherein the P-type well region is the emitter of the PNP element, the N-type carrier storage layer is the base of the PNP element, and the N-type gallium oxide drift region is the collector of the PNP element. The self-controlled PMOS element, the gate-controlled NMOS element, and the PNP element together form the equivalent circuit of the gallium oxide IGBT device.

5. The gallium oxide IGBT device according to claim 3, characterized in that, Also includes: Gate metal disposed above the gate and emitter metal disposed above the emitter.

6. The gallium oxide IGBT device according to claim 1, characterized in that, The heavily doped P-type substrate is specifically a heavily doped P-type nickel oxide substrate or a heavily doped P-type copper oxide substrate.

7. A method for manufacturing a gallium oxide IGBT device, characterized in that, Applied to the gallium oxide IGBT device according to any one of claims 1 to 6; the method includes: S1: The N-type gallium oxide buffer layer, the N-type gallium oxide drift region, and the P-type body region are sequentially grown on the heavily doped P-type substrate; S2: The gate trench and the emitter deep trench are formed on the P-type body region by combining a feedback control algorithm based on tunneling current. S3: The P-type layer is generated at the bottom of the gate trench and the bottom of the emitter deep trench by ion implantation; S4: At a preset time interval, polysilicon deposition is performed in the gate trench and the emitter deep trench to generate the emitter and gate; S5: The doped contact region, namely the heavily doped N-type layer and the heavily doped P-type layer, is generated above the P-type well region by ion implantation. S6: Deposit gate metal and emitter metal to obtain the gallium oxide IGBT device.

8. The method for manufacturing a gallium oxide IGBT device according to claim 7, characterized in that, S2 specifically includes: S201: Etching a trench of a predetermined depth in the P-type body region, wherein the trench includes the gate trench and the emitter deep trench; S202: Calculate the tunneling current of the trench sidewall under a preset voltage; S203: Calculate the etching rate and trench sidewall inclination angle based on the tunneling current; S204: Adjust the etching parameters according to the trench sidewall inclination angle, wherein the etching parameters include ion bombardment energy and passivation gas ratio; S205: Etch according to the etching rate and the etching parameters to obtain the gate trench and the emitter deep trench.

9. The method for manufacturing a gallium oxide IGBT device according to claim 8, characterized in that, Specifically, S204 is: If the inclination angle of the trench sidewall is less than the preset inclination angle of the trench sidewall, the ion bombardment energy is increased; otherwise, the ion bombardment energy is reduced and the passivation gas ratio is increased until the inclination angle of the trench sidewall is consistent with the preset inclination angle of the trench sidewall.

10. The method for manufacturing a gallium oxide IGBT device according to claim 7, characterized in that, Following S6, it also includes: The gate metal and the emitter metal undergo pretreatment including chemical polishing and mechanical polishing.

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