Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same for improving short circuit tolerance. A semiconductor device includes a semiconductor substrate including a drift layer, first and second base layers provided side by side on an upper surface side of the drift layer, and a source layer and a contact layer selectively provided on the upper surface side of the second base layer and having higher impurity concentrations than the first base layer and the second base layer, respectively. The semiconductor device is further provided with: a gate oxide film provided on the first base layer, the second base layer, the source layer, and the contact layer; a gate electrode provided on the gate oxide film; an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing a part of the source layer and a plurality of second contact holes exposing a part of the contact layer; a source electrode connected to the source layer via the first contact hole and connected to the contact layer via the second contact hole; and a drain electrode connected to the lower surface side of the drift layer. The first and second contact holes are separated by an interlayer insulating film.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] Patent document 1 discloses a planar SiC-MOSFET. Since planar MOSFETs have smaller parasitic capacitances compared to trench MOSFETs, they are suitable for high-speed driving applications.

[0003] Patent Document 1: Japanese Patent Application Publication No. 10-233503

[0004] However, in planar MOSFETs, since the repeating direction of the cells is the same as the length direction of the channel, the channel length needs to be shortened when the cell spacing is reduced. As a result, there is a problem of reduced short-circuit withstand capability. Summary of the Invention

[0005] In order to solve the above-mentioned problems, the present disclosure aims to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve short-circuit withstand capability.

[0006] The first aspect of this disclosure relates to a semiconductor device comprising: a semiconductor substrate having a drift layer of a first conductivity type, a first base layer of a first conductivity type and a second base layer of a second conductivity type disposed side-by-side on the upper surface side of the drift layer, a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the first base layer, and a contact layer of a second conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the second base layer; a gate oxide film disposed on the first base layer, the second base layer, the source layer and the contact layer; a gate electrode disposed on the gate oxide film; an interlayer insulating film disposed on the semiconductor substrate such that it covers the gate oxide film and the gate electrode and having a plurality of first contact holes exposing a portion of the source layer and a plurality of second contact holes exposing a portion of the contact layer; a source electrode connected to the source layer via the first contact holes and connected to the contact layer via the second contact holes; and a drain electrode connected to the lower surface side of the drift layer, wherein the first contact holes and the second contact holes are separated by the interlayer insulating film.

[0007] The second aspect of this disclosure relates to a semiconductor device comprising: a semiconductor substrate having a drift layer of a first conductivity type, a first base layer of a first conductivity type and a second base layer of a second conductivity type disposed side-by-side on the upper surface of the drift layer, a source layer of a first conductivity type selectively disposed on the upper surface of the second base layer and having an impurity concentration higher than that of the first base layer, and a contact layer of a second conductivity type selectively disposed on the upper surface of the second base layer and having an impurity concentration higher than that of the second base layer; a gate oxide film disposed on the first base layer, the second base layer, the source layer and the contact layer; and a gate electrode disposed on the gate oxide film. Above; an interlayer insulating film is disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and has a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer; a source electrode is connected to the source layer via the first contact holes and to the contact layer via the second contact holes; and a drain electrode is connected to the lower surface side of the drift layer, wherein the openings of the first contact holes and the openings of the second contact holes are alternately arranged facing a first direction when viewed from above, and the width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction.

[0008] The third aspect of this disclosure relates to a method for manufacturing a semiconductor device, comprising: a step of forming a drift layer of a first conductivity type on a semiconductor substrate; a step of forming a first base layer of the first conductivity type by ion implantation of a first impurity on the upper surface side of the drift layer; a step of forming a second base layer of the second conductivity type disposed side-by-side with the first base layer on the upper surface side of the drift layer by forming a first mask on the upper surface side of the first base layer and ion implanting a second impurity; a step of forming a thin film on the upper surface and sidewalls of the first mask and the upper surface of the second base layer; a step of forming a second mask having the first mask by etching the thin film; a step of forming a source layer of the first conductivity type selectively disposed on the upper surface side of the second base layer by ion implantation of a first impurity on the upper surface side of the second base layer and the second mask; and a step of removing a second impurity. The process includes: a masking process; a process of forming a second conductivity type contact layer selectively disposed on the upper surface of the second base layer by selectively ion implanting a second impurity on the upper surface side of the source layer; a process of forming a gate oxide film on the first base layer, the second base layer, the source layer, and the contact layer; a process of forming a gate electrode on the gate oxide film; a process of forming an interlayer insulating film disposed on the semiconductor substrate in a manner covering the gate oxide film and the gate electrode, having a plurality of first contact holes exposing a portion of the source layer and a plurality of second contact holes exposing a portion of the contact layer; a process of forming a source electrode connected to the source layer via the first contact holes and connected to the contact layer via the second contact holes; and a process of forming a drain electrode on the lower surface side of the drift layer, wherein the first contact holes and the second contact holes are separated by the interlayer insulating film.

[0009] The fourth aspect of this disclosure relates to a method for manufacturing a semiconductor device, comprising: a step of forming a drift layer of a first conductivity type on a semiconductor substrate; a step of forming a first base layer of the first conductivity type by ion implantation of a first impurity on the upper surface side of the drift layer; a step of forming a second base layer of the second conductivity type disposed side-by-side with the first base layer on the upper surface side of the drift layer by forming a first mask on the upper surface side of the first base layer and ion implanting a second impurity; a step of forming a thin film on the upper surface and sidewalls of the first mask and the upper surface of the second base layer; a step of forming a second mask having the first mask by etching the thin film; a step of forming a source layer of the first conductivity type selectively disposed on the upper surface side of the second base layer by ion implantation of a first impurity on the upper surface side of the second base layer and the second mask; a step of removing the second mask; and a step of selectively ion implanting a second impurity on the upper surface side of the source layer. The process includes: forming a second conductivity type contact layer selectively disposed on the upper surface side of the second base layer; forming a gate oxide film on the first base layer, the second base layer, the source layer, and the contact layer; forming a gate electrode on the gate oxide film; forming an interlayer insulating film disposed on the semiconductor substrate in a manner covering the gate oxide film and the gate electrode, and having a plurality of first contact holes exposing a portion of the source layer and a plurality of second contact holes exposing a portion of the contact layer; forming a source electrode connected to the source layer via the first contact holes and connected to the contact layer via the second contact holes; and forming a drain electrode on the lower surface side of the drift layer, wherein the openings of the first contact holes and the openings of the second contact holes are alternately arranged facing a first direction when viewed from above, and the width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction.

[0010] According to the first to fourth embodiments of this disclosure, the area of ​​the source layer connected to the source electrode through multiple first contact holes is reduced. As a result, the short-circuit withstand capability can be improved. Attached Figure Description

[0011] Figure 1 This is a top view showing the configuration of the semiconductor device according to Embodiment 1 of this disclosure.

[0012] Figure 2 It is along Figure 1 A sectional view of AA′.

[0013] Figure 3 It is along Figure 1 A cross-sectional view of BB′.

[0014] Figure 4 It is along Figure 1 A cross-sectional view of CC'.

[0015] Figure 5 This is a first diagram illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0016] Figure 6 This is a second diagram illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0017] Figure 7 This is the third figure illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0018] Figure 8 This is the fourth figure, illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0019] Figure 9 This is the fifth figure, illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0020] Figure 10 This is the sixth figure, illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0021] Figure 11 This is the seventh figure, illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0022] Figure 12 This is Figure 8, which illustrates the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0023] Figure 13 This is the ninth figure, illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0024] Figure 14 This is Figure 10, which illustrates the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure.

[0025] Figure 15 This is a top view showing the configuration of the semiconductor device according to Embodiment 2 of this disclosure.

[0026] Figure 16 It is along Figure 15 A sectional view of AA′.

[0027] Figure 17 It is along Figure 15 A cross-sectional view of BB′.

[0028] Figure 18 It is along Figure 15 A cross-sectional view of CC'.

[0029] Figure 19This is a top view showing the configuration of the semiconductor device according to Embodiment 3 of this disclosure.

[0030] Figure 20 It is along Figure 19 A sectional view of AA′.

[0031] Figure 21 It is along Figure 19 A cross-sectional view of BB′.

[0032] Figure 22 It is along Figure 19 A cross-sectional view of CC'.

[0033] Figure 23 This is a top view showing the configuration of the semiconductor device according to Embodiment 4 of this disclosure.

[0034] Figure 24 It is along Figure 23 A sectional view of AA′.

[0035] Figure 25 It is along Figure 23 A cross-sectional view of BB′.

[0036] Figure 26 It is along Figure 23 A cross-sectional view of CC'.

[0037] Figure 27 This is a top view showing the configuration of the semiconductor device according to Embodiment 5 of this disclosure.

[0038] Figure 28 It is along Figure 27 A sectional view of AA′.

[0039] Figure 29 It is along Figure 27 A cross-sectional view of BB′.

[0040] Figure 30 It is along Figure 27 A cross-sectional view of CC'.

[0041] Figure 31 This is a top view showing the configuration of the semiconductor device according to Embodiment 6 of this disclosure.

[0042] Figure 32 It is along Figure 31 A sectional view of AA′.

[0043] Figure 33 It is along Figure 31 A cross-sectional view of BB′.

[0044] Figure 34 It is along Figure 31A cross-sectional view of CC'.

[0045] Figure 35 This is a top view showing the configuration of the semiconductor device according to Embodiment 7 of this disclosure.

[0046] Figure 36 It is along Figure 35 A sectional view of AA′.

[0047] Figure 37 It is along Figure 35 A cross-sectional view of BB′.

[0048] Figure 38 It is along Figure 35 A cross-sectional view of CC'.

[0049] Figure 39 This is a top view showing the configuration of the semiconductor device according to Embodiment 8 of this disclosure.

[0050] Figure 40 It is along Figure 39 A sectional view of AA′.

[0051] Figure 41 It is along Figure 39 A cross-sectional view of BB′.

[0052] Figure 42 It is along Figure 39 A cross-sectional view of CC'.

[0053] Figure 43 This is a top view showing the configuration of a semiconductor device according to a first variation of Embodiment 2 of this disclosure.

[0054] Figure 44 This is a top view showing the configuration of a semiconductor device according to a second variation of Embodiment 2 of this disclosure.

[0055] Explanation of reference numerals in the attached figures

[0056] 2... First direction; 4... Second direction; 10... Semiconductor substrate; 30... n-type drift layer; 40... n-type base layer; 50... p-type base layer; 60... n+ type source layer; 70... p+ type contact layer; 80... p-type diffusion layer; 90... Contact hole; 90a... p contact hole; 90b... n contact hole; 100... Source electrode; 110... Gate electrode; 120... Gate oxide film; 130... Interlayer insulating film; 140... Drain electrode; 1000... Semiconductor device; 2000... Semiconductor device; 2000a... Semiconductor device; 2000b... Semiconductor device; 3000... Semiconductor device; 4000... Semiconductor device; 5000... Semiconductor device; 6000... Semiconductor device; 7000... Semiconductor device; 8000... Semiconductor device. Detailed Implementation

[0057] The semiconductor device and its manufacturing method according to the embodiments will be described with reference to the accompanying drawings. The same or corresponding components are labeled with the same reference numerals, and sometimes repeated descriptions are omitted.

[0058] Figure 1 This is a top view showing the configuration of the semiconductor device according to Embodiment 1 of this disclosure. Figure 1 The planar layout of the cell region of a semiconductor device 1000, which is a planar MOSFET, is shown.

[0059] Among them, Figure 1 For ease of explanation, the source electrode, interlayer insulating film, gate electrode, and passivation film are not illustrated. The same applies to the top view showing the configuration of the semiconductor device shown below.

[0060] Semiconductor device 1000 includes an n-type base layer 40 extending in a first direction 2. P-type base layers 50 extending in the first direction 2 are disposed on both sides of the n-type base layer 4 in a second direction 4. The width of the p-type base layer 50 in the second direction 4 is referred to as the channel length 6. An n+ type source layer 60 extending in the first direction 2 is disposed on the side of the p-type base layer 50 in the second direction 4 where the n-type base layer 40 is not disposed. The impurity concentration of the n+ type source layer 60 is higher than that of the n-type base layer 40.

[0061] A portion of the n+ type source layer 60 is covered by a p+ type contact layer 70. The impurity concentration of the p+ type contact layer 70 is higher than that of the p-type base layer 50. The p+ type contact layers 70 are arranged at constant intervals toward the first direction 2 in a manner that discretely covers the n+ type source layer 60.

[0062] Here, the n-type base layer 40, p-type base layer 50, n+ type source layer 60, and p+ type contact layer 70 are referred to as the active region. The active region is the region where current flows when the semiconductor device 1000, which functions as a MOSFET, is turned on.

[0063] The p+ type contact layer 70 is provided to stabilize the potential of the p-type base layer 50 at 0V, the same potential as the source electrode 100, by making an ohmic contact with it. If the potential of the p-type base layer 50 is unstable, the voltage applied to the region of the gate oxide film 120 sandwiched between the p-type base layer 50 and the gate electrode 110 changes, and the conduction characteristics during switching change. The p+ type contact layer 70 suppresses this change.

[0064] Furthermore, a p-contact hole 90a is disposed in the region of the n+ type source layer 60 covered by the p+ type contact layer 70. And an n-contact hole 90b is disposed in the region of the n+ type source layer 60 not covered by the p+ type contact layer 70. That is, the p-contact hole 90a and the n-contact hole 90b are separated by the interlayer insulating film 130, which will be described later.

[0065] The openings of both the p-contact hole 90a and the n-contact hole 90b are rectangular in shape and size. Furthermore, when viewed from above, the p-contact holes 90a and 90b are alternately arranged at a constant interval towards the first direction 2, with their centers overlapping the center of the width of the n+ type source layer 60 in the second direction 4. Additionally, the area occupied by the n-contact hole 90b in the active region is smaller than the area of ​​the n-contact hole 90b when it is not separated by the interlayer insulating film 130 described later.

[0066] Furthermore, although examples of rectangular shapes for the openings of the p-contact hole 90a and the n-contact hole 90b are shown here, this is not a limitation; for example, they could also be circular or elliptical. Additionally, when the openings of the p-contact hole 90a and the n-contact hole 90b are rectangular, their lengths in the first direction 2 and the second direction 4 can be completely equal. Alternatively, in the above case, the width of the n-contact hole 90b in the first direction 2 can be smaller than the width of the p-contact hole 90a in the first direction 2. According to this method, the area of ​​the n-contact hole 90b can be further reduced to a smaller area than when it is not separated by the interlayer insulating film 130 described later.

[0067] Alternatively, the number of n-contact holes 90b in the semiconductor device 1000 as a whole can be reduced by increasing the spacing between n-contact holes 90b and p-contact holes 90a.

[0068] Figure 2 It is along Figure 1A sectional view of AA′. Wherein, in Figure 2 For ease of illustration, the passivation film is not shown in the diagram. The same applies in the cross-sectional view along AA′ shown below.

[0069] The semiconductor device 1000 includes a semiconductor substrate 10. The semiconductor substrate 10 may be formed of a wide-bandgap semiconductor. The wide-bandgap semiconductor may be, for example, silicon carbide, gallium nitride-based materials, or diamond.

[0070] The semiconductor substrate 10 has an n+ type substrate layer 20. The n+ type substrate layer 20 is formed, for example, from silicon carbide. A drain electrode 140 is connected to the lower surface side of the n+ type substrate layer 20. An n- type drift layer 30 is connected to the upper surface side of the n+ type substrate layer 20.

[0071] An n-type base layer 40 is disposed on the upper surface of the n-type drift layer 30. A p-type base layer 50 is disposed on both sides of the n-type base layer 40. That is, the n-type base layer 40 and the p-type base layer 50 are disposed side by side on the upper surface of the n-type drift layer 30.

[0072] An n+ type source layer 60 is selectively disposed on the upper surface side of the p-type base layer 50. The n+ type source layer 60 is a source layer with a higher impurity concentration than the n-type base layer 40. Furthermore, a p+ type contact layer 70 is selectively disposed on the upper surface side of the p-type base layer 50, on the side of the n+ type source layer 60 that is not connected to the p-type base layer 50. The p+ type contact layer 70 is a contact layer with a higher impurity concentration than the p-type base layer 50.

[0073] That is, the p-type base layer 50 is thicker than the n+ type source layer 60 and the p+ type contact layer 70. Furthermore, the p+ type contact layer 70 is thicker than the n+ type source layer 60. And, for example, the thickness of the n-type base layer 40 can be equal to that of the p-type base layer 50.

[0074] A gate oxide film 120 is disposed on the n-type base layer 40, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70. A gate electrode 110 is disposed on the gate oxide film 120.

[0075] The upper surfaces of the gate electrode 110 and the gate oxide film 120 are covered by the interlayer insulating film 130. The upper surfaces of the interlayer insulating film 130 and the p+ type contact layer 70 are covered by the source electrode 100.

[0076] Figure 1 The multiple p-contact holes 90a shown are as follows Figure 2 The configuration shown exposes a portion of the p+ type contact layer 70 from the interlayer insulating film 130. That is, the p+ type contact layer 70 is electrically connected to the source electrode 100 through the p-contact hole 90a.

[0077] Figure 3 It is along Figure 1 A sectional view of BB′. Wherein, Figure 3 For ease of illustration, the passivation film is not shown in the diagram. The same applies in the cross-sectional view along BB′ shown below.

[0078] Figure 3 The sectional view shown is consistent with the view at the point where it does not pass through the p+ type contact layer 70. Figure 2 The sectional views shown are different. Therefore, only the composition and... Figure 2 Different parts of the sectional view shown are omitted from the description.

[0079] An n+ type source layer 60 is selectively disposed on the upper surface side of the p-type base layer 50. That is, the p-type base layer 50 is thicker than the n+ type source layer 60.

[0080] A gate oxide film 120 is disposed on the n-type base layer 40, the p-type base layer 50, and the n+ type source layer 60. In addition, the interlayer insulating film 130 and the upper surface of the n+ type source layer 60 are covered by the source electrode 100.

[0081] like Figure 3 As shown, Figure 1 The n-contact hole 90b shown is configured to expose the n+ type source layer 60 from the interlayer insulating film 130. That is, the n+ type source layer 60 is electrically connected to the source electrode 100 through the n-contact hole 90b.

[0082] Figure 4 It is along Figure 1 A sectional view of CC'. Wherein... Figure 4 For ease of illustration, the passivation film is not shown in the diagram. The same applies in the cross-sectional view along CC′ shown below.

[0083] The semiconductor device 1000 includes a semiconductor substrate 10. The semiconductor substrate 10 has an n+ type substrate layer 20. A drain electrode 140 is connected to the lower surface of the n+ type substrate layer 20. An n- type drift layer 30 is connected to the upper surface of the n+ type substrate layer 20.

[0084] A p-type base layer 50 is disposed on the upper surface of the n-type drift layer 30. An n+ type source layer 60 and a p+ type contact layer 70 are alternately disposed on the upper surface of the p-type base layer 50. The upper surface of the boundary between the n+ type source layer 60 and the p+ type contact layer 70 is covered by an interlayer insulating film 130. The interlayer insulating film 130, the upper surface of the n+ type source layer 60, and the upper surface of the p+ type contact layer 70 are covered by a source electrode 100.

[0085] Also Figure 2As shown, the p+ type contact layer 70 is electrically connected to the source electrode 100 through the p-contact hole 90a. Additionally, as... Figure 3 As shown, the n+ type source layer 60 is electrically connected to the source electrode 100 through the n contact hole 90b.

[0086] Furthermore, the area of ​​the n+ type source layer 60 connected to the source electrode 100 through multiple n-contact holes 90b is smaller than the area of ​​the n-contact holes 90b when they are not separated by the interlayer insulating film 130.

[0087] Next, a method for manufacturing a semiconductor device according to this embodiment will be described. Although a method for manufacturing a semiconductor device 1000 will be described here, the basic structure of the methods for manufacturing semiconductor devices according to this disclosure is all the same. The methods for manufacturing semiconductor devices according to each embodiment are represented by replacing the size of the constituent elements or the type of implanted ions in the method for manufacturing semiconductor device 1000 with the constituent elements that are replaced.

[0088] Figure 5 This is a first diagram illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. The semiconductor device 1000 is formed on an n+ type substrate layer 20.

[0089] The following diagram, illustrating the manufacturing process of the semiconductor device 1000, shows the process along... Figure 1 The cross-sectional view of AA′ is equivalent to the cross-sectional structure.

[0090] Figure 6 This is a second figure illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, an n-type drift layer 30 is formed on the upper surface of the n+ type substrate layer 20, for example, by epitaxial growth.

[0091] Figure 7 This is the third figure illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, the n-type base layer 40 is formed by ion implantation of n-type impurities such as N onto the upper surface side of the n-type drift layer 30. The n-type base layer 40 may be selectively formed on a portion of the upper surface of the n-type drift layer 30 by using a photomask, or it may be formed entirely on the upper surface of the n-type drift layer 30 without using a photomask.

[0092] Figure 8 This is the fourth figure illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, a first mask 42 is formed on the upper surface side of the n-type base layer 40 with a partial opening corresponding to the formation region of the p-type base layer 50. The first mask 42 is formed, for example, by film deposition of a thin film 44 such as a CVD film, photolithography, and dry etching.

[0093] Figure 9 This is the fifth figure illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, a p-type base layer 50 disposed side-by-side with the n-type base layer 40 is formed on the upper surface side of the n-type drift layer 30 by ion implantation of p-type impurities such as Al onto the upper surface side of the n-type base layer 40. In this ion implantation, n-type impurities such as N may also be shallowly implanted.

[0094] Along with the aforementioned ion implantation, the region covered by the first mask 42 maintains the n-type base layer 40 unchanged, while the region not covered by the first mask 42 forms the p-type base layer 50. That is, the outer surface of the channel region of the ultimately obtained semiconductor device 1000 is an n-type base layer 40. As a result, since the channel is easily induced, the threshold voltage can be reduced.

[0095] Figure 10 This is the sixth figure illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, a thin film 52 is formed on the upper surface and sidewalls of the first mask 42 and on the upper surface of the p-type base layer 50. The thin film 52 is, for example, a CVD film.

[0096] Figure 11 Figure 7 illustrates the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, a second mask 54 having a first mask 42 is formed by etching a thin film 52. Specifically, the thin film 52 is etched until an isolator 52a is formed on the sidewall of the first mask 42. This etching is achieved, for example, by using anisotropic etching such as dry etching under conditions where there is almost no etching in the sidewall direction of the first mask 42.

[0097] Figure 12 This is the eighth figure illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, an n+ type source layer 60 is selectively disposed on the upper surface side of the p-type base layer 50 by ion implantation of n-type impurities such as N on the upper surface side of the p-type base layer 50 and the second mask 54.

[0098] In the ion implantation described above, the region covered by the second mask 54 is maintained, while an n+ type source layer 60 is formed in the region not covered by the second mask 54. The second mask 54 is formed in a self-matching manner relative to the first mask 42. Therefore, the alignment of the p-type base layer 50 and the n+ type source layer 60 does not deviate, and the length of the channel region does not change. As a result, the variation in threshold voltage, which is significantly affected by alignment deviation, can be eliminated. That is, the semiconductor device 1000 according to this embodiment can not only improve the short-circuit withstand capability itself, but also suppress the difference in short-circuit withstand capability.

[0099] Figure 13This is Figure 9, illustrating the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, for example, the second mask 54 is removed by wet etching using HF or the like.

[0100] Figure 14 Figure 10 illustrates the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. Here, a p+ type contact layer 70 is selectively disposed on the upper surface side of the p-type base layer 50 by selectively ion implanting p-type impurities such as Al on the upper surface side of the n+ type source layer 60.

[0101] The ion implantation described above is performed after a mask with an opening corresponding to the formation region of the p+ type contact layer 70 has been formed. In the case of ion implantation at high temperature to increase the implantation dose, the mask can be formed, for example, by CVD film deposition, photolithography, and dry etching. In the case of ion implantation at room temperature, the mask can be formed, for example, by photomask formation. The mask formed before ion implantation is removed after ion implantation is completed, for example, by wet etching using HF or the like.

[0102] Next, a gate oxide film 120 is formed on the n-type base layer 40, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70 using conventional methods. Next, a gate electrode 110 is formed on the gate oxide film 120 using conventional methods. Next, an interlayer insulating film 130 is formed using conventional methods. This interlayer insulating film 130 is disposed on the semiconductor substrate 10 such that it covers the gate oxide film 120 and the gate electrode 110, and has a plurality of n-contact holes 90b exposing a portion of the n+ type source layer 60 and a plurality of p-contact holes 90a exposing a portion of the p+ type contact layer 70.

[0103] Next, a source electrode 100 is formed using conventional methods. This source electrode 100 is connected to the n+ type source layer 60 via an n-contact hole 90b and to the p+ type contact layer 70 via a p-contact hole 90a. Additionally, a drain electrode 140 is formed on the lower surface side of the n-type drift layer 30 using conventional methods. Furthermore, a passivation film or the like can also be formed using conventional methods. Through the above processes, a semiconductor device 1000 is formed.

[0104] The effects exhibited by the semiconductor device 1000 according to this embodiment will be explained. In conventional semiconductor devices, the contact holes expose both the p+ type contact layer 70 and the n+ type source layer 60 simultaneously. That is, both the p+ type contact layer 70 and the n+ type source layer 60 are electrically connected to the source electrode 100.

[0105] On the other hand, the semiconductor device 1000 according to this embodiment forms a p-contact hole 90a that electrically connects the p+ type contact layer 70 to the source electrode 100 and an n-contact hole 90b that electrically connects the n+ type source layer 60 to the source electrode 100.

[0106] If the area of ​​the n-type contact hole 90b is reduced, the contact resistance in the current path from the drain electrode 140 to the source electrode 100 becomes non-negligible. That is, a voltage drop occurs between the source electrode 100 and the adjacent layer. Specifically, a potential difference is generated between the source electrode 100 and the n+ type source layer 60.

[0107] Here, in the semiconductor device 1000 according to this embodiment, the area occupied by the n-contact hole 90b in the active region is smaller than the area of ​​the n-contact hole 90b when it is not separated by the interlayer insulating film 130. That is, the area of ​​the n+ type source layer 60 connected to the source electrode 100 through the n-contact hole 90b is smaller than the area when it is not separated by the interlayer insulating film 130.

[0108] As a result, the voltage drop in the source electrode 100-n+ type source layer 60 can be made greater than the case where the n-contact hole 90b is not separated by the interlayer insulating film 130. Here, the potential of the p+ type contact layer 70 is the same as the potential of the p-type base layer 50. That is, the potential of the n+ type source layer 60 can be made higher than the potential of the p-type base layer 50 by an amount equivalent to the voltage drop in the source electrode 100-n+ type source layer 60.

[0109] If the potential of the n+ source layer 60 is higher than that of the p-type base layer 50, a substrate bias effect can be generated. The substrate bias effect refers to the effect that makes reversal less likely. More specifically, firstly, because the potential of the n+ source layer 60 is higher than that of the p-type base layer 50, a reverse bias is applied to the PN junction of the n+ source layer 60 and the p-type base layer 50, causing the depletion layer to expand. As a result, a negative fixed charge is generated in the depletion layer of the p-type base layer 50, neutralizing the positive charge generated when the switch is turned on. That is, reversal is less likely.

[0110] The substrate bias effect generated by the potential difference between the n+ source layer 60 and the p-type base layer 50 varies depending on the current flowing through the n+ source layer 60. The larger the current, the greater this variation, resulting in a higher effectiveness in reducing the gate voltage. That is, while the substrate bias effect is small under normal conditions, its effectiveness is high under abnormal conditions such as short-circuit current surges. Therefore, it does not significantly affect losses under normal conditions and can effectively reduce short-circuit current.

[0111] Furthermore, the semiconductor device 1000 involved in this embodiment is a planar MOSFET. When increasing the channel density of a planar MOSFET to improve its characteristics, it is necessary to reduce the cell pitch. In reducing the cell pitch, the length direction of the channel length 6 is the same as the direction of reduction. Therefore, when reducing the cell pitch, it is necessary to shorten the channel length 6.

[0112] However, shortening the channel length by 6 results in a lower threshold voltage. This leads to a higher saturation current and consequently, a lower short-circuit withstand capability. Therefore, in planar MOSFETs, to compensate for the problems caused by shortening the channel length by 6, it is necessary to improve the short-circuit withstand capability without hindering the reduction in cell spacing.

[0113] The semiconductor device 1000 according to this embodiment can improve short-circuit withstand capability without hindering cell pitch reduction. That is, the semiconductor device 1000 according to this embodiment can achieve both improved characteristics and increased short-circuit withstand capability in a planar MOSFET.

[0114] Furthermore, when cell pitch reduction is performed in a trench MOSFET, the length direction of the channel is different from the direction of reduction. Therefore, in a trench MOSFET, it is not necessary to shorten the channel length when cell pitch reduction is performed. That is, the semiconductor device 1000 according to this embodiment exhibits particularly high performance in planar MOSFETs.

[0115] As described above, in the semiconductor device 1000 according to this embodiment, the area of ​​the n+ type source layer 60 connected to the source electrode 100 through the n-contact hole 90b is smaller than the area of ​​the n-contact hole 90b when it is not separated by the interlayer insulating film 130. As a result, the short-circuit withstand capability can be improved.

[0116] Furthermore, in this embodiment, the openings of the p-contact hole 90a and the n-contact hole 90b have the same shape and size, and are arranged alternately and periodically toward the first direction 2 when viewed from above. As a result, stable dimensional control can be achieved during the manufacturing process of the semiconductor device 1000 because dimensional differences within the chip or wafer can be suppressed.

[0117] Furthermore, as a variation of this embodiment, a method can be listed where the area occupied by the n-contact hole 90b in the active region is reduced. For example, it is possible to make the width of the n-contact hole 90b in the first direction 2 smaller than the width of the p-contact hole 90a in the first direction 2. With this change, the short-circuit withstand capability can be further improved.

[0118] Implementation Method 2

[0119] Figure 15 This is a top view showing the configuration of the semiconductor device according to Embodiment 2 of this disclosure. Figure 15 The planar layout of the cell region of a semiconductor device 2000, which is a planar MOSFET, is shown. The semiconductor device 2000 differs from the semiconductor device 1000 in that the length of the first direction 2 of the p+ type contact layer 70 is longer, and the p contact hole 90a and n contact hole 90b are arranged alternately in pairs.

[0120] The openings of both the p-contact hole 90a and the n-contact hole 90b are rectangular in shape and size. Furthermore, when viewed from above, the p-contact holes 90a and 90b are arranged alternately at constant intervals, with their centers overlapping the center of the width of the n+ type source layer 60 in the second direction 4. Additionally, the area occupied by the n-contact hole 90b in the active region is smaller than the area occupied by the p-contact hole 90a in the active region.

[0121] Furthermore, although the n-contact hole 90b and p-contact hole 90a are shown here in a configuration that alternates between each pair at a constant interval when viewed from above in the first direction 2, this is not a limitation and they may also be configured periodically, for example.

[0122] An example is shown where the openings of the n-contact hole 90b and the p-contact hole 90a are periodically configured. Figure 43 This is a top view showing the configuration of a semiconductor device according to a first variation of Embodiment 2 of the present disclosure. In the semiconductor device 2000a, the opening of one n-contact hole 90b and the openings of two p-contact holes 90a are arranged alternately at a constant interval in the first direction 2 when viewed from above.

[0123] Figure 44 This is a top view showing the configuration of a semiconductor device according to a second variation of Embodiment 2 of the present disclosure. In the semiconductor device 2000b, the openings of the two n-contact holes 90b and the openings of the three p-contact holes 90a are arranged alternately at constant intervals facing the first direction 2 when viewed from above.

[0124] Here, a first contact hole group is defined as m n-contact holes 90b arranged at constant intervals facing the first direction 2, and a second contact hole group is defined as n p-contact holes 90a arranged at constant intervals facing the first direction 2. In this case, the semiconductor device according to this embodiment is a semiconductor device in which the first contact hole group and the second contact hole group are arranged at constant intervals facing the first direction 2 when viewed from above. Here, m is a value of 1 or more and n less. According to this method, the area of ​​the n-contact holes 90b can be further reduced to a smaller area than that when they are not separated by the interlayer insulating film 130.

[0125] Figure 16 It is along Figure 15 A sectional view of AA. Because Figure 16 Is with Figure 2 The same diagram is used, so the explanation is omitted.

[0126] Figure 17 It is along Figure 15 A cross-sectional view of BB′. Because Figure 17 Is with Figure 3 The same diagram is used, so the explanation is omitted.

[0127] Figure 18 It is along Figure 15 A cross-sectional view of CC'. Figure 18 The length of the n+ type source layer 60 and the p+ type contact layer 70 in the first direction 2 is longer than that of the n+ type source layer 60 and the p+ type contact layer 70. Figure 4 different.

[0128] As described above, in the semiconductor device 2000 according to this embodiment, the area of ​​the n+ type source layer 60 connected to the source electrode 100 through a plurality of n-contact holes 90b is smaller than the area of ​​the n-contact holes 90b when they are not separated by the interlayer insulating film 130. As a result, the short-circuit withstand capability can be improved.

[0129] Furthermore, in the semiconductor device 2000 according to this embodiment, the openings of the p-contact hole 90a and the n-contact hole 90b are rectangular in shape and size, and are arranged alternately at a constant interval in the first direction 2 when viewed from above. As a result, dimensional differences within the chip or wafer can be suppressed during the manufacturing process of the semiconductor device 1000, thus enabling stable dimensional control.

[0130] Implementation Method 3

[0131] Figure 19 This is a top view showing the configuration of the semiconductor device according to Embodiment 3 of this disclosure. Figure 19 The planar layout of the cell region of a semiconductor device 3000, which is a planar MOSFET, is shown. The semiconductor device 3000 differs from the semiconductor device 1000 in that the length of the second direction 4 of the p+ type contact layer 70 is longer.

[0132] A portion of the n+ type source layer 60 and the p-type base layer 50 are covered by a p+ type contact layer 70. The p+ type contact layer 70 is arranged in a first direction 2 such that it discretely covers the n+ type source layer 60 and the p-type base layer 50. The length of the p+ type contact layer 70 in a second direction 4 is longer than the length of the n+ type source layer 60 in a second direction 4.

[0133] Figure 20 It is along Figure 19 A sectional view of AA′. Figure 20 In terms of not having an n+ type source layer 60, it is similar to Figure 2 different.

[0134] An n-type base layer 40 is disposed on the upper surface of the n-type drift layer 30. P-type base layers 50 are disposed on both sides of the n-type base layer 40. A p+ type contact layer 70 is selectively disposed on the upper surface of the p-type base layer 50. That is, the p-type base layer 50 is thicker than the p+ type contact layer 70. Furthermore, a gate oxide film 120 is disposed on the n-type base layer 40, the p-type base layer 50, and the p+ type contact layer 70.

[0135] Figure 21 It is along Figure 19 A cross-sectional view of BB′. Because Figure 21 Is with Figure 3 The same diagram is used, so the explanation is omitted.

[0136] Figure 22 It is along Figure 19 A cross-sectional view of CC'. Because Figure 22 Is with Figure 4 The same diagram is used, so the explanation is omitted.

[0137] As described above, in the semiconductor device 3000 according to this embodiment, the area of ​​the n+ type source layer 60 connected to the source electrode 100 through the n-contact hole 90b is smaller than the area of ​​the n-contact hole 90b when it is not separated by the interlayer insulating film 130. As a result, the short-circuit withstand capability can be improved.

[0138] Furthermore, the semiconductor device 3000 involved in this embodiment is... Figure 20 The region shown does not have an n+ type source layer 60. That is, the semiconductor device 3000 has a region where the p-type base layer 50 and the p+ type contact layer 70 are connected only through a path that does not pass through the n+ type source layer 60. In this region, no channel is generated when the switch is in the on state. As a result, since the semiconductor device 3000 can reduce the channel area occupied in the entire active region, the saturation current can be reduced and the short-circuit withstand capability can be further improved.

[0139] Implementation Method 4

[0140] Figure 23 This is a top view showing the configuration of the semiconductor device according to Embodiment 4 of this disclosure. Figure 23 The planar layout of the cell region of a semiconductor device 4000, which is a planar MOSFET, is shown. Semiconductor device 4000 differs from semiconductor device 1000 in that it has a JFET region 8.

[0141] JFET region 8 is disposed between first region 7 and second region 9. JFET region 8 has an n-type base layer 40 extending in a first direction 2. A portion of the n-type base layer 40 is replaced by a p-type diffusion layer 80. Specifically, the p-type diffusion layer 80 and the n-type base layer 40 are alternately arranged at a constant interval facing the first direction 2 when viewed from above. In addition, the p-type diffusion layer 80 and the p+ type contact layer 70 are alternately arranged at a constant interval facing the second direction 4 when viewed from above.

[0142] The p-type diffusion layer 80 is disposed in the first direction 2 in a manner that discretely covers the n-type base layer 40. The length of the p-type diffusion layer 80 in the second direction 4 is longer than the width of the n-type base layer 40 in the second direction 4. Therefore, the p-type diffusion layer 80 is connected to the p-type base layer 50.

[0143] Figure 24 It is along Figure 23 A sectional view of AA′. Figure 24 In terms of having a p-type diffusion layer 80 instead of an n-type base layer 40, and... Figure 2 different.

[0144] A p-type diffusion layer 80 is disposed on the upper surface of the n-type drift layer 30. A p-type base layer 50 is disposed on both sides of the p-type diffusion layer 80. A gate oxide film 120 is disposed on the p-type diffusion layer 80, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70.

[0145] Figure 25 It is along Figure 23 A cross-sectional view of BB′. Because Figure 25 Is with Figure 3 The same diagram is used, so the explanation is omitted.

[0146] Figure 26 It is along Figure 23 A cross-sectional view of CC'. Figure 26 In terms of replacing a portion of the n+ type source layer 60 with the p+ type contact layer 70, and... Figure 4 different.

[0147] As described above, in the semiconductor device 4000 according to this embodiment, the area of ​​the n+ type source layer 60 connected to the source electrode 100 through the n-contact hole 90b is smaller than the area of ​​the n-contact hole 90b when it is not separated by the interlayer insulating film 130. As a result, the short-circuit withstand capability can be improved.

[0148] Furthermore, the semiconductor device 4000 involved in this embodiment is... Figure 24The region shown does not have an n-type base layer 40. That is, the semiconductor device 4000 has a region where the p-type base layer 50 and the n-type drift layer 30 are connected only through a path that does not pass through the n-type base layer 40. In this region, no channel is generated when the switch is in the on state. As a result, since the semiconductor device 4000 can reduce the channel region occupied in the entire active region, the saturation current can be reduced and the short-circuit withstand capability can be further improved.

[0149] Implementation Method 5

[0150] Figure 27 This is a top view showing the configuration of the semiconductor device according to Embodiment 5 of this disclosure. Figure 27 The planar layout of the cell region of a semiconductor device 5000, which is a planar MOSFET, is shown. The semiconductor device 5000 differs from the semiconductor device 1000 in that the p+ type contact layer 70 has a larger area and has contact holes 90 instead of p contact holes 90a and n contact holes 90b.

[0151] A portion of the n+ type source layer 60 is covered by a p+ type contact layer 70. The p+ type contact layers 70 are arranged at constant intervals toward the first direction 2 in a manner that discretely covers the n+ type source layer 60.

[0152] Additionally, a contact hole 90 is disposed in the n+ type source layer 60. The contact hole 90 extends in the first direction 2, covering both the area covered by the p+ type contact layer 70 and the area not covered by the p+ type contact layer 70. That is, the contact hole 90 is composed of p-contact holes 90a and n-contact holes 90b alternately arranged in the first direction 2. The width of the contact hole 90 in the second direction 4 is, for example, smaller than the length of the p+ type contact layer 70 in the second direction 4.

[0153] Here, the width of the opening in the first direction 2 of the n-type contact hole 90b is shorter than the width of the opening in the first direction 2 of the p-type contact hole 90a. Therefore, the area of ​​the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is smaller than the area of ​​the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90.

[0154] Figure 28 It is along Figure 27 A sectional view of AA′. Figure 28 and Figure 2 The difference is that it has a contact hole 90 instead of a p contact hole 90a, and the length of the first direction 2 of the p+ type contact layer 70 is longer.

[0155] Figure 29 It is along Figure 27 A cross-sectional view of BB′. Figure 29 In terms of having contact hole 90 instead of contact hole 90b, and... Figure 3 different.

[0156] Figure 30 It is along Figure 27 A cross-sectional view of CC'. Figure 30 and Figure 4 The differences are: the lengths of the first direction 2 of the n+ type source layer 60 and the p+ type contact layer 70 are different, and they do not have an interlayer insulating film 130.

[0157] A p-type base layer 50 is disposed on the upper surface of the n-type drift layer 30. An n+ type source layer 60 and a p+ type contact layer 70 are alternately disposed on the upper surface of the p-type base layer 50. The upper surfaces of the n+ type source layer 60 and the p+ type contact layer 70 are covered by the source electrode 100.

[0158] Next, the effects exhibited by the semiconductor device 5000 according to this embodiment will be explained. In the semiconductor device 5000 according to this embodiment, the width of the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is smaller than the width of the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90. As a result, the potential of the n+ type source layer 60 can be made higher than the potential of the p-type base layer 50 by an amount equivalent to the voltage drop between the source electrode 100 and the n+ type source layer 60 through the contact hole 90.

[0159] Therefore, the semiconductor device 5000 according to this embodiment exhibits the same effects as those shown in Embodiment 1. That is, the short-circuit withstand capability can be improved in the semiconductor device 5000 according to this embodiment. In addition, the semiconductor device 5000 according to this embodiment can achieve both the performance improvement and the increase in short-circuit withstand capability achieved by the reduction of cell pitch in a planar MOSFET.

[0160] Furthermore, in this embodiment, the resistance in the path represented by resistor 55b is greater than the resistance in the path represented by resistor 55a. That is, in this embodiment, the voltage drop in the path represented by resistor 55b can be greater than the voltage drop in the path represented by resistor 55a. As a result, the potential of the n+ type source layer 60 can be further higher than the potential of the p-type base layer 50.

[0161] As described above, in the semiconductor device 5000 according to this embodiment, the width of the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is smaller than the width of the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90. As a result, the short-circuit withstand capability can be improved.

[0162] Implementation Method 6

[0163] Figure 31 This is a top view showing the configuration of the semiconductor device according to Embodiment 6 of this disclosure. Figure 31 The planar layout of the cell region of a semiconductor device 6000, which is a planar MOSFET, is shown. Semiconductor device 6000 differs from semiconductor device 5000 in that it has a JFET region 8.

[0164] JFET region 8 is disposed between first region 7 and second region 9. JFET region 8 has an n-type base layer 40 extending in a first direction 2. A portion of the n-type base layer 40 is replaced by a p-type diffusion layer 80. Specifically, the p-type diffusion layer 80 and the n-type base layer 40 are alternately arranged at a constant interval facing the first direction 2 when viewed from above. In addition, the p-type diffusion layer 80 and the p+ type contact layer 70 are alternately arranged at a constant interval facing the second direction 4 when viewed from above.

[0165] The p-type diffusion layer 80 is disposed in the first direction 2 in a manner that discretely covers the n-type base layer 40. The length of the p-type diffusion layer 80 in the second direction 4 is longer than the width of the n-type base layer 40 in the second direction 4. Therefore, the p-type diffusion layer 80 is connected to the p-type base layer 50.

[0166] Figure 32 It is along Figure 31 A sectional view of AA′. Figure 32 In terms of having a p-type diffusion layer 80 instead of an n-type base layer 40, and... Figure 28 different.

[0167] A p-type diffusion layer 80 is disposed on the upper surface of the n-type drift layer 30. A p-type base layer 50 is disposed on both sides of the p-type diffusion layer 80. A gate oxide film 120 is disposed on the p-type diffusion layer 80, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70.

[0168] Figure 33 It is along Figure 31 A cross-sectional view of BB′. Because Figure 33 Is with Figure 29 The same diagram is used, so the explanation is omitted.

[0169] Figure 34 It is along Figure 31 A cross-sectional view of CC'. Because Figure 34 Is with Figure 30 The same diagram is used, so the explanation is omitted.

[0170] As described above, in the semiconductor device 6000 according to this embodiment, the width of the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is smaller than the width of the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90. As a result, the short-circuit withstand capability can be improved.

[0171] Furthermore, the semiconductor device 6000 involved in this embodiment is... Figure 32 The region shown does not have an n-type base layer 40. That is, the semiconductor device 6000 has a region where the p-type base layer 50 and the n-type drift layer 30 are connected only through a path that does not pass through the n-type base layer 40. In this region, no channel is generated when the switch is in the on state. As a result, since the semiconductor device 6000 can reduce the channel region occupied in the entire active region, the saturation current can be reduced and the short-circuit withstand capability can be further improved.

[0172] Implementation Method 7

[0173] Figure 35 This is a top view showing the configuration of the semiconductor device according to Embodiment 7 of this disclosure. Figure 35 The planar layout of the cell region of a semiconductor device 7000, which is a planar MOSFET, is shown. Semiconductor device 7000 differs from semiconductor device 5000 in that it has a JFET region 8a.

[0174] JFET region 8a is disposed between first region 7 and second region 9. JFET region 8a has an n-type base layer 40 extending in a first direction 2. A portion of the n-type base layer 40 is covered by a p-type diffusion layer 80. Specifically, the p-type diffusion layer 80 and the n-type base layer 40 are alternately arranged at a constant interval facing the first direction 2 when viewed from above. In addition, the region sandwiched between the p-type diffusion layer 80 and the p+ type contact layer 70 and another p+ type contact layer 70 is alternately arranged at a constant interval facing the second direction 4 when viewed from above.

[0175] Furthermore, the length of the p-type diffusion layer 80 in the first direction 2 is greater than the length of the opening in the first direction 2 of the n-type contact hole 90b. That is, one end of the p-type diffusion layer 80 in the first direction 2 and one end of the p+ type contact layer 70 in the first direction 2 are arranged facing the second direction 4. In this arrangement region, no channel is generated when the switch is in the on state. This region is the region that is in contact with the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90.

[0176] Figure 36 It is along Figure 35 A sectional view of AA′. Because Figure 36 Is with Figure 28The same diagram is used, so the explanation is omitted.

[0177] Figure 37 It is along Figure 35 A cross-sectional view of BB′. Figure 37 In terms of having a p-type diffusion layer 80 instead of an n-type base layer 40, and... Figure 29 different.

[0178] A p-type diffusion layer 80 is disposed on the upper surface of the n-type drift layer 30. A p-type base layer 50 is disposed on both sides of the p-type diffusion layer 80. A gate oxide film 120 is disposed on the p-type diffusion layer 80, the p-type base layer 50 and the n+ type source layer 60.

[0179] Figure 38 It is along Figure 35 A cross-sectional view of CC'. Because Figure 38 Is with Figure 30 The same diagram is used, so the explanation is omitted.

[0180] As described above, in the semiconductor device 7000 according to this embodiment, the width of the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is smaller than the width of the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90. As a result, the short-circuit withstand capability can be improved.

[0181] Furthermore, the semiconductor device 7000 involved in this embodiment is... Figure 37 The region shown does not have an n-type base layer 40. That is, the semiconductor device 7000 has a region where the p-type base layer 50 and the n-type drift layer 30 are connected only through a path that does not pass through the n-type base layer 40. In this region, no channel is generated when the switch is in the on state. As a result, since the semiconductor device 7000 can reduce the channel region occupied in the entire active region, the saturation current can be reduced and the short-circuit withstand capability can be further improved.

[0182] Furthermore, in the semiconductor device 7000 according to this embodiment, no channel is generated in the region connected to the n+ type source layer 60, which is connected to the source electrode 100 through the contact hole 90, when the switch is in the on state. The region of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is the region where current most easily flows when the switch is in the on state. Therefore, by not generating a channel in the region where current most easily flows when the switch is in the on state, the semiconductor device 7000 can suppress current concentration in one place.

[0183] Implementation Method 8

[0184] Figure 39This is a top view showing the configuration of the semiconductor device according to Embodiment 8 of this disclosure. Figure 39 The planar layout of the cell region of a semiconductor device 8000, which is a planar MOSFET, is shown. The semiconductor device 8000 differs from the semiconductor device 5000 in that the length of the second direction 4 of the p+ type contact layer 70 is longer.

[0185] A portion of the n+ type source layer 60 and the p-type base layer 50 are covered by a p+ type contact layer 70. The p+ type contact layer 70 is arranged in a first direction 2 such that it discretely covers the n+ type source layer 60 and the p-type base layer 50. The length of the p+ type contact layer 70 in a second direction 4 is longer than the length of the n+ type source layer 60 in a second direction 4.

[0186] Figure 40 It is along Figure 39 A sectional view of AA′. Because Figure 40 Is with Figure 20 The same diagram is used, so the explanation is omitted.

[0187] Figure 41 It is along Figure 39 A cross-sectional view of BB′. Because Figure 41 Is with Figure 29 The same diagram is used, so the explanation is omitted.

[0188] Figure 42 It is along Figure 39 A cross-sectional view of CC'. Because Figure 42 Is with Figure 30 The same diagram is used, so the explanation is omitted.

[0189] As described above, in the semiconductor device 8000 according to this embodiment, the width of the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is smaller than the width of the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90. As a result, the short-circuit withstand capability can be improved.

[0190] Furthermore, the semiconductor device 8000 involved in this embodiment is... Figure 40 The region shown does not have an n+ type source layer 60. That is, the semiconductor device 8000 has a region where the p-type base layer 50 and the p+ type contact layer 70 are connected only through a path that does not pass through the n+ type source layer 60. In this region, no channel is generated when the switch is in the on state. As a result, since the semiconductor device 8000 can reduce the channel area occupied in the entire active region, the saturation current can be reduced and the short-circuit withstand capability can be further improved.

[0191] The various methods disclosed herein are hereby recorded as appendices.

[0192] (Note 1) A semiconductor device, wherein,

[0193] The aforementioned semiconductor device includes:

[0194] A semiconductor substrate has a drift layer of a first conductivity type, a first base layer of a first conductivity type and a second base layer of a second conductivity type disposed side by side on the upper surface side of the drift layer, a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the first base layer, and a contact layer of a second conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the second base layer.

[0195] A gate oxide film is disposed on the first base layer, the second base layer, the source layer, and the contact layer.

[0196] The gate electrode is disposed on the aforementioned gate oxide film;

[0197] An interlayer insulating film is disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and has a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer.

[0198] The source electrode is connected to the source layer via the first contact hole and to the contact layer via the second contact hole; and

[0199] The drain electrode is connected to the lower surface of the aforementioned drift layer.

[0200] The first contact hole and the second contact hole are separated by the interlayer insulating film.

[0201] (Note 2) In the semiconductor device according to Note 1, wherein,

[0202] When viewed from above, the openings of the first contact hole and the second contact hole are alternately arranged facing the first direction.

[0203] The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole.

[0204] (Note 3) The semiconductor device according to Note 1 or 2, wherein,

[0205] The openings of the first contact hole and the second contact hole have the same shape and size, and are arranged alternately at constant intervals facing the first direction when viewed from above.

[0206] (Note 4) The semiconductor device according to any one of Notes 1 to 3, wherein,

[0207] The openings of the first contact hole and the second contact hole have the same shape and size.

[0208] A first contact hole group is formed by arranging m of the aforementioned first contact holes at constant intervals in a first direction.

[0209] A second contact hole group is formed, in which n of the aforementioned second contact holes are arranged at constant intervals facing the first direction.

[0210] When viewed from above, the first contact hole group and the second contact hole group are arranged alternately at a constant interval, facing the first direction.

[0211] m is a value greater than 1 and less than n.

[0212] (Appendix 5) A semiconductor device, wherein,

[0213] The aforementioned semiconductor device includes:

[0214] A semiconductor substrate has a drift layer of a first conductivity type, a first base layer of a first conductivity type and a second base layer of a second conductivity type disposed side by side on the upper surface side of the drift layer, a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the first base layer, and a contact layer of a second conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the second base layer.

[0215] A gate oxide film is disposed on the first base layer, the second base layer, the source layer, and the contact layer.

[0216] The gate electrode is disposed on the aforementioned gate oxide film;

[0217] An interlayer insulating film is disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and has a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer.

[0218] The source electrode is connected to the source layer via the first contact hole and to the contact layer via the second contact hole; and

[0219] The drain electrode is connected to the lower surface of the aforementioned drift layer.

[0220] The openings of the first contact hole and the second contact hole are alternately arranged facing the first direction when viewed from above.

[0221] The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction.

[0222] (Note 6) The semiconductor device according to any one of Notes 1 to 5, wherein,

[0223] The region having the second base layer and the contact layer connected only through a path not via the source layer.

[0224] (Note 7) The semiconductor device according to any one of Notes 1 to 6, wherein,

[0225] The aforementioned semiconductor substrate further comprises a second conductivity type diffusion layer disposed above the aforementioned drift layer and below the aforementioned gate oxide film.

[0226] The aforementioned contact layers are arranged at constant intervals facing the first direction when viewed from above.

[0227] The aforementioned diffusion layer and the aforementioned first base layer are arranged alternately at a constant interval toward the aforementioned first direction when viewed from above.

[0228] When viewed from above, the aforementioned diffusion layer and contact layer are alternately arranged at constant intervals in a direction perpendicular to the aforementioned first direction, i.e., the second direction.

[0229] The region having the second base layer and the drift layer connected only through a path not via the first base layer.

[0230] (Note 8) The semiconductor device according to any one of Notes 1 to 7, wherein,

[0231] The aforementioned semiconductor substrate further comprises a second conductivity type diffusion layer disposed above the aforementioned drift layer and below the aforementioned gate oxide film.

[0232] The aforementioned contact layers are arranged at constant intervals facing the first direction when viewed from above.

[0233] The aforementioned diffusion layer and the aforementioned first base layer are arranged alternately at a constant interval toward the aforementioned first direction when viewed from above.

[0234] The regions sandwiched between the aforementioned diffusion layer, the aforementioned contact layer, and another aforementioned contact layer are arranged alternately at constant intervals in a direction perpendicular to the aforementioned first direction, i.e., the second direction, when viewed from above.

[0235] The region having the second base layer and the drift layer connected only through a path not via the first base layer.

[0236] (Note 9) The semiconductor device according to any one of Notes 1 to 8, wherein,

[0237] The aforementioned semiconductor substrate is formed from a wide-bandgap semiconductor.

[0238] (Note 10) A method for manufacturing a semiconductor device, wherein,

[0239] The method for manufacturing the above-mentioned semiconductor device includes:

[0240] The process of forming a drift layer of the first conductivity type on a semiconductor substrate;

[0241] The process of forming a first base layer of a first conductivity type by ion implanting a first impurity onto the upper surface side of the drift layer;

[0242] The process of forming a second base layer of a second conductivity type arranged side by side with the first base layer on the upper surface side of the drift layer by forming a first mask on the upper surface side of the first base layer and ion implanting a second impurity;

[0243] The process of forming a thin film on the upper surface and sidewalls of the first mask and on the upper surface of the second base layer;

[0244] The process of forming a second mask having the first mask by etching the above-mentioned thin film;

[0245] The process of forming a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer by ion implanting a first impurity on the upper surface side of the second base layer and the second mask.

[0246] The process of removing the second mask mentioned above;

[0247] The process of forming a second type of contact layer selectively disposed on the upper surface side of the second base layer by selectively ion implanting the second impurity on the upper surface side of the source layer;

[0248] The process of forming a gate oxide film on the first base layer, the second base layer, the source layer and the contact layer;

[0249] The process of forming a gate electrode on the aforementioned gate oxide film;

[0250] A process of forming an interlayer insulating film disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and having a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer.

[0251] The process of forming a source electrode that is connected to the source layer via the first contact hole and to the contact layer via the second contact hole; and

[0252] The process of forming a drain electrode on the lower surface side of the aforementioned drift layer,

[0253] The first contact hole and the second contact hole are separated by the interlayer insulating film.

[0254] (Appendix 11) A method for manufacturing a semiconductor device, wherein,

[0255] The method for manufacturing the above-mentioned semiconductor device includes:

[0256] The process of forming a drift layer of the first conductivity type on a semiconductor substrate;

[0257] The process of forming a first base layer of a first conductivity type by ion implanting a first impurity onto the upper surface side of the drift layer;

[0258] The process of forming a second base layer of a second conductivity type arranged side by side with the first base layer on the upper surface side of the drift layer by forming a first mask on the upper surface side of the first base layer and ion implanting a second impurity;

[0259] The process of forming a thin film on the upper surface and sidewalls of the first mask and on the upper surface of the second base layer;

[0260] The process of forming a second mask having the first mask by etching the above-mentioned thin film;

[0261] The process of forming a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer by ion implanting a first impurity on the upper surface side of the second base layer and the second mask;

[0262] The process of removing the second mask mentioned above;

[0263] The process of forming a second type of contact layer selectively disposed on the upper surface side of the second base layer by selectively ion implanting the second impurity on the upper surface side of the source layer;

[0264] The process of forming a gate oxide film on the first base layer, the second base layer, the source layer and the contact layer;

[0265] The process of forming a gate electrode on the aforementioned gate oxide film;

[0266] A process of forming an interlayer insulating film disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and having a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer.

[0267] The process of forming a source electrode that is connected to the source layer via the first contact hole and to the contact layer via the second contact hole; and

[0268] The process of forming a drain electrode on the lower surface side of the aforementioned drift layer,

[0269] The openings of the first contact hole and the second contact hole are alternately arranged facing the first direction when viewed from above.

[0270] The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor substrate has a drift layer of a first conductivity type, a first base layer of a first conductivity type and a second base layer of a second conductivity type disposed side by side on the upper surface side of the drift layer, a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the first base layer, and a contact layer of a second conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the second base layer; A gate oxide film is disposed on the first base layer, the second base layer, the source layer, and the contact layer; A gate electrode is disposed on the gate oxide film; An interlayer insulating film is disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and has a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer. The source electrode is connected to the source layer via the first contact hole and to the contact layer via the second contact hole; as well as The drain electrode is connected to the lower surface side of the drift layer. The first contact hole and the second contact hole are separated by the interlayer insulating film.

2. The semiconductor device according to claim 1, characterized in that, The openings of the first contact hole and the second contact hole are alternately arranged facing the first direction when viewed from above. The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole.

3. The semiconductor device according to claim 1, characterized in that, The openings of the first contact hole and the second contact hole have the same shape and size, and are arranged alternately at constant intervals facing the first direction when viewed from above.

4. The semiconductor device according to claim 1, characterized in that, The openings of the first contact hole and the second contact hole have the same shape and size. A first contact hole group is formed, in which m of the first contact holes are arranged at constant intervals in a first direction. A second contact hole group is formed, in which n second contact holes are arranged at constant intervals facing the first direction. When viewed from above, the first and second contact hole groups are arranged alternately at a constant interval, facing the first direction. m is a value greater than 1 and less than n.

5. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor substrate has a drift layer of a first conductivity type, a first base layer of a first conductivity type and a second base layer of a second conductivity type disposed side by side on the upper surface side of the drift layer, a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the first base layer, and a contact layer of a second conductivity type selectively disposed on the upper surface side of the second base layer and having an impurity concentration higher than that of the second base layer; A gate oxide film is disposed on the first base layer, the second base layer, the source layer, and the contact layer; A gate electrode is disposed on the gate oxide film; An interlayer insulating film is disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and has a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer. The source electrode is connected to the source layer via the first contact hole and to the contact layer via the second contact hole; as well as The drain electrode is connected to the lower surface side of the drift layer. The openings of the first contact hole and the second contact hole are alternately arranged facing the first direction when viewed from above. The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction.

6. The semiconductor device according to claim 1 or 5, characterized in that, The region having the second base layer and the contact layer connected only through a path not via the source layer.

7. The semiconductor device according to claim 1 or 5, characterized in that, The semiconductor substrate further comprises a diffusion layer of a second conductivity type disposed above the drift layer and below the gate oxide film. The plurality of contact layers are arranged at constant intervals facing a first direction when viewed from above. The diffusion layer and the first base layer are arranged alternately at a constant interval toward the first direction when viewed from above. When viewed from above, the diffusion layer and the contact layer are alternately arranged at constant intervals in a direction perpendicular to the first direction, i.e., the second direction. The semiconductor device has a region in which the second base layer and the drift layer are connected only through a path that does not pass through the first base layer.

8. The semiconductor device according to claim 1 or 5, characterized in that, The semiconductor substrate further comprises a diffusion layer of a second conductivity type disposed above the drift layer and below the gate oxide film. The plurality of contact layers are arranged at constant intervals facing a first direction when viewed from above. The diffusion layer and the first base layer are arranged alternately at a constant interval toward the first direction when viewed from above. The region sandwiched between the diffusion layer, the contact layer, and another contact layer is arranged alternately at constant intervals in a direction perpendicular to the first direction, i.e., the second direction, when viewed from above. The semiconductor device has a region in which the second base layer and the drift layer are connected only through a path that does not pass through the first base layer.

9. The semiconductor device according to claim 1 or 5, characterized in that, The semiconductor substrate is formed of a wide-bandgap semiconductor.

10. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device comprises: The process of forming a drift layer of the first conductivity type on a semiconductor substrate; The process of forming a first base layer of a first conductivity type by ion implantation of a first impurity onto the upper surface side of the drift layer; The process of forming a second base layer of a second conductivity type arranged side by side with the first base layer on the upper surface side of the drift layer by forming a first mask on the upper surface side of the first base layer and ion implanting a second impurity; The process of forming a thin film on the upper surface and sidewalls of the first mask and on the upper surface of the second base layer; The process of forming a second mask having the first mask by etching the thin film; The process of forming a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer by ion implanting a first impurity on the upper surface side of the second base layer and the second mask; The process of removing the second mask; The process of selectively ion implanting the second impurity onto the upper surface side of the source layer to form a contact layer of a second conductivity type selectively disposed on the upper surface side of the second base layer; The process of forming a gate oxide film on the first base layer, the second base layer, the source layer and the contact layer; The process of forming a gate electrode on the gate oxide film; The process of forming an interlayer insulating film disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and having a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer; The process of forming a source electrode that is connected to the source layer via the first contact hole and to the contact layer via the second contact hole; and The process of forming a drain electrode on the lower surface side of the drift layer. The first contact hole and the second contact hole are separated by the interlayer insulating film.

11. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device comprises: The process of forming a drift layer of the first conductivity type on a semiconductor substrate; The process of forming a first base layer of a first conductivity type by ion implantation of a first impurity onto the upper surface side of the drift layer; The process of forming a second base layer of a second conductivity type arranged side by side with the first base layer on the upper surface side of the drift layer by forming a first mask on the upper surface side of the first base layer and ion implanting a second impurity; The process of forming a thin film on the upper surface and sidewalls of the first mask and on the upper surface of the second base layer; The process of forming a second mask having the first mask by etching the thin film; The process of forming a source layer of a first conductivity type selectively disposed on the upper surface side of the second base layer by ion implanting a first impurity on the upper surface side of the second base layer and the second mask; The process of removing the second mask; The process of selectively ion implanting the second impurity onto the upper surface side of the source layer to form a contact layer of a second conductivity type selectively disposed on the upper surface side of the second base layer; The process of forming a gate oxide film on the first base layer, the second base layer, the source layer and the contact layer; The process of forming a gate electrode on the gate oxide film; The process of forming an interlayer insulating film disposed on the semiconductor substrate in such a way as to cover the gate oxide film and the gate electrode, and having a plurality of first contact holes that expose a portion of the source layer and a plurality of second contact holes that expose a portion of the contact layer; The process of forming a source electrode that is connected to the source layer via the first contact hole and to the contact layer via the second contact hole; and The process of forming a drain electrode on the lower surface side of the drift layer. The openings of the first contact hole and the second contact hole are alternately arranged facing the first direction when viewed from above. The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction.

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