Image sensor and manufacturing method thereof

Abstract

An image sensor and a method of manufacturing the same are provided. The image sensor includes a substrate, a pixel region defined by an isolation structure in the substrate, a first floating diffusion region on the pixel region, a source follower gate electrode on the substrate, and a first buried line on the isolation structure. A first buried line electrically connects the first floating diffusion region to the source follower gate electrode, and the first buried line is disposed in the substrate. The first buried line includes a first line portion extending from the first floating diffusion region in a first direction and a second line portion extending from the source follower gate electrode in a second direction crossing the first direction.

Description

Technical Field

[0001] This disclosure relates to an image sensor and a method of manufacturing an image sensor, and more specifically, to an image sensor having improved electrical and optical properties. Background Technology

[0002] Image sensors convert optical images into electrical signals. Recently, with the development of the computer and communications industries, there has been an increasing demand for image sensors with improved performance in various fields such as digital cameras, camcorders, personal communication systems (PCS), game consoles, security cameras, and medical miniature cameras.

[0003] Different types of image sensors exist, such as charge-coupled devices (CCDs) and CMOS image sensors. CMOS image sensors are simple to drive, and because the signal processing circuitry is integrated on a single chip, they can be offered in small-size products. CMOS image sensors also have relatively low power consumption, and therefore can be easily applied to products with limited battery capacity. Furthermore, CMOS process technology can be compatiblely used for CMOS image sensors, thereby reducing manufacturing costs. Therefore, the use of CMOS image sensors is rapidly increasing because, with technological advancements, CMOS image sensors can provide high resolution. Summary of the Invention

[0004] One aspect is to provide an image sensor with improved electrical and optical properties.

[0005] On the other hand, it provides a method for manufacturing image sensors with improved electrical and optical properties.

[0006] The aspects are not limited to those mentioned above, and those skilled in the art will clearly understand from the detailed description of the various embodiments below that other aspects not mentioned will be apparent.

[0007] According to one or more embodiments, an image sensor is provided, comprising: a substrate; a pixel region defined in the substrate by an isolation structure; a first floating diffusion region on the pixel region; a source follower gate electrode on the substrate; and a first buried line on the isolation structure. The first buried line electrically connects the first floating diffusion region to the source follower gate electrode, and the first buried line is disposed in the substrate. The first buried line includes a first line portion extending from the first floating diffusion region in a first direction and a second line portion extending from the source follower gate electrode in a second direction intersecting the first direction.

[0008] According to another aspect of one or more embodiments, an image sensor is provided, comprising: a substrate; a pixel region defined in the substrate by an isolation structure; a first floating diffusion region on the pixel region; a source follower gate electrode on the substrate; a first buried line on the isolation structure; and a first source follower contact on the source follower gate electrode, wherein the first buried line electrically connects the first floating diffusion region to the source follower gate electrode, and the first source follower contact contacts each of the source follower gate electrode and the first buried line.

[0009] According to another aspect of one or more embodiments, an image sensor is provided, comprising: a substrate including a first pixel group and a second pixel group adjacent to the first pixel group in a first direction, each of the first pixel group and the second pixel group including a 2×2 pixel array; an isolation structure disposed in the substrate and isolating the first pixel group, the second pixel group and the pixels; a first floating diffusion region located at the center of the first pixel group; a second floating diffusion region located at the center of the second pixel group; a source follower gate electrode disposed on the substrate in one pixel of the first pixel group; a photoelectric conversion unit disposed in the substrate of each pixel; a first transmission gate electrode adjacent to the first floating diffusion region in each pixel of the first pixel group; a second transmission gate electrode adjacent to the second floating diffusion region in each pixel of the second pixel group; a first buried line disposed in the substrate and electrically connecting the first floating diffusion region to the source follower gate electrode; and a first source follower contact on the source follower gate electrode, wherein the first floating diffusion region is electrically connected to the first source follower contact through the first buried line.

[0010] According to another aspect of one or more embodiments, a method for manufacturing an image sensor is provided, the method comprising: forming a pixel region defined by an isolation structure on a substrate; forming a first floating diffusion region and a first buried line in the substrate; forming a source follower gate electrode on the pixel region, the first buried line electrically connecting the first floating diffusion region to the source follower gate electrode; and forming a first source follower contact on the source follower gate electrode. Forming the first floating diffusion region and the first buried line includes forming a first etched portion by etching an upper portion of the substrate and an upper portion of the isolation structure, and filling the first etched portion with a semiconductor material. Attached Figure Description

[0011] The above and other aspects are further described with reference to the accompanying drawings, which are included to provide a further understanding and are incorporated in and constitute a part of this specification, and in the drawings:

[0012] Figure 1 This is a schematic plan view of an image sensor according to some embodiments;

[0013] Figure 2It shows that lines have been added. Figure 1 A plan view of the image sensor;

[0014] Figure 3 yes Figure 2 A partial perspective view of the image sensor;

[0015] Figure 4 yes Figure 2 The circuit diagram of the image sensor;

[0016] Figure 5 It is based on some implementation methods along Figure 2 A cross-sectional view taken from line A-A';

[0017] Figure 6 It is based on some implementation methods along Figure 2 A cross-sectional view taken from line B-B';

[0018] Figure 7A It is based on some implementation methods Figure 6 An enlarged view of region M in the cross-sectional diagram;

[0019] Figure 7B It is based on some implementation methods Figure 6 An enlarged view of region M in the cross-sectional diagram;

[0020] Figures 8A to 16B This is a diagram illustrating a method for manufacturing an image sensor according to some embodiments;

[0021] Figure 17 This is a plan view of an image sensor according to some implementation methods;

[0022] Figure 18 and Figure 19 It is a plan view of an image sensor according to some embodiments; and

[0023] Figure 20 and Figure 21 This is a cross-sectional view of an image sensor according to some implementation methods. Detailed Implementation

[0024] Various embodiments will be described in more detail below with reference to the accompanying drawings. Throughout this document, terms indicating order, such as “first,” “second,” etc., are used to distinguish elements having the same / similar functions, and ordinal numbers may be interchanged depending on the order in which the terms are mentioned. As used herein, phrases of the form “at least one of A, B, or C” include, within their scope, “A only,” “B only,” “C only,” “A and B,” “A and C,” “B and C,” and “A, B, and C.”

[0025] Figure 1This is a schematic plan view of an image sensor according to some implementation methods. Figure 2 It shows that lines have been added. Figure 1 A plan view of the image sensor. Figure 3 yes Figure 2 A partial perspective view of the image sensor. Figure 4 yes Figure 2 Circuit diagram of the image sensor. Figure 5 It is based on some implementation methods along Figure 2 A cross-sectional view taken from line A-A'. Figure 6 It is based on some implementation methods along Figure 2 The cross-sectional view taken by line B-B'.

[0026] refer to Figures 1 to 6 The image sensor 100 is provided with a substrate 1. The substrate 1 may include a plurality of pixels PX arranged in two dimensions along a first direction D1 and a second direction D2 that intersect each other. Figure 1 A pixel PX is shown as an example. The substrate 1 may include a first surface 1a and a second surface 1b opposite to each other (see [reference]). Figure 3 Light can be incident on substrate 1 through the second surface 1b. Substrate 1 can be a silicon-on-insulator (SOI) substrate, an epitaxial layer, or a single-crystal wafer comprising silicon and / or germanium. A well region PW can be formed in substrate 1 (see [reference]). Figure 5 The well region PW may be doped with an impurity of a first conductivity type. In some embodiments, the first conductivity type may be, for example, P-type. In some embodiments, the first conductivity type impurity may be, for example, boron. However, the embodiments are not limited thereto, and in some embodiments, other materials may be used for the first conductivity type impurity. In some embodiments, the first conductivity type may be N-type.

[0027] The substrate 1 may include an isolation structure 10, which isolates and defines the photoelectric conversion units PD from each other. The isolation structure 10 may be disposed in the substrate 1. In a plan view, the isolation structure 10 may have a grid shape. The isolation structure 10 may include an isolation conductive pattern disposed therein and an isolation insulating pattern between the isolation conductive pattern and the substrate 1. The isolation structure 10 may penetrate the substrate 1. For ease of illustration, the isolation structure 10 has already been shown... Figure 3 omitted.

[0028] The pixels PX constituting a 2×2 array can be arranged in multiple pixel groups. These multiple pixel groups can be arranged along a first direction D1 and a second direction D2. (See reference) Figure 1 and Figure 2The pixel group may include a first pixel group GRP1 and a second pixel group GRP2 arranged along a first direction D1. The first pixel group GRP1 may include a first pixel PX (1), a second pixel PX (2), a third pixel PX (3), and a fourth pixel PX (4) arranged clockwise. The second pixel group GRP2 may include a fifth pixel PX (5), a sixth pixel PX (6), a seventh pixel PX (7), and an eighth pixel PX (8) arranged clockwise. The isolation structure 10 can isolate the pixel groups GRP1 and GRP2 from each other. The isolation structure 10 can isolate the pixels PX from each other in each of the pixel groups GRP1 and GRP2. The isolation structure 10 may be omitted at the center of each of the pixel groups GRP1 and GRP2.

[0029] A photoelectric conversion unit (PD) can be disposed in each of the pixels (PX) on the substrate 1. The PD can be doped with an impurity of a second conductivity type opposite to the first conductivity type. In some embodiments, the second conductivity type can be, for example, N-type. In some embodiments, the second conductivity type impurity can be, for example, phosphorus or arsenic. However, the embodiments are not limited thereto, and in some embodiments, the second conductivity type impurity can be P-type. The PD, which is an N-type impurity region, can form a PN junction with the well region (PW), which is a P-type impurity region, to constitute a photodiode. When light is incident on the PN junction, electron-hole pairs can be generated. Electrons can move to the PD, which is an N-type impurity region, and can accumulate.

[0030] The substrate 1 may include a device isolation structure 20, which is disposed adjacent to a first surface 1a of the substrate 1 in each pixel PX and defines a first active region ACT1 and a second active region ACT2. The device isolation structure 20 may be formed using a shallow trench isolation (STI) method. The device isolation structure 20 may be formed as a single-layer or multi-layer structure of at least one of a silicon oxide film, a silicon nitride film, or a silicon oxide nitride film. In some embodiments, the device isolation structure 20 may be formed by doping a portion of the substrate 1 with an impurity of the same first conductivity type as the impurity doped in the substrate 1, and the device isolation structure 20 may have a higher doping concentration than the remaining portion of the substrate 1. In some embodiments, the isolation structure 10 may penetrate the device isolation structure 20. The device isolation structure 20 may be omitted at the center of each of the first pixel group GRP1 and the second pixel group GRP2. For ease of illustration, the device isolation structure 20 has been omitted. Figure 3 omitted.

[0031] Multiple transmission transistors can be arranged on the first active region ACT1 of the first pixel PX(1) to the eighth pixel PX(8). For example, the multiple transmission transistors may include a first transmission transistor T1, a second transmission transistor T2, a third transmission transistor T3, a fourth transmission transistor T4, a fifth transmission transistor T5, a sixth transmission transistor T6, a seventh transmission transistor T7, and an eighth transmission transistor T8. One end of the transmission transistor (one of the first to eighth transmission transistors T1 to T8) can be connected to the photoelectric conversion unit PD in each pixel PX. Each transmission transistor (one of the first to eighth transmission transistors T1 to T8) may include a floating diffusion region FD disposed in the substrate 1 and a transmission gate electrode TG disposed next to the floating diffusion region FD. The transmission gate electrode TG of the first pixel PX(1) to the eighth pixel PX(8) may be referred to as the first transmission gate electrode TG(1), the second transmission gate electrode TG(2), the third transmission gate electrode TG(3), the fourth transmission gate electrode TG(4), the fifth transmission gate electrode TG(5), the sixth transmission gate electrode TG(6), the seventh transmission gate electrode TG(7), and the eighth transmission gate electrode TG(8). A transfer gate electrode TG may include a first sub-transfer gate Ta and a second sub-transfer gate Tb that are separate from each other. The floating diffusion region FD may be doped with impurities of a second conductivity type.

[0032] The floating diffusion areas FD of the first pixel PX(1) to the fourth pixel PX(4) can be connected to each other and form the first common floating diffusion area FDC1 at the center of the first pixel group GRP1. The floating diffusion areas FD of the fifth pixel PX(5) to the eighth pixel PX(8) can be connected to each other and form the second common floating diffusion area FDC2 at the center of the second pixel group GRP2. The first pixel PX(1) to the fourth pixel PX(4) can share the first common floating diffusion area FDC1. The fifth pixel PX(5) to the eighth pixel PX(8) can share the second common floating diffusion area FDC2.

[0033] The first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 can be connected with the floating diffusion region FD (see...). Figure 4 The floating diffusion region FD is doped with the same concentration of a second conductivity type impurity as the floating diffusion region FD. For clarity, a portion of the floating diffusion region FD is referred to as the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2, but the terms first common floating diffusion region FDC1, second common floating diffusion region FDC2, and floating diffusion region FD can be substantially the same, and in some embodiments, there may be no boundary between them, and they can be used interchangeably. The first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 can also be referred to as the floating diffusion region FD.

[0034] The gate electrode of the driving transistor or the gate electrode of the dummy transistor can be disposed on each of the second active regions ACT2 of the first pixel PX(1) to the eighth pixel PX(8). The second active region ACT2 can have an "L" shape in the planar view.

[0035] Specifically, refer to Figure 1 The gate electrode GE of the driving transistor can be located at the center of the second active region ACT2 of the first pixel PX(1) of the first pixel group GRP1. This structural configuration is because, since the junction area, which will be described later, is located on the first buried line, the gate electrode of the transistor of the second sub-chip CH2 can be positioned instead of a dummy gate electrode. The source / drain regions SD, doped with impurities of the second conductivity type, can be provided on both sides of the gate electrode GE in the substrate 1.

[0036] In some embodiments, a first dummy gate electrode may be disposed at the center of the second active region ACT2 of the first pixel PX(1) of the first pixel group GRP1. A first contact region may be disposed in the substrate 1 on one side of the first dummy gate electrode. The first contact region may be doped with impurities of a first conductivity type at a higher concentration than the impurities in the well region PW of the substrate 1. The first contact region may be in contact with the well region PW of the first pixel group GRP1. A source / drain region SD doped with impurities of a second conductivity type may be disposed in the substrate 1 on the other side of the first dummy gate electrode.

[0037] The second dual-conversion gate electrode DCG2 can be disposed at the center of the second active region ACT2 of the second pixel PX(2) of the first pixel group GRP1. Source / drain regions SD doped with impurities of the second conductivity type can be disposed on both sides of the second dual-conversion gate electrode DCG2 in the substrate 1, and can together with the second dual-conversion gate electrode DCG2 form a [structure / structure]. Figure 4 The second dual-conversion transistor DCX2.

[0038] The first dual-conversion gate electrode DCG1 can be disposed at the center of the second active region ACT2 of the third pixel PX(3) of the first pixel group GRP1. The source / drain regions SD doped with impurities of the second conductivity type can be disposed on both sides of the first dual-conversion gate electrode DCG1 in the substrate 1, and can together with the first dual-conversion gate electrode DCG1 form a [structure / structure]. Figure 4 The first dual-conversion transistor DCX1.

[0039] The first source follower gate electrode SF1 can be disposed at the center of the second active region ACT2 of the fourth pixel PX(4) of the first pixel group GRP1. The source / drain regions SD doped with impurities of the second conductivity type can be disposed on both sides of the first source follower gate electrode SF1 in the substrate 1, and can together with the first source follower gate electrode SF1 form a [structure / structure]. Figure 4 The first source follower transistor S1.

[0040] The fifth pixel PX(5) of the second pixel group GRP2 is located next to the fourth pixel PX(4) of the first pixel group GRP1 in the first direction D1. The second source follower gate electrode SF2 can be disposed at the center of the second active region ACT2 of the fifth pixel PX(5) of the second pixel group GRP2. The source / drain regions SD doped with impurities of the second conductivity type can be disposed on both sides of the second source follower gate electrode SF2 in the substrate 1, and can be formed together with the second source follower gate electrode SF2. Figure 4 The second source follower transistor S2. Regarding... Figure 1-6 In the illustrated embodiment, the second source follower gate electrode SF2 and the first source follower gate electrode SF1 can be integrally connected to each other and can form a single source follower gate electrode SF. That is, the source follower gate electrode SF can traverse the isolation structure 10 between the first pixel group GRP1 and the second pixel group GRP2.

[0041] The select gate electrode SEL can be disposed at the center of the second active region ACT2 of the sixth pixel PX(6) of the second pixel group GRP2. Source / drain regions SD doped with impurities of the second conductivity type can be disposed on both sides of the select gate electrode SEL in the substrate 1, and can form a structure together with the select gate electrode SEL. Figure 4 The selection transistor SE.

[0042] The reset gate electrode RG can be disposed at the center of the second active region ACT2 of the seventh pixel PX(7) of the second pixel group GRP2. Source / drain regions SD doped with impurities of the second conductivity type can be disposed on both sides of the reset gate electrode RG in the substrate 1, and can form a structure together with the reset gate electrode RG. Figure 4 The reset transistor RX.

[0043] The gate electrode GE of the driving transistor can be located at the center of the second active region ACT2 of the eighth pixel PX(8) of the second pixel group GRP2. This structural configuration is because, since the junction area, which will be described later, is located on the first buried line, the gate electrode of the transistor of the second sub-chip CH2 can be positioned instead of a dummy gate electrode. The source / drain regions SD, doped with impurities of the second conductivity type, can be provided on both sides of the gate electrode GE in the substrate 1.

[0044] In some embodiments, the second dummy gate electrode may be disposed at the center of the second active region ACT2 of the eighth pixel PX(8) of the second pixel group GRP2. A junction region may be disposed in the substrate 1 on one side of the second dummy gate electrode. The junction region may be doped with impurities of a first conductivity type at a higher concentration than the well region PW of the substrate 1. The junction region may be in contact with the well region PW of the second pixel group GRP2. The source / drain region SD may be disposed in the substrate 1 on the other side of the second dummy gate electrode.

[0045] refer to Figure 2 and Figure 3 The transmission gate connection line TGL can connect the first sub-transmission gate Ta and the second sub-transmission gate Tb, which are adjacent to each other, on a first active region ACT1.

[0046] refer to Figure 2 The source / drain region SD on one side of each of the first source follower gate electrode SF1 and the second source follower gate electrode SF2 can be connected to the pixel voltage line MPL. The source / drain region SD on one side of each of the gate electrodes GE can be connected to the pixel voltage line MPL.

[0047] The source / drain regions SD on the other side of each of the first source follower gate electrode SF1 and the second source follower gate electrode SF2, and the source / drain region SD on one side of the select gate electrode SEL, can be connected to the SF-SEL connection line SSL. The SF-SEL connection line SSL can have an "L" shape in the plan view. The source / drain region SD on the other side of the select gate electrode SEL can be connected to the output line Vout. The connections between other transistors can be... Figure 4 The connection relationships are the same.

[0048] refer to Figures 1 to 4 According to Figure 1-4 In the image sensor 100 of the embodiment shown, the first pixel PX(1) to the eighth pixel PX(8) arranged in the first pixel group GRP1 and the second pixel group GRP2 can share the first source follower transistor S1 and the second source follower transistor S2, the reset transistor RX, the first double conversion transistor DCX1 and the second double conversion transistor DCX2, and the selection transistor SE.

[0049] In operation, by turning on one of the transmission transistors in pixel PX (one of the first transmission transistor T1 to the eighth transmission transistor T8), electrons accumulated in the photoelectric conversion section PD can be moved to the floating diffusion region FD. Therefore, the voltage level of the floating diffusion region FD can be changed. The reset transistor RX can reset the floating diffusion region FD. For example, with the first dual-conversion transistor DCX1 and the second dual-conversion transistor DCX2 turned on, the reset transistor RX can electrically connect the floating diffusion region FD to the power supply voltage Vpix based on an electrical signal (reset signal) applied to the reset gate electrode RG. The reset transistor RX can remove or release electrons stored in the floating diffusion region FD by driving the floating diffusion region FD with the power supply voltage Vpix based on the reset signal.

[0050] The first source follower transistor S1 and the second source follower transistor S2 can be connected in parallel to form a finger-type source follower transistor SX. The source follower transistor SX can have a source follower gate electrode SF in which the first source follower gate electrode SF1 and the second source follower gate electrode SF2 are connected. The source follower gate electrode SF can be connected to the floating diffusion region FD.

[0051] The source follower transistor SX can be connected between the supply voltage Vpix and the select transistor SE. The voltage level at one end of the source follower transistor SX can be changed based on the voltage level of the floating diffusion region FD, and when the select transistor SE is turned on, the output signal can be transmitted through the output line Vout.

[0052] Source follower transistors are more sensitive to the inherent thermal and flicker noise of transistor elements than transfer, reset, and select transistors. Noise present in a source follower transistor element is transmitted to the internal circuitry as is, leading to image quality degradation. Forming the source follower transistor into a finger-like shape can help reduce this effect of the transistor element's inherent thermal and flicker noise and fully read the potential of the floating diffusion region FD. Furthermore, the amount of current in the source follower transistor SX can be increased. Therefore, the linearity of the voltage-current curve of the source follower transistor SX can be improved, and noise such as random noise and random telegraph signals can be reduced.

[0053] The first dual-conversion transistor DCX1 and the second dual-conversion transistor DCX2 can be connected between the floating diffusion region FD and the reset transistor RX. When the first dual-conversion transistor DCX1 and the second dual-conversion transistor DCX2 are off, the full-well capacity (FWC) of the pixel PX can be the capacitance of the floating diffusion region FD. When at least one of the first dual-conversion transistor DCX1 or the second dual-conversion transistor DCX2 is on, the FWC of the pixel PX can increase compared to the capacitance of the floating diffusion region FD. The first dual-conversion transistor DCX1 and the second dual-conversion transistor DCX2 can both be off under low illumination. Under intermediate illumination, the first dual-conversion transistor DCX1 can be on, and the second dual-conversion transistor DCX2 can be off. The first dual-conversion transistor DCX1 and the second dual-conversion transistor DCX2 can both be on under high illumination. As described above, the conversion gain of the pixel PX can be changed by turning the first dual-conversion transistor DCX1 and the second dual-conversion transistor DCX2 on / off according to the illumination. Therefore, a clear image with improved high dynamic range (HDR) characteristics can be provided.

[0054] In full mode, in image sensor 100, turn-on voltages can be sequentially applied to the first transmission gate electrode TG (1) to the eighth transmission gate electrode TG (8), and a signal for each pixel PX can be output. In some embodiments, in binning mode, turn-on voltages can be simultaneously applied to the transmission gate electrode TG of each pixel group, and a signal can be output for each pixel group.

[0055] The first buried line (BFD) can be provided in the upper part of the substrate 1. The first buried line (BFD) can be provided on the upper surface of the isolation structure 10. The first buried line (BFD) can extend along the isolation structure 10. The first buried line (BFD) can have a grid shape in a plan view. The upper surface of the first buried line (BFD) can be substantially coplanar with the upper surfaces of the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2. The first buried line (BFD) and the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 can form a connecting line FDL.

[0056] The upper surface of the first buried line BFD can be located at a lower level than the upper surface of the source follower gate electrode SF and the upper surface of the transfer gate electrode TG (in Figure 3 (Best viewed from the center). The bottom surface of the first buried line BFD can be located at a level higher than the bottom surface of the transfer gate electrode TG (in... Figure 5 For the best view, see also the description below. Figure 14A The transmission gate connection line (TGL) and the pixel voltage line (MPL) can be located at a higher level than the first buried line (BFD).

[0057] The first buried wire (BFD) can directly contact each of the first common floating diffusion region (FDC1), the second common floating diffusion region (FDC2), and the source follower gate electrode (SF). The first buried wire (BFD) can electrically connect the first common floating diffusion region (FDC1), the second common floating diffusion region (FDC2), and the source follower gate electrode (SF) to each other. The boundaries between the first buried wire (BFD) and the first common floating diffusion region (FDC1), and between the first buried wire (BFD) and the second common floating diffusion region (FDC2), may not be visually distinguishable.

[0058] The first buried line BFD may include a first buried portion B1 extending from the first common floating diffusion region FDC1 in a first direction D1. The first buried line BFD may include a second buried portion B2 extending from the source follower gate electrode SF in a second direction D2 to the first buried portion B1. The first buried portion B1 and the second buried portion B2 may extend in directions that intersect each other and may meet and contact each other. The first buried portion B1 and the second buried portion B2 may extend along the isolation structure 10. The width of the first buried portion B1 in the second direction D2 and the width of the second buried portion B2 in the first direction D1 may be smaller than the width of the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 in the second direction D2.

[0059] The first buried portion B1 may extend in the first direction D1 and electrically connect the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 to each other. At least a portion of the second buried portion B2 may perpendicularly overlap with the source follower gate electrode SF. In some embodiments, the first buried line BFD may extend and may be connected to the source / drain region SD on one side of the first dual-conversion gate electrode DCG1.

[0060] The first buried line BFD may include the same material as the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2. The first buried line BFD may include a semiconductor material. For example, in some embodiments, the first buried line BFD may include silicon.

[0061] refer to Figure 5 and Figure 6The gate insulating film Gox can be interposed between the transfer gate electrode TG and the substrate 1. The gate insulating film Gox can also be interposed between the gate electrodes RG, DCG1, DCG2, SF1, SF2, SEL, and GE of other driving transistors and the substrate 1. The gate insulating film Gox can comprise a single layer or multiple layers of at least one of silicon oxide, metal oxide, silicon nitride, or silicon nitride. The transfer gate electrode TG and the gate electrodes RG, DCG1, DCG2, SF1, SF2, SEL, and GE can be formed from doped polycrystalline silicon or at least one of a metal such as tungsten or aluminum.

[0062] The photoelectric conversion unit PD disposed in the substrate 1 in the pixel PX can overlap with a corresponding one of the transmission gate electrodes TG and a corresponding one of the gate electrodes RG, DCG1, DCG2, SF1, SF2, SEL, and GE (see [reference]). Figure 1 , Figure 2 and Figure 5 The side surface of the transfer gate electrode TG may be covered with spacers 25. The spacers 25 may comprise a single layer or multiple layers of at least one of silicon oxide, silicon nitride, or silicon nitride.

[0063] The first surface 1a of substrate 1 and the gate electrodes TG, RG, DCG1, DCG2, SF1, SF2, SEL, and GE may be covered with a first interlayer insulating layer IL1. The first interlayer insulating layer IL1 may include an etch stop film 3 and a planarization film 5. The etch stop film 3 may be formed conformally. The planarization film 5 may fill the space between the gate electrodes TG, RG, DCG1, DCG2, SF1, SF2, SEL, and GE. The lower surface of the planarization film 5 may be coplanar with the upper surface of the etch stop film 3 on the gate electrodes TG, RG, DCG1, DCG2, SF1, SF2, SEL, and GE. The etch stop film 3 may have etch selectivity relative to the planarization film 5. The etch stop film 3 may be formed of, for example, SiN, SiCN, or SiON. The planarization film 5 may be formed of, for example, silicon oxide or a porous insulator.

[0064] First contact plugs 15a, 15b, and 15c can penetrate the first interlayer insulating layer IL1. First contact plugs 15a, 15b, and 15c may include a first gate contact plug 15a, a second gate contact plug 15b, and a first source follower contact 15c. First gate contact plug 15a can penetrate the etch stop film 3 and planarization film 5 of the first interlayer insulating layer IL1 to contact a corresponding gate electrode among gate electrodes TG, RG, DCG1, DCG2, SF1, SF2, and SEL. Second gate contact plug 15b can penetrate the etch stop film 3 and planarization film 5 of the first interlayer insulating layer IL1 to contact a corresponding source / drain region SD among the source / drain regions SD. First gate contact plugs 15a and second gate contact plugs 15b may include a conductive material. For example, in some embodiments, first gate contact plugs 15a and second gate contact plugs 15b may include tungsten. In some embodiments, the first gate contact plug 15a and the second gate contact plug 15b may be formed of polysilicon doped with impurities.

[0065] Figure 7A It is based on some implementation methods Figure 6 A magnified view of region M. (Refer to...) Figure 6 and Figure 7A The first source follower contact 15c is described in more detail.

[0066] refer to Figure 6 and Figure 7A A gate insulating film (Gox) may be provided on the device isolation structure 20 and the first buried line (BFD). The gate insulating film (Gox) may comprise a single layer or multiple layers of at least one of silicon oxide, metal oxide, silicon nitride, or silicon nitride. A source follower gate electrode (SF) and a spacer 25 may be provided on the gate insulating film (Gox). The spacer 25 may cover a portion of the side surface of the source follower gate electrode (SF). A first interlayer insulating layer (IL1) may be provided on the source follower gate electrode (SF) and the gate insulating film (Gox). Specifically, an etch stop film (3) and a planarization film (5) may be sequentially provided on the upper surface of each of the source follower gate electrode (SF) and the gate insulating film (Gox).

[0067] The first source follower contact 15c can penetrate the etch stop film 3 and planarization film 5 of the first interlayer insulating layer IL1 to contact the source follower gate electrode SF and the first buried line BFD. The bottom surface CTS1 of the first source follower contact 15c can contact the second buried portion B2 of the first buried line BFD. In other words, the lowest surface of the first source follower contact 15c can contact the second buried portion B2 of the first buried line BFD. The level of the bottom surface CTS1 of the first source follower contact 15c can be lower than the level of the upper surface of the first buried line BFD. The width of the first source follower contact 15c in the second direction D2 can be greater than the width of the first gate contact plug 15a and the second gate contact plug 15b. In other words, the minimum width of the first source follower contact 15c in the second direction D2 can be greater than the maximum width of the first gate contact plug 15a and the second gate contact plug 15b.

[0068] The first source follower contact 15c may include a first portion PT1 and a second portion PT2 on the first portion PT1. The first portion PT1 may be the portion that directly contacts the first buried line BFD. The lower portion of the first portion PT1 may be buried in the first buried line BFD. The second portion PT2 may include the portion that directly contacts the source follower gate electrode SF.

[0069] The first portion PT1 may have a first sidewall SW1 adjacent to the source follower gate electrode SF. The second portion PT2 may have a second sidewall SW2 adjacent to the source follower gate electrode. The first sidewall SW1 may be offset from the second sidewall SW2 in the second direction D2. The first sidewall SW1 may be spaced apart from the second sidewall SW2 in the second direction D2. At least a portion of the first sidewall SW1 may contact the spacer 25. The first sidewall SW1 may be spaced apart from the source follower gate electrode SF in the second direction D2. At least a portion of the second sidewall SW2 may be in direct contact with the source follower gate electrode SF and the etch stop film 3 of the first interlayer insulating layer IL1.

[0070] The second portion PT2 may include a first connecting outer wall CTS2 extending in the second direction D2. The first connecting outer wall CTS2 may connect to the first sidewall SW1 and the second sidewall SW2. The first connecting outer wall CTS2 may contact the source follower gate electrode SF and the spacer 25. The level of the first connecting outer wall CTS2 may be lower than the level of the upper surface of the source follower gate electrode SF. The level of the first connecting outer wall CTS2 may be higher than the level of the upper surface of the first buried line BFD. The first connecting outer wall CTS2 may be located on the boundary between the first portion PT1 and the second portion PT2.

[0071] The corresponding widths WD1 and WD2 of the first portion PT1 and the second portion PT2 can be increased in the vertical direction D3 of the bottom surface CTS1 away from the first source follower contact 15c. The maximum width of the first portion PT1 can be less than the minimum width of the second portion PT2. The difference between the maximum width of the first portion PT1 and the minimum width of the second portion PT2 can be equal to the width of the first connecting outer wall CTS2. The width of the first source follower contact 15c can change discontinuously at the boundary between the first portion PT1 and the second portion PT2.

[0072] The upper surface of the first source follower contact 15c can contact the etch stop film 3 of the second interlayer insulating layer IL2, which will be described later. The first liner M1 can be omitted from the first source follower contact 15c. As a result, the degrees of freedom for the liners in the second to fourth interlayer insulating layers IL2, IL3, and IL4 can be increased. In some embodiments, the first liner M1 can be provided on the first source follower contact 15c.

[0073] Figure 7B It is based on some implementation methods Figure 6 A magnified view of region M.

[0074] refer to Figure 7B The third portion PT3 can be inserted between the first portion PT1 and the second portion PT2 of the first source follower contact 15c. The third portion PT3 may include a third sidewall SW3 that contacts the gate electrode SF of the source follower. The third sidewall SW3 may be offset from the second sidewall SW2 in the second direction D2. The third sidewall SW3 may be spaced apart from the second sidewall SW2 in the second direction D2. The first sidewall SW1 may be spaced apart from the third sidewall SW3 in the second direction D2.

[0075] The third part PT3 may include a second connecting outer wall CTS3 extending in the second direction D2. At least a portion of the second connecting outer wall CTS3 may contact the spacer 25. The second connecting outer wall CTS3 may connect the first sidewall SW1 and the third sidewall SW3. The level of the second connecting outer wall CTS3 may be lower than the level of the first connecting outer wall CTS2. The level of the second connecting outer wall CTS3 may be between the level of the first connecting outer wall CTS2 and the level of the bottom surface CTS1 of the first source follower contact 15c.

[0076] The width WD3 of the third part PT3 can be increased in the vertical direction D3 of the bottom surface CTS1 away from the first source follower contact 15c. The minimum width of the third part PT3 can be greater than the maximum width of the first part PT1. The maximum width of the third part PT3 can be less than the minimum width of the second part PT2. The difference between the minimum width of the third part PT3 and the maximum width of the first part PT1 can be equal to the width of the second connecting outer wall CTS3. The difference between the maximum width of the third part PT3 and the minimum width of the second part PT2 can be equal to the width of the first connecting outer wall CTS2.

[0077] The width of the first source follower contact 15c may vary discontinuously at the boundary between the first portion PT1 and the third portion PT3. The width of the first source follower contact 15c may also vary discontinuously at the boundary between the second portion PT2 and the third portion PT3. Therefore, the first source follower contact 15c may include at least one discontinuous width variation.

[0078] The first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 can be electrically connected to the first source follower contact 15c via the first buried wire BFD. Therefore, the gate contact can be omitted on the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2.

[0079] refer to Figures 1 to 6 The image sensor according to various embodiments may include a first buried line BFD that connects the source follower gate electrode SF, the first common floating diffusion region FDC1, and the second common floating diffusion region FDC2 to each other. Since the first buried line BFD is buried in the substrate 1, the degree of freedom in designing the line arrangement can be increased.

[0080] Furthermore, the gate contacts directly connected to the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 can be omitted from the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2. Therefore, junction leakage between the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 and the gate contacts can be prevented / reduced.

[0081] return Figure 5The second to fourth interlayer insulating layers IL2, IL3, and IL4 can be sequentially stacked on the first interlayer insulating layer IL1. At least a portion of the second to fourth interlayer insulating layers IL2, IL3, and IL4 may include sequentially stacked etch stop film 3 and planarization film 5. The transmission gate connection TGL, the SF-SEL connection SSL, and the first liner M1 can be disposed in the second interlayer insulating layer IL2. The second contact plug 23 can penetrate the third interlayer insulating layer IL3 and can be connected to at least one of the first liner M1. The second liner M2 can be disposed on the third interlayer insulating layer IL3.

[0082] A fixed charge film 24 can be disposed on a second surface 1b of the substrate 1 to contact the second surface 1b. The fixed charge film 24 can contact the second surface 1b. The fixed charge film 24 can include a metal oxide film or a metal fluoride film containing oxygen or fluorine in insufficient amounts compared to the stoichiometric ratio. Therefore, the fixed charge film 24 can have a negative fixed charge. The fixed charge film 24 can be formed from a metal oxide or a metal fluoride comprising at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. Hole accumulation can occur around the fixed charge film 24. Therefore, the occurrence of dark current and white spots can be effectively reduced. The fixed charge film 24 can be at least one of an aluminum oxide film or a hafnium oxide film.

[0083] An antireflective film 42 may be disposed below a fixed-charge film 24. The antireflective film 42 may include, for example, a silicon nitride. A first grid pattern 48a and a second grid pattern 50a may be sequentially stacked on the antireflective film 42. The first grid pattern 48a and the second grid pattern 50a may have a grid shape in a planar view. The first grid pattern 48a and the second grid pattern 50a may expose the antireflective film 42.

[0084] The sidewalls of the second grid pattern 50a can be aligned with the sidewalls of the first grid pattern 48a. The first grid pattern 48a and the second grid pattern 50a can prevent crosstalk between adjacent pixels. The first grid pattern 48a can include a light-blocking material, such as titanium or tungsten. The second grid pattern 50a can include an organic material. The second grid pattern 50a can have a lower refractive index than the color filters CF1 and CF2. For example, the second grid pattern 50a can have a refractive index of about 1.3 or less.

[0085] Multiple color filters can be arranged on the antireflective film 42. In some embodiments, the multiple color filters may include a first color filter CF1 and a second color filter CF2. Color filters CF1 and CF2 may have different colors for each of the pixel groups GRP1 and GRP2. That is, the first color filter CF1 may be disposed below the first pixel group GRP1. The first pixel PX(1) to the fourth pixel PX(4) of the first pixel group GRP1 may be covered by the first color filter CF1 of the same color. The second color filter CF2 may be disposed below the second pixel group GRP2. The fifth pixel PX(5) to the eighth pixel PX(8) of the second pixel group GRP2 may be covered by the second color filter CF2 of the same color.

[0086] The first color filter CF1 and the second color filter CF2 may comprise a photoresist material to which dyes or pigments have been added. Multiple color filters may be arranged two-dimensionally along a first direction D1 and a second direction D2 constituting the color filter array. The color filter array may have an RGB pattern formed by red (R), green (G), and blue (B), or an RGBW pattern including white pixels. The white pixels may be pixels that sense all colors of light or all visible light. Color filters may be omitted from the white pixels, and a portion of the microlens ML may be located thereon in place of the color filters. The color filter array may have a complementary color pattern formed by cyan, yellow, and magenta. The color filter array may be in the form of a Bayer pattern, a 2×2 four-pattern pattern, a 3×3 nine-pattern pattern, or a 4×4 sixteen-pattern pattern.

[0087] Microlenses ML can be arranged below the first color filter CF1 and the second color filter CF2. The ends of the microlenses ML can contact and connect with each other. The first pixel group GRP1 can be covered by one microlens ML. The second pixel group GRP2 can be covered by another microlens ML. The image sensor 100 can perform an autofocus function by causing a phase shift in the output values ​​of pixels PX at different positions in a pixel group GRP1 or GRP2.

[0088] The image sensor 100 can also operate in global shutter mode. For operation in global shutter mode, the image sensor 100 may further include a pre-charge transistor, a sampling transistor, a capacitor, etc., connected to the output line Vout.

[0089] Figures 8A to 16B This is a diagram illustrating a method for manufacturing an image sensor according to some embodiments. Specifically, Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16AIt is along Figure 2 A cross-sectional view taken from line A-A'. Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B It is along Figure 2 The cross-sectional view taken by line B-B'.

[0090] refer to Figure 1 , Figure 8A and Figure 8B A substrate 1 may be provided, comprising a first surface 1a and a second surface 1b that are opposite to each other. A well region PW, an isolation structure 10, a device isolation structure 20, and a photoelectric conversion unit PD may be formed in the substrate 1. The lower surface of the isolation structure 10 may be spaced apart from the second surface 1b of the substrate 1. A source / drain region SD may be formed in the substrate 1.

[0091] An etch stop film 3, a first molding film ML1, a second molding film ML2, and a third molding film ML3 can be sequentially formed on the first surface 1a of the substrate 1. The first molding film ML1 may include a material that is etch-selective relative to the material of the etch stop film 3 and the isolation structure 10. For example, the first molding film ML1 may be a spin-coated hard mask (SOH). The second molding film ML2 and the third molding film ML3 may include materials that are etch-selective relative to the material of the first molding film ML1.

[0092] A first mask pattern MP1 can be formed on the third mold ML3. The first mask pattern MP1 may include a material that has etch selectivity relative to the first mold ML1.

[0093] refer to Figure 9A and Figure 9B The first to third mold films ML1, ML2, and ML3 can be etched by performing an etching process using the first mask pattern MP1 as a mask. Afterward, the second mold film ML2 and the third mold film ML3 can be removed. The height of the first mold film ML1 can be reduced.

[0094] The first etched portion FD_R can be formed by using the first etch film ML1 as a mask to perform the etching process. The first etched portion FD_R can be formed by etching the etch stop film 3, the upper portion of the isolation structure 10, and the upper portion of the substrate 1. The first etched portion FD_R may include a first recess R1 exposing the etched substrate 1 and a second recess R2 exposing the etched isolation structure 10. The bottom surface of the first recess R1 and the bottom surface of the second recess R2 may be at the same level. For example, in some embodiments, the bottom surfaces of the first recess R1 and the second recess R2 may be coplanar. In some embodiments, the bottom surfaces of the first recess R1 and the second recess R2 may be at different levels.

[0095] The second recess R2 may include a first recess portion and a second recess portion. The first recess portion may correspond to... Figure 1 The first buried portion B1, and the second recessed portion can correspond to Figure 1 The second buried portion B2. The first recessed portion may extend from the first recess R1 in the first direction D1. The second recessed portion may extend from the first recessed portion in the second direction D2.

[0096] refer to Figure 10A and Figure 10B A diffusion film PFD can be formed on the etch stop film 3 and the first etch portion FD_R. The diffusion film PFD can include a semiconductor material. For example, in some embodiments, the diffusion film PFD can include polycrystalline silicon.

[0097] refer to Figure 11A and Figure 11B The diffusion film PFD can be etched, and the interconnect line FDL can be formed by performing etch-back and / or chemical mechanical polishing (CMP) processes on the diffusion film PFD. Specifically, forming the interconnect line FDL may include forming a first common floating diffusion region FDC1 and a second common floating diffusion region FDC2 in a first recess R1 and forming a first buried line BFD in a second recess R2.

[0098] refer to Figure 12A and Figure 12B The etching stop film 3 on substrate 1 can be removed, and a second mask pattern MP2 can be formed. The second mask pattern MP2 may include a material that has etching selectivity relative to substrate 1. For example, the second mask pattern MP2 may include SiON.

[0099] The gate hole GH1 can be formed by etching the upper portion of the substrate 1 using the second mask pattern MP2 as a mask. The bottom surface of the gate hole GH1 can be lower than the bottom surface of the first buried line BFD.

[0100] refer to Figure 13A and Figure 13B The gate insulating film Gox can be conformally formed on the first surface 1a of the substrate 1 and the gate hole GH1. The gate insulating film Gox can include a single layer or multiple layers of at least one of silicon oxide, metal oxide, silicon nitride or silicon nitride.

[0101] A preliminary gate film (PGL) can be formed on the gate insulating film (Gox). The preliminary gate film (PGL) may include a metallic material. For example, in some embodiments, the preliminary gate film (PGL) may include at least one of doped polysilicon, tungsten, or aluminum.

[0102] refer to Figure 14A and Figure 14B The transmission gate electrode TG and the gate electrodes RG, DCG1, DCG2, SF, SEL and GE of the driving transistor can be formed by etching the gate insulating film Gox and the preliminary gate film PGL through a patterning process.

[0103] The spacer film 25 can be conformally formed on the front side of the substrate 1. For example, as Figure 14A and Figure 14B As shown, the spacer film 25 can cover the upper surface and sidewalls of the transfer gate electrode TG and the source follower gate electrode SF. The spacer film 25 can be a single layer or multiple layers of at least one of silicon oxide, silicon nitride, or silicon nitride.

[0104] refer to Figure 15A and Figure 15B The spacer 25 can be formed by etching the spacer film 25 using a patterning process. The spacer 25 can be formed on the sidewall of the transmission gate electrode TG and on the sidewall of each of the gate electrodes RG, DCG1, DCG2, SF, SEL and GE of the driving transistor.

[0105] An etch stop film 3 is conformally stacked on the first surface 1a of the substrate 1. A planarization film 5 is stacked on the etch stop film 3, and in some embodiments, the planarization film 5 can have a flat upper surface by performing a chemical mechanical polishing (CMP) process. The planarization film 5 can be formed to fill the space between the transfer gate electrode TG and the gate electrodes RG, DCG1, DCG2, SF1, SF2, and SEL, and can also have a flat upper surface. Therefore, a first interlayer insulating layer IL1 comprising the etch stop film 3 and the planarization film 5 can be formed.

[0106] refer to Figure 16A and Figure 16BThe first contact hole HL1, the second contact hole HL2, and the third contact hole HL3 can be formed by etching the first interlayer insulating layer IL1 using a patterning process. The first contact hole HL1 can penetrate the planarization film 5 and the etch stop film 3 of the first interlayer insulating layer IL1 and expose the source / drain region SD. The second contact hole HL2 can penetrate the planarization film 5 and the etch stop film 3 of the first interlayer insulating layer IL1 and expose the corresponding transfer gate electrode TG and the corresponding gate electrodes RG, DCG1, DCG2, SEL, and GE of the driving transistor.

[0107] The third contact hole HL3 can penetrate the planarization film 5 and etch stop film 3 of the first interlayer insulating layer IL1, and expose the source follower gate electrode SF and the first buried line BFD. The width of the third contact hole HL3 can decrease towards the bottom surface of the first buried line BFD. The width of the third contact hole HL3 can change discontinuously. This structural configuration is because the source follower gate electrode SF, spacer 25, and first buried line BFD have different etch selectivity relative to the patterning etching process.

[0108] Return to reference Figure 5 The first contact plugs 15a and 15b and the first source follower contact 15c can be formed by filling the first to third contact holes HL1, HL2 and HL3 with conductive material.

[0109] The second interlayer insulating layer IL2 can be formed on the first interlayer insulating layer IL1. The transfer gate connection line TGL, the SF-SEL connection line SSL, and the first substrate M1 can be formed in the second interlayer insulating layer IL2 by performing etching, plating, CMP, and other processes.

[0110] A third interlayer insulation layer IL3, a second contact plug 23, a fourth interlayer insulation layer IL4, a second liner M2, etc. are formed on the second interlayer insulation layer IL2.

[0111] A portion of the substrate 1 can be removed by performing a back-side grinding process on the second side 1b of the substrate 1, thereby exposing the isolation structure 10.

[0112] Subsequently, refer to Figure 5 A fixed charge film 24, an anti-reflection film 42, a first grid pattern 48a and a second grid pattern 50a, color filters CF1 and CF2, and a microlens ML are formed on the second surface 1b of the substrate 1.

[0113] Figure 17 This is a plan view of an image sensor according to some implementation methods.

[0114] refer to Figure 17A third pixel group GRP3, adjacent to the first pixel group GRP1 in the second direction D2, and a fourth pixel group GRP4, adjacent to the second pixel group GRP2 in the second direction D2, can be disposed on the substrate 1. The fourth pixel group GRP4 can be disposed below the third pixel group GRP3.

[0115] The third common floating diffusion region FDC3 can be provided at the center of the third pixel group GRP3. The fourth common floating diffusion region FDC4 can be provided at the center of the fourth pixel group GRP4. The third common floating diffusion region FDC3 and the fourth common floating diffusion region FDC4 can be substantially the same as the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2.

[0116] The first pixel group GRP1 to the fourth pixel group GRP4 can form a first shared group. A first buried pattern FDC5 can be provided at the center of the first shared group. The first buried pattern FDC5 can be an extension and expansion of the first buried line BFD. In some embodiments, the first buried pattern FDC5 can include polysilicon.

[0117] A common ground region (CGN) can be provided on the first buried pattern FDC5. In some embodiments, the common ground region (CGN) may be doped with impurities of a first conductivity type. The common ground region (CGN) may be doped with impurities of a conductivity type different from that of the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2. The concentration of impurities in the common ground region (CGN) may be higher than the concentration of impurities in the well region PW of the substrate 1. The common ground region (CGN) can be formed by connecting the respective ground regions (CGN) of the first pixel group GRP1 to the fourth pixel group GRP4 to each other.

[0118] The common ground area CGN can be connected to the grounding wire GNL via grounding contact 16. Grounding contact 16 can penetrate the first interlayer insulation layer IL1 and can be connected to the common ground area CGN. The grounding wire GNL can be provided in the second interlayer insulation layer IL2.

[0119] According to some implementations, since the common ground region CGN is formed on the first buried pattern FDC5, the common ground region CGN can be omitted in the pixel areas of the first pixel group GRP1 to the fourth pixel group GRP4. Therefore, the gate electrode of the existing dummy transistor can be used as the gate electrode of the driving transistor.

[0120] Figure 18 and Figure 19 It is a plan view of an image sensor according to various embodiments. Figure 18 and Figure 19 Is with Figure 1 A plan view of the corresponding image sensor.

[0121] refer to Figure 18 and Figure 19 The outlines of the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 in the plan view can be various. In some embodiments, the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 can have a quadrilateral outline without a central portion, such as... Figure 18 As shown in the diagram. The first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 may vertically overlap with the first active region ACT1 of the first pixel PX(1) to the fourth pixel PX(4). In some embodiments, the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 may have annular contours. In some embodiments, the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 may have a contour in which each of the opposing sidewalls is recessed toward the center, such as... Figure 19 As shown in the diagram. In various embodiments, the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 can have various polygonal profiles.

[0122] Figure 20 This is a cross-sectional view of an image sensor according to some implementation methods.

[0123] refer to Figure 20 The image sensor 102 may include a substrate 1 having a pixel array area APS, an optical black area OB and a pad area PR, a liner 200 on a first surface 1a of the substrate 1, and a base substrate 400 on the liner 200.

[0124] Substrate 200 may include upper substrate 221 and lower substrate 223. Pixel array region APS may include reference... Figures 1 to 6 The pixel PX is described.

[0125] A first connection structure 50, a first conductive pad 81, and a volume color filter 90 can be provided on a substrate 1 in the optical black area OB. The first connection structure 50 may include a first light-shielding pattern 51, an insulating pattern 53, and a first cover pattern 55. The first light-shielding pattern 51 may be formed of a conductive material. The first light-shielding pattern 51 may include, for example, titanium or tungsten.

[0126] The first light-shielding pattern 51 can be provided on the second surface 1b of the substrate 1. The first light-shielding pattern 51 can conformally cover the inner walls of the fourth trench TR4 and the third trench TR3. The first light-shielding pattern 51 can penetrate the photoelectric conversion layer 150 and the upper substrate 221 and connect the photoelectric conversion layer 150 and the substrate 200.

[0127] The first optical shielding pattern 51 can be combined with Figure 2The isolation structure 10 has an isolation conductive pattern contact. The first conductive pad 81 can be electrically connected to the isolation conductive pattern of the isolation structure 10. The first light shielding pattern 51 can block light incident on the optical black area OB.

[0128] The first conductive pad 81 can be provided inside the third trench TR3 and fill the remaining portion of the third trench TR3. The first conductive pad 81 can include a metallic material, such as aluminum. A negative bias voltage can be applied to the isolation conductive pattern through the first conductive pad 81. Therefore, white spots or dark current can be prevented / reduced.

[0129] The insulating pattern 53 may fill the remaining portion of the fourth trench TR4. The insulating pattern 53 may penetrate all or part of the photoelectric conversion layer 150 and the substrate 200. A first cover pattern 55 may be provided on the upper surface of the insulating pattern 53. The first cover pattern 55 may be provided on the insulating pattern 53.

[0130] A volume color filter 90 may be provided on a first conductive pad 81, a first light-shielding pattern 51, and a first cover pattern 55. The volume color filter 90 may cover the first conductive pad 81, the first light-shielding pattern 51, and the first cover pattern 55. A first protective film 71 may be provided on the volume color filter 90 and encapsulate the volume color filter 90.

[0131] Multiple pixels PX can also be disposed in the optical black area OB, and a first reference photoelectric conversion unit PD' and a second reference region 111 can be disposed in the pixel PX. The first reference photoelectric conversion unit PD' provides a first reference charge amount that can be generated in a state where light is blocked. The first reference charge amount can be a relative reference value when calculating the charge amount generated from the pixel PX. The second reference region 111 provides a second reference charge amount that can be generated in a state where the photoelectric conversion unit PD is not provided. The second reference charge amount can be used as information for removing process noise.

[0132] A second connection structure 60, a second conductive pad 83, and a second protective film 73 may be provided on the substrate 1 in the pad area PR. The second connection structure 60 may include a second light-shielding pattern 61, an insulating pattern 63, and a second cover pattern 65.

[0133] The second light-shielding pattern 61 can be provided on the second surface 1b of the substrate 1. The second light-shielding pattern 61 can conformally cover the inner walls of the sixth trench TR6 and the fifth trench TR5. The second light-shielding pattern 61 can penetrate the photoelectric conversion layer 150 and the upper substrate 221 and connect the photoelectric conversion layer 150 and the substrate 200. The second light-shielding pattern 61 can contact the lines in the lower substrate 223. The second light-shielding pattern 61 can be electrically connected to the lines in the substrate 200. The second light-shielding pattern 61 can include a metallic material, such as titanium or tungsten.

[0134] A second conductive pad 83 may be provided inside the fifth trench TR5 and fill the remaining portion of the fifth trench TR5. The second conductive pad 83 may include a metallic material, such as aluminum. The second conductive pad 83 may serve as an electrical connection path to the outside of the image sensor device. An insulating pattern 63 may fill the remaining portion of the sixth trench TR6. The insulating pattern 63 may penetrate all or part of the photoelectric conversion layer 150 and the substrate 200. A second cover pattern 65 may be provided on the insulating pattern 63. A second protective film 73 may cover a portion of the second light-shielding pattern 61 and the second cover pattern 65.

[0135] refer to Figures 1 to 6 The structure of the image sensor described can also be applied to sensors with similar characteristics to the one described below. Figure 21 A 3-chip image sensor.

[0136] Figure 21 This is a cross-sectional view of an image sensor according to some implementation methods.

[0137] refer to Figure 21 The image sensor 103a may have a structure in which a first sub-chip CH1, a second sub-chip CH2, and a third sub-chip CH3 are sequentially stacked. The first sub-chip CH1 includes a first substrate SB1 and a first interlayer insulating layer IL1 covering the front side of the first substrate SB1. The first substrate SB1 may be a semiconductor substrate or an insulating substrate. The first interlayer insulating layer IL1 may have a single-layer or multi-layer structure of at least one of SiO2, SiN, SiCN, SiON, or SiOCH. Logic circuitry may be arranged in the first sub-chip CH1. The logic circuitry may include a row driver, a row decoder, a column decoder, a timing generator, a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. A first peripheral transistor PTR1, a first contact plug CT1, and a first line IT1 may be arranged on the first substrate SB1 to form the logic circuitry. A first device isolation portion ST1 may be provided on the first substrate SB1 to define an active region for the first peripheral transistor PTR1. A first conductive pad CP1 may be arranged at the upper end of the first interlayer insulating layer IL1.

[0138] The second sub-chip CH2 is bonded to the first sub-chip CH1. The second sub-chip CH2 may include a second substrate SB2. The front side SB2_F of the second substrate SB2 may be covered with a second interlayer insulating layer IL2. The front side SB2_F of the second substrate SB2 may face the first sub-chip CH1. Figure 4The driving transistors RX, DCX1, DCX2, SX, and SE shown can be arranged on the front side SB2_F of the second substrate SB2 in the main region of the second sub-chip CH2. Each of the gate electrodes RG, DCG1, DCG2, SF1, SF2, and SEL can have a planar or vertical shape. The driving transistors RX, DCX1, DCX2, S1, S2, and SE can have a FinFET, a multi-bridge FET (MBCFET), or a gate all-around FET (GAAFET) structure.

[0139] The second peripheral transistor PTR2 can be disposed on the front side SB2_F of the second substrate SB2 in the peripheral region of the second sub-chip CH2. The second device isolation portion ST2 can be disposed on the front side SB2_F of the second substrate SB2 to define the active region for driving transistors RX, DCX1, DCX2, SX, and SE, as well as the second peripheral transistor PTR2. The second contact plug CT2 and the second line IT2 can be disposed in the second interlayer insulating layer IL2. The second conductive pad CP2 can be disposed at the lower end of the second interlayer insulating layer IL2. The lower surface of the second interlayer insulating layer IL2 can contact the upper surface of the first interlayer insulating layer IL1. The second conductive pad CP2 can contact the first conductive pad CP1 respectively. There may be no boundary surface between the second conductive pad CP2 and the first conductive pad CP1 that contacts the second conductive pad CP2, and the corresponding first conductive pad CP1 and second conductive pad CP2 can be integral.

[0140] The rear side SB2_B of the second substrate SB2 can be sequentially covered by the first rear insulating film BL1 and the second rear insulating film BL2. The fourth line IT4 can be disposed within the second rear insulating film BL2. The third conductive pad CP3 can be disposed at the upper end of the second rear insulating film BL2. The through-path TV can penetrate the first rear insulating film BL1, the second substrate SB2, the second device isolation portion ST2, and a portion of the second interlayer insulating layer IL2. The through-path TV can gradually taper downwards. The through-path insulating film TL can be inserted between the through-path TV and the second substrate SB2.

[0141] The third sub-chip CH3 is bonded to the second sub-chip CH2. The third sub-chip CH3 includes a third substrate SB3. The third substrate SB3 may include a pixel array region APS and an edge region ER. The pixel array region APS may include a plurality of pixels PX. An isolation structure 10 may be disposed in the third substrate SB3 and may isolate the pixels PX from each other. A photoelectric conversion unit PD is disposed in the third substrate SB3 in each of the pixels PX. The front side SB3_F of the third substrate SB3 may face the second sub-chip CH2. A third device isolation unit ST3 may be disposed on the front side SB3_F of the third substrate SB3 to define the active region for transmitting transistors T1 to T8. Figure 4 ).

[0142] The transfer gate electrode TG and the floating diffusion region FD can be arranged on the front side SB3_F of the third substrate SB3. The front side SB3_F of the third substrate SB3 can be covered by a third interlayer insulating layer IL3. The third contact plug CT3, the third line IT3, etc., can be arranged in the third interlayer insulating layer IL3. The floating diffusion region FD of the third sub-chip CH3 can be connected to the source follower gate electrode SF of the source follower transistor SX of the second sub-chip CH2. The gate electrode GE of the third sub-chip CH3 can be replaced by the gate electrode of the transistor of the second sub-chip CH2.

[0143] The lower surface of the third interlayer insulating layer IL3 can contact the upper surface of the second rear insulating film BL2 of the second sub-chip CH2. A fourth conductive pad CP4 can be disposed at the lower end of the third interlayer insulating layer IL3. The fourth conductive pad CP4 can contact the third conductive pad CP3. There may be no boundary surface between the fourth conductive pad CP4 and the third conductive pad CP3 that contacts the fourth conductive pad CP4, and the corresponding third conductive pad CP3 and fourth conductive pad CP4 may be integral.

[0144] The rear side SB3_B of the third substrate SB3 may be covered with a third back insulating film FL. The third back insulating film FL may include at least one of a fixed charge film, an anti-reflection film, a planarization film, or a protective film. The grid pattern WG, color filters CF1 and CF2, and microlens ML may be arranged on the third back insulating film FL in the pixel array region APS. The first optical black pattern BT, the second optical black pattern CFB, the lens residue layer MLR, etc., may be sequentially arranged on the third back insulating film FL in the edge region ER. The first optical black pattern BT may have the same material and the same thickness as the grid pattern WG. The second optical black pattern CFB may include a blue color filter. The lens residue layer MLR may have the same material as the microlens ML. Other structures may be the same as / similar to the structures described above.

[0145] The positions of conductive pads CP1 to CP4 and through-path TV can be varied and are not limited to these. Figure 21 Those. The arrangement of the transmission transistors T1 to T8 and the drive transistors RX, DCX1, DCX2, S1, S2 and SE can be various, and is not limited to. Figure 21 Those. Figure 4 The pre-charge transistor, sampling transistor, capacitor, etc., not shown, can be disposed in at least one of the first sub-chip CH1 or the second sub-chip CH2.

[0146] According to various embodiments, the floating diffusion region and the source follower gate electrode can be electrically connected to each other via buried lines. The buried lines can be disposed in the upper portion of the substrate and extend along the isolation structure. Source follower contacts can be disposed on the source follower gate electrode, and the source follower contacts can be electrically connected to the floating diffusion region via the buried lines. Therefore, contacts directly connected to the floating diffusion region can be omitted, thus preventing / reducing junction leakage between the floating diffusion region and the contacts. Furthermore, since the lines are buried in the substrate, the design flexibility of the line arrangement is increased.

[0147] In some implementations, a grounding region can be formed on the buried line. Therefore, the gate electrode of an existing dummy transistor in the pixel region can be used as the gate electrode of the driving transistor. As a result, the electrical characteristics of the image sensor can be improved.

[0148] Although various embodiments have been described with reference to the accompanying drawings, those skilled in the art will readily understand that various additional embodiments consistent with this disclosure can be performed in other specific forms without altering the technical concept or essential characteristics. Therefore, the above embodiments should be considered illustrative and not construed as restrictive. Figures 1 to 10B The implementation methods can be combined with each other. All such modifications, variations, and combinations are intended to be included within the scope of the appended claims.

[0149] This patent application claims priority to Korean Patent Application No. 10-2024-0075721, filed on June 11, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. An image sensor, comprising: substrate; The pixel region is defined in the substrate by an isolation structure; A first floating diffusion region is located on the pixel region; The source follower gate electrode is located on the substrate; as well as The first burial line is located on the isolation structure. The first buried line electrically connects the first floating diffusion region to the source follower gate electrode. The first buried line is disposed in the substrate, and The first burial line includes: The first line portion extends from the first floating diffusion region in a first direction, and The second line portion extends from the source follower gate electrode in a second direction that intersects with the first direction.

2. The image sensor according to claim 1, further comprising a second floating diffusion region spaced apart from the first floating diffusion region. The first burial line electrically connects the first floating diffusion region to the second floating diffusion region.

3. The image sensor of claim 1, wherein the level of the upper surface of the first buried line is lower than the level of the upper surface of the source follower gate electrode.

4. The image sensor of claim 1, wherein the first buried line comprises the same material as the material of the first floating diffusion region.

5. The image sensor according to claim 1, wherein the image sensor comprises a plurality of said pixel regions, The plurality of pixel regions share the first floating diffusion region.

6. The image sensor of claim 1, further comprising a first source follower contact on the source follower gate electrode, The first source follower contact is in contact with each of the source follower gate electrode and the first buried line.

7. The image sensor of claim 6, wherein the first floating diffusion region is electrically connected to the first source follower contact via the first buried line.

8. The image sensor of claim 6, wherein the first source follower contact comprises a first contact portion and a second contact portion on the first contact portion. The first contact portion is in direct contact with the first burial line. The second contact portion is in direct contact with the gate electrode of the source follower, and The maximum width of the first contact portion is less than the minimum width of the second contact portion.

9. The image sensor of claim 8, wherein the first contact portion includes a first sidewall adjacent to the source follower gate electrode. The second contact portion includes a second sidewall adjacent to the source follower gate electrode. The first sidewall is offset from the second sidewall in the second direction, and The first sidewall is spaced apart from the source follower gate electrode in the second direction.

10. The image sensor of claim 1, further comprising a first contact area on the first buried line, The first ground region is doped with impurities of a different conductivity type than the impurities in the first floating diffusion region.

11. An image sensor, comprising: substrate; The pixel region is defined in the substrate by an isolation structure; A first floating diffusion region is located on the pixel region; The source follower gate electrode is located on the substrate; The first burial line is located on the isolation structure; as well as The first source follower contact is on the gate electrode of the source follower. The first buried line electrically connects the first floating diffusion region to the source follower gate electrode, and The first source follower contact is in contact with each of the source follower gate electrode and the first buried line.

12. The image sensor of claim 11, wherein the first floating diffusion region is electrically connected to the first source follower contact via the first buried line.

13. The image sensor of claim 11, wherein the first source follower contact comprises a first contact portion and a second contact portion on the first contact portion. The first contact portion is in direct contact with the first burial line. The second contact portion is in direct contact with the gate electrode of the source follower, and The maximum width of the first contact portion is less than the minimum width of the second contact portion.

14. The image sensor of claim 13, wherein the first contact portion includes a first sidewall adjacent to the source follower gate electrode. The second contact portion includes a second sidewall adjacent to the source follower gate electrode. The first sidewall is offset from the second sidewall in a direction parallel to the upper surface of the substrate, and The first sidewall is spaced apart from the source follower gate electrode.

15. The image sensor of claim 14, wherein the second contact portion further comprises a connecting outer wall, the connecting outer wall connecting the first sidewall and the second sidewall. The connecting outer wall extends in a first direction extending from the upper surface of the substrate, and At least a portion of the connecting outer wall is in contact with the source follower gate electrode.

16. A method for manufacturing an image sensor, the method comprising: A pixel region defined by an isolation structure is formed on the substrate; A first floating diffusion region and a first buried line are formed in the substrate; A source follower gate electrode is formed on the pixel region, and the first buried line electrically connects the first floating diffusion region to the source follower gate electrode; as well as A first source follower contact is formed on the gate electrode of the source follower. The formation of the first floating diffusion zone and the first burial line includes: The first etched portion is formed by etching the upper portion of the substrate and the upper portion of the isolation structure, and The first etched portion is filled with semiconductor material.

17. The method of claim 16, wherein forming the first source follower contact comprises: A first interlayer insulating layer is formed covering the source follower gate electrode and the first buried line; as well as A first contact hole is formed in the first interlayer insulating layer by performing a patterning process. The first contact hole exposes at least a portion of the source follower gate electrode and at least a portion of the first buried line.

18. The method of claim 17, wherein the level of the exposed upper surface of the source follower gate electrode is higher than the level of the bottom surface of the first contact hole.

19. The method of claim 16, wherein the first etched portion includes a first recess exposing the substrate and a second recess exposing the isolation structure. The second depression includes: The first portion extends from the first recess in a first direction; as well as The second part extends from the first part in a second direction that intersects the first direction.

20. The method of claim 16, further comprising forming a second floating diffusion region spaced apart from the first floating diffusion region. The first burial line electrically connects the first floating diffusion region to the second floating diffusion region.

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