Solar cell and RCA cleaning method

Abstract

The invention discloses a solar cell and an RCA cleaning method, and belongs to the technical field of solar cells. According to the invention, the doped polycrystalline silicon layer in the non-grid line region and the doped ions in the bottom substrate can be completely removed, so that parasitic absorption can be greatly reduced, the battery efficiency can be improved, and meanwhile, the condition of short circuit caused by contact between the grid line region and the non-grid line region is effectively avoided; meanwhile, on one hand, a large-size side tower base can be obtained, so that the insulativity of the front face and the back face of the substrate can be improved, electric leakage caused by edge PN junction residues can be effectively reduced, on the other hand, a large-size tower base can be obtained in a non-grid line area, the passivation effect can be improved, and the light absorption capacity can be improved. The photoelectric conversion efficiency is further improved; the tower footing with a small grid line area improves ohmic contact, so that the solar cell has good photoelectric conversion efficiency.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a solar cell and an RCA cleaning method. Background Technology

[0002] The core of TOPCon (Tunnel Oxide Passivating Contact) battery's back-side polyfin technology lies in the presence of a doped polysilicon layer only in the grid line region, while the non-grid line region remains undoped. This design significantly reduces parasitic absorption and carrier recombination in the grid line region, thereby improving battery efficiency. Traditional polyfin battery fabrication methods primarily involve forming a locally doped polysilicon layer to create a height difference between the grid line and non-grid line regions. Furthermore, to further improve conversion efficiency, steps involving forming different tower morphologies in different regions are also included. For example, patent CN116779694A discloses a method for fabricating a Topcon battery with a linear poly structure on the back side, using etching and localized coating to create the height difference, and employing wet chemical cleaning to form towers of different sizes in the grid line and non-grid line regions. Additionally, to improve leakage current, towers are also formed on the side of the substrate. For example, patent CN117334592A discloses a method for detecting edge leakage in Topcon batteries. This method uses a wet chemical cleaning process to form a tower base on the side of the substrate, and the larger the tower base size, the better the improvement effect. In the prior art, the steps of forming the height difference and forming the tower base are usually performed separately, which is a cumbersome process. Moreover, different regions have different requirements for the size of the tower base, making it difficult to ensure that the requirements for the tower base morphology are met simultaneously. Summary of the Invention

[0003] The purpose of this application is to provide a solar cell and an RCA cleaning method that can simultaneously achieve a height difference between the substrate in the back grid line region and the substrate in the non-grid line region, and form different tower base morphologies in the non-grid line region, the side surface and the grid line region of the substrate.

[0004] To achieve the above objectives, this application provides a solar cell, comprising: a substrate; the back side of the substrate includes a grid line region and a non-grid line region;

[0005] The gate line region is provided with a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer sequentially along the thickness direction of the substrate; the non-gate line region is not provided with a tunneling layer and a doped polysilicon layer; the substrate height in the non-gate line region is lower than the substrate height in the gate line region, thus forming a height difference H;

[0006] Tower bases are formed in the gate line region, non-gate line region, and side surface of the substrate; the width of the tower base in the non-gate line region of the substrate is greater than the width of the tower base on the side surface of the substrate, and the width of the tower base on the side surface of the substrate is greater than the width of the tower base in the gate line region of the substrate.

[0007] Optionally, the difference between the width of the non-gateline region tower base of the substrate and the width of the side tower base of the substrate is 3μm-20μm.

[0008] Optionally, the difference between the width of the side base of the substrate and the width of the gate area base of the substrate is 2μm-20μm.

[0009] Optionally, the width of the side base of the substrate is 12μm-25μm, including the values ​​at both ends.

[0010] Optionally, the width of the non-gateline region of the substrate is 15μm-30μm, including the values ​​at both ends;

[0011] And / or, the width of the gate line region base of the substrate is 8μm-10μm, including the values ​​at both ends.

[0012] Optionally, the height difference H between the gate line region and the non-gate line region is 0.5μm-6μm, including the values ​​at both ends.

[0013] To achieve the above objectives, this application also provides an RCA cleaning method for use in the aforementioned solar cell fabrication process, comprising:

[0014] S1: The substrate to be cleaned is placed in HF and subjected to the first acid wash to obtain a first substrate with the oxide layers on the front and side surfaces of the substrate to be cleaned removed.

[0015] S2: The first substrate is placed in a first mixed solution for cleaning. The first mixed solution includes 2%-4% NaOH and 1%-1.5% additives. The temperature of the first mixed solution is 65℃-70℃ and the cleaning time is 250s-500s, so that a height difference H is formed between the substrate in the non-gate area on the back side of the first substrate and the substrate in the gate area, and a tower base is formed on the side of the first substrate to obtain the second substrate, which is then rinsed with deionized water.

[0016] S3: The second substrate is placed in a second mixture for cleaning, the second mixture including alkaline solution and hydrogen peroxide, to obtain a third substrate, which is then rinsed with deionized water;

[0017] S4: The third substrate is placed in an acid bath for a second acid wash to remove the remaining oxide layer, and the alkaline solution is neutralized to obtain the fourth substrate, which is then rinsed with deionized water.

[0018] S5: The fourth substrate is placed in a third mixed solution for cleaning, the third mixed solution including alkaline solution and hydrogen peroxide, to obtain a fifth substrate, which is then rinsed with deionized water;

[0019] S6: The fifth substrate is placed in an acid bath for a third acid wash to obtain the sixth substrate, which is then rinsed with deionized water.

[0020] S7: Rinse the sixth substrate to obtain the seventh substrate;

[0021] S8: Dry the seventh substrate and set it aside for later use.

[0022] Optionally, in step S3, the alkaline solution in the second mixture is NaOH with a concentration of 1%-1.5%, including both values; the concentration of hydrogen peroxide in the second mixture is 2%-4%, including both values; the temperature of the second mixture is 60℃-65℃, including both values; and the cleaning time of the second mixture is 90s-120s, including both values.

[0023] And / or, in step S5, the alkali solution in the third mixture is NaOH with a concentration of 1%-1.5%, including both ends of the value; the concentration of hydrogen peroxide in the third mixture is 2%-4%, including both ends of the value; the temperature of the third mixture is 60℃-65℃, including both ends of the value; and the cleaning time of the third mixture is 90s-120s, including both ends of the value.

[0024] Optionally, in step S4, the second pickling uses HF, the concentration of which is 10%-15%, including both values; the temperature of which is room temperature; and the cleaning time of which is 100s-130s, including both values.

[0025] And / or, in step S6, the third pickling uses HF, the concentration of which is 10%-15%, including both values; the temperature of which is room temperature; and the cleaning time of which is 100s-130s, including both values.

[0026] Optionally, the sixth substrate may be rinsed using a slow lifting method;

[0027] And / or, in step S8, the seventh substrate is dried using CDA with high temperature and hot air in the drying tank; the high temperature is 90℃-100℃, including the values ​​at both ends.

[0028] Obviously, the solar cell provided in this application has a lower substrate height in the non-grid region than in the grid region, creating a height difference. This ensures complete removal of doped polycrystalline silicon layers and doped ions from the underlying substrate in the non-grid region, significantly reducing parasitic absorption and improving cell efficiency. It also effectively prevents short circuits caused by contact between the grid and non-grid regions. Furthermore, the width of the substrate base in the non-grid region is greater than the width of the side bases, and vice versa. This results in larger side bases, improving insulation on both the front and back sides of the substrate and effectively reducing leakage caused by residual edge PN junctions. The larger bases in the non-grid region also improve passivation and light absorption, thus increasing photoelectric conversion efficiency. The smaller bases in the grid region improve ohmic contact, resulting in better photoelectric conversion efficiency. This application also provides an RCA cleaning method with the aforementioned advantages. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application;

[0031] Figure 2 A height difference test diagram of the back grid line area and the non-grid line area provided in an embodiment of this application;

[0032] Figure 3 A schematic diagram of the boundary region between the back-side gate line region and the non-gate line region provided in this application embodiment;

[0033] Figure 4 A schematic diagram of the height difference structure between the back-side gate line region and the non-gate line region provided in an embodiment of this application;

[0034] Figure 5 and Figure 6 A schematic diagram of the side profile of a tower base provided in an embodiment of this application;

[0035] Figure 7 A schematic diagram of the topography of the tower base in the non-grid area on the back side provided in this application embodiment;

[0036] Figure 8A schematic diagram of the tower base morphology in the back grid area provided in an embodiment of this application;

[0037] Figure 9 and Figure 10 This is a schematic diagram of the side tower base morphology of a traditional Polyfin battery.

[0038] The annotations in the attached figures are explained as follows:

[0039] 11-Substrate; 12-Emitter; 13-Front-side passivation layer; 14-Antireflection layer; 15-Front-side gate line; 161-First tunneling layer; 171-First doped polysilicon layer; 162-Second tunneling layer; 171-Second doped polysilicon layer; 18-Back-side passivation layer; 19-Internal reflection layer; 20-Back-side gate line. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] Please refer to Figure 1 , Figure 1 This application provides a schematic diagram of the structure of a solar cell, which may include: a substrate 11; the back side of the substrate 11 includes a grid line region and a non-grid line region;

[0042] The gate line region is provided with a first tunneling layer 161, a first doped polysilicon layer 171, a second tunneling layer 162 and a second doped polysilicon layer 172 in sequence along the thickness direction of the substrate 11; the non-gate line region is not provided with a tunneling layer and a doped polysilicon layer; the height of the substrate 11 in the non-gate line region is lower than the height of the substrate 11 in the gate line region, so that a height difference H is formed.

[0043] Tower bases are formed in the gate line region, non-gate line region, and side surface of substrate 11; the width of the tower base in the non-gate line region of substrate 11 is greater than the width of the tower base on the side surface of substrate 11; the width of the tower base on the side surface of substrate 11 is greater than the width of the tower base in the gate line region of substrate 11.

[0044] It should be noted that, in this embodiment, the thickness direction of the substrate 11 refers to the direction perpendicular to the surface of the substrate 11, i.e. Figure 1 The X direction in the equation.

[0045] In this embodiment, the height difference H between the gate line region and the non-gate line region can be 0.5μm-6μm, including the values ​​at both ends. Preferably, in this embodiment, the height difference H between the gate line region and the non-gate line region can be 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm…5.8μm, 5.9μm or 6μm.

[0046] In this embodiment, the difference between the width of the non-gateline region base of the substrate 11 and the width of the side base of the substrate 11 can be 3μm-20μm. Preferably, in this embodiment, the difference between the width of the non-gateline region base of the substrate 11 and the width of the side base of the substrate 11 can be 3μm, 4μm, 5μm, 6μm, 7μm...18μm, 19μm or 20μm.

[0047] In this embodiment, the difference between the width of the side base of the substrate 11 and the width of the gate line area base of the substrate 11 can be 2μm-20μm. Preferably, in this embodiment, the difference between the width of the side base of the substrate 11 and the width of the gate line area base of the substrate 11 can be 2μm, 3μm, 4μm, 5μm, 6μm, 7μm...18μm, 19μm or 20μm.

[0048] The width of the non-gate region tower base of substrate 11 and the width of the side tower base of substrate 11, as well as the width of the side tower base of substrate 11 and the width of the gate region tower base of substrate 11, all have appropriate differences, which enable the solar cell to have a better passivation effect and a better light absorption capacity, thereby improving the photoelectric conversion efficiency and performance of the solar cell.

[0049] In this embodiment, the width of the side base of the substrate 11 can be 12μm-25μm, including the values ​​at both ends. Preferably, in this embodiment, the width of the side base of the substrate 11 can be 12μm, 13μm, 14μm, 15μm, 16μm, 17μm...23μm, 24μm or 25μm.

[0050] In this embodiment, the width of the non-gateline region base of the substrate 11 can be 15μm-30μm, including the values ​​at both ends. Preferably, the width of the non-gateline region base of the substrate 11 in this embodiment can be 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm…28μm, 29μm or 30μm.

[0051] In this embodiment, the width of the gate line region base of the substrate 11 can be 8μm-10μm, including the values ​​at both ends. Preferably, in this embodiment, the width of the gate line region base of the substrate 11 can be 8μm, 9μm, or 10μm.

[0052] The appropriate tower base dimensions of the grid line region, non-grid line region, and side of the substrate in this application effectively avoid lattice defects and stress in the solar cell, while giving the solar cell good light absorption capability, resulting in good photoelectric conversion efficiency and cell performance.

[0053] Preferably, in this embodiment, the height difference H between the gate line region and the non-gate line region can be 3 μm. In this embodiment, the width of the side base of the substrate 11 can be 20 μm. It should be noted that in this embodiment, when the height difference H between the gate line region and the non-gate line region is 3 μm, the width of the side base of the substrate 11 can reach 20 μm. At the same time, it can also ensure that the non-gate line region obtains a base with a width greater than 20 μm, and the gate line region obtains a base with a width less than 20 μm. This can ensure the complete removal of doped ions from the polysilicon layer in the non-gate line region and the underlying substrate 11, as well as better insulation of the front and back sides of the substrate 11, better passivation effect in the non-gate line region, and better ohmic contact in the gate line region.

[0054] This embodiment does not limit the specific type of substrate 11; substrate 11 can be, but is not limited to, an N-type substrate or a P-type substrate. This embodiment does not limit the specific type of substrate 11; substrate 11 can be, but is not limited to, a silicon substrate. This embodiment does not limit the specific thickness of substrate 11; for example, the thickness of substrate 11 can be 100μm-200μm, including the values ​​at both ends. Preferably, in this embodiment, the thickness of substrate 11 can be 100μm, 101μm, 102μm, 103μm, 104μm…198μm, 199μm, or 200μm.

[0055] This embodiment does not limit the specific types of the first tunneling layer 161 and the second tunneling layer 162. The first tunneling layer 161 and the second tunneling layer 162 may include, but are not limited to, silicon oxide layers. This embodiment does not limit the specific types of the first doped polysilicon layer 171 and the second doped polysilicon layer 172. The specific types of the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be N-type doped polysilicon layers; when the substrate 11 is a P-type substrate, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 can be P-type doped polysilicon layers. The N-type doped polysilicon layer contains N-type impurities, and the P-type doped polysilicon layer contains P-type impurities. Furthermore, in this embodiment, a back passivation layer 18 can be provided on the surface of the second doped polysilicon layer 172 away from the second tunneling layer 162 and in the non-gate area to improve the passivation effect; an inner reflection layer 19 can be provided on the surface of the back passivation layer 18 away from the substrate 11 to reduce light reflection; a back gate line 20 can be provided on the surface of the inner reflection layer 19 away from the back passivation layer 18, and the back gate line 20 sequentially penetrates the inner reflection layer 19, the back passivation layer 18, the second doped polysilicon layer 172 and the second tunneling layer 162 along the thickness direction, and contacts the first doped polysilicon layer 171.

[0056] This embodiment does not limit the specific type of the back passivation layer 18, which may include, but is not limited to, an aluminum oxide layer. This embodiment does not limit the specific type of the inner reflective layer 19, which may include, but is not limited to, a silicon nitride layer. This embodiment does not limit the specific type of the back gate line 20, which may be, but is not limited to, a metal gate line.

[0057] Furthermore, in this embodiment, an emitter 12 may be disposed on the front side of the substrate 11; a front passivation layer 13 may be disposed on the surface of the emitter 12 away from the substrate 11 to improve the passivation effect; an anti-reflection layer 14 may be disposed on the surface of the front passivation layer 13 away from the emitter 12 to reduce light reflection; a front gate line 15 may be disposed on the surface of the anti-reflection layer 14 away from the front passivation layer 13, and the front gate line 15 sequentially penetrates the anti-reflection layer 14 and the front passivation layer 13 along the thickness direction and contacts the emitter 12.

[0058] This embodiment does not limit the specific type of emitter 12. The specific type of emitter 12 can be determined according to the specific type of substrate 11. For example, when substrate 11 is an N-type substrate, emitter 12 can be a P-type emitter; when substrate 11 is a P-type substrate, emitter 12 can be an N-type emitter. In this embodiment, the P-type emitter is doped with P-type impurities, and the N-type emitter is doped with N-type impurities.

[0059] This embodiment does not limit the specific type of the front passivation layer 13, which may include, but is not limited to, an aluminum oxide layer. This embodiment does not limit the specific type of the antireflection layer 14, which may include, but is not limited to, a silicon nitride layer. This embodiment does not limit the specific type of the front gate line 15, which may be, but is not limited to, a metal gate line.

[0060] Furthermore, in order to improve the light trapping effect of the front side of the substrate 11, the front side of the substrate 11 in this embodiment may have a pyramidal textured surface.

[0061] Based on the above embodiments, in this application, the substrate height in the non-gate region is lower than that in the gate region, creating a height difference. This ensures the complete removal of doped ions from the polysilicon layer in the non-gate region and the underlying substrate, thereby significantly reducing parasitic absorption and improving battery efficiency. Simultaneously, it effectively avoids short circuits caused by contact between the gate and non-gate regions. Furthermore, the width of the substrate base in the non-gate region is greater than the width of the side base, and vice versa. This results in larger side bases, improving insulation on both the front and back sides of the substrate and effectively reducing leakage caused by residual edge PN junctions. Additionally, the larger base in the non-gate region enhances passivation and light absorption, thus improving photoelectric conversion efficiency. The smaller base in the gate region improves ohmic contact, resulting in better photoelectric conversion efficiency.

[0062] This application also provides an RCA cleaning method, which can be used in the above-described solar cell fabrication process, including:

[0063] S1: Place the substrate to be cleaned in HF and perform the first acid wash to obtain the first substrate with the oxide layers on the front and side surfaces of the substrate to be cleaned removed.

[0064] It should be noted that in this embodiment, step S1 is performed in an acid pickling tank, and the purpose of this step is to prepare for subsequent polishing.

[0065] In this embodiment, the substrate to be cleaned includes at least the following: a first tunneling layer 161, a first doped polysilicon layer 171, a second tunneling layer 162, a second doped polysilicon layer 172, and a first impurity oxide layer are sequentially disposed along the thickness direction on the front, back, and side surfaces of the substrate to be cleaned.

[0066] It should be noted that, in this embodiment, a substrate to be cleaned needs to be provided before step S1. This embodiment does not limit the specific method of providing the substrate to be cleaned; the specific method can be determined according to the specific structure of the solar cell required. For example, the following methods can be used:

[0067] An emitter 12 and a second impurity oxide layer are formed sequentially along the thickness direction on the front side of the substrate 11, and the second impurity layer is deposited around the side of the substrate 11.

[0068] After the front side of the substrate 11 is processed, a first tunneling layer 161, a first doped polysilicon layer 171, a second tunneling layer 162, a second doped polysilicon layer 172, and a first impurity oxide layer are formed on the back side of the substrate 11 in sequence along the thickness direction. The first tunneling layer 161, the first doped polysilicon layer 171, the second tunneling layer 162, the second doped polysilicon layer 172, and the first impurity oxide layer are all deposited around the side and front side of the substrate 11 to obtain the substrate to be cleaned.

[0069] Accordingly, in this embodiment, the oxide layers on the front and side of the substrate to be cleaned removed in step 1 specifically include: a first impurity oxide layer plated around the front of the substrate to be cleaned, and a first impurity oxide layer and a second impurity oxide layer plated around the side of the substrate to be cleaned.

[0070] Accordingly, the remaining oxide layer removed in step 4 of this embodiment specifically includes: a first impurity oxide layer in the gate line region on the back side of the third substrate, and a second impurity oxide layer on the front side of the third substrate.

[0071] Furthermore, in order to improve the light trapping effect on the front side of the substrate 11, this embodiment forms an emitter 12 and a second impurity oxide layer arranged sequentially along the thickness direction on the front side of the substrate 11, and the second impurity layer is deposited around the side of the substrate 11. It may also include forming a pyramid textured surface on the front side of the substrate 11.

[0072] It should be noted that in this embodiment, the emitter 12 is generally formed on the front side of the substrate 11 by impurity diffusion. During the impurity diffusion process, a second impurity oxide layer is formed on the surface of the emitter 12 away from the substrate 11. This embodiment does not limit the specific type of the second impurity oxide layer. The specific type of the second impurity oxide layer can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the second impurity oxide layer can be a P-type oxide layer; when the substrate 11 is a P-type substrate, the second impurity oxide layer can be an N-type oxide layer. The P-type oxide layer may include, but is not limited to, a BSG (Borosilicate Glass) layer; the N-type oxide layer may include, but is not limited to, a PSG (Phosphorosilicate Glass) layer.

[0073] It should be noted that in this embodiment, the first doped polysilicon layer 171 and the second doped polysilicon layer 172 are generally formed by impurity diffusion. During the impurity diffusion process, a first impurity oxide layer is formed on the surface of the second doped polysilicon layer 172 away from the second tunneling layer 162. This embodiment does not limit the specific type of the first impurity oxide layer. The specific type of the first impurity oxide layer can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the first impurity oxide layer can be an N-type oxide layer; when the substrate 11 is a P-type substrate, the first impurity oxide layer can be a P-type oxide layer.

[0074] It should be noted that in this embodiment, alkaline polishing is performed before step S1. This process forms a base in both the gate line region and the non-gate line region of the substrate 11. Therefore, before RCA cleaning, the gate line region and the non-gate line region of the substrate to be cleaned already have bases of the same or approximately the same width. When the substrate to be cleaned is subsequently subjected to RCA cleaning, the surface of the base in the gate line region is covered with a first tunneling layer 161, a first doped polysilicon layer 171, a second tunneling layer 162, and a second doped polysilicon layer 172, etc., so it is not affected by the corrosion of the RCA cleaning solution, and the width of the base remains unchanged. However, the base in the non-gate line region is more affected by the corrosion of the RCA cleaning solution, and the width of the base will increase. Moreover, this change in the width of the base is formed by the corrosion of the non-gate line region of the substrate during the formation of the side base in the RCA cleaning process.

[0075] S2: The first substrate is placed in a first mixed solution for cleaning. The first mixed solution includes 2%-4% NaOH and 1%-1.5% additives. The temperature of the first mixed solution is 65℃-70℃ and the cleaning time is 250s-500s, so that a height difference H is formed between the substrate in the non-gate line area on the back side of the first substrate and the substrate in the gate line area, and a tower base is formed on the side of the first substrate to obtain the second substrate, which is then rinsed with deionized water.

[0076] It should be noted that, before step S2 in this embodiment, a laser is used to irradiate the non-gateline area on the back side of the first substrate to remove the first impurity oxide layer in the non-gateline area. Laser irradiation removes only the first impurity oxide layer in the non-gateline area, while retaining the first impurity oxide layer in the gateline area. During subsequent cleaning, this first impurity oxide layer in the non-gateline area can protect the surface of the second doped polysilicon layer 172 in the gateline area.

[0077] It should be noted that the purpose of cleaning in the first mixed solution in this embodiment is to remove the second doped polysilicon layer 172, the second tunneling layer 162, the first doped polysilicon layer 171, the first tunneling layer 161 and part of the substrate 11 in the non-gate area, as well as the second doped polysilicon layer 172, the second tunneling layer 162, the first doped polysilicon layer 171 and the first tunneling layer 161 on the front and side of the substrate 11. This can create a height difference H between the substrate 11 in the gate area and the substrate 11 in the non-gate area on the back of the first substrate, and the height of the substrate 11 in the non-gate area is lower than the height of the substrate 11 in the gate area. At the same time, it can increase the width of the tower base in the non-gate area and form a tower base on the side of the substrate 11. The width of the tower base in the non-gate area of ​​the substrate 11 is greater than the width of the tower base on the side of the substrate 11, and the width of the tower base on the side of the substrate 11 is greater than the width of the tower base in the gate area of ​​the substrate. This step can be performed in the polysilicon removal process.

[0078] It should be noted that in this embodiment, the concentration of NaOH can be 2%-4%, including both values; the concentration of the additive can be 1%-1.5%, including both values; the temperature of the first mixture can be 65℃-70℃, including both values; and the cleaning time can be 250s-500s, including both values. This embodiment, by controlling at least two process parameters, can simultaneously achieve a suitable height difference between the substrate 11 in the gate line region and the substrate 11 in the non-gate line region, and control the tower base morphology of the non-gate line region and the sides of the substrate 11, ensuring that the tower base morphology of each region meets the requirements.

[0079] Preferably, in this embodiment, the concentration of NaOH can be 4.2%; the concentration of the additive can be 1.04%; the temperature of the first mixture can be 68°C; the cleaning time can be 400s; correspondingly, the height difference H between the gate line region and the non-gate line region can be 3μm; and the width of the side column base of the substrate 11 can be 20μm. It should be noted that the preferred process parameter formulation in this embodiment, compared to the traditional formulation, increases the concentration of NaOH, decreases the concentration of the additive, increases the temperature, and increases the cleaning time. Through this process parameter formulation, the optimal height difference H between the gate line region and the non-gate line region, as well as the optimal column base dimensions for the gate line region, the non-gate line region, and the side column base of the substrate 11, can be obtained simultaneously.

[0080] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the residual NaOH on the surface of the second substrate; this step is performed in a water washing tank. S3: The second substrate is placed in a second mixed solution for cleaning, the second mixed solution including alkaline solution and hydrogen peroxide, to obtain a third substrate, which is then rinsed with deionized water.

[0081] It should be noted that the purpose of using the second mixture for cleaning in this embodiment is to remove residual dirt on the surface of the second substrate; this step is performed in the post-cleaning tank.

[0082] In this embodiment, the alkaline solution in the second mixture can be NaOH with a concentration of 1%-1.5%, including both values. Preferably, the concentration of NaOH in this embodiment can be 1%, 1.1%, 1.2%, 1.3%, 1.4%, or 1.5%. The concentration of hydrogen peroxide in the second mixture in this embodiment can be 2%-4%, including both values. Preferably, the concentration of hydrogen peroxide in this embodiment can be 2%, 3%, or 4%. The temperature of the second mixture in this embodiment can be 60℃-65℃, including both values. Preferably, the temperature of the second mixture in this embodiment can be 60℃, 61℃, 62℃, 63℃, 64℃, or 65℃. Preferably, the cleaning time of the second mixture in this embodiment can be 90s-120s, including both values.

[0083] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the second mixture remaining on the surface of the third substrate; this step is performed in a water washing tank.

[0084] S4: Place the third substrate in an acid bath for a second acid wash to remove the remaining oxide layer, neutralize the alkaline solution to obtain the fourth substrate, and then rinse with deionized water.

[0085] In this embodiment, the second pickling can use HF, and the concentration of HF can be 10%-15%, including both values. Preferably, the concentration of HF in this embodiment can be 10%, 11%, 12%, 13%, 14%, or 15%. Preferably, the temperature of HF in this embodiment can be room temperature. Preferably, the cleaning time of HF in this embodiment can be 100s-130s, including both values.

[0086] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the acid solution remaining on the surface of the fourth substrate; this step is performed in a water rinsing tank.

[0087] S5: The fourth substrate is placed in the third mixture for cleaning. The third mixture includes alkaline solution and hydrogen peroxide to obtain the fifth substrate, which is then rinsed with deionized water.

[0088] It should be noted that the purpose of using the third mixed solution for cleaning in this embodiment is to rinse away residual dirt on the surface of the fourth substrate; this step is performed in the post-cleaning tank.

[0089] In this embodiment, the alkaline solution in the third mixture can be NaOH with a concentration of 1%-1.5%, including both ends of the concentration range. Preferably, the concentration of NaOH in this embodiment can be 1%, 1.1%, 1.2%, 1.3%, 1.4%, or 1.5%. The concentration of hydrogen peroxide in the third mixture in this embodiment can be 2%-4%, including both ends of the concentration range. Preferably, the concentration of hydrogen peroxide in this embodiment can be 2%, 3%, or 4%. The temperature of the third mixture in this embodiment can be 60℃-65℃, including both ends of the temperature range. Preferably, the temperature of the third mixture in this embodiment can be 60℃, 61℃, 62℃, 63℃, 64℃, or 65℃. Preferably, the cleaning time of the third mixture in this embodiment can be 90s-120s, including both ends of the temperature range.

[0090] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the third mixture remaining on the surface of the fifth substrate; this step is performed in a water washing tank.

[0091] S6: Place the fifth substrate in an acid bath for a third acid wash to obtain the sixth substrate, and then rinse with deionized water.

[0092] Furthermore, in this embodiment, after rinsing with deionized water to remove desorbed impurities and residual hydrogen peroxide on the surface of substrate 11, the process may further include:

[0093] It should be noted that the purpose of the third acid wash in this embodiment is to clean the impurities attached to the surface of the fifth substrate.

[0094] In this embodiment, the third pickling can use HF, and the concentration of HF can be 10%-15%, including both values. Preferably, the concentration of HF in this embodiment can be 10%, 11%, 12%, 13%, 14%, or 15%. Preferably, the temperature of HF in this embodiment can be room temperature. Preferably, the cleaning time of HF in this embodiment can be 100s-130s, including both values.

[0095] It should be noted that the purpose of rinsing with deionized water in this embodiment is to remove the desorbed impurities and the acid solution remaining on the surface of the sixth substrate; this step is performed in a water rinsing tank.

[0096] S7: Rinse the sixth substrate to obtain the seventh substrate.

[0097] It should be noted that the purpose of step S7 in this embodiment is to rinse away the impurities attached to the surface of the sixth substrate.

[0098] Preferably, in this embodiment, the sixth substrate can be rinsed using a slow-pull method; this step is performed in a slow-pull groove.

[0099] S8: Dry the seventh substrate and set it aside for later use.

[0100] It should be noted that in this embodiment, after completing step S8, the subsequent process of battery cell fabrication is carried out.

[0101] Preferably, in this embodiment, CDA (Compressed Dry Air) is used to dry the seventh substrate using high temperature and hot air in the drying tank; the high temperature can be 90℃-100℃, including both ends.

[0102] Furthermore, this embodiment may further include the following after step S8:

[0103] A back passivation layer 18 is formed on the surface of the second doped polysilicon layer 172 away from the second tunneling layer 162 and in the non-gate area to improve the passivation effect.

[0104] An inner reflective layer 19 is formed on the surface of the back passivation layer 18 that is away from the substrate 11 to reduce light reflection;

[0105] A back gate line 20 is formed on the surface of the inner reflective layer 19 away from the back passivation layer 18, and the back gate line 20 sequentially penetrates the inner reflective layer 19, the back passivation layer 18, the second doped polysilicon layer 172 and the second tunneling layer 162 along the thickness direction, and contacts the first doped polysilicon layer 171.

[0106] Furthermore, this embodiment may also include the following after step S8:

[0107] A passivation layer 13 is formed on the surface of the emitter 12 away from the substrate 11 to improve the passivation effect;

[0108] An anti-reflection layer 14 is formed on the surface of the passivation layer 13 facing away from the emitter 12 to reduce light reflection;

[0109] A front gate line 15 is formed on the surface of the antireflection layer 14 away from the front passivation layer 13, and the front gate line 15 passes through the antireflection layer 14 and the front passivation layer 13 sequentially along the thickness direction and contacts the emitter 12.

[0110] Based on the above embodiments, the process parameters used for cleaning the substrate in this application are a mixture of 2%-4% NaOH and 1%-1.5% additives, with a temperature of 65℃-70℃ and a cleaning time of 250s-500s. While cleaning the de-coating, the non-gateline area on the back side is etched. By controlling at least two process parameters, a height difference can be simultaneously achieved between the gateline and non-gateline areas, with the substrate height in the non-gateline area being lower than that in the gateline area. Additionally, the width of the base in the non-gateline area can be increased, and a base can be formed on the side of the substrate. The width of the base in the non-gateline area is greater than the width of the base on the side of the substrate, and the width of the base on the side of the substrate is greater than that in the gateline area. The width simplifies the process flow and can simultaneously achieve: (1) ensuring the complete removal of doped polysilicon layers and doped ions in the bottom substrate in the non-gate region, thereby greatly reducing parasitic absorption and improving battery efficiency, while effectively avoiding short circuits caused by contact between the gate region and the non-gate region; (2) obtaining a larger side tower base, thereby improving the insulation of the front and back sides of the substrate, thereby effectively reducing leakage caused by residual edge PN junctions; obtaining a larger tower base in the non-gate region can not only improve the passivation effect, but also improve the light absorption capacity, thereby improving the photoelectric conversion efficiency; the smaller tower base in the gate region improves the ohmic contact, giving it better photoelectric conversion efficiency.

[0111] Furthermore, the finished solar cells provided in this embodiment were compared and verified with different height differences. The batch printing data (i.e., the efficiency data of the finished solar cells) obtained are shown in Table 1. The electrical performance parameters of the cells obtained include: conversion efficiency (represented by Eta), open circuit voltage (represented by Voc), short circuit current (represented by Isc), fill factor (represented by FF), series resistance (represented by Rs), parallel resistance (represented by Rsh), and reverse current at -10V (represented by Irev10). The height difference test diagram of the back grid area and the non-grid area is shown in Table 1. Figure 2 As shown; the structure of the boundary area between the back grid line area and the non-grid line area is as follows. Figure 3 As shown; the height difference structure between the back grid line area and the non-grid line area is as follows. Figure 4 As shown.

[0112] Table 1 Batch Printing Data

[0113]

[0114] As can be seen from Table 1, the effect is optimal when the height difference H between the grid line region and the non-grid line region is 3 μm.

[0115] Under the process parameters that create a 3μm height difference: 4.2% NaOH and 1.04% additive, 68℃ temperature and 400s cleaning time (compared to the original formulation, the NaOH concentration was increased, the additive concentration was decreased, the temperature was increased, and the cleaning time was increased), the width of the resulting side column base is 20μm, and the morphology of the side column base is as follows. Figure 5 and Figure 6 As shown, from Figure 5 and Figure 6 This shows that the edge etching is more complete, and the front and back sides of the substrate are more insulating. Furthermore, as... Figure 7 and Figure 8 As shown, both the non-gateline region and the gateline region on the back side will form a tower base, and the size of the tower base in the non-gateline region is greater than the size of the tower base on the side of the substrate 11, which is greater than the size of the tower base in the gateline region.

[0116] Figure 9 and Figure 10 The side column morphology of a conventional Polyfin battery was obtained under the original formulation conditions (i.e., the formulation before changes to the concentration of NaOH, the concentration of additives, the temperature, and the cleaning time): 3.7% NaOH and 1.3% additives, a temperature of 65°C, and a cleaning time of 290s. The width of the column was approximately 10μm.

[0117] The base size of this embodiment is larger than that of a traditional Polyfin battery, which can further improve the insulation of the front and back sides and more effectively reduce leakage caused by residual edge PN junctions.

[0118] In addition, dark current verification was performed on the finished solar cells provided in this embodiment: both experimental groups were finished solar cells provided in this embodiment, and the difference between the two experimental groups was the process time; the control group was a conventional Polyfin cell obtained under the conventional formula of the production line, and the batch printing data (i.e. the efficiency data of the finished solar cells) obtained are shown in Table 2.

[0119] Table 2 Batch Printing Data

[0120]

[0121] As can be seen from Table 2, the Irev10 of both experimental groups was reduced compared to the control group: from 0.1A-0.2A to 0.04A. Obviously, this embodiment has a better effect on improving leakage current than the traditional Polyfin battery.

[0122] This document uses specific examples to illustrate the principles and implementation methods of this application. The various embodiments are progressive, with each embodiment focusing on its differences from others. Similar or identical parts between embodiments can be referred to interchangeably. The descriptions of the embodiments above are merely illustrative of the method and core ideas of this application. For those skilled in the art, various improvements and modifications can be made to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0123] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A solar cell, characterized by, The application relates to a substrate, which comprises: a substrate; a gate line area and a non-gate line area on the back of the substrate; a first tunnel layer, a first doped polysilicon layer, a second tunnel layer and a second doped polysilicon layer arranged in sequence along the thickness direction of the substrate in the gate line area; no tunnel layer and doped polysilicon layer are arranged in the non-gate line area; the height of the substrate in the non-gate line area is lower than the height of the substrate in the gate line area, so that a height difference H is formed; a tower base is formed on the gate line area, the non-gate line area and the side surface of the substrate; the width of the tower base in the non-gate line area of the substrate is greater than the width of the tower base on the side surface of the substrate, and the width of the tower base on the side surface of the substrate is greater than the width of the tower base in the gate line area of the substrate. The difference between the width of the tower base in the non-gate line area of the substrate and the width of the tower base on the side surface of the substrate is 3-20 mu m. The difference between the width of the tower base on the side surface of the substrate and the width of the tower base in the gate line area of the substrate is 2-20 mu m. The width of the tower base on the side surface of the substrate is 12-25 mu m, including the values at both ends.

2. The solar cell according to claim 1, characterized in that, The width of the tower base in the non-gate line area of the substrate is 15-30 mu m, including the values at both ends.

3. The solar cell according to claim 1, characterized in that, The width of the tower base in the gate line area of the substrate is 8-10 mu m, including the values at both ends.

4. The solar cell of claim 1, wherein The height difference H between the gate line area and the non-gate line area is 0.5-6 mu m, including the values at both ends.

5. The solar cell of claim 1, wherein The process for preparing the solar cell according to any one of claims 1-6 comprises the following steps: S1: placing a to-be-cleaned substrate in HF to perform first acid washing, so as to obtain a first substrate with the oxide layer on the front surface and the side surface of the to-be-cleaned substrate removed; 6. The solar cell of claim 1, wherein S2: placing the first substrate in a first mixed solution to perform cleaning, the first mixed solution comprising 2%-4% concentration of NaOH and 1%-1.5% concentration of an additive, the temperature of the first mixed solution being 65-70 DEG C, and the cleaning time being 250-500 s, so that a height difference H is formed between the substrate in the non-gate line area and the substrate in the gate line area on the back of the first substrate, and a tower base is formed on the side surface of the first substrate, thereby obtaining a second substrate, which is then rinsed with deionized water; 7. A RCA cleaning method characterized by, S3: placing the second substrate in a second mixed solution to perform cleaning, the second mixed solution comprising lye and hydrogen peroxide, thereby obtaining a third substrate, which is then rinsed with deionized water; S4: placing the third substrate in an acid tank to perform second acid washing, so as to remove the remaining oxide layer and neutralize the lye, thereby obtaining a fourth substrate, which is then rinsed with deionized water; S5: placing the fourth substrate in a third mixed solution to perform cleaning, the third mixed solution comprising lye and hydrogen peroxide, thereby obtaining a fifth substrate, which is then rinsed with deionized water; S6: placing the fifth substrate in an acid tank to perform third acid washing, thereby obtaining a sixth substrate, which is then rinsed with deionized water; S7: rinsing the sixth substrate, thereby obtaining a seventh substrate; S8: drying the seventh substrate. ​ ​ ​ 8. The RCA cleaning method of claim 7, wherein, In step S3, the concentration of NaOH in the second mixed solution is 1%-1.5%, and the concentration of hydrogen peroxide in the second mixed solution is 2%-4%; the temperature of the second mixed solution is 60-65℃; the cleaning time of the second mixed solution is 90-120s. In step S5, the concentration of NaOH in the third mixed solution is 1%-1.5%, the concentration of hydrogen peroxide in the third mixed solution is 2%-4%; the temperature of the third mixed solution is 60-65℃; the cleaning time of the third mixed solution is 90-120s.

9. The RCA cleaning method of claim 7, wherein, In step S4, the concentration of HF in the second acid cleaning is 10%-15%; the temperature of the HF is room temperature; the cleaning time of the HF is 100-130s. In step S6, the concentration of HF in the third acid cleaning is 10%-15%; the temperature of the HF is room temperature; the cleaning time of the HF is 100-130s.

10. The RCA cleaning method of claim 7, wherein, The sixth substrate is cleaned by slow pulling method. In step S8, the seventh substrate is dried by CDA using high temperature and hot air in the drying tank; the temperature of the high temperature is 90-100℃.

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