Semiconductor packaging structure, manufacturing method and semiconductor device

Abstract

The invention belongs to the technical field of semiconductor manufacturing, and provides a semiconductor packaging structure, a manufacturing method and a semiconductor device.The semiconductor packaging structure comprises a first substrate, an insulating layer, a conductive part and a chip, the first substrate comprises a substrate body and a heat dissipation layer, the heat dissipation layer is connected to the second surface of the substrate body, and the contact area is smaller than the area of the second surface; a second groove is formed between the side face of the heat dissipation layer and the substrate body, a lead hole is formed in the second groove, the insulating layer covers the side wall of the lead hole, the bottom face of the second groove and at least part of the first surface of the substrate body, the conductive part is formed on the insulating layer and arranged with the first substrate in a spaced mode, and the third surface of the chip is connected to the first substrate or the conductive part. The first substrate forms a thermoelectric separation structure or a direct type heat conduction structure, so that the heat conductivity coefficient of the light-emitting element can be effectively improved, the heat dissipation effect of the device is enhanced, the size of the first substrate can be reduced, and the problem that the welding void rate is increased during subsequent mounting is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor packaging structure, a manufacturing method and a semiconductor device. BACKGROUND

[0002] In the field of semiconductor technology, power type patch LED elements have been widely used in lighting, display and other fields due to their high power, long service life, compact structure and other advantages. The traditional power type patch LED element is usually packaged by a high-power vertical chip, a fluorescent conversion component and a high-thermal-conductivity substrate. In practical applications, end users usually use surface mount (SET) soldering process to mount the power type patch LED element on the designed printed circuit board or metal heat sink. Since the substrate of ceramic material has more excellent heat dissipation performance than the substrate of other materials, the existing high-power LED packaging technology generally takes ceramic substrate as the main one.

[0003] However, as the chip power continues to increase, in order to meet the heat dissipation demand, the size of the ceramic substrate also continues to increase, for example, a 3535 substrate is selected when the chip power is 10W-20W, a 5050 substrate is selected when the chip power is 20W-30W, a 7070 substrate is selected when the chip power is 30W-50W, and so on. Although the large-size ceramic substrate improves the heat dissipation effect to a certain extent, during the soldering process, due to the physical properties of the ceramic material and the interaction between the ceramic material and the solder material, it is difficult to achieve complete uniform contact and filling, which leads to the problem of easy increase of soldering void rate, and the increase of the soldering void rate will inevitably reduce the heat dissipation capacity of the device, and further affect the performance and service life of the LED element.

[0004] In addition, there is a problem of mismatch of the thermal expansion coefficient between the large-size ceramic substrate and the metal heat sink. The difference between the thermal expansion coefficients of the ceramic material and the metal material is large, and the expansion and contraction degrees between the two are different during the soldering process, which causes stress in the soldering layer. When the stress accumulates to a certain extent, the soldering layer is prone to cracking, which weakens the heat dissipation effect of the device and reduces the working performance. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor packaging structure, a manufacturing method and a semiconductor device to improve the heat dissipation effect of the high-power LED element.

[0006] In a first aspect, the present application provides a semiconductor package structure, comprising a first substrate, an insulating layer, a conductive part and a chip. The first substrate comprises a substrate body and a heat dissipation layer, the substrate body has a first surface and a second surface arranged oppositely, the heat dissipation layer is connected to the second surface of the substrate body, and the area of the projection of the heat dissipation layer is smaller than the area of the second surface when viewed along the thickness direction of the substrate body, so that a second groove is formed between the side surface of the heat dissipation layer and the substrate body, and a lead hole penetrating through the substrate body is arranged in the second groove; the insulating layer covers the sidewall of the lead hole, the bottom surface of the second groove and at least part of the first surface; the conductive part is formed on the insulating layer and filled into the lead hole, and the conductive part and the first substrate are arranged spaced apart from each other; the chip has a third surface, and the third surface of the chip is connected to the first substrate or the conductive part; wherein the ratio of the area of the chip to the area of the projection of the substrate body is greater than or equal to 20% when viewed along the thickness direction of the substrate body.

[0007] In a second aspect, the present application provides a manufacturing method of a semiconductor package structure, comprising the following steps:

[0008] providing a first substrate and a chip, the first substrate comprises a heat dissipation layer and a substrate body arranged in layers, the substrate body has a first surface and a second surface arranged oppositely, the heat dissipation layer is connected to the second surface of the substrate body, and the chip has a fourth surface and a third surface arranged oppositely;

[0009] graphically etching the heat dissipation layer to form a second groove exposing the second surface;

[0010] etching the substrate body to form a lead hole;

[0011] forming an insulating layer on the surface of the substrate body, the insulating layer covers the sidewall of the lead hole, the bottom surface of the second groove and at least part of the first surface;

[0012] forming a conductive part on the insulating layer, the conductive part fills the lead hole and is arranged spaced apart from the first substrate;

[0013] connecting the third surface of the chip to the first substrate or the conductive part.

[0014] In a third aspect, the present application provides a semiconductor device, comprising a second substrate, a solder layer and a plurality of semiconductor package structures as described above, the solder layer is located between the second substrate and the semiconductor package structure, so as to connect a plurality of semiconductor package structures to the second substrate.

[0015] Compared with the prior art, the semiconductor packaging structure, the manufacturing method and the semiconductor device provided by the application have at least the following beneficial effects:

[0016] In the semiconductor packaging structure, the second surface of the substrate body is provided with a heat dissipation layer, the substrate body is provided with a lead hole, the conductive part realizes electrical connection of both sides of the substrate body through the lead hole, and is spaced apart from the first substrate through the insulating layer. For a vertical structure chip, the insulating layer completely covers the first surface of the substrate body, the third surface of the chip is connected to the conductive part, and the first substrate constitutes a thermoelectric separation structure. For a horizontal vertical thermoelectric separation chip, the insulating layer covers part of the first surface of the substrate body, the chip is connected to the first substrate, and the first substrate constitutes a direct type heat conduction structure. The heat conduction coefficient of the light emitting element can be effectively improved, and the heat dissipation effect of the device is improved.

[0017] In addition, under the condition of meeting the conductive requirement of the device, the size of the conductive part can be minimized to increase the area of the heat dissipation layer, and the heat dissipation effect of the device is further improved. By controlling the ratio of the projection area of the chip to the projection area of the substrate body to be not less than 20%, the first substrate can have a smaller size under the condition of meeting the heat dissipation requirement of the device, and the problem of increasing the soldering cavity rate caused by the large size of the substrate can be effectively improved in the mounting process of the semiconductor packaging structure, and the heat dissipation performance of the device is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0019] Figure 1 A structure schematic diagram of a semiconductor device provided by Embodiment One of the application is shown.

[0020] Figure 2 A structure schematic diagram of a semiconductor packaging structure provided by Embodiment One of the application is shown.

[0021] Figure 3 A top view structure schematic diagram of a semiconductor packaging structure provided by Embodiment One of the application is shown.

[0022] Figure 4 A structure schematic diagram of another semiconductor packaging structure provided by Embodiment Two of the application is shown.

[0023] Figure 5 And Figure 6Schematic diagrams respectively showing top structures of two semiconductor package structures provided by Embodiment Two of the present application.

[0024] Figure 7 A flowchart schematically showing a manufacturing method of a semiconductor package structure provided by Embodiment Three of the present application.

[0025] Figure 8 A flowchart schematically showing the manufacturing method provided by Embodiment Three of the present application. Figure 7 A schematic diagram showing a structure of providing a first substrate in the manufacturing method.

[0026] Figure 9 A schematic diagram showing a structure of forming a second recess in the manufacturing method. Figure 7 A schematic diagram showing a structure of forming a first recess in the manufacturing method.

[0027] Figure 10 A schematic diagram showing a structure of forming a first recess in the manufacturing method. Figure 7 A schematic diagram showing a structure of forming a first recess in the manufacturing method.

[0028] Figure 11 A schematic diagram showing a structure of forming a first recess in the manufacturing method. Figure 12 A schematic diagram showing a structure of forming a first recess in the manufacturing method. Figure 7 A schematic diagram showing a structure of forming a first recess in the manufacturing method.

[0029] Figure 13 A schematic diagram showing a structure of forming a first recess in the manufacturing method. Figure 14 A schematic diagram showing a structure of forming a first recess in the manufacturing method. Figure 7 A schematic diagram showing a structure of forming a first recess in the manufacturing method.

[0030] Explanation of Reference Signs:

[0031] 10, semiconductor package structure; 11, first substrate; 111, substrate body; 112, heat dissipation layer; 113, heat conduction layer; 114, lead hole; 1141, first lead hole; 1142, second lead hole; 115, first recess; 116, second recess; 12, insulating layer; 13, conductive part; 131, first conductive part; 1311, first wiring layer; 1312, second wiring layer; 1313, first conductive column; 132, second conductive part; 1321, third wiring layer; 1322, fourth wiring layer; 1323, second conductive column; 14, chip; 141, first electrode; 142, second electrode; 21, second substrate; 22, solder layer. DETAILED DESCRIPTION

[0032] In order to make the technical purposes, technical solutions and technical effects of the present application clearer, the technical solutions in the present application will be described clearly and completely below in conjunction with embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of embodiments of the application is not intended to limit the scope of the application as claimed but merely represents selected embodiments of the application. Based upon the embodiments of the application described herein, all other embodiments obtained by persons of ordinary skill in the art without departing from the spirit of the application are within the scope of the application. Furthermore, the terms "first", "second", etc. are used only for descriptive purposes and not to indicate or imply relative importance.

[0034] In the description of the present application, it should be noted that the description of the terms "one embodiment", "some embodiments", "optional embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in connection with the implementation or example are included in at least one implementation or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0035] In the prior art, with reference to Figure 1 To meet the heat dissipation needs of different power LED elements, as the power of the chip continues to increase, the size of the ceramic substrate used in the packaging process also continues to increase. However, when the LED element is attached to the PCB or heat sink, during the soldering process of the large-size ceramic substrate, due to the physical properties of the ceramic material and the interaction between the solder material, it is difficult to achieve complete uniform contact and filling, resulting in the problem of increased solder void rate during the soldering process when attaching the semiconductor packaging structure 10, and the increase in the solder void rate reduces the heat dissipation capacity of the device, affecting the working performance and service life of the LED element. In addition, there is a problem of mismatch of the coefficient of thermal expansion between the large-size ceramic substrate and the metal heat sink. The difference in the coefficient of thermal expansion between the ceramic material and the metal material is large, and the accumulation of stress during the soldering process makes the soldering layer 22 prone to cracking, reducing the heat dissipation capacity and working performance of the LED element.

[0036] To overcome the above problems and defects, the present application provides a semiconductor packaging structure, a manufacturing method and a semiconductor device, which will be described in detail through the following specific embodiments.

[0037] In a first aspect, the present application provides a semiconductor packaging structure, comprising:

[0038] The first substrate includes a substrate body and a heat dissipation layer, the substrate body has a first surface and a second surface arranged oppositely, the heat dissipation layer is connected to the second surface of the substrate body, and the area of the projection of the heat dissipation layer is smaller than the area of the second surface in the thickness direction of the substrate body, so that a second groove is formed between the side surface of the heat dissipation layer and the substrate body, and the lead hole penetrating through the substrate body is arranged in the second groove;

[0039] The insulating layer covers the side wall of the lead hole, the bottom surface of the second groove, and at least part of the first surface;

[0040] The conductive part is formed on the insulating layer and filled into the lead hole, and the conductive part and the first substrate are arranged apart from each other;

[0041] The chip has a third surface, and the third surface of the chip is connected to the first substrate or the conductive part;

[0042] The ratio of the area of the chip to the area of the projection of the substrate body is greater than or equal to 20% in the thickness direction of the substrate body.

[0043] In the semiconductor packaging structure, the conductive part is arranged on the opposite sides of the substrate body, the electrical connection of the two sides of the substrate body is realized through the lead hole, the insulating layer can completely cover the first surface of the substrate body or cover part of the first surface of the substrate body, for a vertical structure chip, one electrode is arranged on the third surface of the chip, the insulating layer completely covers the first surface of the substrate body, the third surface of the chip is connected to the conductive part, so as to fix the chip on the first substrate and realize the electrical connection between the electrode and the conductive part, and the first substrate forms a thermoelectric separation structure, for a horizontal and vertical heat separation chip, the insulating layer covers part of the first surface of the substrate body, the third surface of the chip is connected to the first substrate, and the electrode of the chip can be electrically connected between the conductive part, and the first substrate forms a direct type heat conduction structure, therefore, the semiconductor packaging structure can effectively improve the thermal conductivity of the light emitting element, and further improve the heat dissipation effect of the device.

[0044] In addition, under the condition of meeting the conductive requirement of the device, the area of the conductive part can be reduced to the maximum extent, and the area of the heat dissipation layer can be increased, so as to further improve the thermal conductivity of the light emitting element and enhance the heat dissipation effect of the device. Moreover, by controlling the ratio of the projection area of the chip to the projection area of the substrate body to be not less than 20%, the first substrate can have a smaller size under the condition of meeting the heat dissipation requirement of the device, which helps to improve the problem of increasing the soldering cavity rate due to the large size of the substrate in the process of mounting the semiconductor packaging structure, and further improves the heat dissipation effect of the device.

[0045] Optionally, the chip comprises a first electrode and a second electrode, the lead hole comprises a first lead hole and a second lead hole, the conductive part comprises a first conductive part and a second conductive part arranged apart from each other, the first conductive part is formed on the insulating layer and fills the first lead hole, the second conductive part is formed on the insulating layer and fills the second lead hole, the first electrode is connected to the first conductive part, and the second electrode is connected to the second conductive part.

[0046] The first conductive part realizes electrical connection between the two sides of the substrate body through the first lead hole, the second conductive part realizes electrical connection between the two sides of the substrate body through the second lead hole, the first electrode is connected to the first conductive part, the second electrode is connected to the second conductive part, the first conductive part is electrically isolated from the second conductive part, and the first electrode and the second electrode are respectively led out. The first conductive part and the second conductive part are both formed on the insulating layer and are electrically isolated from the first substrate, so that the first substrate can form a thermoelectric separation structure or a direct type heat conduction structure during use, thereby improving the heat dissipation capacity of the device.

[0047] Optionally, the first conductive part comprises a first wiring layer, a second wiring layer and a first conductive column, the first conductive column fills the first lead hole, the first wiring layer is located on the insulating layer on the side where the first surface of the substrate body is located and covers the first lead hole, and the second wiring layer is located on the insulating layer on the side where the second surface of the substrate body is located and covers the first lead hole.

[0048] The second conductive part comprises a third wiring layer, a fourth wiring layer and a second conductive column, the second conductive column fills the second lead hole, the third wiring layer is located on the insulating layer on the side where the first surface of the substrate body is located and covers the second lead hole, and the fourth wiring layer is located on the insulating layer on the side where the second surface of the substrate body is located and covers the second lead hole.

[0049] The first electrode of the chip is electrically connected to the first wiring layer, and the first electrode is led out by using the second wiring layer. The second electrode of the chip is electrically connected to the third wiring layer, and the second electrode is led out by using the fourth wiring layer.

[0050] Optionally, the second electrode is located on the third surface of the chip, and the projection plane of the chip is located in the projection plane of the third wiring layer in the thickness direction of the substrate body. The third surface of the chip is connected to the third wiring layer. By controlling the third wiring layer to have a large area, sufficient space can be reserved for packaging of the chip to fix the chip on the first substrate and electrically connect the second electrode of the chip to the third wiring layer.

[0051] Optionally, viewed from above along the thickness direction of the substrate body, the projection surface of the second wiring layer is located within the projection surface of the first wiring layer, and the projection surface of the first wiring layer has a U-shaped structure. The projection surfaces of the third wiring layer and the chip are both located within the U-shaped structure of the projection surface of the first wiring layer. By controlling the fourth wiring layer to have a U-shaped structure, the length of the leads can be reduced while reserving sufficient space for chip packaging, facilitating the lead-out of electrodes. By controlling the second wiring layer to have a smaller area, the area of ​​the heat dissipation layer can be increased while ensuring the conductivity requirements of the device, thereby improving the heat dissipation capacity of the device.

[0052] Optionally, the chip has a fourth surface on the side away from the first substrate, and both the first electrode and the second electrode are located on the fourth surface of the chip. The insulating layer also has a first opening exposing the first surface. The third surface of the chip is connected to the first substrate through the first opening. Viewed from above along the thickness direction of the substrate body, the projected surface of the chip is spaced apart from the first wiring layer and the third wiring layer, respectively. The chip is a horizontally and vertically thermoelectrically separated chip, connecting the third surface of the chip to the first substrate. The first substrate and the conductive parts are electrically isolated through the insulating layer, forming a direct-down heat-conducting structure on the first substrate. This effectively improves the thermal conductivity of the light-emitting element and enhances the heat dissipation performance of the device.

[0053] Optionally, the first substrate further includes a thermally conductive layer connected to a first surface of the substrate body. A third surface of the chip is connected to the side of the thermally conductive layer away from the substrate body. Viewed from above along the thickness direction of the substrate body, the projection surface of the chip lies within the projection surface of the thermally conductive layer, and the area of ​​the projection surface of the thermally conductive layer is smaller than the area of ​​the first surface, forming a first groove between the side of the thermally conductive layer and the substrate body. An insulating layer covers the bottom surface of the first groove, and the first wiring layer and the third wiring layer are located on the insulating layer within the first groove. By providing a thermally conductive layer between the chip and the substrate body, the surface of the thermally conductive layer and the surface of the conductive portion can be made nearly flat, which helps improve the heat dissipation capacity of the device. By controlling the area of ​​the thermally conductive layer to be smaller than the area of ​​the first surface, sufficient space is reserved for forming the conductive portion. By controlling the projection area of ​​the chip to be smaller than the projection area of ​​the thermally conductive layer, sufficient space is reserved for chip packaging.

[0054] Optionally, when viewed from above along the thickness direction of the substrate body, the ratio of the area of ​​the heat dissipation layer to the area of ​​the second surface is greater than or equal to 40%, which helps to improve the thermal conductivity of the light-emitting element and enhance the heat dissipation performance of the device.

[0055] Optionally, when viewed from above along the thickness direction of the substrate body, the ratio of the area of ​​the heat dissipation layer to the area of ​​the second surface is 60% to 90%. By controlling the above-mentioned area ratio to not exceed 90%, sufficient space can be reserved for forming the conductive part to meet the conductivity requirements of the device. By controlling the above-mentioned area ratio to not be less than 60%, the area of ​​the heat dissipation layer can be maximized while meeting the conductivity requirements of the device, thereby improving the thermal conductivity of the light-emitting element and enhancing the heat dissipation performance of the device.

[0056] Optionally, when viewed from above along the thickness direction of the substrate body, the ratio of the area of ​​the chip to the area of ​​the projected surface of the substrate body is 40% to 90%. By controlling the above-mentioned area ratio to not exceed 90%, sufficient space can be reserved for forming conductive parts. By controlling the above-mentioned area ratio to not be less than 40%, the size of the first substrate can be reduced to the maximum extent while meeting the conductivity requirements, thus improving the problem of increased solder void rate caused by a large substrate size.

[0057] Optionally, when viewed from above along the thickness direction of the substrate body, the projection surface of the chip is located within the projection surface of the heat dissipation layer, which helps to enhance the heat dissipation effect of the chip and ensure that the light-emitting element has a high thermal conductivity.

[0058] Secondly, this application also provides a method for fabricating a semiconductor packaging structure, comprising the following steps:

[0059] A first substrate and a chip are provided. The first substrate includes a heat dissipation layer and a substrate body stacked together. The substrate body has a first surface and a second surface disposed opposite to each other. The heat dissipation layer is connected to the second surface of the substrate body. The chip has a fourth surface and a third surface disposed opposite to each other.

[0060] The heat dissipation layer is patterned and etched to form a second groove that exposes the second surface;

[0061] A lead hole is formed that penetrates the substrate body;

[0062] An insulating layer is formed on the surface of the substrate body, the insulating layer covering the sidewall of the lead hole, the bottom surface of the second groove, and at least a portion of the first surface;

[0063] A conductive portion is formed on the insulating layer, the conductive portion fills the lead hole, and is spaced apart from the first substrate;

[0064] The third surface of the chip is connected to the first substrate or the conductive part.

[0065] In this fabrication method, an insulating layer covers the sidewalls of the lead hole, the bottom surface of the second groove, and at least part of the first surface, electrically insulating the conductive part from the first substrate. The conductive part fills the lead hole, achieving electrical connection between the two sides of the first substrate. The third surface of the chip is connected to the first substrate or the conductive part, making the first substrate form a thermoelectric separation structure or a direct-downward heat conduction structure, effectively improving the thermal conductivity of the light-emitting element and enhancing the heat dissipation performance of the device. Patterned etching of the heat dissipation layer to form the second groove allows the surfaces of the conductive part and the heat dissipation layer to approach a flat surface. While meeting the device's conductivity requirements, the second groove can have a smaller area, allowing the heat dissipation layer to have a larger area, which helps to further enhance the device's heat dissipation effect.

[0066] Optionally, the chip includes a first electrode and a second electrode, the first electrode being located on a fourth surface of the chip, and the second electrode being located on a third surface of the chip. The conductive portion includes a first conductive portion and a second conductive portion, the second conductive portion including a third wiring layer, the third wiring layer being formed on an insulating layer on the side of the first surface of the substrate body. The step of connecting the third surface of the chip to the first substrate or the conductive portion includes:

[0067] The third surface of the chip is fixedly connected to the third wiring layer, and the first electrode is electrically connected to the first conductive part. The chip is a vertical structure chip. By connecting the chip to the third wiring layer, a thermoelectric separation structure is formed on the first substrate, improving the thermal conductivity of the light-emitting element.

[0068] Optionally, the first substrate further includes a thermally conductive layer connected to a first surface of the substrate body; before forming a through-hole through the substrate body, the following steps are further included:

[0069] The thermally conductive layer is patterned and etched to form a first groove exposing the first surface. By etching to form the patterned first groove, space is provided for the formation of the first wiring layer and the third wiring layer, so that the surfaces of the first wiring layer, the third wiring layer and the thermally conductive layer are approximately flat.

[0070] Optionally, the chip includes a first electrode and a second electrode, both of which are located on a fourth surface of the chip, and the conductive portion includes a first conductive portion and a second conductive portion; the step of connecting the third surface of the chip to the first substrate or the conductive portion includes:

[0071] The chip is fixedly connected to the thermal conductive layer;

[0072] The first electrode is electrically connected to the first conductive part, and the second electrode is electrically connected to the second conductive part. The chip is a horizontally and vertically thermoelectrically separated chip. Connecting the chip to the thermally conductive layer makes the first substrate form a direct-downward thermally conductive structure, which improves the thermal conductivity of the light-emitting element and enhances the heat dissipation performance of the device.

[0073] Thirdly, this application also provides a semiconductor device, including a second substrate, a bonding layer, and a plurality of semiconductor packaging structures provided in this application, wherein the bonding layer is located between the second substrate and the semiconductor packaging structures to connect the plurality of semiconductor packaging structures to the second substrate.

[0074] The present application will be described in detail below with reference to specific embodiments.

[0075] Example 1

[0076] This embodiment provides a semiconductor packaging structure 10, referring to... Figure 2 and Figure 3 The semiconductor package structure 10 includes a first substrate 11, an insulating layer 12, a conductive portion 13, and a chip 14.

[0077] The first substrate 11 includes a substrate body 111 and a heat dissipation layer 112. The substrate body 111 has a first surface and a second surface disposed opposite to each other. The heat dissipation layer 112 is connected to the second surface of the substrate body 111 to enhance the heat dissipation capability of the device. Viewed from above along the thickness direction of the substrate body 111, the area of ​​the projected surface of the heat dissipation layer 112 is smaller than the area of ​​the second surface, so that a second groove 116 is formed between the side of the heat dissipation layer 112 and the substrate body 111, providing space for the formation of the conductive portion 13. This ensures that the surfaces of the conductive portion 13 and the heat dissipation layer 112 are flat or nearly flat, facilitating the mounting of the semiconductor package structure 10. A lead hole 114 penetrating the substrate body 111 is provided in the second groove 116 to cooperate with the conductive portion 13 to achieve electrical connection between the two sides of the first substrate 11.

[0078] Reference Figure 8 The first substrate 11 can be a one-piece structure. The surface of the rectangular plate-shaped first substrate 11 can be etched to form a patterned second groove 116. The part of the first substrate 11 within the area enclosed by the second groove 116 is called the heat dissipation layer 112, and the main part of the remaining first substrate 11 is called the substrate body 111. Alternatively, other suitable methods can be used to divide the one-piece structure first substrate 11 into the substrate body 111 and the heat dissipation layer 112.

[0079] In an optional embodiment, the substrate body 111 and the heat dissipation layer 112 may also be of a discrete structure, with the heat dissipation layer 112 connected to the second surface of the substrate body 111 to form the first substrate 11. The pre-made heat dissipation layer 112 may be pressed onto the second surface of the substrate body 111 to fix the heat dissipation layer 112 to the substrate body 111, or other suitable methods may be used to fix the heat dissipation layer 112 to the substrate body 111.

[0080] The materials of the substrate body 111 and the heat dissipation layer 112 can be the same material or different materials. Optionally, the material of the first substrate 11 includes a metallic material, such as copper, aluminum or other suitable metallic materials, or one or more of them.

[0081] In an optional embodiment, viewed from above along the thickness direction of the substrate body 111, the ratio of the area of ​​the heat dissipation layer 112 to the area of ​​the second surface is greater than or equal to 40%. Specifically, the ratio of the area of ​​the heat dissipation layer 112 to the area of ​​the second surface can be, for example, 40%, 50%, 60%, 70%, 80%, 90%, or other suitable values. By controlling the heat dissipation layer 112 to have a relatively large area ratio, it helps to improve the thermal conductivity of the light-emitting element and enhance the heat dissipation effect of the device.

[0082] Furthermore, viewed from above along the thickness direction of the substrate body 111, the ratio of the area of ​​the heat dissipation layer 112 to the area of ​​the second surface is 60% to 90%. By controlling the ratio of the area of ​​the heat dissipation layer 112 to the area of ​​the second surface to not exceed 90%, sufficient space can be reserved for the conductive part 13 to meet the requirements of conductivity; by controlling the ratio of the area of ​​the heat dissipation layer 112 to the area of ​​the second surface to not be less than 60%, the area of ​​the heat dissipation layer 112 can be maximized while meeting the conductivity requirements, thereby improving the thermal conductivity of the light-emitting element.

[0083] Reference Figure 3 The first substrate 11 is provided with at least two through-holes 114. The through-holes 114 are located in the second groove 116 and pass through the substrate body 111, and are used to cooperate with the conductive part 13 to realize the electrical connection between the two sides of the first substrate 11.

[0084] Reference Figure 2 and Figure 3 The insulating layer 12 is located on the surface of the first substrate 11, covering the sidewall of the lead hole 114, the bottom surface of the second groove 116, and the first surface, so as to achieve electrical isolation between the conductive part 13 and the first substrate 11. The material of the insulating layer 12 can be organic resin, aluminum oxide, ceramic filler material, or other suitable materials. Optionally, the material of the insulating layer 12 can be, for example, ceramic-filled epoxy resin.

[0085] The conductive portion 13 is formed on the insulating layer 12 and fills the lead hole 114. The conductive portion 13 and the first substrate 11 are spaced apart by the insulating layer 12. The conductive portion 13 is electrically connected to the chip 14 to realize the electrode lead-out of the chip 14. The material of the conductive portion 13 can be a metal such as copper or aluminum, or other suitable conductive materials.

[0086] Reference Figure 2 Chip 14 includes a first electrode 141 and a second electrode 142, which are electrically opposite. Specifically, the first electrode 141 may be a P-type electrode and the second electrode 142 may be an N-type electrode, or the first electrode 141 may be an N-type electrode and the second electrode 142 may be a P-type electrode. A lead hole 114 includes a first lead hole 1141 and a second lead hole 1142. Conductive portion 13 includes a first conductive portion 131 and a second conductive portion 132 spaced apart from each other. The first conductive portion 131 is formed on the insulating layer 12 and fills the first lead hole 1141; the second conductive portion 132 is formed on the insulating layer 12 and fills the second lead hole 1142. The first electrode 141 is connected to the first conductive portion 131, and the second electrode 142 is connected to the second conductive portion 132.

[0087] In an optional embodiment, refer to Figure 13 The first conductive portion 131 includes a first wiring layer 1311, a second wiring layer 1312, and a first conductive post 1313. The first conductive post 1312 fills the first lead hole 1141. The first wiring layer 1311 is located on the insulating layer 12 on the side where the first surface of the substrate body 111 is located and covers the first lead hole 1141. The second wiring layer 1312 is located on the insulating layer 12 on the side where the second surface of the substrate body 111 is located and covers the first lead hole 1141. The first conductive post 1312 is connected to the first wiring layer 1311 and the second wiring layer 1312 respectively, so that the first conductive portion 131 is formed as a whole, realizing the electrical connection between the two sides of the first substrate 11, thereby realizing the lead-out of the first electrode. The first wiring layer 1311 and the second wiring layer 1312 can be formed by deposition, coating or other suitable methods, or the pre-made first wiring layer 1311 and the second wiring layer 1312 can be pressed onto the surface of the substrate body 111 to form the first conductive portion 131.

[0088] In an optional embodiment, the second conductive portion 132 includes a third wiring layer 1321, a fourth wiring layer 1322, and a second conductive post 1323. The second conductive post 1323 fills the second lead hole 1142. The third wiring layer 1321 is located on the insulating layer 12 on the side where the first surface of the substrate body 111 is located and covers the second lead hole 1142. The fourth wiring layer 1322 is located on the insulating layer 12 on the side where the second surface of the substrate body 111 is located and covers the second lead hole 1142. The second conductive post 1323 is connected to the third wiring layer 1321 and the fourth wiring layer 1322 respectively, so that the second conductive portion 132 forms an integral whole, realizing the electrical connection between the two sides of the first substrate 11, so as to realize the lead-out of the second electrode. The third wiring layer 1321 and the fourth wiring layer 1322 can be formed by deposition, coating or other suitable methods, or the pre-made third wiring layer 1321 and the fourth wiring layer 1322 can be pressed onto the surface of the substrate body 111 to form the second conductive portion 132.

[0089] Chip 14 has a fourth surface and a third surface disposed opposite to each other. A first electrode is located on the fourth surface of chip 14, and a second electrode is located on the third surface of chip 14. Chip 14 can be, for example, an LED chip or other suitable power device. Optionally, the power of chip 14 is greater than 20W. Specifically, the power of chip 14 can be, for example, 20W, 30W, 50W, or other suitable values. Since the light-emitting element using this embodiment has a higher thermal conductivity than light-emitting elements using traditional ceramic substrates such as aluminum nitride ceramic substrates, the first substrate 11 can have a smaller size while meeting the heat dissipation requirements of the device. This is especially true for high-power and ultra-high-power LED chips, thereby significantly reducing the size of the first substrate 11 and effectively improving the problem of increased solder void rate during the mounting process.

[0090] In an optional embodiment, viewed from above along the thickness direction of the substrate body 111, the projection surface of the chip 14 lies within the projection surface of the third wiring layer 1321, and the third surface of the chip 14 is connected to the third wiring layer 1321 to fix the chip 14 onto the first substrate 11. By making the third wiring layer 1321 have a large area, sufficient space can be provided for the mounting of the chip 14, so as to fix the chip 14 onto the first substrate 11 and make electrical connection between the second electrode of the chip 14 and the second conductive portion 132.

[0091] In an optional embodiment, refer to Figure 3Viewed from above along the thickness direction of the substrate body 111, the projection surface of the first wiring layer 1311 has a U-shaped structure. The projection surfaces of the third wiring layer 1321 and the chip 14 are both located within the U-shaped structure of the projection surface of the fourth wiring layer 1322. By controlling the first wiring layer 1311 to have a U-shaped structure, the length of the leads can be reduced while providing sufficient space for the chip 14 packaging, facilitating the lead-out of electrodes. Furthermore, the projection surface of the second wiring layer 1312 is located within the projection surface of the first wiring layer 1311, which helps to increase the area of ​​the heat dissipation layer 112 and improve the heat dissipation effect of the device while ensuring the conductivity requirements of the device.

[0092] Furthermore, viewed from above along the thickness direction of the substrate body 111, the first wiring layer 1311 is, for example, a U-shaped structure, the third wiring layer 1321 is, for example, a rectangular structure, and the second wiring layer 1312 and the fourth wiring layer 1322 are both rectangular strip structures, which makes the heat dissipation layer 112 have a large area ratio, thereby enabling the light-emitting element to have better thermal conductivity within a limited size.

[0093] In an optional embodiment, when viewed from above along the thickness direction of the substrate body 111, the ratio between the area of ​​the chip 14 and the area of ​​the projected surface of the substrate body 111 is greater than or equal to 20%. Specifically, the ratio between the area of ​​the chip 14 and the area of ​​the projected surface of the substrate body 111 can be, for example, 20%, 30%, 50%, 70%, 80%, 90%, or other suitable values. By controlling the area ratio of the projected surface between the chip 14 and the substrate body 111 to be not less than 20%, it helps to reduce the size of the first substrate 11, improve the problem of increased solder void rate caused by excessively large substrate size, and ensure that the device has good heat dissipation performance.

[0094] Furthermore, the ratio between the area of ​​chip 14 and the area of ​​the projected surface of substrate body 111 is 40% to 90%. By controlling the ratio between the area of ​​chip 14 and the area of ​​the projected surface of substrate body 111 to not exceed 90%, sufficient space can be reserved for conductive part 13. By controlling the above-mentioned area ratio to be not less than 40%, the size of the first substrate 11 can be reduced to the maximum extent while meeting the conductivity requirements, and the problem of increased solder void rate caused by large substrate size can be significantly improved.

[0095] In this embodiment, when viewed from above along the thickness direction of the substrate body 111, the projection surface of the chip 14 is located within the projection surface of the heat dissipation layer 112, which can ensure the heat transfer effect of the first substrate 11 to the chip 14, improve the thermal conductivity of the light-emitting element, and ensure that the device has good heat dissipation capability.

[0096] In an optional embodiment, chip 14 is an LED light-emitting element, and semiconductor package structure 10 further includes a fluorescence conversion section disposed on the surface of chip 14 for converting the light emitted by the LED light-emitting element.

[0097] This embodiment also provides a semiconductor device, see reference. Figure 1 The system includes a second substrate 21, a bonding layer 22, and several semiconductor packaging structures 10. The bonding layer 22 is located between the second substrate 21 and the semiconductor packaging structures 10, and the semiconductor packaging structures 10 are fixedly connected to the second substrate 21 through the bonding layer 22. The second substrate 21 can be a metal heat sink, a PCB, etc.

[0098] When the size of the first substrate 11 in the semiconductor package structure 10 is too large, the welding void ratio is likely to increase during the welding process of forming the welding layer 22, resulting in poor heat dissipation of the device. When the first substrate 11 is made of ceramic material, the welding layer 22 is prone to cracking due to the mismatch of thermal expansion coefficient.

[0099] The light-emitting element using this embodiment has a higher thermal conductivity, reaching or exceeding 300 W / (m·K). Compared to light-emitting elements using traditional ceramic substrates, such as aluminum nitride ceramic substrates, whose thermal conductivity is 170 W / (m·K) to 230 W / (m·K), the semiconductor device using this embodiment exhibits superior heat dissipation performance. Furthermore, while meeting the device's heat dissipation requirements, the first substrate 11 can have a smaller size, effectively improving the problem of increased solder voids. Moreover, the first substrate 11 can be made of a metallic material, effectively preventing the solder layer 22 from cracking due to a mismatch in the coefficients of thermal expansion between the first substrate 11 and the second substrate 21.

[0100] Example 2

[0101] This embodiment provides a semiconductor packaging structure 10, referring to... Figure 4 and Figure 5 It also includes a first substrate 11, an insulating layer 12, a conductive part 13 and a chip 14. The similarities with Embodiment 1 will not be repeated, and the differences are as follows.

[0102] In this embodiment, chip 14 has a fourth surface and a third surface disposed opposite to each other. The fourth surface is located on the side of chip 14 away from the first substrate 11. Chip 14 includes a first electrode 141 and a second electrode 142, both of which are located on the fourth surface of chip 14. Optionally, chip 14 is a horizontally and vertically thermoelectrically separated chip, including a substrate and a stacked structure formed on the substrate. The size of the stacked structure is smaller than the size of the substrate, such that a stepped structure is formed on the side of chip 14, and the first electrode 141 and the second electrode 142 are both formed on the stepped structure.

[0103] The insulating layer 12 also has a first opening exposing the first surface. The third surface of the chip 14 is connected to the first substrate 11 through the first opening. Viewed from above along the thickness direction of the substrate body 111, the projection surface of the chip 14 is spaced apart from the first wiring layer 1311 and the third wiring layer 1321, respectively, to provide sufficient space for chip 14 mounting. The first conductive part 131 and the second conductive part 132 are electrically insulated from the first substrate 11 through the insulating layer 12, so that the first substrate 11 is thermally and electrically separated. The chip 14 is connected to the first substrate 11, and the first substrate 11 forms a direct-down heat conduction structure, which further increases the thermal conductivity of the light-emitting element, so that the semiconductor device formed by mounting has better heat dissipation performance.

[0104] Reference Figure 4 The first substrate 11 further includes a thermally conductive layer 113, which is connected to the first surface of the substrate body 111. The third surface of the chip 14 is connected to the side of the thermally conductive layer 113 away from the substrate body 111. By providing the thermally conductive layer 113 between the chip 14 and the substrate body 111, the surface of the thermally conductive layer 113 and the surface of the conductive portion 13 can be made to be nearly flat, which helps to improve the heat dissipation effect of the device. Viewed from above along the thickness direction of the substrate body 111, the area of ​​the projected surface of the thermally conductive layer 113 is smaller than the area of ​​the first surface, so that a first groove 115 is formed between the side of the thermally conductive layer 113 and the substrate body 111. The insulating layer 12 covers the bottom surface of the first groove 115, and the first wiring layer 1311 and the third wiring layer 1321 are located on the insulating layer 12 within the first groove 115. Viewed from above along the thickness direction of the substrate body 111, the projected surface of the chip 14 is located within the projected surface of the thermally conductive layer 113, which can provide sufficient mounting space for the chip 14 and ensure the heat conduction effect of the chip 14.

[0105] The thickness of the heat-conducting layer 113 can be set according to the thickness of the first wiring layer 1311, the third wiring layer 1321 and the insulating layer 12. Optionally, the sum of the thickness of the first wiring layer 1311 or the third wiring layer 1321 and the thickness of the insulating layer 12 is equal to or approximately equal to the thickness of the heat-conducting layer 113, so that the surface of the heat-conducting layer 113 and the surface of the conductive part 13 are close to a flat surface.

[0106] The thermally conductive layer 113 can be made of the same or different material as the substrate body 111. The thermally conductive layer 113 can be discretely structured from the substrate body 111. It can be formed on the surface of the substrate body 111 by deposition or other suitable methods, or the thermally conductive layer 113 can be pressed onto the substrate body 111 to fix the thermally conductive layer 113 to one side of the substrate body 111. Alternatively, the thermally conductive layer 113 can be integrally structured with the substrate body 111. This can be achieved by etching the surface of the rectangular plate-shaped first substrate 11 to form a patterned first groove 115, with the portion of the first substrate 111 within the area enclosed by the first groove 115 serving as the thermally conductive layer 113, and the remaining main structure serving as the substrate body 111. Alternatively, other suitable methods can be used to divide the first substrate 11 into the substrate body 111, the thermally conductive layer 113, and the heat dissipation layer 112.

[0107] In this embodiment, viewed from above along the thickness direction of the substrate body 111, the first wiring layer 1311 and the third wiring layer 1321 can be rectangular structures or other suitable structures. The first wiring layer 1311 at least covers the first lead hole 1141, and the third wiring layer 1321 at least covers the second lead hole 1142. The heat-conducting layer 113 is provided at intervals between the first wiring layer 1311 and the third wiring layer 1321.

[0108] Reference Figure 5 and Figure 6 The heat-conducting layer 113 can be a rectangular structure located between the first wiring layer 1311 and the third wiring layer 1321, or it can be an I-shaped structure extending to opposite sides of the first wiring layer 1311 and opposite sides of the third wiring layer 1321. Optionally, when viewed from above along the thickness direction of the substrate body 111, the projection surface of the heat-conducting layer 113 lies within the projection surface of the heat dissipation layer 112. In this embodiment, by controlling the heat-conducting layer 113 to have a large area ratio, it helps to further increase the area of ​​the heat-conducting layer 113, increase the thermal conductivity of the light-emitting element, and thus improve the heat dissipation performance of the device.

[0109] Example 3

[0110] This embodiment provides a method for fabricating a semiconductor packaging structure, referring to... Figure 7 The process includes steps S1 to S6. Using this fabrication method, any of the semiconductor packaging structures 10 described in the foregoing embodiments can be prepared, as detailed below.

[0111] Step S1: Provide a first substrate 11 and a chip 14. The first substrate 11 includes a heat dissipation layer 112 and a substrate body 111 stacked together. The substrate body 111 has a first surface and a second surface disposed opposite to each other. The heat dissipation layer 112 is connected to the second surface of the substrate body 111. The chip 14 has a fourth surface and a third surface disposed opposite to each other.

[0112] Reference Figure 8 The heat dissipation layer 112 and the substrate body 111 can be an integral structure or a discrete structure. Optionally, the first substrate 11 can be an integral structure, and the first substrate 11 can be divided into the heat dissipation layer 112 and the substrate body 111. The heat dissipation layer 112 is connected to one side of the substrate body 111, and the contact surface is used as the second surface of the substrate body 111. The material of the first substrate 11 can be copper, aluminum or other suitable metal materials.

[0113] In an optional embodiment, the first substrate 11 may further include a thermally conductive layer 113, which is connected to the first surface of the substrate body 111. The thermally conductive layer 113 and the substrate body 111 may be an integral structure or a discrete structure. Further, if the first substrate 11 is an integral structure, the first substrate 11 may be divided into a thermally conductive layer 113, a substrate body 111 and a heat dissipation layer 112 that are stacked sequentially.

[0114] Step S2: Pattern the heat dissipation layer 112 to form a second groove 116 that exposes the second surface.

[0115] Reference Figure 9 The conductive portion 13 includes a first conductive portion 131 and a second conductive portion 132. The first conductive portion 131 includes a second wiring layer 1312, and the second conductive portion 132 includes a fourth wiring layer 1322. Based on a pre-designed pattern of the second wiring layer 1312 and the fourth wiring layer 1322, the heat dissipation layer 112 is patterned and etched to form a second groove 116, which provides space for forming the second wiring layer 1312 and the fourth wiring layer 1322. The depth of the second groove 116 can be set according to the thickness of the insulating layer 12 and the thickness of either the second wiring layer 1312 or the fourth wiring layer 1322.

[0116] In an optional embodiment, the second groove 116 includes two rectangular grooves located on opposite sides of the heat dissipation layer 112, or the second groove 116 may employ other suitable structures. In the step of etching the heat dissipation layer 112, dry etching or wet etching can be used to etch the heat dissipation layer 112. For example, a chemical solution suitable for etching the heat dissipation layer 112 can be used to etch the heat dissipation layer 112 to form the patterned second groove 116.

[0117] Step S3: Form a lead hole 114 that penetrates the substrate body 111.

[0118] Similarly, refer to Figure 9 The first substrate 11 is provided with a plurality of lead holes 114. The specific number and position of the lead holes 114 can be set according to the position and number of the first electrode and the second electrode in the chip 14, so as to facilitate the electrode lead-out of the chip 14 through the conductive part 13. The first substrate 11 includes at least two lead holes 114. The lead holes 114 include one or more first lead holes 1141. The plurality of first lead holes 1141 are spaced apart from each other and formed in the second groove 116. Their positions correspond to the positions of the first electrodes. The number of first lead holes 1141 can be, for example, one, two, three or other suitable values. The lead holes 114 also include one or more second lead holes 1142. The plurality of second lead holes 1142 are spaced apart from each other and formed in the second groove 116. Their positions correspond to the positions of the second electrodes. The number of second lead holes 1142 can be, for example, one, two, three or other suitable values.

[0119] The first conductive portion 131 further includes a first conductive post 1312, and the second conductive portion 132 further includes a second conductive post 1323. In the step of forming the lead hole 114, a dry etching method or a wet etching method can be used to etch the substrate body 111 to form the lead hole 114. The size of the lead hole 114 can be set according to the thickness of the insulating layer 12 and the size of the first conductive post 1312 and the second conductive post 1323. The diameter of the lead hole 114 can be 30μm to 100μm. Specifically, the diameter of the lead hole 114 can be, for example, 30μm, 50μm, 80μm, 100μm or other suitable sizes. Optionally, the diameter of the lead hole 114 is 30μm to 50μm.

[0120] In an optional embodiment, refer to Figure 8 and Figure 10 The first substrate 11 further includes a thermally conductive layer 113, which is connected to the first surface of the substrate body 111. Before performing step S3, the following steps are also included: patterning and etching the thermally conductive layer 113 to form a first groove 115 that exposes the first surface, for providing space for forming the third wiring layer 1321 and the fourth wiring layer 1322.

[0121] Specifically, the conductive portion 13 includes a first conductive portion 131 and a second conductive portion 132. The first conductive portion 131 further includes a first wiring layer 1311, and the second conductive portion 132 further includes a third wiring layer 1321. Based on a pre-designed pattern of the first wiring layer 1311 and the third wiring layer 1321, the thermally conductive layer 113 is patterned by etching to form a first groove 115, providing space for the formation of the first wiring layer 1311 and the third wiring layer 1321. The depth of the first groove 115 can be set according to the thickness of the insulating layer 12 and the thickness of either the first wiring layer 1311 or the third wiring layer 1321. In the step of etching the thermally conductive layer 113, dry etching or wet etching can be used to pattern the thermally conductive layer 113. For example, a chemical solution suitable for etching the thermally conductive layer 113 can be used to etch the thermally conductive layer 113 to form the patterned first groove 115.

[0122] Step S4: An insulating layer 12 is formed on the surface of the substrate body 111. The insulating layer 12 covers the sidewall of the lead hole 114, the bottom surface of the second groove 116, and at least part of the first surface.

[0123] The insulating layer 12 can be made of organic resin, aluminum oxide, ceramic filler or other suitable material. It can be formed on the surface of the substrate body 111 by coating, deposition or other suitable methods, and the insulating layer 12 covers the sidewall of the lead hole 114, the bottom surface of the second groove 116 and at least part of the first surface.

[0124] Specifically, refer to Figure 11 and Figure 12 When the second electrode of chip 14 is located on its third surface, the insulating layer 12 completely covers the first surface. When both the first and second electrodes of chip 14 are located on its fourth surface, the insulating layer 12 covers the bottom surface of the first groove 115. The thickness of the insulating layer 12 can be set according to actual needs. For example, the thickness of the insulating layer 12 can be 10μm, 12μm, 15μm, or any value between the above endpoints or other suitable values.

[0125] Step S5: A conductive portion 13 is formed on the insulating layer 12. The conductive portion 13 fills the lead hole 114 and is spaced apart from the first substrate 11.

[0126] Reference Figure 13 and Figure 14The first conductive portion 131 includes a first wiring layer 1311, a second wiring layer 1312, and a first conductive post 1312; the second conductive portion 132 includes a third wiring layer 1321, a fourth wiring layer 1322, and a second conductive post 1323; the lead hole 114 includes a first lead hole 1141 and a second lead hole 1142; the step of forming the conductive portion 13 on the insulating layer 12 includes: forming a first conductive post 1312 filling the first lead hole 1141 and a second conductive post 132 filling the second lead hole 1142, respectively. 3; A second wiring layer 1312 and a fourth wiring layer 1322 are formed on the insulating layer 12 in the second groove 116, and the second wiring layer 1312 covers the first lead hole 1141 and the fourth wiring layer 1322 covers the second lead hole 1142; A first wiring layer 1311 and a third wiring layer 1321 are formed on the insulating layer 12 on the side where the first surface of the substrate body 111 is located, and the first wiring layer 1311 covers the first lead hole 1141 and the third wiring layer 1321 covers the second lead hole 1142.

[0127] The first wiring layers 1311 to the fourth wiring layers 1322 can be formed by deposition, coating, or other suitable methods, or the pre-formed first wiring layers 1311 to the fourth wiring layers 1322 can be laminated onto the surface of the substrate body 111 to form the first wiring layers 1311 to the fourth wiring layers 1322. Specifically, the first conductive pillar 1312 and the second conductive pillar 1323 can be formed, for example, by deposition or other suitable processes, or by laminating copper foil onto the surface of the substrate body 111 to form the first wiring layers 1311 to the fourth wiring layers 1322.

[0128] In an optional embodiment, refer to Figure 14 The second electrode is located on the third surface of the chip 14. The step of forming a conductive portion 13 on the insulating layer 12 includes: forming a first wiring layer 1311 and a third wiring layer 1321 on the insulating layer 12 in the first groove 115, and making the first wiring layer 1311 cover the first lead hole 1141 and the third wiring layer 1321 cover the second lead hole 1142.

[0129] Step S6: Connect the third surface of the chip 14 to the first substrate 11 or the conductive part 13.

[0130] In an optional embodiment, refer to Figure 2The chip 14 includes a first electrode 141 and a second electrode 142. The first electrode 141 is located on the fourth surface of the chip 14, and the second electrode 142 is located on the third surface of the chip 14. The conductive portion 13 includes a first conductive portion 131 and a second conductive portion 132. The second conductive portion 132 includes a third wiring layer 1321. The third wiring layer 1321 is formed on the insulating layer 12 on the side where the first surface of the substrate body 111 is located. Step S6 includes connecting the third surface of the chip 14 to the third wiring layer 1321 and electrically connecting the first electrode 141 to the first conductive portion 131.

[0131] Furthermore, viewed from above along the thickness direction of the substrate body 111, the area of ​​the third wiring layer 1321 is greater than or equal to the area of ​​the projected surface of the chip 14. The third surface of the chip 14 is connected to the third wiring layer 1321 to fix the chip 14 on the first substrate 11, so that the second electrode of the chip 14 is electrically connected to the third wiring layer 1321. Wires are used to connect to the first electrode and the first wiring layer 1311 respectively, so that the first electrode of the chip 14 is electrically connected to the first wiring layer 1311.

[0132] In an optional embodiment, refer to Figure 4 The chip 14 includes a first electrode 141 and a second electrode 142, both of which are located on the fourth surface of the chip 14. The conductive part 13 includes a first conductive part 131 and a second conductive part 132. The first substrate 11 also includes a thermally conductive layer 113. Step S6 includes: fixing the chip 14 to the thermally conductive layer 113; electrically connecting the first electrode 141 to the first conductive part 131 and the second electrode 142 to the second conductive part 132.

[0133] Furthermore, when viewed from above along the thickness direction of the substrate body 111, the area of ​​the thermally conductive layer 113 is greater than or equal to the area of ​​the projected surface of the chip 14. The third surface of the chip 14 is connected to the thermally conductive layer 113 to fix the chip 14 on the first substrate 11. The first electrode and the first wiring layer 1311 are connected by wires, and the second electrode and the third wiring layer 1321 are connected to make the chip 14 electrically connected to the conductive part 13.

[0134] The fabrication method of this embodiment is used to prepare any of the semiconductor packaging structures in this application. Therefore, the fabrication method of this embodiment also has the beneficial effects of the foregoing embodiments.

[0135] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify, alter, or combine the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: The first substrate includes a substrate body and a heat dissipation layer. The substrate body has a first surface and a second surface disposed opposite to each other. The heat dissipation layer is connected to the second surface of the substrate body. When viewed from above along the thickness direction of the substrate body, the area of ​​the projected surface of the heat dissipation layer is smaller than the area of ​​the second surface, so that a second groove is formed between the side of the heat dissipation layer and the substrate body. A lead hole penetrating the substrate body is provided in the second groove. An insulating layer covers the sidewall of the lead hole, the bottom surface of the second groove, and at least a portion of the first surface; A conductive portion is formed on the insulating layer and filled into the lead hole, wherein the conductive portion and the first substrate are spaced apart from each other; A chip having a third surface, the third surface of the chip being connected to the first substrate or the conductive portion; When viewed from above along the thickness direction of the substrate body, the ratio of the area of ​​the chip to the area of ​​the projected surface of the substrate body is greater than or equal to 20%.

2. The semiconductor packaging structure according to claim 1, characterized in that, The chip includes a first electrode and a second electrode, the lead hole includes a first lead hole and a second lead hole, the conductive portion includes a first conductive portion and a second conductive portion disposed at intervals from each other, the first conductive portion is formed on the insulating layer and fills the first lead hole, the second conductive portion is formed on the insulating layer and fills the second lead hole, the first electrode is connected to the first conductive portion, and the second electrode is connected to the second conductive portion.

3. The semiconductor packaging structure according to claim 2, characterized in that, The first conductive portion includes a first wiring layer, a second wiring layer, and a first conductive pillar. The first conductive pillar fills the first lead hole. The first wiring layer is located on an insulating layer on the side where the first surface of the substrate body is located and covers the first lead hole. The second wiring layer is located on an insulating layer on the side where the second surface of the substrate body is located and covers the first lead hole. The second conductive portion includes a third wiring layer, a fourth wiring layer, and a second conductive pillar. The second conductive pillar fills the second lead hole. The third wiring layer is located on an insulating layer on the side of the first surface of the substrate body and covers the second lead hole. The fourth wiring layer is located on an insulating layer on the side of the second surface of the substrate body and covers the second lead hole.

4. The semiconductor packaging structure according to claim 3, characterized in that, The second electrode is located on the third surface of the chip. When viewed from above along the thickness direction of the substrate body, the projection surface of the chip is located within the projection surface of the third wiring layer, and the third surface of the chip is connected to the third wiring layer.

5. The semiconductor packaging structure according to claim 4, characterized in that, Viewed from above along the thickness direction of the substrate body, the projection surface of the second wiring layer is located within the projection surface of the first wiring layer, and the projection surface of the first wiring layer has a U-shaped structure. The projection surfaces of the third wiring layer and the chip are both located within the U-shaped structure of the projection surface of the first wiring layer.

6. The semiconductor packaging structure according to claim 3, characterized in that, The chip has a fourth surface on the side away from the first substrate. The first electrode and the second electrode are both located on the fourth surface of the chip. The insulating layer also has a first opening that exposes the first surface. The third surface of the chip is connected to the first substrate through the first opening. When viewed from above along the thickness direction of the substrate body, the projection surface of the chip is spaced apart from the first wiring layer and the third wiring layer, respectively.

7. The semiconductor packaging structure according to claim 6, characterized in that, The first substrate further includes a thermally conductive layer connected to a first surface of the substrate body. The third surface of the chip is connected to the side of the thermally conductive layer away from the substrate body. Viewed from above along the thickness direction of the substrate body, the projection surface of the chip is located within the projection surface of the thermally conductive layer, and the area of ​​the projection surface of the thermally conductive layer is smaller than the area of ​​the first surface, so that a first groove is formed between the side of the thermally conductive layer and the substrate body. The insulating layer covers the bottom surface of the first groove, and the first wiring layer and the third wiring layer are located on the insulating layer within the first groove.

8. The semiconductor packaging structure according to claim 1, characterized in that, Viewed from above along the thickness direction of the substrate body, the ratio of the area of ​​the heat dissipation layer to the area of ​​the second surface is greater than or equal to 40%.

9. The semiconductor packaging structure according to claim 8, characterized in that, Viewed from above along the thickness direction of the substrate body, the ratio of the area of ​​the heat dissipation layer to the area of ​​the second surface is 60% to 90%.

10. The semiconductor packaging structure according to claim 1, characterized in that, Viewed from above along the thickness direction of the substrate body, the ratio of the area of ​​the chip to the area of ​​the projected surface of the substrate body is 40% to 90%.

11. The semiconductor packaging structure according to claim 1, characterized in that, Viewed from above along the thickness direction of the substrate body, the projection surface of the chip is located within the projection surface of the heat dissipation layer.

12. A method for fabricating a semiconductor package structure, characterized in that, Includes the following steps: A first substrate and a chip are provided. The first substrate includes a heat dissipation layer and a substrate body stacked together. The substrate body has a first surface and a second surface disposed opposite to each other. The heat dissipation layer is connected to the second surface of the substrate body. The chip has a fourth surface and a third surface disposed opposite to each other. The heat dissipation layer is patterned and etched to form a second groove that exposes the second surface; A lead hole is formed that penetrates the substrate body; An insulating layer is formed on the surface of the substrate body, the insulating layer covering the sidewall of the lead hole, the bottom surface of the second groove, and at least a portion of the first surface; A conductive portion is formed on the insulating layer, the conductive portion fills the lead hole, and is spaced apart from the first substrate; The third surface of the chip is connected to the first substrate or the conductive part.

13. The method for fabricating a semiconductor packaging structure according to claim 12, characterized in that, The chip includes a first electrode and a second electrode, the first electrode being located on the fourth surface of the chip and the second electrode being located on the third surface of the chip. The conductive portion includes a first conductive portion and a second conductive portion, the second conductive portion including a third wiring layer, the third wiring layer being formed on an insulating layer on the side of the first surface of the substrate body. The step of connecting the third surface of the chip to the first substrate or the conductive portion includes: The third surface of the chip is fixedly connected to the third wiring layer, and the first electrode is electrically connected to the first conductive part.

14. The method for fabricating a semiconductor packaging structure according to claim 12, characterized in that, The first substrate further includes a thermally conductive layer connected to a first surface of the substrate body; prior to forming a through-hole in the substrate body, the method further includes the following steps: The thermally conductive layer is patterned and etched to form a first groove that exposes the first surface.

15. The method for fabricating a semiconductor packaging structure according to claim 14, characterized in that, The chip includes a first electrode and a second electrode, both of which are located on the fourth surface of the chip. The conductive portion includes a first conductive portion and a second conductive portion. The step of connecting the third surface of the chip to the first substrate or the conductive portion includes: The chip is fixedly connected to the thermal conductive layer; The first electrode is electrically connected to the first conductive part, and the second electrode is electrically connected to the second conductive part.

16. A semiconductor device, characterized in that, The device includes a second substrate, a bonding layer, and several semiconductor package structures as described in any one of claims 1 to 11, wherein the bonding layer is located between the second substrate and the semiconductor package structures to connect the several semiconductor package structures to the second substrate.

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