Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; an electrode portion disposed on the insulating layer; and a surface treatment part which is arranged on the electrode part. The electrode portion includes: a first pad disposed on the insulating layer; and a second pad disposed on the insulating layer and spaced apart from the first pad in a horizontal direction. The surface treatment portion includes: a first surface layer disposed to cover a portion of a top surface of the first pad; and a second surface layer disposed to surround a top surface and a side surface of the second pad.

Description

Technical Field

[0001] The embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Technology

[0002] The miniaturization, weight reduction, and integration of electronic components are accelerating, resulting in finer linewidths in circuits. In particular, as semiconductor chip design rules are integrated at the nanometer scale, the linewidths of the circuitry on the packaging substrate or printed circuit board (PCB) on which the semiconductor chip is mounted are refined to a few micrometers or smaller.

[0003] Various processes have been proposed to increase the circuit density of PCBs, i.e., to minimize the linewidth of the circuits. Semi-additive process (SAP) methods and improved semi-additive process (MSAP) have been proposed to prevent linewidth loss during the etching step that patterns the circuits after copper plating.

[0004] Subsequently, to achieve finer circuit patterns, the prior art uses the embedded trace substrate (hereinafter referred to as 'ETS') method, which embeds copper foil into an insulating layer. The ETS method fabricates copper circuits in an embedded form within the insulating layer, rather than forming copper circuits on the surface of the insulating layer, and therefore there is no circuit loss due to etching, which is beneficial for refining circuit spacing.

[0005] In addition, these circuit boards include bumps for mounting semiconductor devices or connecting to an external substrate.

[0006] Traditional circuit boards form bumps by electroplating on the topmost pad portion. For this purpose, a seed layer for electroplating the bumps is provided between the pad portion and the bump portion.

[0007] However, during the process of forming and / or removing the seed layer for electroplating bumps, conventional circuit boards may suffer damage to the protective layer and contamination of the circuit board surface.

[0008] Furthermore, since the bump protrudes from the pad when the seed layer is between the bump and the pad, conventional circuit boards have limitations in ensuring adhesion between the bump and the pad, and in some cases, there are reliability issues with the bump peeling off from the pad. Summary of the Invention

[0009] [Technical Issues]

[0010] The embodiments provide a circuit board with a novel structure and a semiconductor package including the circuit board.

[0011] Furthermore, this embodiment provides a circuit board having a plurality of highly uniform bump portions and a semiconductor package including the circuit board.

[0012] Furthermore, this embodiment provides a circuit board with improved adhesion between the pad portion and the bump portion, and a semiconductor package including the circuit board.

[0013] The technical problems to be solved by the proposed embodiments are not limited to those described above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description of the proposed embodiments.

[0014] [Technical Solution]

[0015] A circuit board according to an embodiment includes: an insulating layer; an electrode portion disposed on the insulating layer; and a surface treatment portion disposed on the electrode portion, wherein the electrode portion includes: a first pad disposed on the insulating layer; and a second pad disposed on the insulating layer and spaced apart from the first pad in a horizontal direction, wherein the surface treatment portion includes: a first surface layer configured to cover a portion of the upper surface of the first pad; and a second surface layer configured to surround the upper surface and side surface of the second pad.

[0016] Furthermore, the electrode portion further includes: a third pad disposed on the insulating layer and spaced apart from the first pad and the second pad in the horizontal direction; and a bump portion disposed on the third pad, wherein the surface treatment portion further includes a third surface layer configured as a side surface surrounding the bump portion.

[0017] Furthermore, the first surface layer and the second surface layer comprise the same material.

[0018] Furthermore, the third surface layer comprises a material different from the materials of the first surface layer and the second surface layer.

[0019] In addition, the first surface layer and the second surface layer are electroless nickel immersion gold (ENIG) layers or electroless nickel immersion gold (ENEPIG) layers, and the third surface layer is an organic solderability protectant (OSP) layer.

[0020] Furthermore, the third surface layer does not contact the third pad.

[0021] Furthermore, the third pad is provided in a plurality of circumferential directions along the upper surface of the insulating layer and is disposed in an outer region of the upper surface of the insulating layer adjacent to the side surface of the insulating layer, while the first pad and the second pad are disposed in an inner region of the upper surface of the insulating layer other than the outer region.

[0022] Furthermore, the circuit board further includes a protective layer disposed on the insulating layer, wherein the protective layer includes a first through-hole that overlaps with the first pad in the vertical direction, a second through-hole that overlaps with the second pad in the vertical direction, and a third through-hole that overlaps with the third pad in the vertical direction, and at least one of the first through-hole to the third through-hole has a width in the horizontal direction that is different from the width of at least one other through-hole in the horizontal direction.

[0023] Furthermore, the width of the first through-hole in the horizontal direction is smaller than the width of the first pad in the horizontal direction, and the width of the second through-hole in the horizontal direction is larger than the width of the second pad in the horizontal direction.

[0024] Furthermore, the width of the third through hole in the horizontal direction is smaller than the width of the third pad in the horizontal direction.

[0025] Furthermore, the width of the protrusion in the horizontal direction is smaller than the width of the third through hole in the horizontal direction, and the inner wall of the third through hole does not contact the protrusion.

[0026] Furthermore, the semiconductor package further includes a conductive bonding portion disposed between the third pad and the bump portion.

[0027] Furthermore, the conductive bonding portion comprises the same material as the first surface layer and the second surface layer.

[0028] Furthermore, the conductive bonding portion is placed flat on the third pad, and the bump portion does not overlap with the conductive bonding portion in the horizontal direction.

[0029] Furthermore, the conductive bonding portion includes solder, and the conductive bonding portion includes: a flat portion disposed between the third pad and the bump portion; and an extension portion extending from the flat portion and disposed between the inner wall of the third through hole and the side surface of the bump portion.

[0030] Furthermore, the upper surface of the extension includes a convex surface, and at least a portion of the third surface layer is positioned to overlap with and cover the convex surface of the extension in the horizontal direction.

[0031] Meanwhile, the semiconductor package according to the embodiment includes the circuit board described above, and further includes semiconductor devices disposed on the first pad and the second pad.

[0032] Furthermore, the semiconductor package further includes a motherboard disposed on the bump portion.

[0033] Furthermore, the semiconductor package further includes a molding member for molding the semiconductor device and the bump portion, wherein the molding member contacts the third surface layer but does not contact the bump portion.

[0034] Meanwhile, the semiconductor package according to the embodiment includes: an insulating layer; an electrode portion disposed on the insulating layer; and a surface treatment portion disposed on the electrode portion, wherein the electrode portion includes: a first pad to a third pad disposed on the insulating layer and spaced apart from each other in a horizontal direction; and a bump portion disposed on the third pad; and the surface treatment portion includes: a first surface layer configured to cover a portion of the upper surface of the first pad; a second surface layer configured to surround the upper surface and side surface of the second pad; and a third surface layer configured to surround the side surface of the bump portion; wherein the third pad is disposed in a plurality of outer regions adjacent to the side surface of the upper surface of the insulating layer along the circumferential direction of the upper surface of the insulating layer, and the first pad and the second pad are disposed in an inner region of the upper surface of the insulating layer other than the outer regions.

[0035] [Beneficial Effects]

[0036] The circuit board and semiconductor package including the circuit board in this embodiment include an insulating layer, an electrode portion disposed on the insulating layer, and a surface treatment portion disposed on the surface of the electrode portion. Furthermore, the electrode portion includes a plurality of pads. The plurality of pads includes a first pad and a second pad connected to a semiconductor device. Additionally, the plurality of pads includes a third pad that is horizontally spaced from the first and second pads and connected to the motherboard. Furthermore, the electrode portion includes a bump portion disposed on the third pad. The surface treatment portion includes a first surface layer disposed on the first pad, a second surface layer disposed on the second pad, and a third surface layer disposed on the bump portion. The first and second surface layers are electroless nickel immersion gold (ENIG) layers or electroless nickel immersion gold (ENEPIG) layers, and the third surface layer is an organic solderability protectant (OSP) layer.

[0037] At this point, the third surface layer contacts the molding member of the molded semiconductor device. The third surface layer is placed on the side surface of the bump and may not contact conductive adhesives such as solder. Therefore, this embodiment allows a third surface layer to be provided on the surface of the bump using a relatively low-cost OSP method. Thus, this embodiment can reduce the unit price of the semiconductor package. Furthermore, this embodiment allows for the provision of a third surface layer on the side surface of the bump to protect the bump from contaminants such as external moisture or particles that may be exposed during the semiconductor package manufacturing process, and can address reliability issues such as surface corrosion of the bump.

[0038] Furthermore, this embodiment allows a third surface layer to be placed on the surface of the bump portion, thereby improving adhesion to the molding member. For example, the adhesion between the molding member and the organic third surface layer is higher than that between the molding member and the bump portion, thereby stably protecting the bump portion and the semiconductor device through the molding member.

[0039] Furthermore, the first and second surface layers can improve processability during the mounting of semiconductor devices, thereby allowing the semiconductor devices to be stably realized on the circuit board and thus allowing the semiconductor devices to operate stably.

[0040] Furthermore, the insulating layer includes an overlapping region that overlaps with the semiconductor device in the vertical direction, a first pad and a second pad are placed on the overlapping region, and a plurality of third pads are configured to surround the exterior of the overlapping region. For example, the plurality of third pads are arranged along the circumferential direction of the overlapping region, thereby ensuring the rigidity of the outer region of the circuit board. For example, the bumps, in addition to serving as pillars for attaching the motherboard to the circuit board, can also be used to prevent significant warping of the semiconductor package in a particular direction. Furthermore, embodiments allow the circuit board and the motherboard to be coupled to each other via the bumps, thereby further improving the heat dissipation characteristics of the semiconductor package.

[0041] In addition, the bump portion can be attached to or bonded to a third pad. Here, "attached" or "bonded" can have a different meaning than "formed" through the plating process.

[0042] For example, when a bump is formed by electroplating on a third pad, a seed layer for the bump is provided between the bump and the third pad. Therefore, the comparative example requires a process for forming the seed layer for plating the bump and a process for removing the seed layer by etching, which complicates the product process and may reduce product yield.

[0043] In contrast, the embodiment forms bumps on a separate support substrate and attaches or bonds the bumps formed on the support substrate to a third pad on the circuit board. Therefore, the embodiment can improve the physical and / or electrical reliability of the bumps, thereby enhancing the product reliability of the semiconductor package.

[0044] For example, instead of forming the bump by electroplating on the third pad, the embodiment attaches or bonds the bump formed on a separate support substrate to the third pad. For this purpose, a conductive bonding portion is placed between the third pad and the bump. The conductive bonding portion can be distinguished from the electroless copper plating layer and can provide bonding strength that allows the bump to be stably attached or bonded to the third pad.

[0045] Therefore, the embodiment can remove the electroless copper plating layer that should be disposed between the third pad and the bump, and thus can improve the adhesion between the third pad and the bump. For example, the electroless copper plating layer can have a porous structure, so the adhesion strength to the protective layer can be lower than the adhesion strength of the conductive joint in the embodiment.

[0046] In contrast, compared to electroless copper plating, the conductive bonding portion of this embodiment can have excellent strength, high durability and relatively high adhesion to the protective layer.

[0047] Therefore, this embodiment can improve the adhesion between the conductive bonding portion and the third pad, thereby improving physical reliability by solving the problem of the conductive bonding portion peeling off from the third pad. Furthermore, this embodiment can minimize the transmission loss of signals transmitted through the third pad and the bump portion by improving the adhesion between the third pad and the bump portion, thereby improving communication characteristics.

[0048] Furthermore, in this embodiment, bumps can be formed on a separate support substrate, thereby ensuring that multiple bumps have the same height, which allows the motherboard to be stably attached to the bumps.

[0049] For example, when electroplating is performed on a third pad to form multiple bumps, these bumps may have different heights due to plating variations, thus requiring a polishing process to equalize their heights. In this case, the polishing process can be performed simultaneously with the bumps being placed on the third pad, potentially damaging the circuit board during polishing. For instance, during polishing, semiconductor devices mounted on the circuit board may be subjected to impacts, potentially causing unstable operation.

[0050] In contrast, in this embodiment, after the bumps are formed on a separate support substrate, a polishing process can be performed to make the heights of the multiple bumps equal. Therefore, this embodiment can prevent damage to the semiconductor package during the polishing process, thereby increasing product yield. Furthermore, this embodiment can perform a first polishing process on the support substrate for the bumps, and then perform a second polishing process while the bumps are placed on the third pad. In this case, the amount of polishing in the second polishing process is less than the amount of polishing in the comparative example, thus minimizing potential damage to the circuit board during the polishing process.

[0051] Furthermore, when forming bumps on the third pad by electroplating, the process of plating the bumps must be performed after the formation of the protective layer, and damage or contamination of the protective layer may occur during the process of plating the bumps. Additionally, when forming bumps on the third pad by electroplating, it may be difficult to form bumps within a width smaller than the width of the vias provided in the protective layer. For example, when forming bumps on the third pad by electroplating, the width of the bump in the area overlapping the protective layer in the horizontal direction may be the same as the width of the vias in the protective layer. Therefore, when forming bumps by electroplating on the third pad, the bumps are in contact with the protective layer, and the stress acting on the protective layer is directly transmitted to the bumps, which may lead to physical and / or electrical reliability issues.

[0052] In contrast, the embodiment performs the process of inserting and engaging the protrusion within the third through-hole, while the third through-hole is formed in the protective layer. Accordingly, this embodiment allows the width of the protrusion to be smaller than the width of the third through-hole provided in the protective layer. For example, the side surface of the protrusion can be spaced apart from the inner wall of the third through-hole in the protective layer, without contacting the inner wall of the third through-hole in the protective layer.

[0053] Therefore, this embodiment can prevent stress acting on the protective layer from being transmitted to the bump portion, thereby solving physical and / or electrical reliability problems, such as bump portion delamination from the third pad or bump portion cracking. Furthermore, this embodiment can solve problems such as contamination or damage to the protective layer that occur during the process of plating the bump portion, thereby improving the product reliability of the semiconductor package.

[0054] Furthermore, the protective layer of this embodiment includes a first through-hole that overlaps with the first pad in the vertical direction, a second through-hole that overlaps with the second pad in the vertical direction, and a third through-hole that overlaps with the third pad and the bump portion in the vertical direction. The width of the first through-hole is smaller than the width of the first pad, and the width of the second through-hole is larger than the width of the second pad. In this case, a second through-hole with a relatively large width can be provided between the first through-hole and the third through-hole. For example, the second through-hole can be positioned closer to the third through-hole than to the first through-hole. In addition, the inner wall of the second through-hole does not need to directly contact the second pad.

[0055] Therefore, this embodiment ensures that stress acting from the outside of the protective layer towards the inside of the protective layer is absorbed through the second via. For example, this embodiment prevents stress acting on the protective layer from being transmitted through the second via to the area where the first and second pads are disposed. Each of the first and second pads is a terminal pad electrically connected to a terminal of the semiconductor device. Therefore, when stress is applied to the first and second pads, an electrical open circuit may occur between the circuit board and the semiconductor device, potentially leading to electrical reliability issues in the semiconductor package. Therefore, this embodiment provides a second via in the protective layer to efficiently distribute and / or absorb stress applied to the area where the first and second pads are disposed. Thus, the semiconductor device can be stably mounted on the circuit board. Therefore, this embodiment allows the semiconductor device to operate stably, and thus improves the operational reliability of products such as semiconductor packages and servers using semiconductor packages.

[0056] Furthermore, in this embodiment, first to third vias can be provided in a first protective layer disposed on one surface of the insulating layer, thereby controlling the aperture ratio of the first protective layer. Therefore, this embodiment can prevent significant warping of the semiconductor package in a specific direction by changing the aperture ratio of the first protective layer to the second protective layer. For example, the semiconductor package may warp depending on the difference in wiring density of the electrode portions disposed in each layer of the insulating layer, and therefore, the embodiment can provide first to third vias in the first protective layer to control the aperture ratio, thereby mitigating warping caused by differences in wiring density. Attached Figure Description

[0057] Figure 1 This is a cross-sectional view showing a semiconductor package according to an embodiment.

[0058] Figure 2 It shows the placement. Figure 1 A plan view of the through-hole in the first protective layer on the insulating layer.

[0059] Figure 3 According to the first embodiment Figure 1 A cross-sectional view of region A, in which some components are omitted.

[0060] Figure 4 According to the second embodiment Figure 1 A cross-sectional view of region A, in which some components are omitted.

[0061] Figure 5 According to the third embodiment Figure 1 A cross-sectional view of region A, in which some components are omitted.

[0062] Figure 6 It includes connecting to Figure 1 A cross-sectional view of the semiconductor package of the motherboard.

[0063] Figures 7 to 17 It shows the manufacturing process in sequence. Figure 1 A cross-sectional view of the semiconductor packaging method shown. Detailed Implementation

[0064] In the following description, embodiments will be described in detail with reference to the accompanying drawings. However, the spirit and scope of the invention are not limited to the portion of the described embodiments, and it can be implemented in various other forms. Furthermore, within the spirit and scope of the invention, one or more elements of the embodiments can be selectively combined and rearranged.

[0065] Furthermore, unless otherwise explicitly defined and described, the terms used in the embodiments of this invention (including technical and scientific terms) are to be understood to have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and terms such as those defined in common dictionaries are to be interpreted as having the same meaning as their meaning in the context of the relevant field.

[0066] Furthermore, the terminology used in the embodiments of the present invention is for describing the embodiments and is not intended to limit the invention. In this specification, the singular form may also include the plural form unless specifically stated in the phrase, and when described as “at least one (or more) of A, B, and C,” it may include at least one of all combinations that can be combined among A, B, and C.

[0067] Furthermore, when describing the elements of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only to distinguish elements from other elements, and the terms are not limited to the nature, order, or sequence of the elements.

[0068] Furthermore, when an element is described as “connected,” “linked,” or “connected” to another element, it can include not only when the element is directly “connected,” “linked,” or “connected” to another element, but also when the element is “connected,” “linked,” or “connected” to another element between the element and the other element.

[0069] Furthermore, when described as being formed or placed “on top” or “below” each element, “top” or “below” can include not only when the two elements are directly connected to each other, but also when one or more other elements are formed or placed between the two elements.

[0070] Furthermore, when expressed as "up" or "down", it can include not only the upward direction but also the downward direction based on a single element.

[0071] electronic devices

[0072] Before describing the embodiments, a brief description will be given of the electronic device to which the semiconductor package of the embodiments is applied. The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to the semiconductor package of the embodiments. Various semiconductor devices may be mounted on the semiconductor package.

[0073] Semiconductor devices can include active and / or passive devices. Active devices can be semiconductor chips in the form of integrated circuits (ICs), where hundreds to millions of devices are integrated into a single semiconductor device. Semiconductor devices can be logic chips, memory chips, etc. Logic chips can be central processing units (CPUs), graphics processing units (GPUs), etc. For example, a logic chip can be an application processor (AP) chip that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc., or a chipset that includes a specific combination of those listed so far.

[0074] Memory chips can be stacked memories such as HBM. Memory chips can also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0075] In addition, the semiconductor device can be an integrated passive device (IPD). Alternatively, the semiconductor device can be a multilayer ceramic capacitor (MLCC) or a silicon-based capacitor.

[0076] On the other hand, the product group to which the semiconductor packaging of this embodiment is applied can be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package on Package), and SIP (System in Package), but is not limited thereto.

[0077] Furthermore, the electronic device can be a smartphone, personal digital assistant, digital camera, digital still camera, vehicle, high-performance server, network system, computer, monitor, tablet computer, laptop computer, netbook, television, video game, smartwatch, automobile, etc. However, the embodiments are not limited to these and can be any other electronic device that processes data in addition to these.

[0078] -Circuit Boards and Semiconductor Packaging-

[0079] Figure 1 This is a cross-sectional view showing a semiconductor package according to an embodiment. Figure 2 It shows the placement. Figure 1 A plan view of the through-hole in the first protective layer on the insulating layer. Figure 3 It is based on a first embodiment in which some components are omitted. Figure 1 A cross-sectional view of region A. Figure 4 It is based on a second embodiment in which some components are omitted. Figure 1 A cross-sectional view of region A. Figure 5 It is based on a third embodiment in which some components are omitted. Figure 1 A cross-sectional view of region A, and Figure 6 It includes connecting to Figure 1 A cross-sectional view of the semiconductor package of the motherboard.

[0080] In the following text, reference will be made to Figures 1 to 6 A circuit board and a semiconductor package including the circuit board are described according to an embodiment.

[0081] Before describing the embodiments, the semiconductor package according to the embodiments may have a double-sided molding structure, wherein semiconductor devices 220 and 250 are mounted on both sides of a circuit board, and molding members 230 and 260 are provided to mold the semiconductor devices 220 and 250 mounted on both sides of the circuit board.

[0082] refer to Figure 1 The semiconductor package includes a circuit board, connectors 210 and 240, semiconductor devices 220 and 250, and molding components 230 and 260.

[0083] The circuit board includes an insulating layer 110.

[0084] The insulating layer 110 may include an organic material with excellent processability, allowing for a slimmer substrate, and does not include reinforcing members that allow for miniaturization of electrode portions (e.g., the first electrode 140) disposed in the circuit board. For example, the insulating layer 110 of the circuit board may use ABF (Ajinomoto Build-up Film) (a product released by Ajinomoto Co., Ltd.), and may use FR-4, BT (bismaleimide triazine), PID (photographically imageable dielectric resin), BT, etc., but is not limited to these.

[0085] The insulating layer 110 can be provided in the form of multiple laminated layers. For example... Figure 1As shown, the insulating layer 110 may have a five-layer laminated structure, but is not limited thereto. For example, the insulating layer 110 may have a four-layer or fewer laminated structure, or a six-layer or more laminated structure.

[0086] In one embodiment, the multiple layers of insulating layer 110 may be formed of the same insulating material, but are not limited thereto. At least one of the multiple layers of insulating layer 110 may include an insulating material different from the material of at least the other layers.

[0087] Through the lamination structure of the insulating layer 110 described above, the circuit board of this embodiment can electrically connect semiconductor components and the motherboard.

[0088] At least one of the multiple layers of the insulating layer 110 in one embodiment may include a reinforcing member. In one embodiment, the reinforcing member may refer to glass fiber. In another embodiment, the reinforcing member may refer to GCP (glass core primer). When the reinforcing member refers to glass fiber and the insulating layer including the reinforcing member has a certain thickness, the insulating layer including the reinforcing member can be set as a core layer, thereby allowing the circuit board to be set as a core board.

[0089] Furthermore, at least one of the multiple layers of insulating layer 110 can have its rigidity increased by including reinforcing members. For example, reinforcing members can be used to prevent significant warping of the circuit board and semiconductor package in a particular direction. Therefore, warping of insulating layer 110 during the circuit board manufacturing process can be prevented, thereby improving the positional accuracy of the first electrode 140 and the second electrode 150 of the electrode portion, and further improving the alignment between the first electrode 140 and the second electrode 150 of the electrode portion. Furthermore, since the rigidity of the circuit board is ensured, semiconductor devices can be stably connected to the circuit board, thereby enabling stable operation of the semiconductor devices. Moreover, electronic products such as servers to which the semiconductor package of this embodiment is applied can operate stably, thereby improving product reliability.

[0090] In addition, the circuit board includes a protective layer. For example, the circuit board includes a first protective layer 120 disposed on the insulating layer 110. In addition, the circuit board includes a second protective layer 130 disposed below the insulating layer 110.

[0091] at this time, Figure 1 The semiconductor package can be provided in an inverted state, and in this case, the first protective layer 120 can refer to a protective layer placed below the insulating layer 110, and the second protective layer 130 can refer to a protective layer placed on the insulating layer 110.

[0092] Since the first protective layer 120 and the second protective layer 130 do not have good wettability to solder, the first protective layer 120 and the second protective layer 130 can protect the circuit board from electrical short circuits caused by contact between solders placed on the electrode portion of the circuit board, and can protect the insulating layer 110 from external contaminants such as moisture or particles that may be exposed during the manufacturing process of the circuit board.

[0093] The first protective layer 120 may have through holes. The through holes of the first protective layer 120 may penetrate through the upper and lower surfaces of the first protective layer 120. The through holes of the first protective layer 120 may be provided while overlapping with the electrode portion disposed on the circuit board in the vertical direction.

[0094] refer to Figure 2 The first protective layer 120 may have multiple through holes. The fact that the first protective layer 120 has multiple through holes can mean that the multiple through holes are not connected to each other and are spaced apart in the horizontal direction in the first protective layer 120.

[0095] The first protective layer 120 may have first to third through holes 121, 122, and 123. For example, the first protective layer 120 may have first to third through holes 121, 122, and 123 that overlap with different electrode portions disposed on the insulating layer 110 in the vertical direction. For example, the first electrode 140 of the circuit board may include a pad portion 141 disposed on the insulating layer 110. The pad portion 141 may include first to third pads 141a, 141b, and 141c.

[0096] At this time, each of the first to third through holes 121, 122 and 123 of the first protective layer 120 can overlap with the first to third pads 141a, 141b and 141c of the pad portion 141 in the vertical direction.

[0097] The first through-hole 121 of the first protective layer 120 can overlap with the first pad 141a placed on the insulating layer 110 in the vertical direction. Furthermore, the second through-hole 122 can overlap with the second pad 141b placed on the insulating layer 110 in the vertical direction. Additionally, the third through-hole 123 can overlap with the third pad 141c and the bump portion 170 placed on the insulating layer in the vertical direction.

[0098] The third pad 141c can be disposed in the edge region of the upper surface of the insulating layer 110 adjacent to the side surface of the insulating layer 110. For example, a plurality of third pads 141c can be disposed in the edge region of the upper surface of the insulating layer 110 in the circumferential direction. Therefore, a plurality of third vias 123 can be disposed in the first protective layer 120, and each of the plurality of third vias 123 can overlap with each of the plurality of third pads 141c in the vertical direction.

[0099] The width of the third via 123 of the first protective layer 120 can be smaller than the width of the third pad 141c. The third via 123 of the first protective layer 120 can partially overlap with the upper surface of the third pad 141c in the vertical direction. Therefore, a portion of the upper surface of the third pad 141c can be covered by the first protective layer 120, and the remaining portion of the upper surface of the third pad 141c can be left uncovered by the first protective layer 120 through the third via 123.

[0100] The second through-hole 122 of the first protective layer 120 can overlap with the second pad 141b of the pad portion 141 placed on the insulating layer 110 in the vertical direction. The second pad 141b can be disposed in the inner region of the upper surface of the insulating layer 110. For example, the second pad 141b can be disposed inside the edge region where the third pad 141c is disposed. A plurality of second pads 141b can be disposed on the upper surface of the insulating layer 110. Therefore, a plurality of third through-holes 123 of the first protective layer 120 can be provided, and each of the plurality of third through-holes 123 can overlap with each of the plurality of third pads 141c in the vertical direction.

[0101] The second via 122 of the first protective layer 120 may have a width greater than the width of the second pad 141b. For example, the second via 122 of the first protective layer 120 may completely overlap with the upper surface of the second pad 141b in the vertical direction. Therefore, the upper surface of the second pad 141b may not contact the first protective layer 120. Furthermore, the inner wall of the second via 122 of the first protective layer 120 may be spaced apart from the side surface of the second pad 141b. For example, the inner wall of the second via 122 of the first protective layer 120 may be spaced apart from the side surface of the second pad 141b by a specific horizontal distance along the circumferential direction of the side surface of the second pad 141b. Therefore, each of the upper surface and side surface of the second pad 141b may not contact the first protective layer 120.

[0102] The first through-hole 121 of the first protective layer 120 can overlap with the first pad 141a of the pad portion 141 placed on the insulating layer 110 in the vertical direction. The first pad 141a can be provided in the inner region of the insulating layer 110. For example, the first pad 141a can be provided on the inner side of the edge region where the third pad 141c is placed. A plurality of first pads 141a can be provided on the upper surface of the insulating layer 110. Therefore, a plurality of first through-holes 121 can be provided in the first protective layer 120, and thus, each of the plurality of first through-holes 121 can overlap with each of the plurality of first pads 141a in the vertical direction.

[0103] The width of the first through-hole 121 of the first protective layer 120 may be smaller than the width of the first pad 141a. For example, the first through-hole 121 of the first protective layer 120 may partially overlap with the upper surface of the first pad 141a in the vertical direction. Therefore, at least a portion of the upper surface of the first pad 141a may contact the first protective layer 120, and the remaining portion of the upper surface of the first pad 141a may not contact the first protective layer 120 through the first through-hole 121.

[0104] The second protective layer 130 can be disposed on the lower surface of the insulating layer 110. In this case, the first electrode 140 may include a plurality of fourth pads 142 disposed on the lower surface of the insulating layer 110. The second protective layer 130 may have through-holes that overlap with the plurality of fourth pads 142 in the vertical direction. The width of each through-hole in the second protective layer 130 may be smaller than the width of the fourth pad 142. For example, the second protective layer 130 may only have fourth through-holes corresponding to the first through-holes 121 disposed in the first protective layer 120.

[0105] In this embodiment, the first protective layer 120 is provided with a first through-hole 121, a second through-hole 122, and a third through-hole 123, and the second protective layer 130 is provided with a fourth through-hole, thereby preventing significant warping of the circuit board and semiconductor package in a specific direction. Furthermore, this embodiment allows the first protective layer 120 to have the first through-hole 121, the second through-hole 122, and the third through-hole 123, thereby reducing and / or dispersing the stress applied to the first pad 141a and the second pad 141b, thereby improving the reliability of the electrical connection between the first pad 141a and / or the second pad 141b and the semiconductor device.

[0106] For example, due to differences in the thickness of each layer of insulating layer 110, the physical properties of each layer of insulating layer 110, and the wiring density of the first electrode 140 disposed on each layer of insulating layer 110, the circuit board can be warped into a convex or concave shape. In this case, the first protective layer 120 of this embodiment may include a first through-hole 121, a second through-hole 122, and a third through-hole 123, and the second protective layer 130 may include a fourth through-hole. Therefore, the planar area of ​​the first protective layer 120 disposed on insulating layer 110 may be different from the planar area of ​​the second protective layer 130. For example, the aperture ratio of the through-hole disposed in the first protective layer 120 may be different from the aperture ratio of the through-hole disposed in the second protective layer 130.

[0107] Therefore, this embodiment allows the stress applied by the first protective layer 120 to be different from the stress applied by the second protective layer 130, and prevents the circuit board from warping in a specific direction due to stress differences.

[0108] Furthermore, the first protective layer 120 of this embodiment may be provided with a second through hole 122 adjacent to the third through hole 123. For example, the second through hole 122 of the first protective layer 120 may be provided between the first through hole 121 and the third through hole 123. In this case, the width of the second through hole 122 is greater than the width of the second pad 141b, therefore, the first protective layer 120 may not contact the second pad 141b.

[0109] Therefore, this embodiment allows the absorption of stress acting from the outside to the inside of the first protective layer 120 through the second via 122. For example, this embodiment can prevent stress acting on the first protective layer 120 from being transmitted through the second via 122 to the areas where the first pad 141a and the second pad 141b are disposed. Here, the first pad 141a and the second pad 141b are terminal pads electrically connected to the terminals of the semiconductor device. Therefore, if stress is applied to the first pad 141a and the second pad 141b, an electrical open circuit may occur between the circuit board and the semiconductor device, which may lead to electrical reliability problems in the semiconductor package. Therefore, this embodiment can provide the second via 122 in the first protective layer 120, thereby efficiently distributing and / or absorbing stress acting on the areas where the first pad 141a and / or the second pad 141b are disposed, thereby allowing the semiconductor device to be stably mounted on the circuit board. Therefore, this embodiment can allow the semiconductor device to operate stably, thereby improving the operational reliability of products such as semiconductor packages and servers in which semiconductor packages are applied.

[0110] The circuit board includes an electrode section. Here, an electrode section can refer to a configuration comprising a metallic material. For example, an electrode section can refer to a metallic pattern that transmits electrical signals. However, this embodiment is not limited to this; the electrode section may also include a metallic pattern that does not transmit electrical signals. For example, the electrode section may include a heat dissipation pattern and / or a grounding pattern.

[0111] The electrode portion may include a first electrode 140, a second electrode 150, and a protrusion portion 170.

[0112] The first electrode 140 can be horizontally placed between multiple layers of the insulating layer 110, and can be referred to as a wiring electrode, conductor pattern, metal pattern, circuit pattern, wiring section, circuit section, etc. The second electrode 150 can pass through each of the multiple layers of the insulating layer 110 in the vertical direction, and can be referred to as a via electrode, through electrode, via section, through section, etc.

[0113] The first electrode 140 may include pads and / or traces. The pads of the first electrode 140 may refer to a wiring pattern that overlaps with and is therefore directly connected to the second electrode 150 in the vertical direction. The traces of the first electrode 140 may refer to a wiring pattern of thin and long signal lines that are connected to the pads of the first electrode 140 and thus transmit signals between multiple pads.

[0114] The first electrode 140 includes a wiring layer disposed on the outermost layer of the insulating layer 110. The wiring layer may refer to the wiring electrodes disposed on the uppermost and lowermost layers of the first electrode 140 disposed on each layer of the insulating layer 110.

[0115] The first electrode 140 may include pad portions 141 and 142. Pad portions 141 and 142 may refer to the pads of the first electrode 140 placed on the outermost layer of the circuit board. For example, one of pad portions 141 and 142 may refer to a pad placed on the uppermost layer of the circuit board, and the other may refer to a pad placed on the lowermost layer of the circuit board. For example, pad portion 141 may be referred to as the upper pad portion and may include pads connected to semiconductor devices and pads connected to the motherboard. Furthermore, pad portion 142 may be referred to as the lower pad portion and may include pads connected to semiconductor devices. However, this embodiment is not limited thereto, and the relative positions of pad portions 141 and 142 may change depending on the orientation of the circuit board and / or semiconductor package being viewed.

[0116] The pad portion 141 may include multiple pads. The pad portion 141 may include a first pad 141a, a second pad 141b, and a third pad 141c.

[0117] The first pad 141a and the second pad 141b may be disposed in the inner region of the insulating layer 110, and the third pad 141c may be disposed in the edge region of the upper surface of the insulating layer 110. The edge region may refer to the outer region of the upper surface of the insulating layer 110 adjacent to the side surface of the insulating layer 110.

[0118] Multiple third pads 141c can be disposed in the edge region of the upper surface of the insulating layer 110. For example, multiple third pads 141c can be disposed in the edge region of the upper surface of the insulating layer 110 along the circumferential direction of the upper surface of the insulating layer 110.

[0119] The first pad 141a and the second pad 141b can be disposed in the inner region of the upper surface of the insulating layer 110. For example, the first pad 141a and the second pad 141b can be disposed inside the edge region of the upper surface of the insulating layer 110 surrounded by the third pad 141c.

[0120] For example, the third pad 141c may be a pad connected to the motherboard and may have a width greater than the width of each of the first pad 141a and the second pad 141b.

[0121] In this embodiment, a third pad 141c with a relatively large width in the circumferential direction along the edge region of the upper surface of the insulating layer 110 can be provided. Therefore, this embodiment can increase the rigidity of the edge region of the circuit board and prevent significant warping of the circuit board in a particular direction. Preferably, a bump 170, which will be described later, can be placed on the third pad 141c. The bump 170 can have a thickness greater than a certain level and can be placed on the third pad 141c.

[0122] Therefore, this embodiment can prevent the circuit board from warping into a convex and / or concave shape by utilizing a relatively wide third pad 141c and a bump portion 170 placed on the third pad 141c. Thus, this embodiment allows semiconductor devices to be stably mounted on the circuit board.

[0123] The third pad 141c can overlap with the third via 123 of the first protective layer 120 in the vertical direction. The width of the third pad 141c can be greater than the width of the third via 123. Therefore, a portion of the upper surface of the third pad 141c can be covered by the first protective layer 120, and the remaining portion of the upper surface of the third pad 141c can be left uncovered by the third via 121 without being covered by the first protective layer 120.

[0124] The second pad 141b may overlap with the second via 122 disposed in the first protective layer 120 in the vertical direction. The second pad 141b may be disposed in the inner region of the upper surface of the insulating layer 110. For example, the second pad 141b may be disposed inside the edge region where the third pad 141c is placed. A plurality of second pads 141b may be disposed on the upper surface of the insulating layer 110. The width of the second pad 141b may be smaller than the width of the second via 122 disposed in the first protective layer 120. Therefore, the upper surface and side surface of the second pad 141b may not be covered by the first protective layer 120.

[0125] The first pad 141a may overlap with the first via 121 disposed in the first protective layer 120 in the vertical direction. The first pad 141a may be disposed in the inner region of the upper surface of the insulating layer 110. A plurality of first pads 141a may be disposed on the upper surface of the insulating layer 110. The width of the first pad 141a may be greater than the width of the first via 121 disposed in the first protective layer 120. Therefore, at least a portion of the upper surface of the first pad 141a may contact the first protective layer 120, and the remaining portion of the upper surface of the first pad 141a may not contact the first protective layer 120.

[0126] In this embodiment, a second pad 141b with a width smaller than that of the through-hole in the first protective layer 120 can be included in the pad 141, thereby adjusting the planar area of ​​the first protective layer 120 to prevent stress. Furthermore, since the second pad 141b does not contact the first protective layer 120, the stress applied to the first protective layer 120 can be efficiently distributed and / or mitigated to prevent transmission to the second pad 141b and the adjacent first pad 141a. Thus, this embodiment can stably mount semiconductor devices on the first pad 141a and the second pad 141b, thereby ensuring stable operation of the semiconductor devices and further improving the operational reliability of products such as semiconductor packages and servers in which semiconductor packages are applied.

[0127] Furthermore, the electrode portion of the circuit board includes a bump portion 170 disposed on the third pad 141c. The bump portion 170 may protrude from the third pad 141c with a certain thickness. In this case, the bump portion 170 may be disposed in the edge region of the upper surface of the insulating layer 110 along the circumferential direction of the upper surface of the insulating layer 110. Therefore, this embodiment can ensure the rigidity of the circuit board and the semiconductor package by providing the bump portion 170 along the circumferential direction of the upper surface of the insulating layer 110. For example, in addition to the pillar function for attaching the motherboard to the circuit board, the bump portion 170 may also have the function of preventing the semiconductor package from warping significantly in a certain direction. In addition, the semiconductor package of this embodiment can be connected to the motherboard using the bump portion 170, thereby improving the heat dissipation characteristics of the semiconductor package. For example, due to the trend toward high integration, semiconductor packages used in products providing Internet of Things (IoT), autonomous vehicles, and high-performance servers are increasing in the number of semiconductor devices and / or the size of each semiconductor device, and therefore, the area of ​​the circuit board of the semiconductor package is also increasing. Furthermore, as the area of ​​a semiconductor package increases or the number of semiconductor devices increases, heat generation becomes more severe, necessitating a significant improvement in heat dissipation characteristics. In this context, the embodiment allows the circuit board and motherboard to be connected using bump portions 170, further improving the heat dissipation characteristics of the semiconductor package compared to conventional solder bonding methods. Moreover, this embodiment uses bump portions 170 connecting the circuit board and motherboard, thereby increasing the rigidity of the bump portions and reducing their horizontal width compared to conventional soldering. Therefore, the embodiment improves the integration level of the semiconductor package and further enhances its physical and / or electrical reliability.

[0128] At this point, the bump portion 170 can be attached or bonded to the third pad 141c. Here, "attached" or "bonded" can have a different meaning than "formed" through the plating process.

[0129] For example, a bump can be formed by electroplating on a third pad. In this case, the circuit board includes a seed layer for the bump between the bump and the third pad. Therefore, when a bump is formed by electroplating on the third pad, a process is required to form the seed layer for plating the bump, as well as a process for etching and removing the seed layer, which complicates the product process and may reduce product yield.

[0130] In an embodiment, the bump portion 170 may be formed on a separate support substrate, and the bump portion 170 formed on the support substrate may be attached to or bonded to the third pad 141c of the circuit board. Thus, the embodiment can improve the physical and / or electrical reliability of the bump portion 170, thereby enhancing the product reliability of the semiconductor package.

[0131] For example, instead of forming the bump 170 by performing an electroplating process on the third pad 141c, the embodiment attaches or bonds the bump 170, which is formed on a separate support substrate, to the third pad 141c. For this purpose, the conductive bonding portion 180 is positioned between the third pad 141c and the bump 170.

[0132] The conductive bonding portion 180 can be distinguished from the electroless copper plating layer and can provide bonding force for stably attaching or bonding the bump portion 170 to the third pad 141c.

[0133] Therefore, the embodiment can remove the chemical copper plating layer that should be provided between the third pad 141c and the bump portion 170, thereby improving the adhesion between the third pad 141c and the bump portion 170.

[0134] For example, the electroless copper plating layer can have a porous structure, so the adhesion between the first protective layer 120 and the electroless copper plating layer can be lower than the adhesion between the conductive bonding portion 180 and the first protective layer in this embodiment.

[0135] In contrast, the conductive bonding portion 180 of this embodiment has superior strength and durability compared to the electroless copper plating layer, and also exhibits relatively high adhesion to the first protective layer 120.

[0136] Therefore, this embodiment improves the adhesion between the conductive bonding portion 180 and the third pad 141c, thereby enhancing the physical reliability of the bump portion 170 peeling off from the third pad 141c. Furthermore, this embodiment minimizes the transmission loss of signals transmitted through the third pad 141c and the bump portion 170 by improving the adhesion between the third pad 141c and the bump portion 170, thereby improving communication characteristics.

[0137] Furthermore, in this embodiment, bump portions 170 can be formed on a separate support substrate, thereby ensuring that multiple bumps have the same height, thus allowing the motherboard to be stably attached to the bump portions 170.

[0138] For example, when electroplating a third pad to form multiple bumps, the bumps may have different heights due to plating variations, thus requiring a polishing process to equalize the heights of the bumps. In this case, the polishing process can be performed while the bumps are being placed on the third pad, potentially damaging the circuit board during polishing. For instance, during polishing, semiconductor devices mounted on the circuit board may be subjected to impacts, potentially causing unstable operation of the semiconductor devices.

[0139] In contrast, in this embodiment, after the bump portion 170 is formed on a separate support substrate, a polishing process can be performed to make the height of the multiple bumps equal. Therefore, this embodiment can prevent damage to the semiconductor package during the polishing process, thereby increasing product yield. Furthermore, in this embodiment, a first polishing process of the bump portion 170 can be performed on the support substrate, and then a second polishing process can be performed while the bump portion 170 is placed on the third pad 141c. In this case, the amount of polishing in the second polishing process is less than the amount of polishing in the comparative example, thus minimizing potential damage to the circuit board during the polishing process.

[0140] Furthermore, when forming bumps by electroplating on the third pad, the process of plating the bumps must be performed after the formation of the protective layer, and damage or contamination of the protective layer may occur during the process of plating the bumps. Additionally, when forming bumps by electroplating on the third pad, it may be difficult to form bumps within a width smaller than the width of the vias provided in the protective layer. For example, when forming bumps by electroplating on the third pad, the width of the bump in the area overlapping the first protective layer in the horizontal direction may be the same as the width of the vias in the first protective layer. Therefore, when forming bumps by electroplating on the third pad, the bumps contact the first protective layer, and the stress acting on the protective layer is directly transmitted to the bumps, which may lead to physical and / or electrical reliability issues.

[0141] In contrast, this embodiment performs the process of inserting and engaging the protrusion 170 within the third through-hole 123, while the third through-hole 123 is formed in the first protective layer 120. Therefore, this embodiment allows the width of the protrusion 170 to be smaller than the width of the third through-hole 123 provided in the first protective layer 120. For example, the side surface of the protrusion 170 can be spaced apart from the inner wall of the third through-hole 123 of the first protective layer 120 without contacting the inner wall of the third through-hole 123 of the first protective layer 120.

[0142] Therefore, this embodiment prevents stress acting on the first protective layer 120 from being transmitted to the bump portion 170, thereby solving physical and / or electrical reliability problems, such as delamination of the bump portion 170 from the third pad 141c or cracking of the bump portion 170. Furthermore, this embodiment solves problems that occur during the plating process of the bump portion 170, such as contamination or damage to the first protective layer 120, thereby improving the product reliability of the semiconductor package.

[0143] Furthermore, the circuit board includes a surface treatment section 160. The surface treatment section 160 can be disposed on the surface of the electrode section and can protect the surface of the electrode section from oxidation, etc.

[0144] At this time, the surface treatment section 160 may include a first surface layer 161 placed on the first pad 141a, a second surface layer 162 placed on the second pad 141b, and a third surface layer 163 placed on the bump section 170.

[0145] At this time, at least one of the first surface layer 161, the second surface layer 162 and the third surface layer 163 may include a material different from at least one of the other surface layers.

[0146] For example, this embodiment performs the surface treatment method of at least one of the first pad 141a, the second pad 141b, and the bump portion 170 in a manner different from at least one other surface treatment method.

[0147] At this point, the third surface layer 163 may include an organic material. For example, the third surface layer 163 may be an OSP (organic solderability protectant) layer. For example, the third surface layer 163 may be a surface treatment layer formed using the OSP method.

[0148] Here, the OSP method prevents copper oxidation by applying an organic material to the surface of the bump portion 170 to prevent contact between air and the copper (Cu) surface. For example, during the circuit board manufacturing process after the formation of the bump portion 170, the surface of the bump portion 170 may be exposed, leading to oxidation or damage from various contaminants. Therefore, this embodiment can place a third surface layer 163 on the surface of the bump portion 170 to prevent oxidation and / or damage to the bump portion 170 that may occur during the circuit board manufacturing process. In this case, the OSP method is also referred to as a pre-flux treatment method because the organic material applied to the surface has properties similar to flux.

[0149] The third surface layer 163 contacts the bump portion 170. At this time, the third surface layer 163 can be disposed on the side surface of the bump portion 170, thereby contacting the first molding member 230. Therefore, this embodiment allows the third surface layer 163 to protect the surface of the bump portion 170 during the formation of the bump portion 170 during the circuit board manufacturing process. Furthermore, unlike the first surface layer 161 and the second surface layer 162, the third surface layer 163 may not contact conductive adhesives such as solder. Therefore, this embodiment allows the third surface layer 163, which is relatively cheaper than the first surface layer 161 and the second surface layer 162, to be placed on the surface of the bump portion 170. Thus, this embodiment can reduce the production cost of semiconductor packaging. Furthermore, this embodiment allows the third surface layer 163 to be placed on the bump portion 170, thereby improving adhesion to the first molding member 230. For example, the adhesion between the first molding member 230 and the third surface layer 163 of the organic material is relatively higher than that between the first molding member 230 and the third surface layer 163 of the organic material, and thus the first molding member 230 can stably protect the first molding member 230 and the semiconductor device.

[0150] In contrast, the first surface layer 161 and the second surface layer 162 may comprise materials different from those of the third surface layer 163. For example, the first surface layer 161 and the second surface layer 162 may comprise metallic materials. The first surface layer 161 and the second surface layer 162 may be electroless nickel immersion gold (ENIG) layers or electroless nickel immersion gold (ENEPIG) layers.

[0151] The first surface layer 161 and the second surface layer 162 can have different shapes.

[0152] For example, the second surface layer 162 can be positioned within the second via 122 of the first protective layer 120. In this case, the second via 122 does not contact the upper and lower surfaces of the second pad 141b. Therefore, the second surface layer 162 can be provided to completely cover the upper and side surfaces of the second pad 141b.

[0153] In contrast, the first surface layer 161 is disposed within the first through-hole 121 disposed in the first protective layer 120. The upper surface of the first pad 141a partially overlaps the first through-hole 121 in the vertical direction. Therefore, the first surface layer 161 can be disposed to cover the portion of the upper surface of the first pad 141a that overlaps the first through-hole 121 in the vertical direction.

[0154] Therefore, this embodiment can improve the processability of mounting semiconductor devices using the first surface layer 161 and the second surface layer 162, allowing the semiconductor devices to be stably mounted on the circuit board, and thus allowing the semiconductor devices to operate stably.

[0155] The conductive connection portion 180 is disposed between the third pad 141c and the bump portion 170. The conductive connection portion 180 is disposed within the third through-hole 123 of the first protective layer 120. For example, the conductive connection portion 180 may be disposed on the upper surface of the third pad 141c that overlaps with the third through-hole 123 of the first protective layer 120 in the vertical direction.

[0156] The conductive joint 180 can provide bonding force between the third pad 141c and the bump 170. Furthermore, the conductive joint 180 can electrically connect the third pad 141c and the bump 170.

[0157] In one embodiment, the conductive bonding portion 180 can be formed using the same process as the first surface layer 161 or the second surface layer 162. For example, the conductive bonding portion 180 can be formed together with the first surface layer 161 and the second surface layer 162 during the formation of the first surface layer 161 and the second surface layer 162. For example, the conductive bonding portion 180 can be an electroless nickel immersion gold (ENIG) layer or an electroless nickel immersion palladium immersion gold (ENEPIG) layer. When the conductive bonding portion 180 comprises the same metal material as the first surface layer 161 or the second surface layer 162, the conductive bonding portion 180 can be disposed flatly between the third pad 141c and the bump portion 170.

[0158] In another embodiment, the conductive bonding portion 180 may include solder. For example, the conductive bonding portion 180 may be a solder layer disposed on the third pad 141c. For example, the conductive bonding portion 180 may be solder paste. For example, the conductive bonding portion 150 may include materials containing different components of solder. For example, the conductive bonding portion 150 may include at least one solder selected from the group consisting of Sn-Cu, Sn-Pb, and Sn-Ag-Cu. Furthermore, the conductive bonding portion 180 may include materials containing at least one heterogeneous component selected from Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe. However, this embodiment is not limited to these, and the conductive bonding portion 180 may be composed of solder paste comprising pure solder.

[0159] refer to Figure 3 The conductive bonding portion 180 may include the same material as the first surface layer 161 or the second surface layer 162.

[0160] Therefore, the conductive joint 180 can be disposed flatly on the third pad 141c and the bump 170. For example, the upper surface of the conductive joint 180 may not be higher than the lower surface of the bump 170.

[0161] At this time, the protrusion 170 is placed on the conductive joint 180. The width of the protrusion 170 in the horizontal direction can be smaller than the width of the third through hole 123 of the first protective layer 120. Therefore, the side surface of the protrusion 170 can be spaced apart from the inner wall of the third through hole 123 of the first protective layer 120.

[0162] The third surface layer 163 may be disposed on the surface of the bump portion 170. For example, the third surface layer 163 may be disposed on the side surface of the bump portion 170. However, during the process of manufacturing the circuit board, the third surface layer 163 may also be disposed on the upper surface of the bump portion 170, but may be selectively removed by a polishing process performed after the formation of the first molding member 230.

[0163] The third surface layer 163 may include a first portion 163-1 disposed on the side surface of the protrusion portion 170. The first portion 163-1 of the third surface layer 163 may extend along the side surface of the protrusion portion 170. The third surface layer 163 may include a second portion 163-2 bent from the first portion 163-1. The second portion 163-2 of the third surface layer 163 may extend from the first portion 163-1 and be disposed on the conductive joint portion 180. Therefore, the second portion 163-2 of the third surface layer 163 may cover the upper surface of the conductive joint portion 180, which does not overlap with the protrusion portion 170 in the vertical direction, thereby stably protecting the conductive joint portion 180. At this time, the upper surface of the second portion 163-2 of the third surface layer 163 may be positioned lower than the upper surface of the first protective layer 120. Therefore, the second portion 163-2 of the third surface layer 163 and the upper surface of the first protective layer 120 can have steps, and the first molding member 230 can be disposed on the step between the second portion 163-2 of the third surface layer 163 and the first protective layer 120. Thus, this embodiment can increase the bonding area with the first molding member 230, thereby providing more stable protection for the bump portion 170 and the semiconductor device through the first molding member 230.

[0164] refer to Figure 4 The conductive bonding portion 180 may include the same material as the first surface layer 161 or the second surface layer 162. Therefore, the conductive bonding portion 180 may be disposed flatly on the third pad 141c and the bump portion 170. For example, the upper surface of the conductive bonding portion 180 may not be higher than the lower surface of the bump portion 170.

[0165] At this time, the protrusion 170 is placed on the conductive joint 180. The width of the protrusion 170 in the horizontal direction can be smaller than the width of the third through hole 123 of the first protective layer 120. Therefore, the side surface of the protrusion 170 can be spaced apart from the inner wall of the third through hole 123 of the first protective layer 120.

[0166] The third surface layer 163a may be disposed on the surface of the bump portion 170. For example, the third surface layer 163a may be disposed on the side surface of the bump portion 170. However, during the process of manufacturing the circuit board, the third surface layer 163a may also be disposed on the upper surface of the bump portion 170, but may be selectively removed by a polishing process performed after the formation of the first molding member 230.

[0167] The third surface layer 163a may include a first portion 163-1a disposed on the side surface of the protrusion portion 170. The first portion 163-1a of the third surface layer 163a may extend along the side surface of the protrusion portion 170. The first portion 163-1a of the third surface layer 163a may be disposed along the circumferential direction of the inner wall of the third through hole 123 and may fill the gap between the third through hole 123 and the protrusion portion 170.

[0168] The third surface layer 163a may include a second portion 163-2a that is bent from the first portion 163-1a. The second portion 163-2a of the third surface layer 163a may extend from the first portion 163-1a and be placed on the first protective layer 120.

[0169] The second portion 163-2a of the third surface layer 163a can contact the first protective layer 120 and serve as an anchor to increase the adhesion between the third surface layer 163a and the first protective layer 120. Furthermore, the second portion 163-2a of the third surface layer 163a and the upper surface of the first protective layer 120 can have steps, and the first molding member 230 can be disposed on the steps between the second portion 163-2a of the third surface layer 163a and the first protective layer 120. Thus, this embodiment increases the bonding area with the first molding member 230, thereby providing more stable protection for the bump portion 170 and the semiconductor device through the first molding member 230.

[0170] refer to Figure 5 The conductive joint 180a may include solder.

[0171] Therefore, during the process of engaging the protrusion 170, the conductive joint 180a can extend upward.

[0172] For example, the conductive bonding portion 180a may include a flat portion 180a1 disposed between the third pad 141c and the bump portion 170, and an extension portion 180a2 extending from the flat portion 180a1 toward the upper surface of the first protective layer 120.

[0173] An extension 180a2 of the conductive bonding portion 180a can be disposed between the inner wall of the third through-hole 123 of the first protective layer 120 and the side surface of the protrusion portion 170. The extension 180a2 of the conductive bonding portion 180a can be configured to fill the gap between the inner wall of the third through-hole 123 of the first protective layer 120 and the side surface of the protrusion portion 170. The extension 180a2 can cover at least a portion of the side surface of the protrusion portion 170. For example, the extension 180a2 can be configured to surround at least a portion of the side surface of the protrusion portion 170 that overlaps with the inner wall of the third through-hole 123 of the first protective layer 120 in the horizontal direction. Therefore, this embodiment can further improve the bonding strength between the third pad 141c and the protrusion portion 170 through the extension 180a2 of the conductive bonding portion 180a, thereby solving the reliability problem of the protrusion portion 170 peeling off from the third pad 141c.

[0174] At this time, the upper surface of the extension portion 180a2 of the conductive joint 180a may include a convex surface. For example, the upper surface of the extension portion 180a2 of the conductive joint 180a may have a convex shape facing the upper surface of the protrusion portion 170.

[0175] The third surface layer 163b may be disposed on the surface of the protrusion portion 170. For example, the third surface layer 163b may be disposed on the side surface of the protrusion portion 170. The third surface layer 163b may include a first portion 163-1b disposed on the side surface of the protrusion portion 170. The first portion 163-1b of the third surface layer 163a may extend along the side surface of the protrusion portion 170.

[0176] The third surface layer 163b may include a second portion 163-2b that bends from the first portion 163-1b. The second portion 163-2b of the third surface layer 163b may extend outward from the first portion 163-1b. The second portion 163-2b of the third surface layer 163b may be configured to cover the convex surface of the extension portion 180a2 of the conductive bonding portion 180a. Furthermore, the second portion 163-2b of the third surface layer 163b may cover at least a portion of the upper surface of the first protective layer 120. Therefore, the second portion 163-2b of the third surface layer 163b may overlap with the extension portion 180a2 of the conductive bonding portion 180a in the horizontal direction. Thus, this embodiment can further increase the contact area between the third surface layer 163b and the conductive bonding portion 180a.

[0177] Refer again Figure 1The semiconductor package of the embodiment includes connection portions 210 and 240. For example, the semiconductor package may include a first connection portion 210 disposed on a first pad 141a and a second pad 141b. In addition, the semiconductor package may include a second connection portion 240 disposed below a fourth pad 142 disposed at the lowermost side of the circuit board.

[0178] The first connection portion 210 and the second connection portion 240 can be joined using at least one of wiring bonding, solder bonding and direct metal-to-metal bonding.

[0179] The wiring bonding method uses a conductor such as gold (Au) to electrically connect the electrode part of the circuit board to the terminal of the semiconductor device.

[0180] Solder bonding methods use materials including at least one of Sn, Ag, and Cu to electrically connect the electrode portion of a circuit board to the terminals of a semiconductor device.

[0181] Direct metal-to-metal bonding refers to a process in which heat and pressure are applied between an electrode portion and a terminal of a semiconductor device to recrystallize the electrode portion, thereby directly bonding the electrode portion and the terminal of the semiconductor device without using solder, wiring, or conductive adhesive. In this case, the first connection portion 210 and the second connection portion 240 may refer to a metal layer formed between the electrode portion and the terminal of the semiconductor device through recrystallization.

[0182] For example, the first connection portion 210 and the second connection portion 240 can be electrically connected to the electrode portion and the terminal of the semiconductor device using thermocompression bonding. Thermocompression bonding can reduce the volume of the first connection portion 210 and the second connection portion 240 and prevent short circuits between adjacent connections. Therefore, thermocompression bonding may be advantageous when the terminals and / or electrode portions of the semiconductor device have fine pitch.

[0183] In addition, the semiconductor package may include a semiconductor device disposed on the first connection portion 210 and the second connection portion 240.

[0184] For example, a semiconductor package includes a first semiconductor device 220 coupled to a first connection portion 210. The first semiconductor device 220 may include terminals 221. The terminals 221 of the first semiconductor device 220 may be electrically connected to a first pad 141a and a second pad 141b of a circuit board via the first connection portion 210. According to an embodiment, the first semiconductor device 220 may include conductive posts 222 disposed on the terminals 221, but is not limited thereto. Conductive posts 222 may be provided to separate the terminals 221 of the first semiconductor device 220 from the first pad 141a / second pad 141b at predetermined intervals in a vertical direction, thereby improving the alignment between the terminals 221 of the first semiconductor device 220 and the first pad 141a and second pad 141b.

[0185] This embodiment may include a first molding member 230. The first molding member 230 may mold a bump portion 170 and a first semiconductor device 220 on the insulating layer 110.

[0186] The upper surface of the first molding member 230 may not be higher than the upper surface of the first semiconductor device 220. For example, the upper surface of the first molding member 230 may be positioned on the same plane as the upper surface of the first semiconductor device 220. For example, the upper surface of the first semiconductor device 220 may not be covered by the first molding member 230. Therefore, this embodiment allows the first semiconductor device 220 to be exposed to the outside of the circuit board, thereby allowing heat generated from the first semiconductor device 220 to dissipate easily. Thus, this embodiment improves the heat dissipation characteristics of the semiconductor package, thereby enabling the first semiconductor device 220 to operate more stably.

[0187] The semiconductor package may include a second semiconductor device 250 disposed below the second connection portion 240. The second semiconductor device 250 may be disposed in a plurality of horizontally spaced cells on a circuit board. The terminals 251 of the second semiconductor device 250 may be electrically connected to a fourth pad 142 of the circuit board via the second connection portion 240.

[0188] The semiconductor package may include a second molding member 260. The second molding member 260 may mold a second semiconductor device 250.

[0189] In addition, refer to Figure 6 The semiconductor package may also include a third connection portion 310 disposed on the bump portion 170. In this case, at least a portion of the upper surface of the bump portion 170 may not be covered by the first molding member 230, so the third connection portion 310 may be disposed on the bump portion 170.

[0190] The third connection portion 310 may be disposed on the bump portion 170. The third connection portion 310 may be solder, but is not limited thereto. In addition, the semiconductor package may include a motherboard 320 connected to the bump portion 170 via the third connection portion 310.

[0191] Figures 7 to 17 It shows the manufacturing process in sequence. Figure 1 A cross-sectional view of the semiconductor packaging method shown.

[0192] refer to Figure 7The embodiment can perform processes for manufacturing a substrate. For example, this embodiment can perform a process of preparing a carrier plate, a process of forming a first layer of insulating layer 110 on the carrier plate, and a process of forming a first electrode 140 and a second electrode 150 on the first layer of insulating layer 110. Thereafter, the embodiment can perform a process of removing the carrier plate. Thereafter, the embodiment can repeat the process of laminating additional insulating layers on the upper and lower portions of the first layer of insulating layer 110, and the process of forming the first electrode 140 and the second electrode 150 on the additional insulating layers.

[0193] refer to Figure 8 The embodiment can perform the process of forming a protective layer. For example, the embodiment can perform the process of forming a first protective layer 120 on the uppermost layer of a plurality of insulating layers 110. Furthermore, this embodiment can perform the process of laminating a second protective layer 130 below the lowermost layer of a plurality of insulating layers 110. Thereafter, the embodiment can perform the process of forming through-holes in each of the first protective layer 120 and the second protective layer 130. For example, this embodiment can perform the process of forming a first through-hole 121, a second through-hole 122, and a third through-hole 123 that overlap with a first pad 141a, a second pad 141b, and a third pad 141c of the pad portion 141 in the first protective layer 120 in the vertical direction. Furthermore, this embodiment can perform the process of forming a fourth through-hole in the second protective layer 130 that overlaps with a fourth pad 142 in the vertical direction.

[0194] Next, the embodiment can perform the process of manufacturing the bump portion 170. At this time, the bump portion 170 can be manufactured on a separate support substrate, rather than... Figure 8 On the circuit boards manufactured in China.

[0195] refer to Figure 9 The embodiment can perform the process of fabricating a support substrate. The support substrate may include a support insulating layer CB1 and a support metal layer CB2.

[0196] refer to Figure 10 The embodiment can perform a process of forming a bump portion 170 under the support metal layer CB2. For example, the embodiment can perform a process of laminating a dry film with openings under the support metal layer CB2 and a process of forming the bump portion 170 by filling the openings of the dry film with a conductive material using the support metal layer CB2 as a seed layer.

[0197] refer to Figure 11 This embodiment can be executed via Figure 8The process of forming a conductive bonding portion 180 on the third pad 141c of the manufactured circuit board. In one embodiment, the conductive bonding portion 180 may be an electroless nickel immersion gold (ENIG) layer or an electroless nickel immersion gold (ENEPIG) layer. In another embodiment, the conductive bonding portion 180 may be solder.

[0198] refer to Figure 12 The embodiment can perform the process of bonding the circuit board and the support substrate. For example, this embodiment can perform the process of aligning the bump portion 170 provided on the support substrate and the conductive bonding portion 180 placed on the third pad 141c in the vertical direction, and using the conductive bonding portion 180 to bond the bump portion 170 to the third pad 141c.

[0199] refer to Figure 13 The embodiment can perform a process of removing the support insulating layer and support metal layer of the support substrate provided on the bump portion 170. Thus, the bump portion 170 can have a structure bonded to the conductive bonding portion 180.

[0200] refer to Figure 14 In this embodiment, the process of forming the surface treatment portion 160 can be performed. For example, the embodiment can perform the process of forming a third surface layer 163 on the upper surface and side surface of the bump portion 170. Furthermore, this embodiment can perform the process of forming a first surface layer 161 and a second surface layer 162 on the surfaces of the first pad 141a and the second pad 141b.

[0201] refer to Figure 15 This embodiment can perform the process of placing the first connection portion 210 on the first surface layer 161 and the second surface layer 162. Furthermore, this embodiment can perform the process of placing the second connection portion 240 below the fourth pad 142. Additionally, this embodiment can perform the process of mounting the first semiconductor device 220 on the first connection portion 210 and the process of mounting the second semiconductor device 250 below the second connection portion 240.

[0202] refer to Figure 16 The embodiment can perform the process of forming a first molding member 230 for molding the first semiconductor device 220 and the bump portion 170 and a second molding member 260 for molding the second semiconductor device 250.

[0203] refer to Figure 17The embodiment can perform a polishing process on the upper region of the first molding member 230. At this time, polishing of the upper region of the first molding member 230 can be performed, exposing the upper surface of the first semiconductor device 220, but is not limited thereto. Furthermore, a portion of the third surface layer 163 can be removed during the polishing process of the first molding member 230. For example, when a portion of the third surface layer 163 is removed during the polishing process of the first molding member 230, the third surface layer 163 disposed on the upper surface of the bump portion 170 can be removed; therefore, the third surface layer 163 can be disposed only on the side surface of the bump portion 170.

[0204] On the other hand, when the circuit board of the present invention with the above-described characteristics is used in IT equipment or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when the circuit board with the features of the present invention performs semiconductor packaging functions, it can safely protect semiconductor chips from external moisture or contaminants, or alternatively, it can solve problems such as leakage current, electrical short circuits between terminals, and electrical open circuits at the terminals supplied to the semiconductor chip. Furthermore, when the signal transmission function is dominant, noise problems can be solved. Thus, the circuit board with the above-described characteristics of the present invention can maintain the stable function of IT equipment or home appliances, enabling the entire product and the circuit board to which the present invention is applied to achieve functional unity or technical interlocking.

[0205] When a circuit board having the characteristics of the present invention described above is used in transportation equipment such as vehicles, the problem of signal distortion transmitted to the transportation equipment can be solved. Alternatively, the safety of the transportation equipment can be further improved by safely protecting the semiconductor chip controlling the transportation equipment relative to the outside and solving problems of leakage current or electrical short circuits between terminals or electrical open circuits at the terminals supplied to the semiconductor chip. Therefore, the transportation equipment and circuit board to which the present invention is applied can achieve functional integrity or technical interlocking with each other.

[0206] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, the features, structures, and effects shown in each embodiment can be combined or modified by those skilled in the art with respect to other embodiments. Therefore, it should be understood that content related to such combinations and modifications is included within the scope of the embodiments.

[0207] The above description has focused on the embodiments, but it is illustrative only and does not limit the embodiments. Those skilled in the art will understand that various modifications and applications not shown above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically represented in the embodiments can be modified and implemented. Furthermore, it should be understood that differences relating to these changes and applications are included within the scope of the embodiments as defined in the appended claims.

Claims

1. A circuit board, comprising: Insulating layer; An electrode portion, wherein the electrode portion is placed on the insulating layer; as well as A surface treatment section is disposed on the electrode section. The electrode portion includes: A first pad, the first pad being placed on the insulating layer; and The second pad is placed on the insulating layer and is horizontally spaced from the first pad. The surface treatment section includes: A first surface layer, wherein the first surface layer is configured to cover a portion of the upper surface of the first pad; and A second surface layer is configured to surround the upper and side surfaces of the second pad.

2. The circuit board according to claim 1, wherein, The electrode portion further includes: A third pad, which is placed on the insulating layer and spaced apart from the first and second pads in the horizontal direction; and A bump portion, wherein the bump portion is placed on the third pad. The surface treatment portion further includes a third surface layer, which is configured to surround the side surface of the protrusion portion.

3. The circuit board according to claim 2, wherein, The first surface layer and the second surface layer comprise the same material.

4. The circuit board according to claim 2, wherein, The third surface layer comprises a material different from the materials of the first surface layer and the second surface layer.

5. The circuit board according to claim 2, wherein, The first surface layer and the second surface layer are electroless nickel immersion gold (ENIG) layers or electroless nickel immersion gold (ENEPIG) layers, and The third surface layer is an organic solderability protectant (OSP) layer.

6. The circuit board according to claim 2, wherein, The third surface layer does not contact the third pad.

7. The circuit board according to claim 4, wherein, The third pads are arranged in a plurality of configurations along the circumferential direction of the upper surface of the insulating layer, and are located in the outer region of the upper surface of the insulating layer adjacent to the side surface of the insulating layer. The first pad and the second pad are disposed in the inner region of the upper surface of the insulating layer, excluding the outer region.

8. The circuit board according to claim 2, further comprising: A protective layer is placed on the insulating layer; The protective layer includes a first through-hole overlapping the first pad in the vertical direction, a second through-hole overlapping the second pad in the vertical direction, and a third through-hole overlapping the third pad in the vertical direction. Wherein, the width of at least one of the first through hole to the third through hole in the horizontal direction is different from the width of at least one other through hole in the horizontal direction.

9. The circuit board according to claim 7, wherein, The width of the first through-hole in the horizontal direction is smaller than the width of the first pad in the horizontal direction, and Wherein, the width of the second through hole in the horizontal direction is greater than the width of the second pad in the horizontal direction.

10. The circuit board according to claim 9, wherein, The width of the third through hole in the horizontal direction is smaller than the width of the third pad in the horizontal direction.

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