Readout circuit for reading out current of 10 nA and / or less, use of readout circuit and method for reading out readout circuit

Abstract

The invention relates to a readout circuit (100) for reading out a current of 10 nA or less, wherein the readout circuit arrangement (100) comprises a capacitive current amplifier (10) and a continuous time delta sigma-delta modulator (20) in current mode. The invention further relates to the use of a readout circuit and to a method for reading out a readout circuit.

Description

Technical Field

[0001] This invention relates to a readout circuit for reading currents of 10 nA or less, as well as the use of such a readout circuit and a method for reading such a readout circuit. Background Technology

[0002] Readout circuits for reading current are known from the prior art. For example, the publication of M. Bennati et al., “20.5A Sub-pA ΔΣ Current Amplifier for Single-Molecule Nanosensors”, 2009 IEEE International Solid-State Circuits Conference—Digest of Technical Papers, 2009, pp. 348-349, 349a, doi:10.1109 / ISSCC.2009.4977451, describes a readout circuit with a current of less than 150 fA at 1 kHz and room temperature. rms The background noise operation is described in the circuit concept of a voltage-controlled ΔΣ (Δ-Σ) converter. This circuit concept can be used to read out nanosensors and nanopores. The converter's circuit block in this publication includes a charge integrator followed by a CDS circuit, which helps reduce 1 / f noise and offset, and also serves as a sample-and-hold (S / H) circuit. The abbreviation CSD stands for "correlated double sampling". The preamplifier integrates the input current for 120 μs and then performs an 8 μs reset. Therefore, the CDS block has a total sampling time of 128 μs, which limits the bandwidth to approximately 4 kHz. The feedback capacitor is switched to operate at two different scales of ±200 pA and ±5 nA. After sampling the integrator output through the CDS block, the sampled value is subtracted at the end of the integration time. In summary, the input signal is thus integrated, then differentiated and sampled, resulting in a voltage output proportional to the input current. This publication discloses the separation between the so-called analog front-end device (AFE) and the voltage-to-digital converter. The AFE converts the current input to voltage via correlated double sampling (CDS). The voltage is then converted to a digital output via a voltage Σ-Δ modulator.

[0003] WO 2010 / 122293 A1 discloses an apparatus for detecting the interaction between a molecular entity and membrane proteins in a lipid bilayer. The apparatus includes an arrangement of sensor elements such that they output electrical signals dependent on the occurrence of the interaction. Furthermore, the apparatus includes a detection circuit with a detection channel that amplifies the electrical signals from the sensor elements. Providing more sensor elements than detection channels, and selectively connecting the detection channels to the sensor elements, allows for acceptable performance quality of the sensor elements due to the formation of the lipid bilayer and the presence of an acceptable number of membranes.

[0004] Current measurement becomes challenging when measuring very small currents in the pA range (a situation common in applications such as nanopores and nanosensors), because the output consists of signals in the pA range or smaller in the kHz range. To measure these values, a very low-noise front-end amplifier is typically required.

[0005] For example, the output noise of an integrator is typically sampled twice, necessitating the doubling of the noise using correlated double sampling (CDS). This usually requires the design of a signal-splitting (SH) circuit. The non-ideals of the SH circuit degrade signal quality and therefore require careful design. Summary of the Invention

[0006] Therefore, the fundamental object of the present invention is to provide an improved readout circuit for reading currents of 10 nA or less (particularly very small currents in the range of a few pA). Another object is to provide a readout circuit for reading currents of 10 nA or less (particularly very small currents in the range of a few pA) that allows for the direct digitization of (particularly very small) currents (i.e., the detected signal) without significantly increasing area or current consumption.

[0007] This objective is achieved by using the readout circuit according to claim 1, the readout circuit according to claim 24, and the method according to claim 25.

[0008] According to the proposal, the readout circuit for reading currents of 10 nA and / or less comprises a capacitive current amplifier and a continuous-time increment Σ-Δ modulator in current mode. Using the proposed readout circuit, very small currents in the pA (pi ampere) range can be read and further processed. Specifically, these very small currents in the pA range can be directly digitized. The proposed readout circuit can operate without a CDS circuit. Using the proposed readout circuit, the resets of the capacitive current amplifier and the continuous-time increment Σ-Δ modulator in current mode can be performed sequentially and separately in time, so that background noise is not digitized along with the actual signal and therefore is not output as a digital signal. This background noise is caused by the reset of the capacitive current amplifier. Since the reset of the capacitive current amplifier occurs independently of the reset of the continuous-time increment Σ-Δ modulator in time, the background noise (which is charge noise, the main component of noise) is eliminated, or is not converted into a digital signal at all. Other noise sources that will still be digitized by the proposed circuit have no dominant noise component and are therefore negligible. The proposed readout circuit can also be used for relatively large currents in the nA range. However, a specific feature of the proposed readout circuit is its suitability for detecting currents in the pA range. One advantage of the proposed circuit is that, for example, relatively small currents can be measured by eliminating noise sources (main noise sources), and therefore the proposed circuit is suitable for detecting relatively small and very small currents. In the case of large currents, the proposed circuit allows for higher resolution or a larger background noise budget when other components are used throughout the circuit.

[0009] Another aspect of the invention relates to the use of the readout circuit according to the invention in nanopore readout circuits, in digital X-ray image sensor readout circuits, in gas sensor readout circuits, or in readout circuits for electrochemical sensors. The readout circuit according to the invention can be used in many different sensor circuits to convert small or very small currents detected by the sensor into digital signals, such that the converted digital signals can be used for further evaluation.

[0010] Another aspect of the invention relates to a method for reading out a readout circuit that detects a current of 10 nA and / or less, wherein the readout circuit arrangement includes a capacitive current amplifier and a continuous-time increment Σ-Δ modulator in current mode. The method first involves amplifying an input current I on the order of 10 nA or less. in To obtain the amplified current I out Subsequently, the method includes amplifying the current I... out Convert to numeric value D out Then, further evaluation can be performed using digital values. Input current I inBased on the current detected by the sensor, the sensor is therefore positioned upstream of the readout circuit according to the invention; in other words, the readout circuit is coupled to the sensor that measures (i.e. detects) the input current. Finally, the readout circuit converts the input current into a digital value that can be used for further evaluation.

[0011] The technical teachings described in this paper enable the measurement of currents from 1 pA to 10 nA using a widely studied continuous-time increment Σ-Δ analog-to-digital converter. Specifically, a CDS (correlated double sampling) circuit is not required. Because the readout circuitry itself is simplified, the proposed readout circuitry and corresponding method are both simplified and improved. The technical teachings described in this paper provide an alternative to the widely used correlated double sampling circuitry in charge integrators for measuring input current ranges from 1 pA to 10 nA.

[0012] Of course, each aspect of the readout circuit description can also be implemented as a set of steps, and vice versa. Further details will be discussed in the context of the following diagram. Attached Figure Description

[0013] The preferred embodiments of the present invention will now be explained in detail with reference to the accompanying drawings, wherein:

[0014] Figure 1 The readout circuit according to the present invention is shown;

[0015] Figure 2 shows a known readout circuit in the prior art;

[0016] Figure 3 A more detailed description is provided based on Figure 1 The readout circuit of the present invention;

[0017] Figure 4 A schematic representation of the operating mode of the readout circuit according to the present invention is shown;

[0018] Figure 5 A schematic representation of the readout signal of the readout circuit according to the present invention is shown;

[0019] Figure 6 The simulation results show the power spectral density (PSD) and the noise in the signal band (IBN) relative to frequency when using a continuous-time increment second-order Σ-Δ modulator.

[0020] Figure 7 A schematic representation of the use of the readout circuit according to the invention when detecting current in a nanopore is shown; and

[0021] Figure 8The flowchart of a method for reading a readout circuit according to the present invention is illustrated schematically. Detailed Implementation

[0022] The following will be Figure 1 and Figures 3 to 8 The various aspects of the invention described herein are described in detail. Throughout this application, the same reference numerals refer to elements with the same or identical function, and repetition of reference numerals in all figures is not necessarily required to be interpreted again. Figure 2 illustrates a readout circuit known in the prior art to allow for... Figure 1 The readout circuit of this invention performs a direct comparison.

[0023] Figure 1 A readout circuit 100 according to the present invention is shown. The readout circuit 100 according to the present invention for reading currents of 10 nA and / or less includes a capacitor current amplifier 10 and a continuous-time increment Σ-Δ modulator 20 in current mode. In this case, current mode refers to the current operation of the continuous-time increment Σ-Δ modulator 20. As in... Figure 1 As indicated, both the capacitor current amplifier 10 and the continuous-time increment Σ-Δ modulator 20 can be reset. The capacitor current amplifier 10 is reset by the character Rst. camp The indicator, where camp represents the capacitor amplifier and rst represents reset, refers to the continuous-time increment Σ-Δ modulator 20, defined by the term Rst. ICM The indication is that ICM is a known abbreviation for incremental Σ-Δ modulator. The readout circuit 100 according to the invention for reading currents of 10 nA or less is suitable for reading very small currents of a few pA. In this case, the term "very small current" refers to a current of a few pA (picoamps). As in... Figure 1 As can be seen, the readout circuit 100 is coupled to the sensor 30. In this case, the term "coupled" includes connection via cable. Figure 1 As shown, sensor 30 can be adapted to read out a nanopore, or sensor 30 can be provided by a nanopore. In other words, the nanopore is sensor 30. This nanopore can be used to detect certain molecules. For example, in addition to the input capacitance C... in In addition, sensor 30 also has a resistor R pore Furthermore, nanopores can be thoroughly modeled as pore resistance R. pore and capacitor C in Sensor 30 is not part of the readout circuit 100, which is why sensor 30 is represented by a dashed line. From Figure 1 It can be further concluded that the capacitor current amplifier 10 of the readout circuit 100 receives the input current I. in Amplify input current I inand use it as the amplified current I out The output is sent to the continuous-time increment Σ-Δ modulator 20. Therefore, the continuous-time increment Σ-Δ modulator 20 receives the amplified current I. out and amplify current I out Convert to a digital value D for further processing out .

[0024] In this case, the capacitor current amplifier represents the preamplifier 10 or the AFE (analog front-end) device. Furthermore, the continuous-time increment Σ-Δ modulator 20 represents the analog-to-digital converter.

[0025] Figure 2 illustrates a readout circuit 100' known from the prior art, which includes an integrator 10', a CDS (correlated double sampling) stage 40', an SH (sample and hold) stage 50, and an analog-to-digital converter (ADC). According to the readout circuit 100' of Figure 2 known from the prior art, the detected current I... in It is output as a numeric value.

[0026] Figure 3 A more detailed description is provided based on Figure 1 The readout circuit 100 of the present invention. From Figure 3 It can be seen that, in addition to operational amplifier OP1, capacitor amplifier 10 also includes a first capacitor C1. First switch S1 (Rst) camp The first capacitor S1 and the operational amplifier OP11 are connected in parallel. The first switch S1 (Rst) is connected in parallel with the first capacitor C1 and the operational amplifier OP11. camp When the first switch S1 (Rst) is closed, the capacitor amplifier 10 is reset. camp When the input current I is in the off state, in Collected or scored.

[0027] Preferably, such as Figure 3 As can be seen from this, the current amplifier 10 is configured to amplify the input current I. in To provide an amplification current I at the output of the capacitor current amplifier 10. out And the continuous-time increment Σ-Δ modulator 20 is configured to receive the amplified current I. out And convert it to the numeric value D out Description: Outputs a digital value D at the output of the continuous-time increment Σ-Δ modulator 20. out To further utilize or evaluate the numerical value D out D out This corresponds to the digital current value, which in turn corresponds to the average current value of the sampling interval.

[0028] The term "configuration" should be understood as "configured to do something". The features described by the term "configuration" here are not only applicable to performing related steps / functions, but are specifically designed for this purpose.

[0029] Preferably, as in Figure 3 As can be seen from this, the capacitor current amplifier 10 is configured to respond to the first reset signal RST. camp The current amplifier is reset at this time. To initialize the reset of the capacitor current amplifier, the first switch S1(Rst) is activated. camp The first switch S1 (Rst) is closed. During the current amplifier reset, the first switch S1 (Rst) is closed. camp Therefore, it is in the closed state. In the first switch S1(Rst) camp When the circuit is closed, the feedback capacitor C1 can be reset by discharging it.

[0030] Preferably, as in Figure 3 As can be seen, the continuous time increment Σ-Δ modulator 20 is configured to perform a modulator reset upon receiving the second reset signal RSTICM. The continuous time increment Σ-Δ modulator 20 includes a second switch S2(Rst... ICM To initialize and reset the continuous-time increment Σ-Δ modulator 20, the second switch S2(Rst) ICM The second switch S2 (Rst) is closed during modulator reset. ICM The second switch S2 (Rst) is in the closed state. ICM In the closed state, the other capacitor C3 of the continuous time increment ∑-Δ modulator 20 can be reset by discharging the other capacitor C3.

[0031] First reset signal RST camp The duration 12 of the first pulse and the duration 22 of the second pulse of the second reset signal RSTICM overlap in time, such that the first pulse duration 12 and the second pulse duration 22 begin / start simultaneously at the start of the reset ICM. For example, this can be seen from... Figure 4 As learned from this, preferably, the first cycle duration of the capacitor amplifier 10 corresponds to the second cycle duration of the continuous-time increment Σ-Δ modulator 20. In other words, the two reset signals RST... camp The cycle duration is the same as RSTICM. However, the two reset signals RST... camp The first pulse duration 12 and the second pulse duration 22 of RSTICM are different. Figure 4 In the middle, the first reset signal RST camp The pulse duration is determined by T RST,CAMP The pulse duration of the second reset signal RSTICM is specified by T.RST,ICM Specify. Reset signal RST camp Both the reset signal RSTICM and the T signal have T RST,ICM +T conversion The duration of a single cycle, where T conversion Indicates the conversion time period (conversion cycle duration T) used to digitize the signal. conversion The duration of the cycle. Figure 4 In the middle, the period duration T RST,ICM It seems to be T RST,CAMP It can be twice as much, but it doesn't necessarily have to be. Figure 4 Not drawn to scale. For example, the pulse duration T of capacitor amplifier 19. RST,CAMP It can be 1 microsecond, and the pulse duration T of the incremental Σ-Δ modulator 20. RST,ICM It can be 2 microseconds. The transition time period T conversion It could be, for example, 8 microseconds. This would then result in a total period duration of 10 microseconds, and thus a sampling rate of 100 kHz.

[0032] Figure 4 A schematic representation of the operating mode of the readout circuit 100 according to the present invention when coupled to sensor 30 is shown. Figure 4 The signal amplitude as a function of time is plotted in the image. Reset signal RST camp and RST ICM These are digital signals. Therefore, their voltage levels are either low or high. The low and high voltage values ​​depend on the digital power supply voltage used. In short, units are not needed here because these are digital signals. High indicates true, and low indicates false, which is understood by those skilled in the art and therefore will not be explained further.

[0033] Preferably, the current amplifier 10 includes an output capacitor C2 and at least one feedback capacitor C1, wherein the amplified current I... out It is the input current I in The ratio is M times the value of the output capacitor C2, where M is the ratio between the output capacitor C2 and at least one feedback capacitor C1. For example, the ratio is M = 10, M = 9, or M = 11.

[0034] Preferably, the current amplifier 10 includes at least one operational amplifier OP1, wherein the current amplifier 10 is configured to use at least one operational amplifier OP1 via at least one feedback capacitor C1 to input current I. in Integrating to amplify the input current I in .See Figure 3 Then, the first switch S1(Rs) of the current amplifier 10... tcampThe first switch S1 (Rst) is in the off state, that is, during the integration of at least one operational amplifier OP1. tcamp The circuit is open. The output voltage V of at least one operational amplifier OP1 is... out,op1 Indicates the input current I in The integral. The output voltage V of at least one operational amplifier OP1. out,op1 It is also formed by differentiating the voltage from the capacitance value of the output capacitor C2. Differentiating the voltage should be understood as follows: the current flowing through the capacitor is equal to C*dv / dt! Therefore, C is the capacitance value, v is the voltage difference across the capacitor, and dv / dt refers to the time derivative of the voltage across the capacitor. This is why it is also called voltage differentiation. Therefore, the output current I... out It will be M times the input current I in , where M is the ratio between C2 and C1.

[0035] Preferably, the readout circuit 100 can be coupled to or be coupled to the sensor 30, wherein the capacitive current amplifier 10 is configured to adjust the voltage detected by the sensor 30 in the coupled case, in particular to reset it to the command voltage V. bias Sensor 30 is not necessarily part of readout circuitry 100. Since sensor 30 can be, for example, a nanopore or gas sensor or another type of sensor, sensor 30 in… Figure 1 Only dashed lines are shown in the middle. For example, it can be seen from... Figure 3 As can be seen, when coupled to the readout circuit 100, the sensor is connected to the input of the operational amplifier OP1 of the amplifier 10. This connection can be achieved via a cable or as a direct metal connection on a circuit board. Therefore, the capacitive current amplifier 10 regulates the voltage across the sensor 30 and restores it to the command voltage V. bias .

[0036] Preferably, the current amplifier 10 includes a first switch S1 (Rst) arranged in parallel with the feedback capacitor C1. camp The capacitor current amplifier 10 uses a first pulse width T RST,CAMP The first reset signal Rst camp Close the first switch S1(Rst) camp To reset. This is in, for example... Figure 4 This is illustrated schematically. Here, the first pulse width T RST,CAMP Represented over time. By closing the first switch S1(Rst) camp At least one operational amplifier OP1 restores the voltage across the feedback capacitor C1 to the command voltage V. bias This restores the voltage across the output capacitor C2 to the command voltage V. bias When combined Figures 3 to 5This can be seen from the figures in this application.

[0037] Preferably, for example from Figure 3 As can be seen, the continuous-time increment Σ-Δ modulator 20 includes at least one loop filter 21, a quantizer 24, and a digital filter 23. Here, the loop filter 21 includes at least one second feedback capacitor C3 and at least one loop filter switch S2 (RST). ICM First feedback switch S FB1 Second feedback switch S FB2 and at least one integrator INT ICM,1 The loop filter 21, particularly the loop filter 21 with the aforementioned components, is configured to receive and process the amplified current I. out At least one loop filter switch S2 (RST) ICM This corresponds to the second switch S2 (RST) mentioned earlier. ICM In the closed state, at least one loop filter switch S2(RST) ICM It is used to reset the continuous time increment ∑-Δ modulator 20.

[0038] Preferably, the loop filter 21 has a loop filter output, and the loop filter 21 is configured to provide an output voltage V at the loop filter output. HS The loop filter output is coupled to quantizer 24 to adjust the output voltage V at each clock edge of the clock signal CLK. HS Perform sampling. Figure 3 The coupling between quantizer 24 and loop filter 21 or between quantizer 24 and digital filter 23 is shown.

[0039] Preferably, the quantizer 24 has a quantizer output, and the quantizer 24 is configured to output voltage V. HS Provide feedback current I to loop filter 21 FBp I FBn In particular, it is fed back to regulate the output voltage V within a specific range. HS Preferably, this specific range corresponds to the power supply voltage range, i.e., the range of the power supply voltage of the readout circuit 100. The quantizer 24 is further configured to provide an amplified current I corresponding to the digital bit stream at the quantizer output. out .

[0040] Preferably, digital filter 23 is coupled to the quantizer output and configured to receive and filter the digital bitstream, wherein digital filter 23 is configured to output a digital value D associated with the digital bitstream after the conversion period expires. out This can be seen from Figure 3 I learned this from the middle.

[0041] Preferably, depending on the order of the continuous-time increment Σ-Δ modulator 20, the loop filter 21 includes a switchable feedback current and one or more integrators. For example, in Figure 3 In the text, only an integrator INT is represented. ICM,1 The bitstream received by quantizer 24 corresponds to the amplified current I after passing through loop filter 21. out In other words, the amplification current I at the output of capacitor amplifier 10 out The processing is performed by loop filter 21. Quantizer 24 modulates the output voltage V of loop filter 21 at each clock edge of the clock signal CLK. HS Sampling is performed. The output of quantizer 24 is based on the output voltage V. HS Activation feedback current I FBp or I FBn One of them. Therefore, the output voltage V HS The current I is regulated within a specific range, and the output bitstream of quantizer 24 represents the current I. out The bitstream is filtered by digital filter 23, and a digital output value D is generated at the end of the conversion time. out .

[0042] Preferably, the reset of the continuous time increment Σ-Δ modulator 20 can be achieved by having a second pulse width T. RST,ICM The second reset signal RSTICM is used for control, such as Figure 4 As can be seen from this. The reset continuous-time increment Σ-Δ modulator 20 includes resetting all integrators of the reset loop filter 21, resetting the digital filter 23, and by disconnecting the corresponding switch S. FB2 S FB1 To stop the feedback current I FBn,p Switch S FB2 S FB1 This is required for the normal operation of the continuous time increment Σ-Δ modulator 20.

[0043] The capacitor current amplifier 10 is configured to input the first integrator INT of the increment ∑-Δ20. ICM,1 Noisy virtual grounding and sensitive input current I in Separation. The capacitor current amplifier 10 also reduces the first integrator INT of the continuous-time increment Σ-Δ modulator 20. ICM,1 and the first feedback current I FB Noise requirements. In addition, the capacitor current amplifier 10 is configured to provide the required bias voltage to the sensor 30.

[0044] Preferably, the first reset signal RST of the current amplifier 10 campand the second reset signal RST of the continuous time increment Σ-Δ modulator 20 ICM They each have the same frequency, which defines the Nyquist sampling rate, specifically the first reset signal RST. camp The first pulse duration is 12 and the second reset signal RST ICM The second pulse duration 22 overlaps in time, causing pulse durations 12 and 22 to start simultaneously, for example, in... Figure 4 As can be seen in the document and described in detail above, it is referenced herein. The term Nyquist sampling rate is a term known to those skilled in the art and requires no further explanation.

[0045] Preferably, the readout circuit 100 is configured to perform a modulator reset promptly after the current amplifier reset, particularly with a specific delay after the current amplifier reset, wherein this specific delay is based on the settling time of the integrator 11 of at least one operational amplifier OP1. Figure 4 The specific delay is not shown due to limited representation possibilities. The specific delay is calculated based on the settling time of the integrator 11 of the capacitor amplifier 10, where the specific delay is the bandwidth BW of at least one integrator 11 of the capacitor amplifier 10. INT A function of . A specific delay time is proportional to it; delay time = 5 / BW INT ,

[0046] Among them BW INT This is the bandwidth of the integrator 11 of capacitor amplifier 10 (i.e., operational amplifier OP1), measured in rad / s. The continuous-time increment Σ-Δ modulator 20 amplifies the current I. out Converted to a bit stream, where the amplified current is independent of the initial voltage value at the feedback capacitor C1 or the output capacitor C2.

[0047] Preferably, when coupled to sensor 30, readout circuit 100 is configured to detect sensor input capacitance C of sensor 30 during current amplifier reset. in Charge noise at the current amplifier integrator. In other words, the current amplifier reset RST at the current amplifier integrator. CAMP During this period, that is, when switch S1(RST) CAMP When the circuit is switched on (i.e. closed), the sensor input capacitance C of the sensor 30 is detected. in Charge noise at the location. Switch S1(RST) CAMP It can be modeled as a resistance R on When S1(RST) is closed CAMP When ), operational amplifier OP1 operates as a transimpedance amplifier, and its feedback resistor is S1(RST). CAMP Ron The virtual ground (i.e., negative input) of operational amplifier OP1 is noisy, and the noise depends on switch S1 (RST). CAMP The resistance R on The noise and voltage noise of operational amplifier OP1. When switch S1(RST CAMP When disconnected, in capacitor C in The current noise amplitude at the negative input of operational amplifier OP1 is sampled (see...). Figure 3 In this case, the term sensor 30 refers to a device used to detect physical parameters. Physical parameters are, for example, current, magnetic field, voltage, or mechanical or electrochemical force. After the amplifier is reset by the integrator 11 of the trigger capacitor current amplifier 10, the input capacitor C... in Charge noise is detected or sampled at the location. Charge noise is controlled by the first switch S1 (RST). CAMP The charge noise is caused by the thermal noise of the on-resistance and the input-dependent voltage noise of the operational amplifier OP1. This charge noise also depends on the total input capacitance C. in .

[0048] Preferably, the readout circuit 100 is configured to first check the input capacitor C. in The accumulated charge noise is then integrated via the feedback capacitor C1. Integration occurs after the settling time of the integrator 11 of the capacitor current amplifier 10 has elapsed. The settling time corresponds to a specific delay time, and therefore can be expressed as delay time = 5 / BW. INT To calculate.

[0049] Preferably, the readout circuit 100 is configured to integrate the charge noise via the feedback capacitor C1 during the modulator reset period of the continuous-time increment Σ-Δ modulator 20. Therefore, a digital value 42 for charge noise, independent of the actual measured signal, can be ultimately obtained, such as... Figure 3 As shown. However, the digital value 42 of the charge noise is not included in the digital value 44 of the actual measured signal. In other words, the amplified charge noise is also stored in the output capacitor C2, but because the continuous-time increment Σ-Δ modulator 20′ is in a reset state during the integration of the charge noise, this charge noise will not enter the digital bit stream, and therefore will not enter the digital value D at the output of the digital filter 23. out This is because the charge noise is not transmitted through the first integrator INT of the continuous-time increment Σ-Δ modulator 20. ICM,1 Integrate using the feedback capacitor C3.

[0050] Preferably, due to the upstream capacitor current amplifier 10, at least one integrator INT of the continuous-time increment Σ-Δ modulator 20′ is included. ICM,1 Charge noise for digital value D outThe effect is reduced, especially to a negligible value. In the first integrator INT of the continuous-time incremental Σ-Δ modulator 20... ICM,1 The charge noise accumulated on the total capacitance is drawn into the digital final value D. out However, when the input is mentioned again, its effect is reduced to a negligible value due to the current amplifier.

[0051] Preferably, the readout circuit 100 is configured to input at least one integrator Int of the continuous-time increment Σ-Δ modulator 20 ICM,1 With sensor input capacitance C in Separate, wherein at least one integrator Int ICM,1 The bandwidth is independent of the capacitor. The bandwidth of the readout circuit can be 100kHz. In other words: the capacitor current amplifier 10 will input the first integrator INT of the continuous-time increment Σ-Δ modulator 20. ICM,1 With sensor capacitance C in Separation, that is, when coupled to sensor 30, with respect to the input capacitance C of sensor 30. in Separation. Sensor capacitance C in It can be very large, or it can be changed from one sensor to another. Here, the sensor capacitance C... in It is very large, if it includes up to 10 pF. Therefore, the first integrator of ∑-Δ is INT. ICM,1 The bandwidth is unaffected by the changing capacitance, which is important for the modulator's stability. Large input capacitance C in The bandwidth of integrator 11 is reduced, which in turn reduces the bandwidth of current amplifier 10. This results in integrator 11 requiring more time to stabilize after switch S1 is reset, meaning a reset signal RST is needed. camp A larger pulse width. However, stability remains unaffected.

[0052] Preferably, the corner frequency of the readout circuit 100 corresponds to the reset frequency of the current amplifier reset and the modulator reset. The total bandwidth of the readout circuit 100 depends primarily on the signal transfer function of the digital filter 23, which in turn depends on the configuration of the continuous-time increment Σ-Δ modulator 20 used. However, in all cases, the corner frequency is located at the reset frequency. This means that an analog anti-aliasing filter is not required in this case. However, this anti-aliasing filter can be implemented by using a capacitor current amplifier with a tuned bias current or by using a compensation capacitor of the tuned operational amplifier OP1 to change its transfer function.

[0053] Figure 5A schematic representation of the signal read out by the readout circuit 100 according to the present invention during operation of the readout circuit 100 is shown. The voltage signal is represented in a time stream during operation of the readout circuit. During the reset of the capacitor amplifier 10 and the continuous time increment Σ-Δ modulator 20, the first feedback switch SFB1 and the second feedback switch SFB2 are open.

[0054] Upon receiving the reset signal RST camp When, first close switch S1(RST) camp ) and S2(RST ICM ). Figure 6 The example implementation of the proposed readout circuit 100 using an incremental second-order Σ-Δ modulator 20 is shown, achieving nearly 700 fA. RMS The noise (in-band noise) in the signal band IBN is calculated by the incremental second-order Σ-Δ modulator 20 operating at a clock frequency of 20 MHz and a reset frequency of 100 kHz, corresponding to a total bandwidth of 50 kHz. The power spectral density (PSD) is calculated by first applying a digital filter in the form of a cascaded digital integrator to the two reset signals RST. camp With RST ICM The calculation is performed by filtering the bitstream between the two reset signals RST. In this case, this means using a digital filter in the form of a cascaded digital integrator to filter the two reset signals RST. ICM Between or between two reset signals RST camp The bitstream between the two is filtered. Then, the power spectral density (PSD) is calculated for the current values ​​generated from the digital filter, and the noise over the 50kHz bandwidth is integrated.

[0055] Another aspect of the invention relates to the use of the readout circuit 100 just described in a nanopore readout circuit, or in a digital X-ray image sensor readout circuit, or in a gas sensor readout circuit, or in a readout circuit for an electrochemical sensor. Figure 7 A schematic representation of the use of a readout circuit 100 according to the invention, for example, when detecting current in a nanopore 80, is shown. Figure 7 As shown, the DNA strand 82 of a DNA molecule is guided through a nanopore 80 (DNA refers to deoxyribonucleic acid), where a current in the pA range is generated. This current is detected and ultimately digitized using a readout circuit 100. The nanopore 80 itself is arranged within a lipid bilayer 84. The readout circuit 100 outputs a digital value D. out The final output digital bitstream can be further processed or evaluated by artificial intelligence (AI). Alternatively, other suitable devices can be used to perform the further evaluation instead of AI.

[0056] Another aspect of the invention relates to a method for reading out a readout circuit 100 that detects a current of 10 nA and / or less. This method 800, as... Figure 8 As shown. The readout circuit 100 described herein is used to perform this method. Here, the readout circuit 100 includes a capacitor current amplifier 10 and a continuous-time increment Σ-Δ modulator 20 in current mode. In step 810, the method includes amplifying the input current I by an order of 10 nA or less. in To obtain the amplified current I out In step 820, the amplified input current I... in Used to perform the amplification of current I out Convert to numeric value D out The numerical value D out It can be further processed, as shown, for example, by AI, such as... Figure 7 As shown.

[0057] Preferably, method 800 includes receiving a first reset signal RST. camp The time-reset capacitor current amplifier 10, and upon receiving the second reset signal RST ICM The continuous-time increment Σ-Δ modulator 20 is reset immediately after the reset capacitor current amplifier 10. The delay time described above can be between the reset capacitor current amplifier 10 and the reset continuous-time increment Σ-Δ modulator 20. Refer to the description above.

[0058] Preferably, method 800 includes adjusting the output voltage V at each clock edge of the clock signal CLK. HS Sampling is performed to adjust the output voltage V within a specific range. HS ; and / or receive and filter amplify current I out And after the conversion period expires, the filtered amplified current I will be... out Convert to numeric value D out Furthermore, method 900 preferably includes adjusting the detection voltage, specifically adjusting it to a command voltage V, while coupled to sensor 30. bias Furthermore, method 900 preferably includes, when coupled to sensor 30, performing a current amplifier reset, adjusting the sensor input capacitance C of sensor 30. in Sample charge noise at the location; and / or first at the input capacitance C of sensor 30. inThe charge noise is accumulated and then integrated via the feedback capacitor C1 of the capacitor current amplifier 10; and / or integrated via the feedback capacitor C1 during the modulator reset of the continuous time increment ∑-Δ modulator 20.

[0059] A comparison of this readout circuit 100 with known prior art, M. Bennati et al., “20.5A Sub-pAΔΣ CurrentAmplifier for Single-Molecule Nanosensors,” 2009 IEEE International Solid-State Circuits Conference—Digest of Technical Papers, 2009, pp. 348-349, 349a, doi:10.1109 / ISSCC.2009.4977451, is summarized in the table below (see below).

[0060] Bennati et al. ISSCC 2009 The readout circuit according to the present invention Bandwidth (kHz) 4 50 Noise level (fA / sqrt(Hz)) 5 3 Power consumption (mW) 23 20 Input range (pA) 200 200 <![CDATA[Chip area (mm 2 )]]> 0.5 0.5

[0061] Those skilled in the art will understand that the device features described above can also be interpreted as method steps. To avoid redundancy, detailed repetition of the above content has been omitted in the context of the proposed method 900.

[0062] The advantages of this technique are as follows: the bit stream at the output of the quantizer 24 of the continuous-time increment Σ-Δ modulator 20 represents a segment of the input current signal between two resets (see...). Figure 3 and Figure 4 Compared to time-limited current sampling with correlated double sampling (CDS), it contains more information. Furthermore, the bandwidth of the bitstream is equal to the clock frequency divided by 2. This means that rapid current changes during the transition time will affect the bitstream. For example, these rapid changes can represent characteristic molecular movements in DNA nanopore sequencing, movements that correlated double sampling would fail to detect. For instance, when used as a nanopore readout circuit, it is hoped that sequencing accuracy can be improved if the bitstream, rather than the discrete current samples generated in correlated double sampling, is used as the information source.

[0063] Other advantages include:

[0064] The separation of the reset capacitor current amplifier 10 from the continuous-time increment Σ-Δ modulator 20 eliminates KTC charge noise and noise from switch S1 (RST). camp Other offset charges, such as charge injection and clock feedthrough.

[0065] -Amplification reduces the impact on current source I FBn and I FBpThe noise requirements are reduced, and the noise requirements for the first integrator of the continuous-time increment Σ-Δ modulator 20 are also reduced.

[0066] - Capacitor amplifier 10 will convert the sensor capacitance C in At least one integrator Int of the continuous-time increment Σ-Δ modulator 20 ICM1 Separation, such that at least one integrator Int ICM1 The bandwidth (GBW) is constant.

[0067] - No additional filter is needed to avoid aliasing (anti-aliasing). Filtering is performed by digital filter 23, i.e., at least one integrator Int. ICM1 The GBW can be large to reduce the reset time required by capacitor amplifier 10, thereby reducing information loss.

[0068] - Achieved direct current-to-digital conversion.

[0069] - By adjusting the capacitor and current source I FBn and I FBp It allows for precise scaling.

[0070] Multiplexing is possible, and the input channel can be turned on during the reset of the continuous-time increment Σ-Δ modulator 20 to avoid errors.

[0071] - Reduces production costs, chip area required, and current consumption or usage.

[0072] - The bitstream is much richer in information! You can feed the bitstream directly into the AI ​​without performing any filtering at all.

[0073] - Quantization noise, or Q noise, can always be set below thermal noise to maintain resolution.

[0074] Although some aspects have been described in conjunction with the device or system, it should be understood that these aspects also represent a description of the corresponding method; therefore, blocks or components of the device or system should also be understood as corresponding method steps or features of method steps. For redundancy, representations of the invention in the form of method steps are omitted in this example.

[0075] In the foregoing detailed description, various features have been partially grouped together in the examples to justify this disclosure. This type of disclosure should not be construed as an attempt to make the claimed examples have more features than expressly indicated in each claim. Rather, as reflected in the appended claims, the subject matter may relate only to a portion of the features of a single disclosed example. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim may exist as an individual example. While each claim may exist as an individual example, it is noteworthy that, although a dependent claim refers in its claim to a specific combination with one or more other claims, other examples also include combinations of the subject matter of a dependent claim with other dependent claims, or combinations of each feature with other dependent or independent claims. Such combinations are included unless it is expressly stated that no particular combination is intended to be used. Furthermore, even if a claim does not directly depend on an independent claim, it is intended to include combinations of features of that claim with any other independent claim.

Claims

1. A readout circuit (100) for reading currents of 10 nA and / or less, the readout circuit arrangement (100) including a capacitor current amplifier (10) and a continuous time increment Σ-Δ modulator (20) in current mode.

2. The readout circuit (100) according to claim 1, wherein the current amplifier (10) is configured to amplify the input current I. in To provide an amplified current I at the output of the capacitor current amplifier (100). out And wherein the continuous time increment ∑-Δ modulator (20) is configured to receive the amplified current I out And convert it to the numeric value D out .

3. The readout circuit (100) according to any one of claims 1 or 2, wherein the capacitor current amplifier (10) is configured to receive a first reset signal RST. camp The current amplifier is reset at that time.

4. The readout circuit (100) according to any one of claims 1 to 3, wherein, The continuous-time increment Σ-Δ modulator (20) is configured to, upon receiving the second reset signal RST ICM The modulator is reset at that time.

5. The readout circuit (100) according to any one of claims 1 to 4, wherein the current amplifier (10) includes an output capacitor C2 and at least one feedback capacitor C1, wherein the amplified current I out The input current I in M times, where M is the ratio between the output capacitor C2 and the at least one feedback capacitor C1.

6. The readout circuit (100) of claim 5, wherein the current amplifier (10) includes at least one operational amplifier OP1, wherein the current amplifier (10) is configured to use the at least one operational amplifier OP1 via the at least one feedback capacitor C1 to input current I. in The current amplifier (10) performs integration to amplify the input current I. in .

7. The readout circuit (100) according to any one of claims 1 to 6, wherein the readout circuit (100) is coupled to or is coupled to a sensor (30), wherein the capacitive current amplifier (10) is configured to adjust the voltage detected by the sensor (30) in the coupled case, in particular to reset the voltage to the command voltage V. bias .

8. The readout circuit (100) according to any one of claims 1 to 7, wherein, The current amplifier (10) includes a switch S1, which is arranged in parallel with the feedback capacitor C1, wherein, by using a first pulse width T RST,CAMP The first reset signal RST camp Close the switch S1 to reset the capacitive current amplifier (10).

9. The readout circuit (100) according to any one of claims 1 to 8, wherein, The continuous time increment ∑-Δ modulator (20) includes at least one loop filter (21), a quantizer (24), and a digital filter (23).

10. The readout circuit according to claim 9, wherein the loop filter (21) comprises at least one feedback capacitor C3, at least one loop filter switch S2, a first feedback switch SFB1, a second feedback switch SFB2, and at least one integrator INT. ICM,1 The loop filter (21) is configured to receive and process the amplified current I. out .

11. The readout circuit (100) according to any one of claims 9 or 10, wherein, The loop filter (21) includes a loop filter output, and the loop filter (21) is configured to provide an output voltage V at the loop filter output. HS The output of the loop filter is coupled to the quantizer (24) to sample the output voltage V at each clock edge of the clock signal CLK. HS .

12. The readout circuit (100) according to any one of claims 9 to 11, wherein the quantizer (24) includes a quantizer output, and the quantizer (24) is configured to operate according to the output voltage V. HS Provide feedback current (I) to the loop filter FBp I FBn Specifically, it feeds this back to adjust the output voltage V within a specific range. HS .

13. The readout circuit (100) according to claim 12, wherein the quantizer (24) is configured to provide the amplified current I corresponding to the digital bit stream at the quantizer output. out .

14. The readout circuit (100) according to any one of claims 9 to 13, wherein the digital filter (23) is coupled to the quantizer output and configured to receive and filter the digital bit stream, wherein the digital filter (23) is configured to output a digital value D after the conversion time period expires. out .

15. The readout circuit (100) according to any one of claims 4 to 14, wherein, Through a second pulse width T RST,ICM The second reset signal RST ICM The reset of the continuous time increment ∑-Δ modulator (20) is controllable.

16. The readout circuit (100) according to any one of claims 4 to 15, wherein the first reset signal RST of the current amplifier (10) camp and the second reset signal RST of the continuous time increment Σ-Δ modulator (20) ICM Each has the same frequency, among which, The frequency defines the Nyquist sampling rate, particularly the first reset signal RST. camp The duration of the first pulse (12) and the second reset signal RST ICM The duration of the second pulse (22) overlaps in time, such that the duration of the first pulse and the duration of the second pulse (12, 22) start simultaneously.

17. The readout circuit (100) according to any one of claims 4 to 16, wherein the readout circuit (100) is configured to perform the modulator reset promptly after performing the current amplifier reset, particularly to perform the modulator reset promptly after the current amplifier reset with a specific delay, wherein, The specific delay is based on the settling time of the integrator (11) of the at least one operational amplifier OP1.

18. The readout circuit (100) according to claim 7, wherein, When coupled to the sensor (30), the readout circuit (100) is configured to, during the current amplifier reset, read the sensor input capacitor C of the sensor (30). in Sample charge noise at the location.

19. The readout circuit (100) according to claim 18, wherein, The readout circuit (100) is configured to first check the input capacitor C. in The charge noise is accumulated and then integrated via the feedback capacitor C1.

20. The readout circuit (100) according to claim 19, wherein, The readout circuit (100) is configured to integrate the charge noise via the feedback capacitor C1 during the modulator reset of the continuous time increment ∑-Δ modulator (20).

21. The readout circuit (100) according to any one of claims 2 to 20, wherein, Due to the upstream current amplifier (10), the integrator (INT) ICM,1 The charge noise of the digital value D out The effect is reduced, especially to a negligible value.

22. The readout circuit (100) according to any one of claims 18 to 21, wherein the readout circuit (100) is configured to connect the at least one integrator IntICM,1 with the sensor input capacitor C in Separation, wherein at least one integrator Int ICM,1 The bandwidth is independent of the capacitance.

23. The readout circuit (100) according to any one of claims 4 to 22, wherein, The corner frequency of the readout circuit (100) corresponds to the reset frequency of the current amplifier reset and the modulator reset.

24. The use of the readout circuit (100) according to any one of claims 1 to 23 in a nanopore readout circuit, in a digital X-ray image sensor readout circuit, in a gas sensor readout circuit, or in a readout circuit for an electrochemical sensor.

25. A method for reading out a readout circuit (100) detecting currents of 10 nA and less, wherein the readout circuit arrangement (100) includes a capacitive current amplifier (10) and a continuous-time increment Σ-Δ modulator (20) in current mode, the method comprising: Amplify input current I by 10nA or smaller. in To obtain the amplified current I out ;as well as The amplified current I out Convert to numeric value D out .

26. The method of claim 25, comprising: Upon receiving the first reset signal RST camp The capacitor current amplifier (10) is reset at this time. Upon receiving the second reset signal RST ICM The continuous-time increment ∑-Δ modulator (20) is reset at time, wherein After resetting the capacitor current amplifier (10), the continuous time increment ∑-Δ modulator (20) is reset in a timely manner.

27. The method according to any one of claims 25 to 26, comprising: The output voltage V is measured at each clock edge of the clock signal CLK. HS Sampling is performed to adjust the output voltage V within a specific range. HS ; and / or Receive and filter the amplified current I out And after the conversion period expires, the filtered amplified current I will be... out Convert to the numerical value D out .

28. The method according to any one of claims 25 or 27, comprising: Adjust the detected voltage, especially when coupled to a sensor, to match the command voltage V. bias .

29. The method of claim 28, comprising: When coupled to the sensor (30), when the current amplifier is reset, the sensor input capacitance C of the sensor (30) is... in Sample charge noise at the location; and / or First, the input capacitance C of the sensor (30) in The charge noise is accumulated and then integrated via the feedback capacitor C1 of the current amplifier (10); and / or During the modulator reset of the continuous time increment ∑-Δ modulator (20), the charge noise is integrated via the feedback capacitor C1.

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