Managing contact structures in semiconductor devices

Abstract

The disclosure relates to methods, devices, systems, and techniques for managing contact structures in semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolation layers alternating with each other along a first direction and a second stack of dielectric layers and isolation layers alternating with each other along the first direction. The connection region of the semiconductor device is adjacent to the array region of the semiconductor device in a second direction orthogonal to the first direction. The second stack is in the connection region and is connected to the first stack. The semiconductor device further includes a contact structure extending along the first direction through at least a portion of the second stack.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] Semiconductor devices, such as memory devices, can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers in a similar footprint. 3D memory devices typically include a storage array of storage cells and a peripheral circuit to facilitate operation of the storage array. SUMMARY

[0003] The present disclosure describes methods, devices, systems, and techniques for managing contact structures in semiconductor devices.

[0004] One aspect of the present disclosure features a semiconductor device. The semiconductor device includes a first stack of conductive layers and isolation layers alternating with each other along a first direction, and a second stack of dielectric layers and isolation layers alternating with each other along the first direction. A connection region of the semiconductor device is adjacent to an array region of the semiconductor device in a second direction orthogonal to the first direction. The second stack is in the connection region and connected to the first stack. The semiconductor device further includes a contact structure extending through at least a portion of the second stack along the first direction. A contact structure of the contact structures includes a main body extending along the first direction and a bottom layer extending along a third direction orthogonal to the first direction and the second direction. A first conductive layer of the first stack is coupled to the bottom layer of the contact structure. The first conductive layer has an end portion in contact with the bottom layer of the contact structure. A second conductive layer of the first stack has an end portion in contact with a dielectric layer of the second stack. The end portion of the first conductive layer is between the end portion of the second conductive layer and the main body of the contact structure along the third direction.

[0005] In some embodiments, the semiconductor device further includes a gate line structure extending through the first stack along the first direction. The end portion of the first conductive layer is farther from the gate line structure along the third direction than the end portion of the second conductive layer.

[0006] In some embodiments, the first conductive layer contacts a first spacer layer and a second spacer layer at a location of the end portion of the second conductive layer along the third direction. The first spacer layer is between the first conductive layer and a first isolation layer adjacent to the first conductive layer. The second spacer layer is between the first conductive layer and a second isolation layer adjacent to the first conductive layer.

[0007] In some embodiments, the first liner layer comprises a high-k dielectric material, and the second liner layer comprises the high-k dielectric material.

[0008] In some embodiments, the bottom layer of the contact structure includes a first portion and a second portion. The first portion is located between the first conductive layer and the first insulating layer along the first direction. The first portion contacts the first padding layer along the third direction. The second portion is located between the first conductive layer and the second insulating layer along the first direction. The second portion contacts the second padding layer along the third direction.

[0009] In some embodiments, the contact structure further includes an outer layer surrounding the body. The outer layer and the body are connected to the bottom layer of the contact structure. The outer layer includes a first conductive material. The bottom layer includes the first conductive material. The body includes a second conductive material. The conductive layer includes the second conductive material.

[0010] In some embodiments, the dimension of the bottom layer of the contact structure at a first location along the first direction is smaller than the dimension of the bottom layer of the contact structure at a second location along the first direction. The first and second locations are located between the first conductive layer and the contact structure along the third direction. The first location is closer to the end of the first conductive layer along the third direction than the second location.

[0011] In some embodiments, the contact structure is surrounded by contact spacers comprising a dielectric material.

[0012] Another aspect of this disclosure features a method for forming a semiconductor device. The method includes: forming a semiconductor structure comprising a first stack of conductive and insulating layers alternating with each other along a first direction, and a second stack of dielectric and insulating layers alternating with each other along the first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction orthogonal to the first direction. The second stack is located in the connection region and connected to the first stack. The method further includes: forming a contact structure extending along the first direction through at least a portion of the second stack. Forming the contact structure includes: forming a contact structure comprising a body extending along the first direction and a bottom layer extending along a third direction orthogonal to both the first and second directions. The bottom layer of the contact structure is coupled to a first conductive layer of the first stack. The first conductive layer has an end contacting the bottom layer of the contact structure. The second conductive layer of the first stack has an end contacting the dielectric layer of the second stack. The end of the first conductive layer is located along the third direction between the end of the second conductive layer and the body of the contact structure.

[0013] In some embodiments, the method includes: providing a stack of sacrificial layers and isolation layers alternating with each other along the first direction; forming a contact hole in the connection region, wherein the contact hole extends along the first direction into the stack and reaches a first sacrificial layer in the sacrificial layers; forming a first space in the first sacrificial layer by removing a portion of the first sacrificial layer; and forming a filler body in the contact hole and a filler layer in the first space by filling the contact hole and the first space with a first filler material, wherein the filler body is connected to the filler layer and the filler layer extends along the third direction.

[0014] In some embodiments, forming the semiconductor structure includes forming a gate line gap extending through the first stack along the first direction. The gate line gap includes a first segment in the array region and a second segment in the interconnect region. An isolation structure lies between the first segment and the second segment along the second direction.

[0015] In some embodiments, forming the first space in the first sacrificial layer by removing a portion of the first sacrificial layer includes: etching away a first portion of the first sacrificial layer and portions of two isolation layers adjacent to the first sacrificial layer during a first time period of the etching process; and etching away a second portion of the first sacrificial layer during a second time period of the etching process. The dimension of the first space at a first location along the first direction is smaller than the dimension of the first space at a second location along the first direction. The first location and the second location are arranged along the third third direction between the gate line gap and the contact via. The first location along the third third direction is closer to the gate line gap than the second location.

[0016] In some embodiments, forming the semiconductor structure includes forming a tunnel in the connection region by filling an etch solution through a second segment of the gate line gap to remove a portion of the sacrificial layer in the connection region. The tunnel is between the isolation layers. The second segment of the gate line gap extends through the tunnel along the first direction. The sacrificial layer includes a first sacrificial layer and a second sacrificial layer. The tunnel includes a first tunnel aligned with the fill layer and the first sacrificial layer along the third direction and a second tunnel aligned with the second sacrificial layer along the third direction. The first tunnel exposes the fill layer. The second tunnel exposes the remaining portion of the second sacrificial layer.

[0017] In some embodiments, forming the semiconductor structure includes widening the first tunnel along a third direction by removing a portion of the fill layer. The widened first tunnel exposes the ends of the remaining portion of the fill layer. The ends of the remaining portion of the fill layer are located further away from the second segment of the gate line gap along the third direction than the ends of the remaining portion of the second sacrificial layer.

[0018] In some embodiments, forming the semiconductor structure includes: filling the second segment of the gate line gap and the tunnel with a second filler material; removing the sacrificial layer in the array region by filling the first segment of the gate line gap with an etch solution; removing the second filler material in the second segment of the gate line gap and the tunnel; and forming the first stack by forming a conductive layer of the first stack between the isolation layers. The conductive layer is formed by depositing at least a high-k dielectric material and a first conductive material through the first segment and the second segment of the gate line gap. The conductive layer includes a first conductive layer surrounded by a pad layer, the pad layer including a connected first segment, a second segment, and a third segment. The first conductive layer is located between a first isolation layer and a second isolation layer adjacent to the first conductive layer. The first segment of the pad layer is located between the first conductive layer and the first isolation layer along the first direction. The second segment of the pad layer is located between the first conductive layer and the second isolation layer along the first direction. The third segment of the pad layer is located between the first conductive layer and the filler layer along the third direction.

[0019] In some embodiments, forming the semiconductor structure includes: removing the first filler material from the contact hole; forming a second space aligned with the first sacrificial layer along the third direction by removing the first filler material from the filler layer; removing the third segment of the pad layer to expose the first conductive layer; forming a first recess between the first conductive layer and the first isolation layer by removing a portion of the first segment of the pad layer connected to the third segment of the pad; and forming a second recess between the first conductive layer and the second isolation layer by removing a portion of the second segment of the pad layer connected to the third segment of the pad.

[0020] In some embodiments, forming the contact structure includes: forming an outer layer and a bottom layer of the contact structure by depositing a second conductive material through the contact hole. The outer layer contacts the inner surface of the contact hole. The bottom layer of the contact structure is located in a second space aligned with the first sacrificial layer and contacts the first conductive layer. The bottom layer of the contact structure includes a first portion in the first recess and a second portion in the second recess. Forming the contact structure also includes: forming a body of the contact structure by depositing the first conductive material into the contact hole, wherein the body is surrounded by the outer layer.

[0021] Another aspect of this disclosure features a storage system. The storage system includes: a storage device; and a memory controller coupled to and configured to control the storage device. The storage device includes: a first stack of conductive and insulating layers alternating with each other along a first direction, and a second stack of dielectric and insulating layers alternating with each other along the first direction. A connection region of the storage device is adjacent to an array region of the storage device in a second direction orthogonal to the first direction. The second stack is located in the connection region and connected to the first stack. The storage device further includes: a contact structure extending through at least a portion of the second stack along the first direction. The contact structure includes a body extending along the first direction and a bottom layer extending along a third direction orthogonal to both the first and second directions. A first conductive layer of the first stack is coupled to the bottom layer of the contact structure. The first conductive layer has an end contacting the bottom layer of the contact structure. A second conductive layer of the first stack has an end contacting the dielectric layer of the second stack. The end of the first conductive layer is located between the end of the second conductive layer and the body of the contact structure along the third direction.

[0022] In some embodiments, the first conductive layer contacts the first and second padding layers at the location of the end of the second conductive layer along the third direction. The first padding layer is between the first conductive layer and a first insulating layer adjacent to the first conductive layer. The second padding layer is between the first conductive layer and a second insulating layer adjacent to the first conductive layer. The bottom layer of the contact structure includes a first portion and a second portion. The first portion is between the first conductive layer and the first insulating layer along the first direction. The first portion contacts the first padding layer along the third direction. The second portion is between the first conductive layer and the second insulating layer along the first direction. The second portion contacts the second padding layer along the third direction.

[0023] In some embodiments, the dimension of the bottom layer of the contact structure at a first location along the first direction is smaller than the dimension of the bottom layer of the contact structure at a second location along the first direction. The first and second locations are arranged between the first conductive layer and the contact structure along the third direction. The first location is closer to the first conductive layer along the third direction than the second location. Attached Figure Description

[0024] Figures 1A-1B An exemplary semiconductor device is shown.

[0025] Figures 2A-2Z An example process for manufacturing semiconductor devices is shown.

[0026] Figure 3 A flowchart of an example process for manufacturing semiconductor devices is shown.

[0027] Figure 4 A block diagram of the example system is shown.

[0028] In the various figures, similar reference numerals and labels indicate similar elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0029] The demand for cheaper, higher-density memory devices has led to the formation of memory devices (e.g., 3D NAND flash memory) with a large number of layers and high aspect ratios. For example, a memory device may have multiple stacks, and each stack may contain multiple layers. This large number of layers and high aspect ratio can present challenges to the manufacturing process. For instance, stress issues may become more severe, leading to XY bending problems in the conductive layer filling. In other words, the conductive layer can bend during the fabrication of the memory device. In another example, the connection between the conductive layer and the contact structure may result in the loss of high-k dielectric material in the padding layer between the conductive layer and adjacent insulating layers. That is, the uniformity of the conductive layer structure is affected, thereby reducing the breakdown voltage between the conductive layer and adjacent conductive layers. Therefore, contact structures and manufacturing methods capable of addressing the aforementioned problems are desirable.

[0030] In one or more embodiments of this disclosure, an example semiconductor device is provided. The semiconductor device includes a first stack of alternating conductive and insulating layers and a second stack of alternating dielectric and insulating layers. The semiconductor device also includes a contact structure extending vertically through at least a portion of the second stack. The contact structure includes a body extending vertically and a bottom layer extending horizontally. A first conductive layer of the first stack is coupled to the bottom layer of the contact structure. The first conductive layer has an end contacting the bottom layer of the contact structure. A second conductive layer of the first stack has an end contacting the dielectric layer of the second stack. The end of the first conductive layer extends horizontally between the end of the second conductive layer and the body of the contact structure.

[0031] The embodiments of this disclosure can provide one or more of the following technical advantages and / or benefits. First, in the example semiconductor device described above, the ends of the first conductive layer and the second conductive layer can be offset along a horizontal direction. Therefore, the ends of the first conductive layer can be protected by adjacent isolation layers along a vertical direction, thereby mitigating or resolving breakdown voltage problems caused by losses in the high-k dielectric material. Second, a thicker isolation layer may not be necessary, allowing for smaller semiconductor device dimensions. Third, in some embodiments, the center of the bottom layer of the contact structure can be thicker than the edges of the bottom layer. This feature can reduce potential seams in the filler material used during the fabrication of the contact structure, thereby allowing for easier control over the position of the ends of the first conductive layer. Fourth, the fabrication of the contact structure described in this disclosure is compatible with isolation structures formed to separate the gate line structure into multiple segments. Isolation structures can help release stress in the gate line structure and can allow the conductive layer filling process to be performed in a separate step, thereby improving the quality and reliability of the conductive layer.

[0032] This technology can be applied to any semiconductor structure or device configured to prevent leakage or breakdown, for example, between conductive layers or components. It can be applied to various types of semiconductor devices, volatile memory devices (such as DRAM memory devices), or non-volatile memory (NVM) devices (such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change memory (PCM) (such as phase-change random-access memory (PCRAM)), spin-transfer torque (STT)-magnetoresistive random-access memory (MRAM), etc.). This technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. These technologies can be applied to three-dimensional (3D) memory devices. This technology can be applied to various storage types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., 2-level cell devices), TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Additionally or alternatively, this technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC), solid-state drives (SSDs), and embedded systems.

[0033] Note that in Figures 1A-1BThe X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of various components in a semiconductor device. The substrate of a semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate and a bottom surface on the back side opposite the front side of the substrate, on which components of the semiconductor device may be formed. The Z direction is orthogonal to the X and Y directions. As used in this disclosure, whether a component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the Z direction (i.e., a direction perpendicular to the XY plane, e.g., the thickness direction of the substrate) when the substrate is located in the lowest plane of the semiconductor device in the Z direction. The same concepts used to describe spatial relationships apply throughout this disclosure.

[0034] Figure 1A A top view of an exemplary semiconductor device 100 is shown. In some embodiments, the semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. The semiconductor device 100 may include one or more array regions and one or more interconnect regions, the interconnect regions being configured to provide conductive connections. In some embodiments, such as Figure 1A As shown, the semiconductor device 100 includes an array region 102 and a connection region 104 adjacent to the array region 102 along a first horizontal direction (e.g., the X direction). It should be understood that... Figure 1A The examples provided are for illustrative purposes and are not intended to be interpreted in a limiting sense. In practice, any suitable arrangement of various regions in the semiconductor device 100 can be applied. In some cases, the semiconductor device 100 may have two connecting regions 104 and an array region 102 arranged along the X direction between the two connecting regions 104. In some other cases, the semiconductor device 100 may have two array regions 102 and a connecting region 104 arranged along the X direction between the two array regions 102.

[0035] Semiconductor device 100 includes alternating conductive layers and insulating layers (e.g., as shown in the image). Figure 1B The semiconductor device 100 includes a stack of conductive layers 106A and insulating layers 106B. In some embodiments, a portion of the stack 106 may be in the array region 102, while another portion of the stack 106 may be in the connection region 104. The semiconductor device 100 also includes alternating dielectric and insulating layers (e.g., as shown in the diagram). Figure 1B The stack 108 is a combination of dielectric layer 106D and insulating layer 108B. In some embodiments, the stack 108 may be located in a connection region 104. Stack 106 is connected to stack 108.

[0036] Semiconductor device 100 may include an array of channel structures 110 extending through a stack 106 in array region 102. Each channel structure 110 may be used to form a string of memory cells coupled in series along a vertical direction (e.g., the Z direction) orthogonal to a first horizontal direction. In some embodiments, semiconductor device 100 may include dummy channel structures 112 (also referred to as dummy memory strings) for process variation control during manufacturing and / or for additional mechanical support. Dummy channel structures 112 may extend through the stack 106 in connection region 104. In some embodiments, dummy channel structures 112 may be located in one or more dummy regions or peripheral regions ( Figure 1A (Not shown in the text)

[0037] Semiconductor device 100 may include contact structures 116 in connection region 104. Contact structures 116 may be configured to connect a corresponding conductive layer of the conductive layers of stack 106 to control circuitry. Semiconductor device 100 may include one or more gate line structures 118. Each gate line structure 118 may extend in the X direction. Gate line structures 118 may extend into both array region 102 and connection region 104. In some embodiments, gate line structures 118 may divide the array region into multiple memory blocks. In some embodiments, gate line structures 118 may serve as a common source contact for channel structures 110 in array region 102. Figure 1A As shown, each gate line structure 118 may include a plurality of segments 120 extending along the X direction. The segments 120 may be separated and spaced apart along the X direction by an isolation structure 122. The isolation structure 122 may eliminate or reduce stress built into the gate line structure 118 during the manufacturing process, thereby preventing the gate line structure 18 from bending or breaking. In some embodiments ( Figure 1A (Not shown in the diagram), the gate line structure 118 may further include one or more segments extending along a second horizontal direction (e.g., the Y direction). In some embodiments, the gate line structure 118 may include multiple segments connected in an H-shape or T-shape. In some embodiments, segments 120 of each gate line structure 118 may have similar or identical widths (e.g., along the Y direction). In some other embodiments, segments 120 of each gate line structure 118 may have different widths (e.g., along the Y direction). In some embodiments, the width of segment 120 in connection region 104 is greater than the width of segment 120 in array region 102 along the Y direction. For example, the width of segment 120 in connection region 104 may be approximately 1.5 to 2 times the width of segment 120 in array region 102.

[0038] Figure 1B Semiconductor device 100 is shown along Figure 1AA cross-sectional view of the cut line CC'. Semiconductor device 100 includes a substrate 101, a stack 106 of alternating conductive layers 106A and isolation layers 106B, and a stack 108 of alternating dielectric layers 106D and isolation layers 106B. Each isolation layer 106B may have a portion between two adjacent conductive layers 106A in the stack 106 and another portion between two adjacent dielectric layers 106D in the stack 108. Stacks 106 and 108 are provided on the substrate 101. The substrate 101 may be any suitable semiconductor substrate having any suitable semiconductor material, such as single-crystal, polycrystalline, or single-crystal semiconductor. For example, substrate 101 may include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon on insulator (SOI), germanium on insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, the substrate 101 may be removed from the semiconductor device 100 in a later process of manufacturing the semiconductor device 100. The semiconductor device 100 may include a top layer 107 made of an insulating material (e.g., oxide).

[0039] The stack 106 can extend in a second horizontal direction (e.g., the Y direction), which is parallel to the top surface of the substrate 101 and orthogonal to a first horizontal direction (e.g., the X direction). The conductive layer 106A and the insulating layer 106B can alternate in a vertical direction orthogonal to the second horizontal direction (e.g., the Z direction). The thickness of the conductive layer 106A can be the same or different from each other, for example, in the range of 10-500 nm, e.g., approximately 35 nm. The thickness of the insulating layer 106B can also be the same or different from each other, for example, in the range of 10-500 nm, e.g., approximately 25 nm. Note that... Figure 1B The number of conductive layers 106A and insulating layers 106B shown is for illustrative purposes only, and the stack 106 may include any suitable number of conductive layers 106A and insulating layers 106B. Conductive layer 106A may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicides, or any combination thereof. Insulating layer 106B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, insulating layer 106B may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0040] In some implementations, such as Figure 1BAs shown, the stack 106 includes a padding layer 106C. The padding layer 106C may cover part or all of the sides of the corresponding conductive layer 106A and is located between the conductive layer 106A and two isolation layers 106B adjacent to the corresponding conductive layer 106A. The padding layer 106C may include a high-k dielectric material (e.g., Al2O3). In some examples, the conductive layer 106A includes a metallic material (e.g., W) and an adhesive material (e.g., TiN), and the adhesive material may be deposited between the metallic material and the high-k dielectric material. In some examples, the conductive layer 106A includes a metallic material (e.g., W), and the padding layer 106C includes an adhesive material (e.g., TiN) and a high-k dielectric material.

[0041] Stack 108 includes dielectric layers 106D and isolation layers 106B that alternate with each other along a vertical direction (e.g., the Z direction). Stack 108 can be connected to stack 106. Isolation layer 106B can extend into stack 106 and stack 108 in connection region 104 along a second horizontal direction (e.g., the Y direction). Dielectric layer 106D in stack 108 can extend to and contact a corresponding conductive layer 106A (or a pad layer 106C surrounding the corresponding conductive layer 106A) in stack 106. To fabricate stack 106 and stack 108, a series of alternating dielectric layers 106D and isolation layers 106B can be formed first. Then, dielectric layers 106D in regions of stack 106 can be etched away, for example, through openings formed at locations in gate line structures 118, while dielectric layers 106D in stack 108 remain unchanged. Then, a padding layer 106C and a conductive layer 106A can be formed in the region of the stack 106 to replace the dielectric layer 106D, thereby forming the stack 106.

[0042] The gate line structure 118 may extend through the stack 106 in a vertical direction (e.g., the Z direction). In some embodiments, such as Figure 1B As shown, the gate line structure 118 can extend along the Z-direction from the top layer 107 into the substrate 101. The dummy channel structure 112 can also extend along a vertical direction (e.g., the Z-direction) through the stack 106. In some embodiments, such as Figure 1B As shown, the dummy channel structure 112 can extend along the Z-direction into the substrate 101. The contact structure 116 can extend along the Z-direction through at least a portion of the stack 108 (e.g., a set of dielectric layers 106D and insulating layers 106B of the stack 108). Figure 1BAs shown, the contact structure 116 may include a body 124, an outer layer 125, and a bottom layer 126. The body 124 and the outer layer 125 may extend along the Z direction, and the bottom layer 126 may extend in an XY plane (e.g., orthogonal to the Z direction). The outer layer 125 may surround and contact the body 124. The body 124 and the outer layer 125 may be connected to the bottom layer 126. The body 124 may include a first conductive material. Both the outer layer 125 and the bottom layer 126 may include the same conductive material, which may be referred to as a second conductive material and may be different from the first conductive material of the body 124. In some embodiments, the first conductive material may be a metallic material such as W, and the second conductive material may be TiN. In some embodiments, the contact structure 116 may be surrounded by a contact spacer 127, and the contact spacer 127 may include a dielectric material (e.g., silicon oxide).

[0043] The body 124 has ends 124a and 124b opposite to each other along the Z-direction. End 124a is closer to the top layer 107 along the Z-direction than end 124b. End 124a can be exposed from the top layer 107 and can be configured to couple out to external circuitry (e.g., control circuitry). End 124b is connected to the bottom layer 126. The bottom layer 126 of each contact structure 116 can be coupled to a corresponding conductive layer 106A of the stack 106. For example, as Figure 1B As shown, bottom layer 126 is coupled to conductive layer 106A-1. Both bottom layer 126 and conductive layer 106A-1 are located along the Z-direction between two adjacent isolation layers 106B-1 and 106B-2. Bottom layer 126 contacts end 128 (also referred to as end portion) of conductive layer 106A-1 along the Y-direction. Stack 106 may include another conductive layer 106A-2 not connected to bottom layer 126. Conductive layer 106A-2 has end 130 (or end portion) that contacts dielectric layer 106D-2 of stack 108. End 128 of conductive layer 106A-1 is located along the Y-direction between end 130 of conductive layer 106A-2 and body 124 of contact structure 116. In other words, end 128 of conductive layer 106A-1 is further away from gate line structure 118 along the Y-direction than end 130 of conductive layer 106A-2. End portion 128 may have a surface that contacts the underlying layer 126 and extends in the X direction. It should be understood that, in practice, the surface of end portion 128 may not be flat and may include curved portions. End portion 130 may have a surface that contacts the dielectric layer 106D-2 and extends in the X direction. Similarly, the surface of end portion 130 may not be flat and may include curved portions.

[0044] Conductive layer 106A-1 may contact the padding layers 106C-1 and 106C-2 of stack 106 at the end 130 of conductive layer 106A-2 along the Y direction. Padding layer 106C-1 is located between conductive layer 106A-1 and insulating layer 106B-1 along the Z direction. Padding layer 106C-2 is located between conductive layer 106A-1 and insulating layer 106B-2 along the Z direction. The bottom layer 126 may include two portions 126a and 126b, both of which are in contact with the end 128 of conductive layer 106A-1. For example, portion 126a may be located between conductive layer 106A-1 and insulating layer 106B-1 along the Z direction. Portion 126a may be in contact with padding layer 106C-1 along the Y direction. Portion 126b may be located between conductive layer 106A-1 and insulating layer 106B-2 along the Z direction. Part 126b can contact the liner layer 106C-2 along the Y direction.

[0045] In some embodiments, along the Z-direction, the center of the bottom layer 126 (closer to the body 124 along the Y-direction) may be thicker than the edges of the bottom layer 126 (farther from the body 124 along the Y-axis). For example, the bottom layer 126 may have two cross-sections 132 and 134 orthogonal to the Y-direction. Cross-sections 132 and 134 may be located between the end 128 of the conductive layer 106A-1 and the body 124 (e.g., along the Y-direction). Along the Y-direction, cross-section 132 is closer to the end 128 of the conductive layer 106A-1 than cross-section 134. The dimension of cross-section 132 along the Z-direction is smaller than the dimension of cross-section 134 along the Z-direction.

[0046] Figures 2A-2Z This illustrates the manufacture of semiconductor devices (such as...) Figures 1A-1B Example process of semiconductor device 100 shown. Figures 2A-2Z Cross-sectional views of example semiconductor structures at various stages of the manufacturing process are shown. Specifically, Figure 2A (a)- Figure 2X (a) shows an example semiconductor structure along Figure 1A The cross-sectional view of the cutting line AA'. Figure 2A (b)- Figure 2X (b) shows an example semiconductor structure along Figure 1A The cross-sectional view of the cutting line BB', and Figure 2A (c)- Figure 2C (c) Figure 2C-2 , Figure 2D (c)- Figure 2X (c) Figure 2Y and Figure 2Z An example semiconductor structure is shown along Figure 1A The cross-sectional view of the cutting line CC'.

[0047] likeFigure 2A As shown, a semiconductor structure 200a is formed. The semiconductor structure 200a may have an array region 202 and a connection region 204 adjacent to the array region 202 (e.g., along the X direction). The array region 202 may be... Figure 1A Examples of array regions 102 of semiconductor device 100, and examples of connection regions 204 of semiconductor device 100. Semiconductor structure 200a includes a substrate 201 and a stack 205 of alternating sacrificial layers 206D (also referred to as dielectric layers) and isolation layers 206B provided on the substrate 201. The stack 205 may extend across array region 202 and connection region 204. Sacrificial layers 206D and isolation layers 206B may alternate in a vertical direction (e.g., the Z direction). Isolation layer 206B may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, sacrificial layer 206D may include a dielectric material different from the dielectric material of isolation layer 206B. For example, isolation layer 206B may include silicon oxide, and sacrificial layer 206D may include silicon nitride. In some embodiments, semiconductor structure 200a may also include a polysilicon layer 203 along a vertical direction between stack 205 and substrate 201.

[0048] Semiconductor structure 200a may include channel structure 210 in array region 202 (e.g., Figure 2A (a) shown) and the virtual channel structure 212 in the connecting area (as shown) Figure 2A (as shown in (c)). Each channel structure 210 can be coupled with, for example, Figure 1A The channel structure 110 of the semiconductor device 100 shown is similar to or the same as that shown. Each dummy channel structure 212 can be associated with, for example, Figure 1A The dummy channel structure 112 of the semiconductor device 100 shown is similar to or the same as that shown.

[0049] Semiconductor structure 200a may include a gate line slot 218 extending along the X direction. The gate line slot 218 may extend through the stack 205 along the Z direction. Figure 2A As shown in (b), the gate line gap 218 may include segments 220a, 220b, and 220c separated along the X direction by portions of the stack 205. Segment 220b lies between segments 220a and 220c along the X direction. A protective structure 217 (e.g., polyoxide) may be formed on the bottom of segments 220a-220c of the gate line gap 218 (which may be in contact with the substrate 201) to protect the substrate 201. A filler material (e.g., polysilicon) may be filled into the gate line gap 218.

[0050] Figure 2BSemiconductor structure 200b is shown. Semiconductor structure 200b can be formed by forming contact holes 215 in connection region 204 using an etching process. Contact holes 215 can extend from the top of semiconductor structure 200b (e.g., further away from the surface of substrate 201) to isolation layer 206B-1 of stack 205.

[0051] like Figure 2C As shown in the semiconductor structure 200c, a contact spacer 227 can be deposited on the inner surface of a contact hole 215. The contact hole 215 can be deepened to reach the sacrificial layer 206D-1 of the stack 205. The sacrificial layer 206D-1 lies beneath and contacts the isolation layer 206B-1. A space 214 can be formed in the sacrificial layer 206D-1 by removing a portion of it (e.g., through an etching process). In some embodiments, the contact spacer 227 can protect the sacrificial layer 206D exposed by the contact hole 215 from the etching process.

[0052] In some implementations, such as Figure 2C-2 As shown, the etching process can cause space 214 to expand closer to contact hole 215. For example, a first etchant can be used during a first time period of the etching process. The first etchant can etch away sacrificial layer 206D-1 and the two isolation layers 206B-1 and 206B-2 adjacent to sacrificial layer 206D-1. Therefore, a first portion of sacrificial layer 206D-1 and portions of isolation layers 206B-1 and 206B-2 can be etched away during the first time period of the etching process. A second etchant can be used during a second time period of the etching process. The second etchant can etch away sacrificial layer 206D-1 and has little or no effect on isolation layers 206B-1 and 206B-2. Therefore, a second portion of sacrificial layer 206D-1 can be etched away during the second time period of the etching process. Figure 2C-2 As shown, the dimension of space 214 along the Z direction at position 213a is smaller than the dimension of space 214 along the Z direction at position 213b. Positions 213a and 213b are arranged along the Y direction between the gate line slot 218 and the contact hole 215. Along the Y direction, position 213a is closer to the gate line slot 218 than position 213b.

[0053] Figure 2D A semiconductor structure 200d is shown, which can be formed by filling contact holes 215 and spaces 214 with a filling material (e.g., polysilicon).

[0054] Figure 2EA semiconductor structure 200e is shown, which can be formed by performing a planarization process (such as chemical mechanical polishing (CMP)) to remove excess filler material on top of the semiconductor structure 200d. The semiconductor structure 200e includes a filler body 209 in a contact hole 215 and a filler layer 211 in a space 214. The filler body 209 is connected to the filler layer 211 along the Z-direction. The filler layer 211 extends along the Y-direction.

[0055] Figure 2F A semiconductor structure 200f is shown, which can be formed by depositing a dielectric layer 219 (e.g., silicon oxide) on top of a semiconductor structure 200e.

[0056] like Figure 2G As shown in the semiconductor structure 200g, an opening is formed on the top of a segment 220b of the gate line gap 218 to expose the fill material in the segment 220b. The opening can extend along the Z direction from the top surface of the dielectric layer 219 to the fill material in the segment 220b.

[0057] like Figure 2H As shown in the semiconductor structure 200h, the filler material in section 220b can be removed.

[0058] Figure 2I Semiconductor structure 200i is shown. Semiconductor structure 200i includes a recess 221 connected to a segment 220b of gate line slot 218. The recess 221 can be formed by removing (e.g., by etching) the portion of each sacrificial layer 206D exposed by the segment 220b of gate line slot 218.

[0059] Figure 2J A semiconductor structure 200j including a dielectric layer 223 is shown. The dielectric layer 223 can be formed by depositing a dielectric material (e.g., silicon oxide) in the recess 221 and on the inner surface of a segment 220b of the gate line gap 218. In some embodiments, the dielectric layer 223 may be referred to as an isolation structure that separates segment 220a of the gate line gap 218 from segment 220c of the gate line gap 218. In some embodiments, the isolation structure may also include a filler material (e.g., as referred to later). Figure 2W The filling material is surrounded by a dielectric layer 223 in segment 220b of the gate line gap 218. In some embodiments, the dielectric layer 223 may also cover the top of the dielectric layer 219.

[0060] Figure 2KA semiconductor structure 200k is shown, including an opening 236 formed on top of a segment 220c of a gate line gap 218. The opening 236 may extend along the Z direction from the top of the semiconductor structure 200k to the fill material in the segment 220c.

[0061] like Figure 2L As shown in the semiconductor structure 200l, the filler material in section 220c can be removed.

[0062] Figure 2M A semiconductor structure 200m is shown that includes a tunnel 207 in a connection region 204. The tunnel 207 connects to a segment 220c of a gate line gap 218 and lies between isolation layers 206B of a stack 205 in the connection region 204. In some embodiments, the tunnel 207 can be formed by filling the segment 220c of the gate line gap 218 with an etching solution through an opening 236, thereby removing a portion of the sacrificial layer 206D of the stack 205 in the connection region 204. The tunnel 207 may include tunnel 207a and other tunnels (e.g., 207b). Tunnel 207a is aligned along the Y direction with the fill layer 211 and the sacrificial layer 206D-1. Other tunnels are aligned along the Y direction with other corresponding sacrificial layers. For example, tunnel 207b is aligned along the Y direction with sacrificial layer 206D-2. Tunnel 207a exposes the fill layer 211. Other tunnels expose the ends of the remaining portions of their corresponding sacrificial layers. For example, tunnel 207b exposes the end 229 of the remaining portion of the sacrificial layer 206D-2. In some embodiments, end 229 is further away from the segment 220c of the gate line gap 218 along the Y direction than the end of the fill layer 211 exposed by tunnel 207a.

[0063] Figure 2N Semiconductor structure 200n is shown. Semiconductor structure 200n can be formed by removing a portion of fill layer 211 and widening tunnel 207a along the Y direction. The widened tunnel 207a exposes the end 211a of the remaining portion of fill layer 211. The end 211a is further away from the segment 220c of gate line gap 218 along the Y direction than the ends of the remaining portions of other sacrificial layers (e.g., end 229 of sacrificial layer 206D-2).

[0064] Figure 2O A semiconductor structure 200o is shown. The semiconductor structure 200o can be formed by filling the segment 220c and tunnel 207 of the gate line gap 218 with a filler material (e.g., carbon). In some embodiments, the filler material can also be deposited in the segment 220b and on top of the semiconductor structure 200o, such as... Figure 2O As shown.

[0065] Figure 2PA semiconductor structure 200p is shown, which is formed by removing excess filler material on its top surface using a planarization process (e.g., CMP).

[0066] Figure 2Q A semiconductor structure 200q including a pad layer 231 is shown. The pad layer 231 can be formed by depositing a fill material (e.g., the same fill material as in segment 220c) on top of the semiconductor structure 200q.

[0067] Figure 2R A semiconductor structure 200r is shown, including a dielectric layer 233 formed on top of a pad layer 231. The dielectric layer 233 may comprise any suitable dielectric material (e.g., silicon oxynitride).

[0068] Figure 2S A semiconductor structure 200s including an opening 235 in an array region 202 is shown. The opening 235 may have been formed on top of a segment 220a of a gate line gap 218 by etching away a portion of the top of the semiconductor structure 200r (which may include, for example, a portion of a pad layer 231 and a portion of a dielectric layer 233) to expose the fill material in the segment 220a.

[0069] Figure 2T Semiconductor structure 200t is shown. Semiconductor structure 200t is formed by removing the filler material in segment 220a.

[0070] Figure 2U Semiconductor structure 200u is shown. Semiconductor structure 200u is formed by removing the sacrificial layer 206D of the stack 205 in array region 202. The sacrificial layer 206D in array region 202 can be removed, for example, by filling the segment 220a of the gate line gap 218 with an etch solution. In some embodiments, the dielectric layer 233 can also be removed by the above-described etching process.

[0071] Figure 2V Semiconductor structure 200v is shown. Semiconductor structure 200v is formed by removing the filler material in the pad layer 231, the segments 220b and 220c of the gate line gap 218, and the filler material in the tunnel 207.

[0072] Figure 2WA semiconductor structure 200w including a conductive layer 206A is shown. The conductive layer 206A may be in the tunnel 207 in the connection region 204 and between the isolation layers 206B in the array region 202. In some embodiments, each conductive layer 206A may be surrounded by a corresponding pad layer 206C. The conductive layer 206A may include a conductive material (e.g., W). The pad layer 206C may include a high-k dielectric material (e.g., Al2O3). The pad layer 206C and the conductive layer 206A may be formed, for example, by depositing the high-k dielectric material and the conductive material (e.g., through segments 220a and 220c of the gate line gap 218) into the space between the tunnel 207 and the isolation layer 206B in the array region 202. A filler material (e.g., polysilicon) may be deposited into the segments 220a, 220b, and 220c of the gate line gap 218. In some embodiments, a portion of the insulating layer 206B between the conductive layer 206A and the conductive layer 206A forms a stack 206. A portion of the insulating layer 206B between the sacrificial layer or dielectric layer 206D and the sacrificial layer 206D forms a stack 208. The stack 206 may be... Figure 1B An example of a stack 106 of a semiconductor device 100. Stack 208 may be... Figure 1B An example of a stack 108 of semiconductor device 100.

[0073] The conductive layer 206A-1 can be aligned with the filler layer 211 along the Y direction. In some embodiments, the conductive layer 206A-1 is surrounded by a padding layer in the padding layer 206C. For example... Figure 2W As shown, the padding layer 206C may include segments 206C-1, 206C-2, and 206C-3. Segment 206C-1 is located along the Z-direction between the conductive layer 206A-1 and the insulating layer 206B-1. Segment 206C-2 is located along the Z-direction between the conductive layer 206A-1 and the insulating layer 206B-2. Segment 206C-3 is located along the Y-direction between the conductive layer 206A-1 and the filler layer 211.

[0074] Figure 2X Semiconductor structure 200x is shown. Semiconductor structure 200x can be formed by removing excess filler material on top of semiconductor structure 200w (e.g., using a planarization process, such as CMP).

[0075] Figure 2YSemiconductor structure 200y is shown. Semiconductor structure 200y can be formed by forming an opening on the top of semiconductor structure 200x to expose the filler material in contact hole 215, removing the filler material in contact hole 215, and forming a space 237 (e.g., along the Y direction) aligned with sacrificial layer 206D-1. Space 237 is formed by removing the filler material in filler layer 211. Segment 206C-3 of pad layer 206C may be etched away by an etching process to expose conductive layer 206A-1. In some embodiments, the etching process may remove a portion of segment 206C-1 of pad layer 206C (which is connected to segment 206C-3) and a portion of segment 206C-2 of pad layer 206C (which is connected to segment 206C-3) to form two recesses 239a and 239b. Recess 239a is located along the Z direction between conductive layer 206A-1 and isolation layer 206B-1. Recess 239b is located along the Z-direction between conductive layer 206A-1 and insulating layer 206B-2. Space 237 may include recesses 239a and 239b.

[0076] Figure 2Z A semiconductor structure 200z including contact structure 216 is shown. Semiconductor structure 200z can be coupled with… Figures 1A-1B The semiconductor device 100 shown is similar or identical. Contact structure 216 may include a body 224, an outer layer 225, and a bottom layer 226. The body 224 and outer layer 225 may extend along the Z direction, and the bottom layer 226 may extend in an XY plane (e.g., orthogonal to the Z direction). The outer layer 225 contacts the inner surface of contact hole 215. The bottom layer 226 is in space 237 and contacts conductive layer 206A-1. The bottom layer 226 may include portions 226a in recess 239a and 226b in recess 239b. For example, the outer layer 225 and the bottom layer 226 of contact structure 216 may be formed by depositing conductive material through contact hole 215. The body 224 is surrounded by the outer layer 225. For example, the body may be formed by depositing conductive material into contact hole 215. In some embodiments, both outer layer 225 and bottom layer 226 may include the same conductive material. In some embodiments, the conductive materials of the outer layer 225 and the bottom layer 226 may be different from the conductive material of the body 224. For example, the conductive material of the outer layer 225 and the bottom layer 226 may be TiN, while the conductive material of the body 224 may be a metallic material such as W.

[0077] like Figure 2ZAs shown, the bottom layer 226 contacts the end 228 of the conductive layer 206A-1 along the Y direction. The stack 206 may include another conductive layer 206A-2 not connected to the bottom layer 226. The conductive layer 206A-2 has an end 230 that contacts the dielectric layer (also called the sacrificial layer) 206D-2 of the stack 208. The end 228 of the conductive layer 206A-1 is located along the Y direction between the end 230 of the conductive layer 206A-2 and the body 224 of the contact structure 216. In other words, the end 228 of the conductive layer 206A-1 is further away from the gate line gap 218 along the Y direction than the end 230 of the conductive layer 206A-2.

[0078] Figure 3 A flowchart of example process 300 is shown. Process 300 can be performed to form a semiconductor device (e.g., Figures 1A-1B The semiconductor device 100 shown is referenced. Figures 2A-2Z To describe process 300. Process 300 may include forming Figures 2A-2Z The process of manufacturing a semiconductor structure in process 300 includes one or more steps. It should be understood that the operations shown in process 300 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 3 The different execution orders shown.

[0079] In operation 302, a semiconductor structure is formed (e.g., Figure 2W The semiconductor structure 200w includes a first stack (e.g., stack 206) of alternating conductive layers (e.g., conductive layer 206A) and isolation layers (e.g., isolation layer 206B) along a first direction (e.g., the Z direction) and a second stack (e.g., stack 208) of alternating dielectric layers (e.g., dielectric layer 206D) and isolation layers (e.g., isolation layer 206B) along the first direction. The semiconductor structure includes an array region (e.g., array region 202) and a connection region (e.g., connection region 204) adjacent to the array region in a second direction orthogonal to the first direction (e.g., the X direction). The second stack is located in the connection region and connected to the first stack.

[0080] In operation 304, a contact structure is formed that extends along a first direction through at least a portion of the second stack. In some embodiments, forming the contact structure includes forming a contact structure (e.g., Figure 2ZThe contact structure 216 includes a body (e.g., body 224) extending along a first direction and a bottom layer (e.g., bottom layer 226) extending along a third direction orthogonal to the first and second directions (e.g., the Y direction). The bottom layer of the contact structure is coupled to a first conductive layer (e.g., conductive layer 206A-1) of a first stack. The first conductive layer has an end (e.g., end 228) that contacts the bottom layer of the contact structure. A second conductive layer (e.g., conductive layer 206A-2) of the first stack has an end (e.g., end 230) that contacts a dielectric layer (e.g., dielectric layer 206D-2) of the second stack. The end of the first conductive layer is located between the end of the second conductive layer and the body of the contact structure along a third direction.

[0081] In some embodiments, process 300 includes a stack of sacrificial layers (e.g., sacrificial layer 206D) and isolation layers (e.g., isolation layer 206B) alternating with each other along a first direction. Figure 2A The stack 205). Process 300 also includes forming contact holes in the connection area (e.g., Figure 2C The contact hole 215). The contact hole extends along the first direction into the stack and reaches the first sacrificial layer in the sacrificial layer (e.g., Figure 2C The sacrificial layer 206D-1). Process 300 also includes forming a first space in the first sacrificial layer by removing a portion of the first sacrificial layer (e.g., Figure 2C Space 214). Process 300 also includes forming a filling body in the contact hole (e.g., by filling the contact hole and the first space with a first filling material). Figure 2E The filling body 209), and forms a filling layer in the first space (e.g., such as Figure 2E The filling layer 211 is in the middle. The filling body is connected to the filling layer, and the filling layer extends along a third direction (e.g., the Y direction) orthogonal to the first and second directions.

[0082] In some embodiments, forming the semiconductor structure includes forming a gate line gap extending along a first direction through the first stack (e.g., Figure 2A The gate line gap 218. The gate line gap includes a first segment (e.g., segment 220a) in the array region and a second segment (e.g., segment 220c) in the connection region. Isolation structure (e.g., Figure 2J The dielectric layer 223) is between the first segment and the second segment (e.g., along the X direction).

[0083] In some embodiments, forming a first space in the first sacrificial layer by removing a portion of the first sacrificial layer includes: etching away a first portion of the first sacrificial layer and portions of two isolation layers adjacent to the first sacrificial layer during a first time period of the etching process; and etching away a second portion of the first sacrificial layer during a second time period of the etching process (e.g., refer to...). Figure 2C-2 The first space (e.g., attached). Figure 2C-2 Space 214) in the first position (e.g., Figure 2C-2 At position 213a), the dimension along the first direction is smaller than that of the first space at the second position (e.g., Figure 2C-2 The dimension at position 213b) is along the first direction. The first position and the second position are arranged along the third direction between the gate line gap and the contact hole. Along the third direction, the first position is closer to the gate line gap than the second position.

[0084] In some implementations, forming the semiconductor structure includes forming a tunnel in the connection region by filling a second segment of the gate line gap with an etch solution to remove a portion of the sacrificial layer in the connection region (e.g., Figure 2M The tunnel 207). The tunnel is between the isolation layers, and a second segment of the gate line gap extends through the tunnel along the first direction. The sacrificial layer includes a first sacrificial layer (e.g., Figure 2M The sacrificial layer 206D-1) and the second sacrificial layer (e.g., Figure 2M The sacrificial layer 206D-2). The tunnel includes a first tunnel aligned with the infill layer and the first sacrificial layer along a third direction (e.g., Figure 2M Tunnel 207a) and a second tunnel aligned with the second sacrificial layer along a third direction (e.g., Figure 2M Tunnel 207b). The first tunnel exposes the filling layer, while the second tunnel exposes the end of the remaining portion of the second sacrificial layer (e.g., Figure 2M End portion 229).

[0085] In some implementations, forming a semiconductor structure includes removing a filler layer (e.g., Figure 2N The filling layer 211) is used to expand the first tunnel (e.g., the attached layer) along a third direction (e.g., the Y direction). Figure 2N Tunnel 207a). The enlarged first tunnel exposes the end of the remaining portion of the infill layer (e.g., end 211a). The end of the remaining portion of the infill layer extends along a third direction relative to the second sacrificial layer (e.g., Figure 2N The remaining portion of the sacrificial layer 206D-2) at the end (e.g., Figure 2N The second segment (e.g., segment 220c) further away from the gate line gap (e.g., gate line gap 218) at end 229.

[0086] In some embodiments, forming the semiconductor structure further includes filling with a second filler material (e.g., carbon) (e.g., as referenced). Figure 2O The second segment (e.g., segment 220c) and tunnel (e.g., tunnel 207) of the gate line gap (e.g., gate line gap 218) are also included. Forming the semiconductor structure further includes removing a sacrificial layer (e.g., sacrificial layer 206D) in the array region by filling the first segment (e.g., segment 220a) of the gate line gap with an etch solution. Forming the semiconductor structure also includes removing a second filler material (e.g., as referenced) from the second segment of the gate line gap and the tunnel. Figure 2V The semiconductor structure is further formed by using an isolation layer (e.g., Figure 2W A conductive layer (e.g., between the isolation layer 206B) forms a first stack body. Figure 2W The conductive layer 206A is used to form a first stack (e.g., stack 206). The conductive layer is formed by depositing at least a high-k dielectric material and a first conductive material (e.g., W) through a first segment and a second segment of the gate line gap. The conductive layer includes a padding layer (e.g., Figure 2W The first conductive layer (e.g., the padding layer 206C) is surrounded by the first conductive layer. Figure 2W The conductive layer 206A-1). The pad layer includes a first connected segment (e.g., Figure 2W Section 206C-1), the second section (for example, Figure 2W Section 206C-2) and the third section (e.g., Figure 2W The section shown is 206C-3). The first conductive layer is in the first isolation layer adjacent to the first conductive layer (e.g., Figure 2W The isolation layer 206B-1) and the second isolation layer (e.g., Figure 2W The first segment of the padding layer (e.g., 206B-2) lies between the first conductive layer (e.g., 206A-1) and the first insulating layer (e.g., 206B-1) along a first direction (e.g., the Z direction). The second segment of the padding layer (e.g., 206C-2) lies between the first conductive layer (e.g., 206A-1) and the second insulating layer (e.g., 206B-2) along a first direction (e.g., the Z direction). The third segment of the padding layer (e.g., 206C-3) lies between the first conductive layer (e.g., 206A-1) and the filler layer (e.g., 206B-2) along a third direction (e.g., the Y direction). Figure 2W Between the filling layer 211).

[0087] In some implementations, forming the semiconductor structure includes removing a first filler material from the contact hole (e.g., as referenced). Figure 2YThe semiconductor structure is further formed by removing a first filler material from a filler layer (e.g., filler layer 211) to form a first sacrificial layer (e.g., along a third direction (e.g., the Y direction)). Figure 2Y The second space aligned with the sacrificial layer 206D-1 (e.g., Figure 2Y The semiconductor structure is further comprising removing a third segment (e.g., segment 206C-3) of the pad layer to expose the first conductive layer. The semiconductor structure is further comprising forming a first recess (e.g., space 237) between the first conductive layer and the first insulating layer by removing a portion of the first segment of the pad layer connected to the third segment of the pad layer. Figure 2Y (Recess 239a). Forming the semiconductor structure also includes forming a second recess between the first conductive layer and the second insulating layer by removing a portion of the second segment of the pad layer that is connected to the third segment of the pad layer (e.g., Figure 2Y (Depression 239b).

[0088] In some embodiments, forming the contact structure includes forming the outer layer of the contact structure by depositing a second conductive material (e.g., TiN) through contact holes. Figure 2Z The outer layer 225) and the bottom layer of the contact structure (e.g., Figure 2Z The bottom layer 226). The outer layer contacts the inner surface of the contact hole. The bottom layer of the contact structure is in a second space aligned with the first sacrificial layer (e.g., Figure 2Y In space 237), and with the first conductive layer (e.g., Figure 2Z The conductive layer 206A-1) is a contact. The bottom layer of the contact structure includes a first portion in the first recess (e.g., Figure 2Z Part 226a) and the second part in the second recess (e.g., part 226b). The body of the contact structure (e.g., Figure 2Z The body 224 may be formed by depositing a first conductive material (e.g., W) into the contact hole. The body is surrounded by an outer layer.

[0089] Figure 4 A block diagram of an exemplary system 400 is shown. According to one or more embodiments of this disclosure, system 400 may have one or more semiconductor devices (e.g., memory devices). System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronics, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage. Figure 4As shown, system 400 may include a host device 408 and a storage system 402 having one or more storage devices 404 and a memory controller 406. The host device 408 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host device 408 may be configured to send data to or receive data from one or more storage devices 404.

[0090] Storage device 404 can be any storage device disclosed in this disclosure, such as Figures 1A-1B The illustrated memory device is a NAND flash memory. A memory controller 406 (also referred to as controller circuitry) is coupled to the memory device 404 and the host device 408. Consistent with embodiments of this disclosure, the memory device 404 may include a plurality of conductive interconnects passing through a cover layer, the plurality of conductive interconnects contacting conductive pads in a conductive pad layer, and the memory controller 406 may be coupled to the memory device 404 via at least one of the plurality of conductive interconnects. The memory controller 406 is configured to control the memory device 404. For example, the memory controller 406 may be configured to operate a plurality of channel structures via word lines. The memory controller 406 may manage data stored in the memory device 404 and communicate with the host device 408.

[0091] In some implementations, the memory controller 406 is designed / configured to operate in low-duty-cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media for electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 406 is designed / configured to operate in high-duty-cycle environments, such as SSDs or embedded multi-media cards (eMMCs) and enterprise storage arrays, where the SSDs or eMMCs serve as data storage for mobile devices such as smartphones, tablets, laptops, etc. The memory controller 406 can be configured to control the operation of the storage device 404, such as read, erase, and program (or write) operations. The memory controller 406 can also be configured to manage various functions regarding data stored or to be stored in the storage device 404, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 406 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 404. The memory controller 406 may also perform any other suitable function, such as formatting the memory device 404.

[0092] The memory controller 406 can communicate with external devices (e.g., host device 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0093] The memory controller 406 and one or more memory devices 404 can be integrated into various types of storage devices, such as being included in the same package, like a universal flash storage (UFS) package or an eMMC package. That is, the storage system 402 can be implemented and packaged into different types of end electronic products. In one example, such as... Figure 4 As shown, the memory controller 406 and a single storage device 404 can be integrated into the memory card 402. The memory card 402 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, smart media (SM) cards, Memory Sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0094] The subjects and embodiments of action and operation described in this disclosure can be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or combinations thereof. Embodiments of the subjects described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagated signal.

[0095] Note that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, incorporating other implementations to affect such feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0096] Generally, terms can be understood, at least in part, from their usage in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as “a,” “an,” or “the” can again be understood to convey either a singular or a plural usage. Furthermore, the term “based on” can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0097] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” something with an intermediate feature or layer between them. Furthermore, “above” or “on top of” means not only “above” or “on top of” something but also includes “above” or “on top of” something without an intermediate feature or layer between them (i.e., directly on).

[0098] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship of one element or feature to other elements (single or more) or features (single or more), as shown in the figures. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use or process steps. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0099] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a broad range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0100] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire undercoat or overcoat structure, or may have a range smaller than the undercoat or overcoat structure. Furthermore, a layer may be a region of a continuous structure whose thickness is less than the thickness of a uniform or non-uniform continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways (VIAs) are formed) and one or more dielectric layers.

[0101] As used herein, the term "nominal / nominal value" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a given quantity value that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a given quantity value that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0102] In this disclosure, the terms “horizontal / horizontally / laterally” refer to a surface that is parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” refer to a surface that is orthogonal to the lateral surface of the substrate.

[0103] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0104] This disclosure provides numerous different implementations or examples for carrying out various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include implementations in which the first and second features can be in direct contact, and may also include implementations in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0105] The foregoing description of a particular implementation can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementations.

[0106] While this disclosure contains numerous details of specific embodiments, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from a claimed combination may, in some cases, be removed from the combination, and the claims may be directed to sub-combinations or variations thereof.

[0107] Similarly, although the operations are depicted in the accompanying drawings in a specific order and are recited in the claims, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order, or to perform all the shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0108] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0109] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first stack of conductive and insulating layers alternating along a first direction, and a second stack of dielectric and insulating layers alternating along the first direction, wherein a connection region of the semiconductor device is adjacent to an array region of the semiconductor device in a second direction orthogonal to the first direction, and the second stack is located in the connection region and connected to the first stack; and A contact structure extending along the first direction through at least a portion of the second stack, wherein the contact structure comprises a body extending along the first direction and a bottom layer extending along a third direction orthogonal to the first and second directions. Wherein, a first conductive layer of the first stack is coupled to the bottom layer of the contact structure, the first conductive layer having an end that contacts the bottom layer of the contact structure, wherein a second conductive layer of the first stack has an end that contacts the dielectric layer of the second stack, and wherein the end of the first conductive layer is located between the end of the second conductive layer and the body of the contact structure along the third direction.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a gate line structure that extends through the first stack along the first direction, wherein the end of the first conductive layer is further away from the gate line structure along the third direction than the end of the second conductive layer.

3. The semiconductor device according to claim 2, wherein, The first conductive layer contacts the first pad layer and the second pad layer at the position of the end of the second conductive layer along the third direction, the first pad layer being between the first conductive layer and the first isolation layer adjacent to the first conductive layer, and the second pad layer being between the first conductive layer and the second isolation layer adjacent to the first conductive layer.

4. The semiconductor device according to claim 3, wherein, The first liner layer comprises a high-k dielectric material, and the second liner layer comprises the high-k dielectric material.

5. The semiconductor device according to claim 3, wherein, The bottom layer of the contact structure includes a first part and a second part. Wherein, the first portion lies between the first conductive layer and the first insulating layer along the first direction, and the first portion contacts the first padding layer along the third direction, and The second portion is located between the first conductive layer and the second insulating layer along the first direction, and the second portion contacts the second padding layer along the third direction.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The contact structure further includes an outer layer surrounding the body, and the outer layer and the body are connected to the bottom layer of the contact structure. The outer layer comprises a first conductive material, the bottom layer comprises the first conductive material, the main body comprises a second conductive material, and the conductive layer comprises the second conductive material.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The dimension of the bottom layer of the contact structure at the first position along the first direction is smaller than the dimension of the bottom layer of the contact structure at the second position along the first direction, and The first position and the second position are located between the first conductive layer and the contact structure along the third direction, and the first position is closer to the end of the first conductive layer than the second position along the third direction.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The contact structure is surrounded by contact spacers comprising a dielectric material.

9. A method for forming a semiconductor device, the method comprising: A semiconductor structure is formed, the semiconductor structure including a first stack of conductive layers and isolation layers alternating with each other along a first direction, and a second stack of dielectric layers and isolation layers alternating with each other along the first direction, wherein the semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction orthogonal to the first direction, and the second stack is located in the connection region and connected to the first stack; and A contact structure is formed, the contact structure extending along the first direction through at least a portion of the second stack. The contact structure includes: A contact structure is formed, the contact structure comprising a body extending along the first direction and a bottom layer extending along a third direction orthogonal to the first and second directions, wherein the bottom layer of the contact structure is coupled to a first conductive layer of the first stack, and wherein the first conductive layer has an end that contacts the bottom layer of the contact structure. The second conductive layer of the first stack has an end that contacts the dielectric layer of the second stack, and the end of the first conductive layer is located between the end of the second conductive layer and the body of the contact structure along the third direction.

10. The method according to claim 9, wherein, The method includes: A stack of sacrificial layers and isolation layers alternating with each other along the first direction is provided; A contact hole is formed in the connection region, wherein the contact hole extends along the first direction into the stack and reaches the first sacrificial layer in the sacrificial layer; A first space is formed in the first sacrificial layer by removing a portion of the first sacrificial layer; and By filling the contact hole and the first space with a first filling material, a filling body is formed in the contact hole and a filling layer is formed in the first space, wherein the filling body is connected to the filling layer and the filling layer extends along the third direction.

11. The method according to claim 10, wherein, Forming the semiconductor structure includes: A gate line gap is formed, which extends along the first direction through the first stack. The gate line gap includes a first segment in the array region and a second segment in the connection region, and the isolation structure is located between the first segment and the second segment along the second direction.

12. The method according to claim 11, wherein, Forming the first space in the first sacrificial layer by removing said portion of the first sacrificial layer includes: During the first time period of the etching process, a first portion of the first sacrificial layer and portions of the two isolation layers adjacent to the first sacrificial layer are etched away; and During the second time period of the etching process, a second portion of the first sacrificial layer is etched away. Wherein, the dimension of the first space at the first position along the first direction is smaller than the dimension of the first space at the second position along the first direction, the first position and the second position are arranged between the gate line gap and the contact hole along the third direction, and the first position along the third direction is closer to the gate line gap than the second position.

13. The method according to claim 11, wherein, Forming the semiconductor structure includes: A tunnel is formed in the connection region by filling the second segment of the gate line slot with an etch solution to remove a portion of the sacrificial layer in the connection region, wherein the tunnel is between the isolation layers, and the second segment of the gate line slot extends through the tunnel along the first direction. The sacrificial layer includes a first sacrificial layer and a second sacrificial layer, and the tunnel includes a first tunnel aligned with the filling layer and the first sacrificial layer along the third direction and a second tunnel aligned with the second sacrificial layer along the third direction. The first tunnel exposes the filling layer, and the second tunnel exposes the end of the remaining portion of the second sacrificial layer.

14. The method according to claim 13, wherein, Forming the semiconductor structure includes: The first tunnel is widened along the third direction by removing a portion of the filler layer, wherein the widened first tunnel exposes the end of the remaining portion of the filler layer, and the end of the remaining portion of the filler layer is further away from the second segment of the gate line gap along the third direction than the end of the remaining portion of the second sacrificial layer.

15. The method according to claim 14, wherein, Forming the semiconductor structure includes: The second segment of the gate line gap and the tunnel are filled with a second filler material; The sacrificial layer in the array region is removed by filling the first segment of the gate line gap with an etching solution; The second segment of the gate line gap and the second filler material in the tunnel are removed; and The first stack is formed by forming a conductive layer between the isolation layers, wherein the conductive layer is formed by depositing at least a high-k dielectric material and a first conductive material through the first segment and the second segment of the gate line gap, wherein the conductive layer includes a first conductive layer surrounded by a pad layer, the pad layer including a first segment, a second segment and a third segment connected together, the first conductive layer being between a first isolation layer and a second isolation layer adjacent to the first conductive layer, the first segment of the pad layer being between the first conductive layer and the first isolation layer along the first direction, the second segment of the pad layer being between the first conductive layer and the second isolation layer along the first direction, and the third segment of the pad layer being between the first conductive layer and the fill layer along the third direction.

16. The method according to claim 15, wherein, Forming the semiconductor structure includes: Remove the first filler material from the contact hole; By removing the first filler material from the filler layer, a second space aligned with the first sacrificial layer is formed along the third direction; Remove the third segment of the liner layer to expose the first conductive layer; A first recess is formed between the first conductive layer and the first insulating layer by removing a portion of the first segment of the liner that connects to the third segment of the liner; and A second recess is formed between the first conductive layer and the second insulating layer by removing a portion of the second segment of the liner layer that is connected to the third segment of the liner layer.

17. The method according to claim 16, wherein, Forming the contact structure includes: The outer layer and the bottom layer of the contact structure are formed by depositing a second conductive material through the contact hole, wherein the outer layer contacts the inner surface of the contact hole, and the bottom layer of the contact structure is in a second space aligned with the first sacrificial layer and contacts the first conductive layer, and the bottom layer of the contact structure includes a first portion in the first recess and a second portion in the second recess; and The body of the contact structure is formed by depositing the first conductive material into the contact hole, wherein the body is surrounded by the outer layer.

18. A storage system, comprising: Storage devices; as well as A memory controller, coupled to and configured to control the memory device. The storage device includes: A first stack of conductive and insulating layers alternating along a first direction, and a second stack of dielectric and insulating layers alternating along the first direction, wherein a connection region of the memory device is adjacent to an array region of the memory device in a second direction orthogonal to the first direction, and the second stack is located in the connection region and connected to the first stack; and A contact structure extending along the first direction through at least a portion of the second stack, wherein the contact structure comprises a body extending along the first direction and a bottom layer extending along a third direction orthogonal to the first and second directions. Wherein, a first conductive layer of the first stack is coupled to the bottom layer of the contact structure, the first conductive layer having an end that contacts the bottom layer of the contact structure, a second conductive layer of the first stack having an end that contacts the dielectric layer of the second stack, and the end of the first conductive layer is located between the end of the second conductive layer and the body of the contact structure along the third direction.

19. The storage system according to claim 18, wherein, The first conductive layer contacts the first pad layer and the second pad layer at the position of the end of the second conductive layer along the third direction, the first pad layer being between the first conductive layer and the first isolation layer adjacent to the first conductive layer, and the second pad layer being between the first conductive layer and the second isolation layer adjacent to the first conductive layer. and The bottom layer of the contact structure includes a first portion and a second portion. The first portion is located between the first conductive layer and the first insulating layer along the first direction and contacts the first padding layer along the third direction. The second portion is located between the first conductive layer and the second insulating layer along the first direction and contacts the second padding layer along the third direction.

20. The storage system according to claim 18 or claim 19, wherein, The dimension of the bottom layer of the contact structure at a first position along the first direction is smaller than the dimension of the bottom layer of the contact structure at a second position along the first direction. The first position and the second position are arranged between the first conductive layer and the contact structure along the third direction, and the first position is closer to the first conductive layer along the third direction than the second position.

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