Semiconductor device

Abstract

The semiconductor device includes: a chip having a first main surface; an IGBT region which is formed on the first main surface of the chip; a diode region formed on the first main surface of the chip and adjacent to the IGBT region in a first direction; a gate extension electrode extending across the IGBT region and the diode region continuously in the first direction in a region on the first main surface; and a trench gate structure formed on the first main surface of the chip and extending across the gate extension electrode, the gate extension electrode avoiding a portion directly above the trench gate structure and selectively having a gate resistor at a portion across the diode region.

Description

[0001] This application corresponds to Japanese Patent Application No. 2023-084043 filed on May 22, 2023 with the Japan Patent Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to a semiconductor device. BACKGROUND

[0003] Patent Document 1 discloses an RC-IGBT (Reverse Conducting - Insulated Gate Bipolar Transistor) as an example of a semiconductor device. The RC-IGBT includes an IGBT region and a diode region that are fabricated in common semiconductor layers. The IGBT region includes an IGBT. The diode region includes a diode.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT DOCUMENTS

[0006] Patent Document 1: International Publication No. 2020 / 080476 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] One embodiment of the present application provides a semiconductor device that has a gate resistance without impairing an effective area of an IGBT region.

[0009] SOLUTION TO THE PROBLEM

[0010] One embodiment of the present application provides a semiconductor device including: a chip having a first main surface; an IGBT region formed on the first main surface of the chip; a diode region formed on the first main surface of the chip, adjacent to the IGBT region in a first direction; a gate extension electrode extending continuously across the IGBT region and the diode region in the first direction in a region on the first main surface; and a trench gate structure formed on the first main surface of the chip, extending across the gate extension electrode, a portion of the gate extension electrode avoiding directly above the trench gate structure, and selectively having a gate resistance body in a portion crossing the diode region.

[0011] EFFECT OF THE INVENTION

[0012] According to one embodiment of the present application, it is possible to provide a semiconductor device that has a gate resistance without impairing an effective area of an IGBT region. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1is a schematic plan view of a semiconductor device of one embodiment of the present disclosure.

[0014] Figure 2 is a schematic plan view for describing an internal structure of the semiconductor device.

[0015] Figure 3 is Figure 2 is an enlarged view of a portion surrounded by III of FIG. 1.

[0016] Figure 4 is a cross-sectional view along IV-IV line of FIG. 1. Figure 3

[0017] Figure 5 is a cross-sectional view along V-V line of FIG. 1. Figure 3

[0018] Figure 6 is a cross-sectional view along VI-VI line of FIG. 1. Figure 3

[0019] Figure 7 is a cross-sectional view along VII-VII line of FIG. 1. Figure 3

[0020] Figure 8 is a cross-sectional view along VIII-VIII line of FIG. 1. Figure 3

[0021] Figure 9 is a cross-sectional view along IX-IX line of FIG. 1. Figure 3

[0022] Figure 10 is a cross-sectional view along X-X line of FIG. 1. Figure 3

[0023] Figure 11 is a cross-sectional view along XI-XI line of FIG. 1. Figure 3

[0024] Figure 12 is an enlarged view of a portion surrounded by XII of FIG. 1. Figure 2

[0025] Figure 13 is a cross-sectional view along XIII-XIII line of FIG. 1. Figure 12

[0026] is a diagram showing a modification example of the gate-assisted trench structure of FIG. 1. Figure 14 Figure 12 is a diagram showing a modification example of the gate-assisted trench structure of FIG. 1.

[0027] Figure 15 Figure 12 is a diagram showing a modification example of the gate-assisted trench structure of FIG. 1. ​​​​​​​​​​​

[0028] Figure 16 is a view showing a modification example of the gate-assisted trench structure of Figure 12

[0029] Figure 17 is an enlarged view of a portion surrounded by XVII of Figure 2

[0030] Figure 18 is a sectional view along lines XVIII-XVIII of Figure 17

[0031] Figure 19 is a sectional view along lines XIX-XIX of Figure 17

[0032] Figure 20 is a view showing a modification example of the arrangement pattern of the IGBT region and the diode region.

[0033] Figure 21 is an enlarged view of a portion surrounded by XXI of Figure 20 DETAILED DESCRIPTION

[0034] Next, an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0035] Figure 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure.

[0036] The semiconductor device 1 is an electronic component having an RC-IGBT (Reverse Conducting - Insulated Gate Bipolar Transistor) that integrally has an IGBT and a diode. The semiconductor device 1 includes a rectangular parallelepiped-shaped semiconductor chip 2. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4.

[0037] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in plan view (hereinafter, simply referred to as "plan view") observed from the normal direction Z thereof. The first main surface 3 and the second main surface 4 can also be referred to as a surface and a back surface of the semiconductor chip 2, respectively. The side surface 5A and the side surface 5C extend along a first direction X and are opposed to each other in a second direction Y that intersects the first direction X. The side surface 5B and the side surface 5D extend along the second direction Y and are opposed to each other in the first direction X. Specifically, the second direction Y is orthogonal to the first direction X.

[0038] ​​​​​An electrode film 6 is formed on the first main surface 3. The electrode film 6 includes a plurality of terminal electrodes 7 to 12 and a plurality of wirings 13 to 15. The plurality of terminal electrodes 7 to 11 are arranged at intervals along the side surfaces of the semiconductor chip 2. The plurality of terminal electrodes 7 to 11 are gathered on one side surface (side surface 5B in the present embodiment) of the semiconductor chip 2 and arranged in a row along the side surface 5B. Figure 1

[0039] The electrode film 6 includes a gate terminal electrode 7 and a gate wiring 13 as a structure associated with a gate of the RC-IGBT. The gate wiring 13 transmits a gate signal applied to the gate terminal electrode 7 to the gate of the IGBT.

[0040] The gate terminal electrode 7 is disposed at a central position of the plurality of terminal electrodes 7 to 11. The gate wiring 13 integrally includes a first portion 16 in a ring shape leading from the gate terminal electrode 7 along the side surfaces 5A to 5D of the semiconductor chip 2 and a second portion 17 crossing an active region 18 surrounded by the first portion 16. The gate wiring 13 can also be referred to as a gate finger. In addition, the first portion 16 and the second portion 17 of the gate wiring 13 can also be referred to as an outer side gate finger and an inner side gate finger, respectively. In addition, the first portion 16 and the second portion 17 of the gate wiring 13 can also be referred to as an outer side extension electrode and an inner side extension electrode, respectively.

[0041] The active region 18 is a region in which the RC-IGBT is formed. A region outside the active region 18 is a peripheral region 19. The peripheral region 19 extends in a band shape along a periphery of the active region 18. Specifically, the peripheral region 19 is set to a ring shape (a four-sided ring shape) surrounding the active region 18 in a plan view.

[0042] The active region 18 is divided into a plurality of divided regions 20 by the second portion 17 of the gate wiring 13. The plurality of divided regions 20 are each a rectangular shape extending along the first direction X. The plurality of divided regions 20 are adjacent across the second portion 17 of the gate wiring 13.

[0043] In this manner, the plurality of second portions 17 of the gate wiring 13 cross the active region 18. The plurality of second portions 17 are arranged at intervals in the second direction Y and formed in a stripe shape extending in the first direction X. One end portion and the other end portion of each second portion 17 are connected to different positions in the first portion 16. Each second portion 17 can be such that a base end portion (may also be referred to as a terminal side end portion or a pad side end portion) on the plurality of terminal electrodes 7 to 11 is connected to the first portion 16 and an opposite end portion is not connected to the first portion 16 and becomes a terminal end portion.

[0044] The plurality of second portions 17 include a central wiring 21 extending from a vicinity of the gate terminal electrode 7 and a plurality of side wirings 22 extending from positions apart from the gate terminal electrode 7 in the second direction Y. In the present embodiment, the central wiring 21 is a wiring extending from the vicinity of the gate terminal electrode 7 in the second direction Y.​Figure 1 In the embodiment, one central wiring 21 and two side wirings 22 each on both sides of the second direction Y of the central wiring 21 are provided. Thereby, the active region 18 is divided into six divided regions 20.

[0045] The electrode film 6 includes an emitter terminal electrode 12 as a structure associated with an emitter of the RC-IGBT. The emitter terminal electrode 12 is disposed in each of the divided regions 20. In this way, the emitter terminal electrode 12 is provided one for each of the divided regions 20. A number of the emitter terminal electrodes 12 equal to the number of the divided regions 20 are provided. Of course, a number of the emitter terminal electrodes 12 that are physically separated from each other can be provided in each of the divided regions 20.

[0046] The electrode film 6 also includes a first sense terminal electrode 8, a second sense terminal electrode 9, a current detection terminal electrode 10, and an open terminal electrode 11. The first sense terminal electrode 8 and the second sense terminal electrode 9 transmit a control signal of a sensor region 23 (temperature sensor) disposed at the center of the active region 18. The current detection terminal electrode 10 is an electrode for detecting a current flowing through the active region 18 and taking out to the outside. The open terminal electrode 11 becomes in an electrically floating state.

[0047] The electrode film 6 includes a first sense wiring 14 and a second sense wiring 15. The first sense wiring 14 is electrically connected to the first sense terminal electrode 8. The first sense wiring 14 extends from the peripheral region 19 toward the sensor region 23. The first sense wiring 14 transmits a control signal of the temperature sensor. The second sense wiring 15 is electrically connected to the second sense terminal electrode 9. The second sense wiring 15 extends from the peripheral region 19 toward the sensor region 23. The second sense wiring 15 transmits a control signal of the temperature sensor. The gate wiring 13 (central wiring 21), the first sense wiring 14, and the second sense wiring 15 are parallel at intervals in the first direction X.

[0048] Figure 2 is a schematic plan view for explaining the internal structure of the semiconductor device 1. In Figure 2 In the embodiment, for the sake of clarity, the terminal electrodes 7 to 11 and the gate wiring 13 in the electrode film 6 are shown, and other parts of the electrode film 6 are omitted.

[0049] The active region 18 includes an IGBT region 24 and a diode region 25. In the embodiment, for the sake of clarity, the IGBT region 24 is indicated by hatching. The IGBT region 24 is a region in which an IGBT is formed. The diode region 25 is a region in which a diode is formed. The diode region 25 is adjacent to the IGBT region 24. Figure 2

[0050] ​Specifically, the active region 18 includes the RC-IGBT arrangement 26. The RC-IGBT arrangement 26 is formed with a plurality of (six in this mode) at intervals in the second direction Y. Adjacent RC-IGBT arrangements 26 are separated by the gate wiring 13. The RC-IGBT arrangement 26 has a first end portion on one side (side 5B side) and a second end portion on the other side (side 5D side). The first end portion of the RC-IGBT arrangement 26 can also be referred to as a terminal side end portion, a pad side end portion. The second end portion of the RC-IGBT arrangement 26 can also be referred to as a terminal side end portion.

[0051] The RC-IGBT arrangement 26 has a ring-shaped arrangement repeatedly including the diode region 25, the IGBT region 24, the diode region 25, the IGBT region 24, the diode region 25, ··· arranged in a row along the first direction X from the first end portion toward the second end portion. In this mode, the first end portion of the RC-IGBT arrangement 26 is formed by the diode region 25. In this mode, the second end portion of the RC-IGBT arrangement 26 is formed by the diode region 25. The first end portion of the RC-IGBT arrangement 26 can also be formed by the IGBT region 24. The second end portion of the RC-IGBT arrangement 26 can also be formed by the IGBT region 24.

[0052] In this way, the plurality of IGBT regions 24 are arranged dispersedly in the active region 18. The plurality of IGBT regions 24 are formed at intervals along the first direction X and the second direction Y. In this mode, the plurality of IGBT regions 24 are arranged in a matrix shape in plan view. The plurality of IGBT regions 24 oppose each other along the first direction X and oppose each other along the second direction Y.

[0053] In this mode, the plurality of IGBT regions 24 are each formed in a quadrangular shape in plan view. Specifically, the plurality of IGBT regions 24 are each formed in an oblong shape extending along the second direction Y.

[0054] The width WI of each IGBT region 24 in the first direction X can also be 10 μm or more and 1000 μm or less. The width WI can be 10 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and 1000 μm or less. The width WI is preferably 100 μm or more. The width WI is further preferably 200 μm or more.

[0055] The plurality of diode regions 25 are dispersedly arranged in the active region 18. The plurality of diode regions 25 are formed at intervals along the first direction X and the second direction Y. In this manner, the plurality of diode regions 25 are arranged in a matrix shape in plan view. The plurality of diode regions 25 are opposed to each other along the first direction X, and are opposed to each other along the second direction Y.

[0056] Specifically, the plurality of diode regions 25 are each formed so as to be adjacent to the IGBT region 24 in the first direction X. In this manner, the plurality of diode regions 25 are each formed in a quadrangular shape in plan view. Specifically, the plurality of diode regions 25 are each formed in an oblong shape extending along the second direction Y.

[0057] The planar area of each diode region 25 is preferably equal to or smaller than the planar area of each IGBT region 24. The planar area of each diode region 25 is more preferably smaller than the planar area of each IGBT region 24. The width WD of each diode region 25 in the first direction X is preferably equal to or smaller than the width WI of each IGBT region 24. The width WD of each diode region 25 is more preferably smaller than the width WI of each IGBT region 24.

[0058] The width WD can be equal to or greater than 5 μm and less than 1000 μm. The width WD can be equal to or greater than 5 μm and less than 1000 μm, equal to or greater than 5 μm and less than 100 μm, equal to or greater than 100 μm and less than 200 μm, equal to or greater than 200 μm and less than 300 μm, equal to or greater than 300 μm and less than 400 μm, equal to or greater than 400 μm and less than 500 μm, equal to or greater than 500 μm and less than 600 μm, equal to or greater than 600 μm and less than 700 μm, equal to or greater than 700 μm and less than 800 μm, equal to or greater than 800 μm and less than 900 μm, or equal to or greater than 900 μm and less than 1000 μm. The width WD is preferably equal to or greater than 100 μm. The width WD is more preferably equal to or greater than 200 μm.

[0059] Next, one manner of the planar structure of the active region 18 will be described. Figure 3 is Figure 2 is an enlarged view of the portion surrounded by III, and shows a part of the plurality of IGBT regions 24 and the plurality of diode regions 25. The planar structure of the IGBT region 24 and the diode region 25 described below can be applied to all of the IGBT regions 24 and all of the diode regions 25 of the semiconductor chip 2, or can be selectively applied to several IGBT regions 24 and diode regions 25. That is, the planar structure described below is a structure that can be applied to at least one IGBT region 24 and diode region 25.

[0060] Referring to Figure 3On the first main surface 3 of the semiconductor chip 2, a plurality of trench electrode structures 27 to 29 are formed in a stripe shape. The plurality of trench electrode structures 27 to 29 extend in parallel along the second direction Y. In this way, the plurality of trench electrode structures 27 to 29 are a trench gate structure 27, an emitter trench structure 28, and a diode-side trench structure 29. In Figure 3 In the figure, the trench gate structure 27, the emitter trench structure 28, and the diode-side trench structure 29 are indicated by hatching.

[0061] The plurality of trench gate structures 27 are formed in the IGBT region 24. The trench gate structure 27 is formed in a band shape extending along the second direction Y in plan view. The plurality of trench gate structures 27 are formed in a stripe shape as a whole. The plurality of trench gate structures 27 cross directly below the gate wiring 13 from one side to the other side in the second direction Y. Thus, the shared trench gate structure 27 spans the plurality of division regions 20. The trench gate structure 27 has a terminal portion 30 at each of one side and the other side in the second direction Y. In Figure 3 In the figure, the terminal portion 30 at one side is shown.

[0062] The terminal portion 30 of the trench gate structure 27 is formed for each of a pair of trench gate structures 27. The terminal portion 30 connects the adjacent trench gate structures 27 through the outer peripheral region 19. The terminal portion 30 is formed in a circular shape in plan view.

[0063] The plurality of emitter trench structures 28 are formed in the IGBT region 24. The emitter trench structure 28 is formed in a band shape extending along the second direction Y in plan view. The plurality of emitter trench structures 28 extend side by side with the trench gate structure 27, and the plurality of emitter trench structures 28 and the trench gate structure 27 are formed in a stripe shape as a whole. The plurality of emitter trench structures 28 are sandwiched by the plurality of trench gate structures 27 in the first direction X. In this way, a pair of emitter trench structures 28 are sandwiched by the plurality of trench gate structures 27 in the first direction X.

[0064] The plurality of emitter trench structures 28 do not cross the gate wiring 13, and have a terminal portion 31 on the inner side of the IGBT region 24 away from the gate wiring 13 in the second direction Y. The terminal portion 31 of the emitter trench structure 28 is formed for each of a pair of emitter trench structures 28. The terminal portion 31 connects the adjacent emitter trench structures 28 within the IGBT region 24. The terminal portion 31 is formed in a circular shape in plan view.

[0065] A plurality of diode-side trench structures 29 are formed in the diode region 25. The diode-side trench structures 29 are formed in a band shape extending along the second direction Y in plan view. The plurality of diode-side trench structures 29 are formed as a whole in a stripe shape. The plurality of diode-side trench structures 29 cross directly below the gate wiring 13 from one side to the other side of the second direction Y. Thus, the shared diode-side trench structure 29 spans the plurality of division regions 20. The diode-side trench structure 29 has a terminal portion 32 at each of one side and the other side of the second direction Y. In Figure 3 The terminal portion 32 at one side is shown.

[0066] The terminal portion 32 of the diode-side trench structure 29 is formed with one for each of the pair of diode-side trench structures 29. The terminal portion 32 connects the adjacent diode-side trench structures 29 through the outer peripheral region 19. The terminal portion 32 is formed in a circular shape in plan view.

[0067] The gate wiring 13 is an electrode extending across the plurality of trench gate structures 27 in the first direction X. The gate wiring 13 can also be referred to as a gate extension electrode 33. The gate extension electrode 33 includes a first electrode layer 34 and a second electrode layer 35.

[0068] The second electrode layer 35 is a layer laminated on the first electrode layer 34. The second electrode layer 35 is an electrode layer present on the most surface of the gate extension electrode 33, and can also be referred to as a surface layer. The second electrode layer 35 is a layer having a lower resistance than the first electrode layer 34. The second electrode layer 35 has a contour coinciding with that of the gate extension electrode 33. In this way, the second electrode layer 35 is formed in a band shape extending continuously across the plurality of IGBT regions 24 and the plurality of diode regions 25 arranged alternately. The second electrode layer 35 is a band shape having a constant width in the second direction Y.

[0069] The first electrode layer 34 is formed avoiding the region directly above the diode-side trench structure 29. Specifically, the first electrode layer 34 is selectively divided at a non-contact interval 36 where the second electrode layer 35 and the diode region 25 are opposed to each other. Thus, the first electrode layer 34 is disposed selectively at a contact interval 37 where the second electrode layer 35 and the IGBT region 24 are opposed to each other. That is, the gate extension electrode 33 does not have the first electrode layer 34 directly above the trench gate structure 27, but selectively has the second electrode layer 35. The first electrode layer 34 is formed in a band shape longer in the first direction X, covering the plurality of trench gate structures 27 together. The first electrode layer 34 is a layer electrically connected to the plurality of trench gate structures 27, and can also be referred to as a first contact layer 38.

[0070] A second contact layer 39 is formed on the first main surface 3 of the semiconductor chip 2. The second contact layer 39 is a layer that is electrically connected to the plurality of diode-side trench structures 29. The second contact layer 39 is formed in a band shape that is long in the first direction X, and covers the plurality of diode-side trench structures 29 together. In this way, the second contact layer 39 is separated from the gate extension electrode 33 toward the inner side of the diode region 25, and extends in parallel with the gate extension electrode 33.

[0071] A third contact layer 40 is formed on the first main surface 3 of the semiconductor chip 2. The third contact layer 40 is a layer that is electrically connected to the plurality of emitter trench structures 28. The third contact layer 40 is formed in a planar island shape, and covers the terminal portions 31 of the pair of emitter trench structures 28 together.

[0072] Next, one way of the cross-sectional structure of the active region 18 will be described. Figure 4 is a cross-sectional view along the IV-IV line of Figure 3 Figure 5 is a cross-sectional view along the V-V line of Figure 3 . First, the basic cross-sectional structure of the IGBT region 24 and the diode region 25 will be described with reference to Figure 4 and Figure 5 .

[0073] The semiconductor device 1 includes an n - type drift region 41 formed inside the semiconductor chip 2. Specifically, the drift region 41 is formed in the entire region of the semiconductor chip 2 in the first direction X and the second direction Y. The drift region 41 is formed in the surface layer portion of the first main surface 3 of the semiconductor chip 2 in the normal direction Z (the thickness direction of the semiconductor chip 2). The n-type impurity concentration of the drift region 41 can be 1.0 x 1015cm 13 -3 or less and 1.0 x 1018cm 15 -3 or more.

[0074] In this way, the semiconductor chip 2 has a single-layer structure including an n - type semiconductor substrate 42. The semiconductor substrate 42 can also be a silicon FZ substrate formed by the FZ (Floating Zone) method. The drift region 41 is formed from the semiconductor substrate 42.

[0075] ​​​The semiconductor device 1 includes a collector terminal electrode 43 formed on the second main face 4 of the semiconductor chip 2. The collector terminal electrode 43 is electrically connected to the second main face 4. Specifically, the collector terminal electrode 43 is electrically connected to the IGBT region 24 (a collector region 45 described later) and the diode region 25 (a cathode region 58 described later). The collector terminal electrode 43 forms an ohmic contact with the second main face 4. The collector terminal electrode 43 transmits a collector signal to the IGBT region 24 and the diode region 25.

[0076] The collector terminal electrode 43 can also include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The collector terminal electrode 43 can also have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The collector terminal electrode 43 can also have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner.

[0077] The semiconductor device 1 includes an n-type buffer layer 44 formed in a surface layer portion of the second main face 4 of the semiconductor chip 2. The buffer layer 44 can be formed in the entire region of the surface layer portion of the second main face 4. The n-type impurity concentration of the buffer layer 44 is greater than the n-type impurity concentration of the drift region 41. The n-type impurity concentration of the buffer layer 44 can be 1.0 x 1018cm-3or more and 1.0 x 1020cm-3or less. 15 cm -3 The n-type impurity concentration of the buffer layer 44 can be 1.0 x 1018cm-3or more and 1.0 x 1020cm-3or less. 17 cm -3 The n-type impurity concentration of the buffer layer 44 can be 1.0 x 1018cm-3or more and 1.0 x 1020cm-3or less.

[0078] The thickness of the buffer layer 44 can be 0.5 μm or more and 30 μm or less. The thickness of the buffer layer 44 can be 0.5 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less.

[0079] Each IGBT region 24 includes a p-type collector region 45 formed in a surface layer portion of the second main face 4 of the semiconductor chip 2. The collector region 45 is exposed from the second main face 4. The collector region 45 can also be formed in the entire region of the IGBT region 24 in the surface layer portion of the second main face 4. The p-type impurity concentration of the collector region 45 can be 1.0 x 1018cm-3or more and 1.0 x 1020cm-3or less. 15 cm -3 The p-type impurity concentration of the collector region 45 can be 1.0 x 1018cm-3or more and 1.0 x 1020cm-3or less. 18 cm -3 The p-type impurity concentration of the collector region 45 can be 1.0 x 1018cm-3or more and 1.0 x 1020cm-3or less. The collector region 45 forms an ohmic contact with the collector terminal electrode 43.

[0080] Each IGBT region 24 includes an FET structure 46 formed on the first main face 3 of the semiconductor chip 2. In this mode, each IGBT region 24 includes a trench gate type FET structure 46. Specifically, the FET structure 46 includes a trench gate structure 27 formed on the first main face 3.

[0081] The trench gate structure 27 is formed with a plurality of trenches spaced apart in the first direction X in the IGBT region 24. The distance between two trench gate structures 27 adjacent to each other in the first direction X can also be 1 μm or more and 8 μm or less. The distance between the two trench gate structures 27 can also be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, or 7 μm or more and 8 μm or less.

[0082] Each trench gate structure 27 includes a gate trench 47, a gate insulating layer 48, and a gate electrode layer 49. The gate trench 47 is formed on the first main face 3. The gate trench 47 includes a side wall and a bottom wall. The side wall of the gate trench 47 can also be formed perpendicularly with respect to the first main face 3.

[0083] The side wall of the gate trench 47 can also be inclined downward from the first main face 3 toward the bottom wall. The gate trench 47 can also be formed in a tapered shape in which the opening area of the opening side is larger than the bottom area. The bottom wall of the gate trench 47 can also be formed parallel with respect to the first main face 3. The bottom wall of the gate trench 47 can also be formed in a curved shape toward the second main face 4. The gate trench 47 includes a bottom wall edge portion. The bottom wall edge portion connects the side wall and the bottom wall of the gate trench 47. The bottom wall edge portion can also be formed in a curved shape toward the second main face 4.

[0084] The depth D1 of the gate trench 47 can be 2 μm or more and 10 μm or less. The depth D1 of the gate trench 47 can also be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D1 of the gate trench 47 can also be defined as the distance from the deepest portion of the bottom wall of the gate trench 47 to the first main face 3.

[0085] The width of the gate trench 47 can be 0.5 μm or more and 3 μm or less. The width of the gate trench 47 is the width of the gate trench 47 in the first direction X. The width of the gate trench 47 can be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0086] The gate insulating layer 48 is formed in a film shape along the inner wall of the gate trench 47. The gate insulating layer 48 divides a recess space within the gate trench 47. In this mode, the gate insulating layer 48 contains a silicon oxide film. The gate insulating layer 48 can also contain a silicon nitride film instead of or in addition to the silicon oxide film.

[0087] The gate electrode layer 49 is embedded in the gate trench 47 through the gate insulating layer 48. Specifically, the gate electrode layer 49 is embedded in the recess space divided by the gate insulating layer 48 in the gate trench 47. The gate electrode layer 49 is controlled by a gate signal. The gate electrode layer 49 can also contain conductive polysilicon.

[0088] The FET structure 46 contains a p-type body region 50 formed in a surface layer portion of the first main face 3 of the semiconductor chip 2. The p-type impurity concentration of the body region 50 can be 1.0 x 10 17 cm -3 or more and 1.0 x 10 18 cm -3 or less. The body region 50 is formed on both sides of the trench gate structure 27, respectively. The body region 50 is formed in a strip shape extending along the trench gate structure 27 when viewed in plan. The body region 50 is exposed from the side wall of the gate trench 47. The bottom portion of the body region 50 is formed in a region between the first main face 3 and the bottom wall of the gate trench 47 in the normal direction Z.

[0089] The FET structure 46 contains an n + type emitter region 51 formed in a surface layer portion of the body region 50. The n-type impurity concentration of the emitter region 51 is greater than the n-type impurity concentration of the drift region 41. The n-type impurity concentration of the emitter region 51 can be 1.0 x 10 19 cm -3 or more and 1.0 x 10 20 cm -3 or less.

[0090] In this mode, the FET structure 46 contains a plurality of emitter regions 51 formed on both sides of the trench gate structure 27. The emitter region 51 is formed in a strip shape extending along the trench gate structure 27 when viewed in plan. The emitter region 51 is exposed from the side wall of the first main face 3 and the gate trench 47. The bottom portion of the emitter region 51 is formed in a region between the upper end portion of the gate electrode layer 49 and the bottom portion of the body region 50 in the normal direction Z.

[0091] In this mode, the FET structure 46 contains an n +The carrier storage region 52 has a higher n-type impurity concentration than the drift region 41. The n-type impurity concentration in the carrier storage region 52 can be 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 17 cm -3 the following.

[0092] In this configuration, the FET structure 46 includes a plurality of carrier storage regions 52 formed on both sides of the trench gate structure 27. When viewed from above, the carrier storage regions 52 are formed as strips extending along the trench gate structure 27. The carrier storage regions 52 are exposed from the sidewalls of the gate trench 47. The bottom of the carrier storage regions 52 is formed in the normal direction Z in the region between the bottom of the body region 50 and the bottom wall of the gate trench 47.

[0093] The carrier storage region 52 suppresses the supply of carriers (holes) to the semiconductor chip 2 from being pulled back (discharged) into the main body region 50. As a result, holes accumulate in the region directly below the FET structure 46 in the semiconductor chip 2. Consequently, both the on-resistance and the on-voltage are reduced.

[0094] The FET structure 46 includes contact trenches 53 formed on the first main surface 3 of the semiconductor chip 2. In this configuration, the FET structure 46 includes a plurality of contact trenches 53 formed on both sides of the trench gate structure 27. The contact trenches 53 expose the emitter region 51. In this configuration, the contact trenches 53 extend through the emitter region 51.

[0095] The contact trench 53 and the trench gate structure 27 are formed at intervals in the first direction X. When viewed from above, the contact trench 53 extends in a strip shape along the trench gate structure 27.

[0096] FET structure 46 includes a p-type FET formed in a region along the bottom wall of contact trench 53 in body region 50. + Contact region 54. The p-type impurity concentration in contact region 54 is greater than that in the main body region 50. The p-type impurity concentration in contact region 54 can be 1.0 × 10⁻⁶. 19 cm -3 Above and 1.0×10 20 cm -3 the following.

[0097] The contact area 54 is exposed from the bottom wall of the contact groove 53. The contact area 54 extends in a strip shape along the contact groove 53 when viewed from above. The bottom of the contact area 54 is formed in the normal direction Z in the area between the bottom wall of the contact groove 53 and the bottom of the main body area 50.

[0098] Thus, in the FET structure 46, the gate electrode layer 49 opposes the body region 50 and the emitter region 51 with the gate insulating layer 48 interposed therebetween. In this manner, the gate electrode layer 49 also opposes the carrier storage region 52 with the gate insulating layer 48 interposed therebetween. An IGBT channel is formed in a region between the emitter region 51 and the drift region 41 (carrier storage region 52) in the body region 50. The on / off of the channel is controlled by a gate signal.

[0099] Each IGBT region 24 includes an emitter trench structure 28 in the first main face 3 of the semiconductor chip 2. Specifically, each IGBT region 24 includes a plurality of emitter trench structures 28 formed on both sides of the FET structure 46. The emitter trench structure 28 is formed in a region adjacent to the FET structure 46 in a surface layer portion of the first main face 3. The emitter trench structure 28 is formed in a band shape extending along the second direction Y in plan view. The emitter trench structure 28 can also be in a band shape parallel to the trench gate structure 27.

[0100] The emitter trench structure 28 includes an emitter trench 55, an emitter insulating layer 56, and an emitter potential electrode layer 57. The emitter trench 55 is formed in the first main face 3 of the semiconductor chip 2. The emitter trench 55 includes a side wall and a bottom wall. The side wall of the emitter trench 55 can also be formed perpendicularly with respect to the first main face 3.

[0101] The side wall of the emitter trench 55 can also be inclined downward from the first main face 3 toward the bottom wall. The emitter trench 55 can also be formed in a tapered shape in which an opening area of an opening side is larger than a bottom area. The emitter region 51, the body region 50, and the carrier storage region 52 are exposed from the side wall (outer side wall) of the emitter trench 55 facing the FET structure 46. The bottom wall of the emitter trench 55 can also be formed parallel with respect to the first main face 3. The bottom wall of the emitter trench 55 can also be formed in a curved shape toward the second main face 4. The emitter trench 55 includes a bottom wall edge portion. The bottom wall edge portion connects the side wall and the bottom wall of the emitter trench 55. The bottom wall edge portion can also be formed in a curved shape toward the second main face 4 of the semiconductor chip 2.

[0102] The depth D3 of the emitter trench 55 can be 2 pm or more and 10 pm or less. The depth D3 of the emitter trench 55 can also be 2 pm or more and 3 pm or less, 3 pm or more and 4 pm or less, 4 pm or more and 5 pm or less, 5 pm or more and 6 pm or less, 6 pm or more and 7 pm or less, 8 pm or more and 9 pm or less, or 9 pm or more and 10 pm or less. The depth D3 of the emitter trench 55 can also be equal to the depth D1 of the gate trench 47.

[0103] The width of the emitter trench 55 can also be 0.5 μm or more and 3 μm or less. The width of the emitter trench 55 is the width of the emitter trench 55 in the first direction X. The width of the emitter trench 55 can also be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the emitter trench 55 can also be equal to the width of the gate trench 47.

[0104] An emitter insulating layer 56 is formed as a film along the inner wall of the emitter trench 55. The emitter insulating layer 56 divides a recessed space within the emitter trench 55. In this configuration, the emitter insulating layer 56 comprises a silicon oxide film. The emitter insulating layer 56 may also replace the silicon oxide film or may comprise a silicon nitride film.

[0105] The emitter potential electrode layer 57 is embedded in the emitter trench 55, separated by the emitter insulating layer 56. Specifically, the emitter potential electrode layer 57 is embedded in the recessed space defined by the emitter insulating layer 56 within the emitter trench 55. The emitter potential electrode layer 57 may contain conductive polysilicon. The emitter potential electrode layer 57 is controlled by an emitter signal.

[0106] Reference Figure 5 Each diode region 25 is contained within the surface layer of the second main surface 4 of the semiconductor chip 2. + The cathode region 58 (second impurity region) is a type of region. The n-type impurity concentration in cathode region 58 is greater than that in drift region 41. The n-type impurity concentration in cathode region 58 can be 1.0 × 10⁻⁶. 19 cm -3 Above and 1.0×10 20 cm -3 Below. The cathode region 58 is exposed from the second main surface 4. The cathode region 58 forms an ohmic contact with the collector terminal electrode 43.

[0107] Each diode region 25 includes a unit separation structure 60 that divides the diode unit regions 59. Specifically, each diode region 25 includes multiple unit separation structures 60 that respectively divide multiple diode unit regions 59. The unit separation structure 60 and Figure 3 The diode-side trench structure 29 corresponds to this.

[0108] The unit separation structure 60 includes a unit separation trench 61, a unit separation insulating layer 62, and a unit separation electrode layer 63. The unit separation trench 61 is formed on the first main surface 3. The unit separation trench 61 includes sidewalls and a bottom wall. The sidewalls of the unit separation trench 61 may also be formed perpendicular to the first main surface 3.

[0109] The side wall of the cell separation trench 61 can also be inclined downward from the first main surface 3 toward the bottom wall. The cell separation trench 61 can also be formed in a tapered shape in which the opening area of the opening side is larger than the bottom area. The bottom wall of the cell separation trench 61 can also be formed in parallel with respect to the first main surface 3. The bottom wall of the cell separation trench 61 can also be formed in a curved shape toward the second main surface 4. The cell separation trench 61 includes a bottom wall edge portion. The bottom wall edge portion connects the side wall and the bottom wall of the cell separation trench 61. The bottom wall edge portion can also be formed in a curved shape toward the second main surface 4.

[0110] The depth D2 of the cell separation trench 61 can also be 2 μm or more and 10 μm or less. The depth D2 of the cell separation trench 61 can be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D2 of the cell separation trench 61 can also be equal to the depth D1 of the gate trench 47. The depth D2 of the cell separation trench 61 can also be defined as the distance from the deepest portion of the bottom wall of the cell separation trench 61 to the first main surface 3.

[0111] The width of the cell separation trench 61 can also be 0.5 μm or more and 3 μm or less. The width of the cell separation trench 61 is the width in the first direction X of the cell separation trench 61. The width of the cell separation trench 61 can be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the cell separation trench 61 can also be equal to the width of the gate trench 47.

[0112] The cell separation insulating layer 62 is formed in a film shape along the inner wall of the cell separation trench 61. The cell separation insulating layer 62 divides a recess space within the cell separation trench 61. In this mode, the cell separation insulating layer 62 includes a silicon oxide film. The cell separation insulating layer 62 can also include a silicon nitride film instead of or in addition to the silicon oxide film.

[0113] The cell separation electrode layer 63 is embedded in the cell separation trench 61 through the cell separation insulating layer 62. Specifically, the cell separation electrode layer 63 is embedded in the recess space within the cell separation trench 61 divided by the cell separation insulating layer 62. The cell separation electrode layer 63 is controlled by an emitter signal. The cell separation electrode layer 63 can also include conductive polysilicon.

[0114] Each diode region 25 includes a p -The anode region 64 is of a p-type (first impurity region). The p-type impurity concentration of the anode region 64 can also be lower than the p-type impurity concentration of the body region 50. The p-type impurity concentration of the anode region 64 is preferably less than the p-type impurity concentration of the body region 50. The p-type impurity concentration of the anode region 64 can be 1.0 x 10 15 cm -3 above and less than 1.0 x 10 18 cm -3 .

[0115] The anode region 64 is formed in each diode cell region 59. Thus, a plurality of anode regions 64 are arranged at equal intervals in the first direction X, and are formed in a stripe shape as a whole.

[0116] The anode region 64 forms a pn junction 65 with the semiconductor chip 2. Thus, a pn junction diode D is formed with the anode region 64 as an anode and the semiconductor chip 2 (cathode region 58) as a cathode.

[0117] The anode region 64 includes a diode trench 66 formed in the first main surface 3 of the semiconductor chip 2. In this way, the anode region 64 includes a plurality of diode trenches 66 formed on both sides of the cell separation structure 60. The diode trench 66 exposes the anode region 64. The diode trench 66 is formed at intervals from the cell separation structure 60 in the first direction X. The diode trench 66 extends in a band shape along the cell separation structure 60 when viewed from above.

[0118] The semiconductor device 1 includes an interlayer insulating layer 67 formed on the first main surface 3 of the semiconductor chip 2. The interlayer insulating layer 67 is formed in a film shape along the first main surface 3, and selectively covers the first main surface 3. Specifically, the interlayer insulating layer 67 selectively covers the IGBT region 24 and the diode region 25.

[0119] The interlayer insulating layer 67 can also include silicon oxide or silicon nitride. The interlayer insulating layer 67 can also include at least one of NSG (Non-doped Silicate Glass), PSG (Phosphor Silicate Glass), and BPSG (Boron Phosphor Silicate Glass).

[0120] The thickness of the interlayer insulating layer 67 can also be 0.1 μm or more and 1 μm or less. The thickness of the interlayer insulating layer 67 can be 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0121] In this mode, the interlayer insulating layer 67 has a stacked structure including a first insulating layer 68, a second insulating layer 69, and a third insulating layer 70 stacked in this order from the first main surface 3 side. The first insulating layer 68 preferably contains silicon oxide (e.g., a thermal oxide film). The second insulating layer 69 preferably contains an NGS layer. The second insulating layer 69 can contain a PSG layer or a BPSG layer instead of the NGS layer. The third insulating layer 70 preferably contains a BPSG layer. The third insulating layer 70 can contain an NGS layer or a PSG layer instead of the BPSG layer. The third insulating layer 70 preferably contains an insulating material having a different property from that of the second insulating layer 69.

[0122] The first insulating layer 68 is formed in a film shape on the first main surface 3. The first insulating layer 68 is continuous with the gate insulating layer 48, the emitter insulating layer 56, and the cell separation insulating layer 62. The second insulating layer 69 is formed in a film shape on the first insulating layer 68. The third insulating layer 70 is formed in a film shape on the second insulating layer 69.

[0123] The thickness of the first insulating layer 68 can be 500 A or more and 2000 A or less. The thickness of the first insulating layer 68 can be 500 A or more and 1000 A or less, 1000 A or more and 1500 A or less, or 1500 A or more and 2000 A or less.

[0124] The thickness of the second insulating layer 69 can be 500 A or more and 4000 A or less. The thickness of the second insulating layer 69 can be 500 A or more and 1000 A or less, 1000 A or more and 1500 A or less, 1500 A or more and 2000 A or less, 2000 A or more and 2500 A or less, 2500 A or more and 3000 A or less, 3000 A or more and 3500 A or less, or 3500 A or more and 4000 A or less.

[0125] The thickness of the third insulating layer 70 can be 1000 A or more and 8000 A or less. The thickness of the third insulating layer 70 can be 1000 A or more and 2000 A or less, 2000 A or more and 4000 A or less, 4000 A or more and 6000 A or less, or 6000 A or more and 8000 A or less.

[0126] The interlayer insulating layer 67 includes an emitter opening 71. The emitter opening 71 exposes the contact trench 53. The emitter opening 71 communicates with the contact trench 53. In this way, the contact trench 53 is formed in the first main surface 3 through the first insulating layer 68 and the second insulating layer 69. The emitter opening 71 exposes the contact trench 53 through the third insulating layer 70. The emitter opening 71 forms an opening between the contact trench 53. The opening edge portion of the emitter opening 71 is formed in a curved shape toward the inside of the interlayer insulating layer 67. Thus, the emitter opening 71 has a larger opening width than the opening width of the contact trench 53.

[0127] Referring to Figure 5 , the interlayer insulating layer 67 includes a diode opening 72. The diode opening 72 exposes the diode trench 66. The diode opening 72 communicates with the diode trench 66. In this way, the diode opening 72 is formed in the first main surface 3 through the first insulating layer 68 and the second insulating layer 69. The diode opening 72 exposes the diode trench 66 through the third insulating layer 70. The diode opening 72 forms an opening between the diode trench 66. The opening edge portion of the diode opening 72 is formed in a curved shape toward the inside of the interlayer insulating layer 67. Thus, the diode opening 72 has a larger opening width than the opening width of the diode trench 66.

[0128] The semiconductor device 1 includes an emitter plug electrode 73 buried in a portion of the interlayer insulating layer 67 covering the IGBT region 24. The emitter plug electrode 73 penetrates the interlayer insulating layer 67 and is electrically connected to the emitter region 51 and the contact region 54. Specifically, the emitter plug electrode 73 is buried in the contact trench 53. The emitter plug electrode 73 is electrically connected to the emitter region 51 and the contact region 54 within the contact trench 53.

[0129] In this way, the emitter plug electrode 73 has a layered structure including a barrier electrode layer 74 and a main electrode layer 75. The barrier electrode layer 74 is formed in a film shape along the inner wall of the contact trench 53 in a manner in contact with the interlayer insulating layer 67. The barrier electrode layer 74 divides a recess space within the contact trench 53.

[0130] The barrier electrode layer 74 can also have a single-layer structure including a titanium layer or a titanium nitride layer. The barrier electrode layer 74 can also have a layered structure including a titanium layer and a titanium nitride layer. In this case, the titanium nitride layer can be layered on the titanium layer.

[0131] The main electrode layer 75 is buried in the contact trench 53 through the barrier electrode layer 74. Specifically, the main electrode layer 75 is buried in the recess space divided by the barrier electrode layer 74 in the contact trench 53. The main electrode layer 75 can also include tungsten.

[0132] The semiconductor device 1 includes a diode plug electrode 76 embedded in the diode opening 72. The diode plug electrode 76 is electrically connected to the anode region 64 within the diode opening 72. The diode plug electrode 76 has a structure corresponding to the emitter plug electrode 73. The description on the diode plug electrode 76 applies to the description on the emitter plug electrode 73. In the diode plug electrode 76, the same reference numerals are assigned to the structures corresponding to the structures described on the emitter plug electrode 73 and the description is omitted.

[0133] The above-described emitter terminal electrode 12 is formed on the interlayer insulating layer 67. The emitter terminal electrode 12 can also include at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.

[0134] The emitter terminal electrode 12 can also have a single-layer structure including any one of these conductive materials. The emitter terminal electrode 12 can also have a laminated structure in which at least two of these conductive materials are laminated in any order.

[0135] The thickness of the emitter terminal electrode 12 can be 1.0 μm or more and 6.0 μm or less. The thickness of the emitter terminal electrode 12 can be 1.0 μm or more and 2.0 μm or less, 2.0 μm or more and 4.0 μm or less, or 4.0 μm or more and 6.0 μm or less.

[0136] In this mode, the emitter terminal electrode 12 has a laminated structure including a first electrode layer 77, a second electrode layer 78, and a third electrode layer 79 laminated in this order from the first main surface 3 side. The first electrode layer 77 preferably includes an aluminum-silicon-copper alloy (Al-Si-Cu). The second electrode layer 78 preferably includes titanium nitride (TiN). The second electrode layer 78 can also be referred to as a barrier layer. The third electrode layer 79 preferably includes an aluminum-copper alloy (Al-Cu).

[0137] The emitter terminal electrode 12 is electrically connected to the emitter region 51 and the contact region 54 via the emitter plug electrode 73 over the interlayer insulating layer 67. Specifically, the emitter terminal electrode 12 enters the emitter opening 71 from over the interlayer insulating layer 67. The emitter terminal electrode 12 is electrically connected to the emitter plug electrode 73 in the emitter opening 71. Thus, the emitter terminal electrode 12 is electrically connected to the emitter region 51 and the contact region 54 via the emitter plug electrode 73.

[0138] With reference to Figure 5 The emitter terminal electrode 12 is also electrically connected to the anode region 64 via the diode plug electrode 76 over the interlayer insulating layer 67. Specifically, the emitter terminal electrode 12 enters the diode opening 72 from over the interlayer insulating layer 67. The emitter terminal electrode 12 functions as an anode terminal electrode in the diode region 25.

[0139] The emitter terminal electrode 12 is in contact with the inner wall of the diode opening 72. The emitter terminal electrode 12 is electrically connected to the anode region 64 at the diode opening 72. The emitter terminal electrode 12 is electrically connected to the diode plug electrode 76 at the diode opening 72.

[0140] Although specific illustrations are omitted, the gate terminal electrode 7, the first sensing terminal electrode 8, the second sensing terminal electrode 9, the current detection terminal electrode 10, and the open terminal electrode 11 are similarly formed on the interlayer insulating layer 67 as the emitter terminal electrode 12.

[0141] The plurality of terminal electrodes 7 to 12 can each include at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. The plurality of terminal electrodes 7 to 12 can each have a single-layer structure including any one of these conductive materials. The plurality of terminal electrodes 7 to 12 can each have a layered structure in which at least two of these conductive materials are stacked in any order. In this manner, the plurality of terminal electrodes 7 to 12 include the same conductive material as the emitter terminal electrode 12.

[0142] In a case where a wire (e.g., a bonding wire) is connected to each of the plurality of terminal electrodes 7 to 12, a single-layer electrode composed of a nickel layer or a gold layer, or a layered electrode including a nickel layer and a gold layer can be formed on each of the plurality of terminal electrodes 7 to 12. In the layered electrode, the gold layer can be formed on the nickel layer.

[0143] In addition, the plurality of wiring lines 13 to 15 can each include at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. The plurality of wiring lines 13 to 15 can each have a single-layer structure including any one of these conductive materials. The plurality of wiring lines 13 to 15 can each have a layered structure in which at least two of these conductive materials are stacked in any order. In this manner, the plurality of terminal electrode wiring lines 13 to 15 include the same conductive material as the emitter terminal electrode 12.

[0144] Next, other modes of the cross-sectional structure of the active region 18 will be described. Figure 6 is a cross-sectional view along the VI-VI line of Figure 3 . Figure 7 is a cross-sectional view along the VII-VII line of Figure 3 . Reference is made to Figure 6 and Figure 7 to describe a connection mode of the third contact layer 40 to the emitter terminal electrode 12 and a connection mode of the second contact layer 39 to the emitter terminal electrode 12. Hereinafter, the same reference numerals are assigned to structures corresponding to the structures already described with respect to the semiconductor device 1 and the description is omitted.

[0145] Referring to Figure 6 , the emitter potential electrode layer 57 of the emitter trench structure 28 has an extraction electrode layer 80 extracted from the emitter trench 55 to the first main face 3. The extraction electrode layer 80 is Figure 3 a third contact layer 40. Specifically, the extraction electrode layer 80 is formed inside the interlayer insulating layer 67. The extraction electrode layer 80 is extracted to the first insulating layer 68 and a region between the first insulating layer 68 and the third insulating layer 70. The extraction electrode layer 80 is electrically connected to the emitter terminal electrode 12. An emitter signal applied to the extraction electrode layer 80 is transmitted to the emitter potential electrode layer 57 via the extraction electrode layer 80.

[0146] The interlayer insulating layer 67 includes a first opening 81. The first opening 81 exposes the extraction electrode layer 80 in the IGBT region 24. The first opening 81 is formed so as to narrow in opening width from the opening side toward the bottom wall side.

[0147] The semiconductor device 1 includes a first plug electrode 82 embedded in the first opening 81. The first plug electrode 82 is electrically connected to the extraction electrode layer 80 within the first opening 81. The first plug electrode 82 has a structure corresponding to the emitter plug electrode 73. The description on the first plug electrode 82 applies the description on the emitter plug electrode 73. In the first plug electrode 82, the same reference numerals are attached to the structure corresponding to the structure described on the emitter plug electrode 73 and the description is omitted.

[0148] The emitter terminal electrode 12 is electrically connected to the emitter potential electrode layer 57 via the first plug electrode 82 and the extraction electrode layer 80 over the interlayer insulating layer 67.

[0149] Referring to Figure 7 , the cell separation electrode layer 63 of the cell separation structure 60 has an extraction electrode layer 83 extracted from the cell separation trench 61 to the first main face 3. The extraction electrode layer 83 is Figure 3 a second contact layer 39. Specifically, the extraction electrode layer 83 is formed inside the interlayer insulating layer 67. The extraction electrode layer 83 is extracted to the first insulating layer 68 and a region between the first insulating layer 68 and the third insulating layer 70. The extraction electrode layer 83 is electrically connected to the emitter terminal electrode 12. An emitter signal applied to the extraction electrode layer 83 is transmitted to the cell separation electrode layer 63 via the extraction electrode layer 83.

[0150] The interlayer insulating layer 67 includes a second opening 84. The second opening 84 exposes the extraction electrode layer 83 in the diode region 25. The second opening 84 is formed so as to narrow in opening width from the opening side toward the bottom wall side. The second opening 84 is formed in a strip shape extending in the first direction X.

[0151] The semiconductor device 1 includes a second plug electrode 85 embedded in the second opening 84. The second plug electrode 85 is electrically connected to the extraction electrode layer 83 within the second opening 84. The second plug electrode 85 has a structure corresponding to the emitter plug electrode 73. The description of the second plug electrode 85 applies to the description of the emitter plug electrode 73. For the structure of the second plug electrode 85 corresponding to the structure described for the emitter plug electrode 73, the same reference numerals are assigned and the description is omitted.

[0152] The emitter terminal electrode 12 is electrically connected to the cell separation electrode layer 63 via the second plug electrode 85 and the extraction electrode layer 83 over the interlayer insulating layer 67.

[0153] Next, other modes of the cross-sectional structure of the active region 18 are described. Figure 8 is a cross-sectional view along the line VIII-VIII of Figure 3 . Figure 9 is a cross-sectional view along the line IX-IX of Figure 3 . Figure 10 is a cross-sectional view along the line X-X of Figure 3 . Figure 11 is a cross-sectional view along the line XI-XI of Figure 3 . Referring to Figures 8-11 , the connection mode of the first contact layer 38 to the gate extension electrode 33 (the gate wiring 13) and the structure of the semiconductor chip 2 directly below the gate extension electrode 33 are described. Hereinafter, the same reference numerals are assigned to the structures corresponding to the structures already described with respect to the semiconductor device 1 and the description is omitted.

[0154] Referring to Figures 8-11 , the semiconductor device 1 includes a well region 87 of p-type formed in a region (a boundary region 86 between adjacent division regions 20) directly below the gate extension electrode 33 in the surface layer portion of the first main surface 3. In this mode, the well region 87 has a higher p-type impurity concentration than the body region 50. Of course, the well region 87 can also have a lower p-type impurity concentration than the body region 50.

[0155] The well region 87 is formed in a band shape extending in the first direction X along the boundary region 86 in plan view. The well region 87 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3. Referring to Figure 8 , the well region 87 is formed in a region sandwiched by the plurality of trench gate structures 27 and a region sandwiched by the plurality of emitter trench structures 28. In addition, referring to Figure 9 , the well region 87 is formed in a region sandwiched by the plurality of cell separation structures 60.

[0156] The well region 87 is preferably formed deeper than the body region 50 and the anode region 64. The well region 87 is particularly preferably formed deeper than the plurality of trench gate structures 27, the plurality of emitter trench structures 28, and the plurality of cell separation structures 60.

[0157] With reference to Figure 8 and Figure 9 , the well region 87 has a portion covering the bottom walls of the plurality of trench gate structures 27 and the plurality of emitter trench structures 28. The well region 87 crosses the plurality of trench gate structures 27 and the plurality of emitter trench structures 28 in the first direction X, covering the bottom walls of these together.

[0158] With reference to Figure 9 , the well region 87 has a portion covering the bottom walls of the plurality of cell separation structures 60. The well region 87 crosses the plurality of cell separation structures 60 in the first direction X, covering the bottom walls of these together. Further, the well region 87 crosses the plurality of trench gate structures 27 and the plurality of cell separation structures 60 in the first direction X, covering the bottom walls of these together. With reference to Figure 9 , the well region 87 crosses the boundary portion between the IGBT region 24 and the diode region 25 in the first direction X.

[0159] With reference to Figure 10 and Figure 11 , the well region 87 crosses the gate extension electrode 33 in the second direction Y. In this way, the well region 87 has a width greater than the width of the boundary region 86 in the second direction Y. The well region 87 has a lead-out portion 88 leading out from the boundary region 86 into the plurality of division regions 20.

[0160] With reference to Figure 10 , the well region 87 is connected integrally with the body region 50 of the IGBT region 24. The lead-out portion 88 of the well region 87 is connected to the side portion of the body region 50. The well region 87 has an upper side protruding portion 89 protruding upward from the upper end of the body region 50 (the boundary between the body region 50 and the emitter region 51).

[0161] With reference to Figure 11 , the well region 87 is connected integrally with the anode region 64 of the diode region 25. The lead-out portion 88 of the well region 87 is connected to the side portion of the anode region 64. The well region 87 has an upper end at the same height position as the upper end of the anode region 64 (the first main surface 3).

[0162] With reference to Figures 8-11 , the gate electrode layer 49 of the trench gate structure 27 has a lead-out electrode layer 90 leading out from the gate trench 47 to above the first main surface 3. The lead-out electrode layer 90 is Figure 3The first contact layer 38 (the first electrode layer 34) is electrically connected to the lead-out electrode layer 90. A gate signal applied to the lead-out electrode layer 90 is transmitted to the gate electrode layer 49 via the lead-out electrode layer 90.

[0163] Referring to Figures 9-11 , the interlayer insulating layer 67 includes a gate opening 91. The gate opening 91 exposes the lead-out electrode layer 90 in the IGBT region 24. The gate opening 91 is formed so as to be narrower in opening width from the opening side toward the bottom wall side. In this way, a pair of gate openings 91 is formed along the gate extension electrode 33. Referring to Figure 9 , each gate opening 91 extends in a band shape in the first direction X, and has an end portion directly above the boundary portion between the IGBT region 24 and the diode region 25.

[0164] The semiconductor device 1 includes a gate plug electrode 92 embedded in the gate opening 91. The gate plug electrode 92 is electrically connected to the lead-out electrode layer 90 within the gate opening 91. The gate plug electrode 92 has a structure corresponding to the emitter plug electrode 73. The description of the gate plug electrode 92 is applicable to the description of the emitter plug electrode 73. For the structure of the gate plug electrode 92 corresponding to the structure described for the emitter plug electrode 73, the same reference numerals are marked and the description is omitted.

[0165] The gate extension electrode 33 is electrically connected to the gate electrode layer 49 via the gate plug electrode 92 and the lead-out electrode layer 90 over the interlayer insulating layer 67. The second electrode layer 35 of the gate extension electrode 33 has a structure corresponding to the emitter terminal electrode 12. The description of the second electrode layer 35 of the gate extension electrode 33 is applicable to the description of the emitter terminal electrode 12. For the structure of the second electrode layer 35 of the gate extension electrode 33 corresponding to the structure described for the emitter terminal electrode 12, the same reference numerals are marked and the description is omitted.

[0166] As described above, according to the structure shown in Figures 3-11 , the plurality of diode-side trench structures 29 are formed in a stripe shape as a whole. The plurality of diode-side trench structures 29 cross directly below the gate wiring 13 from one side to the other side in the second direction Y. That is, the plurality of diode-side trench structures 29 are not divided for each of the divided regions 20. Thereby, it is possible to reduce the number of the terminal portions 32 of the plurality of diode-side trench structures 29. In this way, the terminal portions 32 of the plurality of diode-side trench structures 29 are selectively formed only in the outer peripheral region 19.

[0167] Since the terminal portions 32 of the multiple diode-side trench structures 29 are circular, they are prone to shape abnormalities compared to stripe shapes due to the deviation of the recess. Therefore, by reducing the number of terminal portions 32 of the multiple diode-side trench structures 29, insulation breakdown at the terminal portions 32 can be suppressed. As a result, the ESD (Electro-Static Discharge) withstand capability of the semiconductor device 1 can be improved.

[0168] Next, other ways of planar structure of active region 18 will be described. Figure 12 yes Figure 2 The enlarged view of the portion enclosed by XII shows a portion of multiple IGBT regions 24 and multiple diode regions 25. The planar structure of the IGBT regions 24 and diode regions 25 described below can be applied to all IGBT regions 24 and all diode regions 25 of the semiconductor chip 2, or selectively applied to several IGBT regions 24 and diode regions 25. That is, the planar structure described below is a structure that can be applied to at least one IGBT region 24 and diode region 25.

[0169] exist Figure 12 In the diode region 25 shown, multiple diode-side trench structures 29 do not traverse the gate wiring 13, and have termination portions 32 on the inner side of the diode region 25 separated from the gate wiring 13 along the second direction Y. A second contact layer 39 covers the termination portions 32 of the multiple diode-side trench structures 29. The second contact layer 39 is electrically connected to the diode-side trench structures 29 via the termination portions 32.

[0170] The semiconductor device 1 includes a plurality of gate auxiliary trench structures 93 formed on a first main surface 3. The plurality of gate auxiliary trench structures 93 are formed directly below the gate extension electrode 33 and are covered by the gate extension electrode 33 when viewed from above. The plurality of gate auxiliary trench structures 93 are trench structures that are longer along the second direction Y.

[0171] exist Figure 12 In this configuration, the multiple gate auxiliary trench structures 93 are multiple elliptical trench structures whose major axis direction is aligned with the second direction Y. The multiple gate auxiliary trench structures 93 can also be formed as a strip extending along the second direction Y when viewed from above. The multiple gate auxiliary trench structures 93 are generally formed in a stripe shape. Each of the multiple gate auxiliary trench structures 93 has a terminal portion 94 on one side and the other side of the second direction Y.

[0172] The terminal portion 94 of the gate auxiliary trench structure 93 is formed for each of the pair of gate auxiliary trench structures 93. The terminal portion 94 extends the adjacent gate auxiliary trench structure 93 in the region directly below the gate extension electrode 33. Figure 10 andFigure 11 The boundary region 86) is connected. The terminal part 94 is formed into a circular shape when viewed from above.

[0173] Furthermore, the diode-side trench structure 29 and the gate-assisted trench structure 93 are formed on the same imaginary straight line 99 extending along the second direction Y (in Figure 12 (The line is represented by a single-dotted line in the text). Therefore, the gate auxiliary trench structure 93 can also be a trench structure formed on the extension line of the second direction Y of the diode-side trench structure 29.

[0174] The first electrode layer 34 of the gate extension electrode 33 is formed as a strip that continuously extends across a plurality of alternately arranged IGBT regions 24 and a plurality of diode regions 25. The first electrode layer 34 is a strip with a constant width in the second direction Y. The first electrode layer 34 and Figure 3 The structures differ; in both the non-contact region 36 and the contact region 37, the first electrode layer 34 is positioned directly below the second electrode layer 35. Thus, the first electrode layer 34 simultaneously covers the plurality of trench gate structures 27 and the plurality of gate auxiliary trench structures 93. In this configuration, the entire gate auxiliary trench structure 93 from one end in the second direction Y to the other is covered by the first electrode layer 34.

[0175] Next, the cross-sectional structure of the gate auxiliary trench structure 93 will be described. Figure 13 It is along Figure 12 A cross-sectional view along line XIII-XIII. Hereinafter, the same reference numerals will be used for the structures corresponding to those already described with respect to semiconductor device 1, and descriptions will be omitted.

[0176] The gate-assisted trench structure 93 includes a gate-assisted trench 95, a gate-assisted insulating layer 96, and a gate-assisted electrode layer 97. The gate-assisted trench 95 is formed on the first main surface 3 of the semiconductor chip 2. The gate-assisted trench 95 includes sidewalls and a bottom wall. The sidewalls of the gate-assisted trench 95 may also be formed perpendicular to the first main surface 3.

[0177] The sidewalls of the gate auxiliary trench 95 may also slope downwards from the first main surface 3 toward the bottom wall. The gate auxiliary trench 95 may also be formed as a cone shape with an opening area larger than the bottom area. The well region 87 is exposed from the sidewalls of the gate auxiliary trench 95. The bottom wall of the gate auxiliary trench 95 may also be formed parallel to the first main surface 3. The bottom wall of the gate auxiliary trench 95 may also be formed as a curve toward the second main surface 4. The gate auxiliary trench 95 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and the bottom wall of the gate auxiliary trench 95. The bottom wall edge portion may also be formed as a curve toward the second main surface 4 of the semiconductor chip 2.

[0178] The depth D4 of the gate auxiliary trench 95 can be 2 μm or more and 10 μm or less. The depth D4 of the gate auxiliary trench 95 can be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D4 of the gate auxiliary trench 95 can also be equal to the depth D1 of the gate trench 47.

[0179] The width of the gate auxiliary trench 95 can be 0.5 μm or more and 3 μm or less. The width of the gate auxiliary trench 95 is the width of the first direction X of the gate auxiliary trench 95. The width of the gate auxiliary trench 95 can be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the gate auxiliary trench 95 can also be equal to the width of the gate trench 47.

[0180] The gate auxiliary insulating layer 96 is formed in a film shape along the inner wall of the gate auxiliary trench 95. The gate auxiliary insulating layer 96 divides a recess space within the gate auxiliary trench 95. In this mode, the gate auxiliary insulating layer 96 includes a silicon oxide film. The gate auxiliary insulating layer 96 can also include a silicon nitride film instead of or in addition to the silicon oxide film.

[0181] The gate auxiliary electrode layer 97 is embedded in the gate auxiliary trench 95 through the gate auxiliary insulating layer 96. Specifically, the gate auxiliary electrode layer 97 is embedded in the recess space divided by the gate auxiliary insulating layer 96 in the gate auxiliary trench 95. The gate auxiliary electrode layer 97 can also include conductive polysilicon. The gate auxiliary electrode layer 97 is controlled to be a gate potential.

[0182] The lead-out electrode layer 90 led out from the gate trench 47 to the first main surface 3 is integrally connected with the gate auxiliary electrode layer 97. That is, the lead-out electrode layer 90 is integrally led out from the gate electrode layer 49 and the gate auxiliary electrode layer 97 to the first main surface 3, and covers the gate trench 47 and the gate auxiliary trench 95.

[0183] Next, the pattern of the gate auxiliary trench structure 93 will be described with reference to FIG. 6. Figures 14-16 The pattern of the gate auxiliary trench structure 93 will be described.

[0184] First, the pattern of the gate auxiliary trench structure 93 will be described with reference to FIG. 6. Figure 14 In this mode, the terminal portion 98 of each gate auxiliary trench structure 93 is disposed at a position inside the both side edges of the first electrode layer 34 in the second direction Y, and is covered by the first electrode layer 34.

[0185] Next, referring to Figure 15 , the plurality of gate auxiliary trench structures 93 can also be formed as independent strips one by one. Each of the gate auxiliary trench structures 93 is a strip-shaped trench structure whose length direction coincides with the second direction Y. In this mode, the terminal portions 98 of each of the gate auxiliary trench structures 93 protrude outward beyond the both side edges of the first electrode layer 34 in the second direction Y and are exposed from the first electrode layer 34.

[0186] Next, referring to Figure 16 , the plurality of gate auxiliary trench structures 93 are trench structures longer in the first direction X. In Figure 16 , a structure in which the elliptical trench structure of Figure 12 is rotated by 90° is shown, but a structure in which the strip-shaped trench structure of Figure 14 and Figure 15 is rotated by 90° is of course also possible.

[0187] As described above, according to the structure shown in Figures 12-16 , the plurality of gate auxiliary trench structures 93 controlled to be the gate potential are formed. Thereby, the gate capacitance can be increased, and thus the ESD tolerance of the gate can be improved. In addition, the plurality of gate auxiliary trench structures 93 are arranged in the free space directly below the gate extension electrode 33 sandwiched by the plurality of diode-side trench structures 29. Therefore, the increase in the chip area and the increase in the gate trench density can be avoided due to the gate auxiliary trench structures 93. Thereby, the increase in the chip cost and the rise in the process difficulty can be suppressed.

[0188] In addition, as shown in Figure 12 , Figure 14 and Figure 15 , if the plurality of gate auxiliary trench structures 93 are trenches longer in the second direction Y, the gate extension electrode 33 and the gate auxiliary trench structure 93 can be reliably connected even if the gate extension electrode 33 is positionally shifted in the second direction Y.

[0189] Next, one mode of the planar structure of the vicinity of the gate terminal electrode 7 will be described. Figure 17 is an enlarged view of the portion surrounded by XVII of Figure 2 , and shows a part of the plurality of IGBT regions 24 and the plurality of diode regions 25. The planar structure of the IGBT regions 24 and the diode regions 25 described below can be applied to all of the IGBT regions 24 and all of the diode regions 25 of the semiconductor chip 2, or can be selectively applied to several IGBT regions 24 and diode regions 25. That is, the planar structure described below is a structure that can be applied to at least one IGBT region 24 and diode region 25.

[0190] In this configuration, the first end of the RC-IGBT array 26 (the end on the side 5B side) is formed by a diode region 25. This diode region 25 is adjacent to multiple terminal electrodes 7-11 and can also be referred to as the pad-adjacent diode region 25A. The pad-adjacent diode region 25A is adjacent to the gate terminal electrode 7 in the first direction X. "Adjacent to the gate terminal electrode 7" can also mean that in the first direction X, there are no other diode regions 25 or IGBT regions 24 sandwiched between the gate terminal electrode 7 and the pad-adjacent diode region 25A.

[0191] In the diode region 25A adjacent to the pad, a plurality of diode-side trench structures 29 do not traverse the gate wiring 13, and have termination portions 32 on the inner side of the diode region 25 separated from the gate wiring 13 along the second direction Y. A second contact layer 39 covers the termination portions 32 of the plurality of diode-side trench structures 29. The second contact layer 39 is electrically connected to the diode-side trench structures 29 via the termination portions 32.

[0192] The gate extension electrode 33 includes an annular peripheral portion 100 surrounding the gate terminal electrode 7 and an extension portion 101 extending in a strip shape from the peripheral portion 100 along a first direction X.

[0193] The peripheral portion 100 surrounds the entire periphery of the gate terminal electrode 7, but may also be partially divided. The end of the side 5B side of the peripheral portion 100 is integrally connected to the first portion 16 of the gate wiring 13. An annular gap region 102 is formed between the peripheral portion 100 and the gate terminal electrode 7.

[0194] The extension 101 extends from the end of the peripheral portion 100 on the side opposite to the end of the side surface 5B in the first direction X. The extension 101 extends in a strip shape in the first direction X.

[0195] exist Figure 17 In the middle, the surrounding portion 100 and the extension portion 101 are formed by a stacked structure of a resistive layer 103 and a wiring layer 104. The lower resistive layer 103 of this stacked structure is a blank area, and the upper wiring layer 104 is a shaded area. The resistive layer 103 also serves as the first electrode layer 34 and the first contact layer 38 mentioned above. The wiring layer 104 also serves as the second electrode layer 35 mentioned above.

[0196] The stacked structure of resistive layer 103 and wiring layer 104, in addition to constituting the gate extension electrode 33, can also partially constitute the gate terminal electrode 7. Figure 17 In the middle, a portion of the resistive layer 103 forms an island-shaped pad support layer 105, and a second electrode layer 35 constituting the peripheral portion 100 and the gate terminal electrode 7 is formed independently on the pad support layer 105.

[0197] The second electrode layer 35 of the peripheral portion 100 is connected to the pad support layer 105 via peripheral contacts 106. In this configuration, a pair of peripheral contacts 106 are formed opposite to the gate terminal electrode 7 in the first direction X. Each of the pair of peripheral contacts 106 is formed at one end on the side 5B side of the peripheral portion 100 and at the opposite end.

[0198] The second electrode layer 35 of the gate terminal electrode 7 is connected to the pad support layer 105 via pad contacts 107. In this configuration, a pair of pad contacts 107 are formed adjacent to the surrounding contacts 106 in the first direction X. Each pair of pad contacts 107 is formed at a position adjacent to each of the surrounding contacts 106.

[0199] Semiconductor device 1 includes a gate resistor 108 adjacent to the gate terminal electrode 7. The gate resistor 108 is selectively formed in the gate extension electrode 33 in a portion that traverses the diode region 25, avoiding the portion directly above the trench gate structure 27. In this manner, the gate resistor 108 is formed in the extension 101 at a position adjacent to the terminal portion 32 of the diode-side trench structure 29 in the second direction Y. More specifically, the gate resistor 108 is formed in a region sandwiched between a plurality of diode-side trench structures 29 opposed to each other by the gate extension electrode 33.

[0200] In the region adjacent to the terminal portion 32, the wiring layer 104 of the gate extension electrode 33 (extension portion 101) is divided into one side and the other side in the first direction X. The gate resistor 108 is formed from a portion of the resistor layer 103 sandwiched between the divided wiring layer 104.

[0201] The extension 101 includes a first extension 109 near the gate terminal electrode 7 and a second extension 110 on the opposite side thereof. The first extension 109 and the second extension 110 are respectively connected to the resistive layer 103 via resistive contacts 111.

[0202] The gate resistor 108 is disposed between the first extension 109 and the second extension 110. The gate resistor 108 is formed as a top view strip of constant width extending along the first direction X.

[0203] The gate resistor 108 may also include a plurality of trench resistor structures 112. The plurality of trench resistor structures 112 are formed as long stripes in the second direction Y between the first extension 109 and the second extension 110. Each trench resistor structure 112 is formed as a long top-view strip in the direction traversing the gate extension electrode 33.

[0204] Next, regarding Figure 17 The cross-sectional structure will be described. Figure 18 It is along Figure 17Cross-sectional view along line XVIII-XVIII of Fig. 18. Figure 19 is along Figure 17 Cross-sectional view along line XIX-XIX of Fig. 18.

[0205] First, the cross-sectional structure of the gate terminal electrode 7 is described with reference to Fig. 18. Figure 18 The well region 87 extends just below the gate terminal electrode 7. The pad support layer 105 (the resistance layer 103, the first electrode layer 34) is formed in the well region 87 with the first insulating layer 68 interposed. The pad support layer 105 is covered with the third insulating layer 70.

[0206] The peripheral contact 106 and the pad contact 107 are embedded in the third insulating layer 70. The peripheral contact 106 and the pad contact 107 can be respectively referred to as a peripheral plug electrode and a pad plug electrode. The peripheral contact 106 and the pad contact 107 have a structure corresponding to the emitter plug electrode 73. The description of the peripheral contact 106 and the pad contact 107 is applicable to the description of the emitter plug electrode 73. In the peripheral contact 106 and the pad contact 107, the same reference numerals are assigned to the structures corresponding to the structures described with respect to the emitter plug electrode 73 and the description is omitted.

[0207] The gate terminal electrode 7 and the peripheral portion 100 are formed on the third insulating layer 70. The gate terminal electrode 7 and the peripheral portion 100 are electrically connected to each other via the pad contact 107, the pad support layer 105, and the peripheral contact 106.

[0208] Next, the cross-sectional structure of the gate resistance 108 is described with reference to Fig. 19. Figure 19 The trench resistance structure 112 is formed in the first main surface 3.

[0209] The trench resistance structure 112 includes the resistance trench 113, the resistance insulating layer 114, and the resistance electrode layer 115. The resistance trench 113 is formed in the first main surface 3 of the semiconductor chip 2. The resistance trench 113 includes a side wall and a bottom wall. The side wall of the resistance trench 113 can also be formed perpendicularly with respect to the first main surface 3.

[0210] The side wall of the resistance trench 113 can also be inclined downward from the first main surface 3 toward the bottom wall. The resistance trench 113 can also be formed in a tapered shape in which an opening area of an opening side is larger than a bottom area. The well region 87 is exposed from the side wall of the resistance trench 113. The bottom wall of the resistance trench 113 can also be formed parallel with respect to the first main surface 3. The bottom wall of the resistance trench 113 can also be formed in a curved shape toward the second main surface 4. The resistance trench 113 includes a bottom wall edge portion. The bottom wall edge portion connects the side wall and the bottom wall of the resistance trench 113. The bottom wall edge portion can also be formed in a curved shape toward the second main surface 4 of the semiconductor chip 2.

[0211] The depth D5 of the resistance trench 113 can also be 2 μm or more and 10 μm or less. The depth D5 of the resistance trench 113 can be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D5 of the resistance trench 113 can also be equal to the depth D1 of the gate trench 47.

[0212] The width of the resistance trench 113 can be 0.5 μm or more and 3 μm or less. The width of the resistance trench 113 is the width of the first direction X of the resistance trench 113. The width of the resistance trench 113 can be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the resistance trench 113 can also be equal to the width of the gate trench 47.

[0213] The resistance insulating layer 114 is formed in a film shape along the inner wall of the resistance trench 113. The resistance insulating layer 114 divides a recess space within the resistance trench 113. In this mode, the resistance insulating layer 114 includes a silicon oxide film. The resistance insulating layer 114 can also include a silicon nitride film instead of or in addition to the silicon oxide film.

[0214] The resistance electrode layer 115 is embedded in the resistance trench 113 through the resistance insulating layer 114. Specifically, the resistance electrode layer 115 is embedded in the recess space divided by the resistance insulating layer 114 in the resistance trench 113. The resistance electrode layer 115 can also include conductive polysilicon. The resistance electrode layer 115 is controlled to be a gate potential.

[0215] The gate resistor 108 has an extraction resistance layer 116 extracted from the resistance trench 113 to the first main face 3. The extraction resistance layer 116 is integrally connected with the resistance electrode layer 115. That is, the extraction electrode layer 90 is integrally extracted from the resistance electrode layer 115 to the first main face 3, and covers the plurality of resistance trenches 113. The pad support layer 105 is covered with the third insulating layer 70.

[0216] The resistance contact 111 is embedded in the third insulating layer 70. The resistance contact 111 can also be referred to as a resistance plug electrode. The resistance contact 111 has a structure corresponding to the emitter plug electrode 73. The description of the resistance contact 111 is applicable to the description of the emitter plug electrode 73. In the resistance contact 111, the same reference numerals are attached to the structures corresponding to the structures described with respect to the emitter plug electrode 73, and the description is omitted.

[0217] The first extension 109 and the second extension 110 are formed on the third insulating layer 70. The first extension 109 and the second extension 110 are electrically connected to each other via the resistance contact 111, the lead resistance layer 116, and the resistance electrode layer 115.

[0218] The portion of the resistance layer 103 in which the first extension 109 and the second extension 110 are laminated is short-circuited at the first extension 109 and the second extension 110 formed of the wiring layer 104 having a lower resistance than the resistance layer 103. Thus, the portion of the resistance layer 103 exposed between the first extension 109 and the second extension 110 forms the gate resistor 108.

[0219] Figure 20 is a drawing showing a modification example of the arrangement pattern of the IGBT region 24 and the diode region 25. Figure 21 is Figure 20 is an enlarged view of the portion of

[0220] Referring to Figure 20 and Figure 21 , the first end portion (the end portion on the side of the side surface 5B) of the RC-IGBT arrangement 26 is formed of the diode region 25. This diode region 25 is a region adjacent to the plurality of terminal electrodes 7 to 11, and can also be referred to as a pad-adjacent diode region 25A. The pad-adjacent diode region 25A is adjacent to the gate terminal electrode 7 in the second direction Y.

[0221] In the pad-adjacent diode region 25A, the plurality of diode-side trench structures 29 do not cross the gate wiring 13, and have terminal portions 32 on the inner side of the diode region 25 separated from the gate wiring 13 in the second direction Y. The second contact layer 39 covers the terminal portions 32 of the plurality of diode-side trench structures 29 in its entirety. The second contact layer 39 is electrically connected to the diode-side trench structures 29 via the terminal portions 32. The terminal portions 32 of the plurality of diode-side trench structures 29 are opposed across the gate terminal electrode 7 and the surrounding portion 100 in the second direction Y.

[0222] The gate resistor 108 is selectively formed in the gate extension electrode 33 so as to cross the diode region 25 at a portion directly above the trench gate structure 27 in the surrounding portion 100. In this manner, the gate resistor 108 is formed in the surrounding portion 100 at a position adjacent to the terminal portion 32 of the diode-side trench structure 29 in the second direction Y. More specifically, the gate resistor 108 is formed in a region sandwiched by the plurality of diode-side trench structures 29 opposed across the gate terminal electrode 7 and the surrounding portion 100 in the second direction Y. A pair of gate resistors 108 are opposed across the gate terminal electrode 7 in the second direction Y.

[0223] In a region adjacent to the terminal portion 32, the wiring layer 104 of the gate extension electrode 33 (the surrounding portion 100) is divided into one side and the other side in the first direction X. The gate resistor 108 is formed of a portion of the resistance layer 103 (the pad support layer 105) sandwiched by the divided wiring layer 104.

[0224] The surrounding portion 100 includes a first surrounding portion 117 connected to the first portion 16 of the gate wiring 13 and a second surrounding portion 118 on the opposite side thereof. The first surrounding portion 117 and the second surrounding portion 118 are connected to the resistance layer 103 via the resistance contact 111, respectively.

[0225] The gate resistor 108 is disposed between the first surrounding portion 117 and the second surrounding portion 118. The gate resistor 108 is formed as a planar band of a constant width extending in the first direction X.

[0226] The gate resistor 108 can also include a plurality of trench resistance structures 112. The plurality of trench resistance structures 112 are formed between the first surrounding portion 117 and the second surrounding portion 118 in a stripe shape longer in the second direction Y. Each of the trench resistance structures 112 is formed in a planar band longer in a direction crossing the gate extension electrode 33.

[0227] As described above, according to Figures 17-21 the structure shown in FIG. 1, the gate resistor 108 is formed in the gate extension electrode 33. The gate resistor 108 constitutes a gate resistor for a gate of the IGBT. For example, the gate resistor 108 is effective in suppressing oscillation (noise) caused by parasitic inductance at the time of turn-off. In addition, the gate resistor 108 is disposed in a free space directly below the gate extension electrode 33 sandwiched by the plurality of diode-side trench structures 29. Therefore, it is possible to avoid an increase in chip area due to the gate resistor 108. Thus, it is possible to provide the semiconductor device 1 having the gate resistor 108 without impairing the effective area of the IGBT region 24.

[0228] The embodiments of the present disclosure have been described, but the present disclosure can be implemented in other ways.

[0229] For example, in each of the above-described embodiments, a structure in which the conduction type of each semiconductor portion is reversed can be employed. That is, a portion of p-type can be formed as n-type, and a portion of n-type can be formed as p-type.

[0230] The embodiments of the present disclosure are illustrative in all respects and are not to be construed as being limited, and are intended to be inclusive in all respects. Modifications are intended to be included.

[0231] The following features can be extracted from the description and drawings of the present specification. Hereinafter, alphanumeric characters represent corresponding constituent elements and the like in the above-described embodiments, but are not intended to limit the scope of each clause to the embodiments.

[0232] [Clause 1-1]

[0233] A semiconductor device 1 includes:

[0234] A chip 2 has a first main surface 3 and a second main surface 4;

[0235] An insulating layer 67 covers the first main surface 3;

[0236] An extension electrode 33 extends in a first direction X in a region on the first main surface 3, includes a first electrode layer 34 formed between the insulating layer 67 and the first main surface 3, and a second electrode layer 35 formed on the insulating layer 67 and electrically connected to the first electrode layer 34;

[0237] A first element region 24 includes an element electrically connected to the extension electrode 33;

[0238] A second element region 25 is adjacent to the first element region 24 in the first direction X and is formed on one side and the other side across the extension electrode 33 in a second direction Y intersecting the first direction X; and

[0239] A second trench electrode structure 29 is formed on the first main surface 3 of the chip 2, crosses the extension electrode 33, and spans a plurality of the second element regions 25 adjacent across the extension electrode 33,

[0240] The extension electrode 33 does not have the first electrode layer 34 directly above the second trench electrode structure 29, and selectively has the second electrode layer 35.

[0241] According to this structure, the second trench electrode structure 29 crosses the extension electrode 33 and spans a plurality of the second element regions 25 adjacent across the extension electrode 33. That is, the second trench electrode structure 29 is not divided for each of the second element regions 25. Thereby, it is possible to reduce the number of terminal portions of the second trench electrode structure 29.

[0242] For example, if the terminal portion of the second trench electrode structure 29 is circular, it is easy to cause a shape abnormality due to a processing deviation. Therefore, by reducing the number of terminal portions of the second trench electrode structure 29, it is possible to suppress insulation breakdown at the terminal portion. As a result, it is possible to improve the ESD (Electro-Static Discharge) tolerance of the semiconductor device 1.

[0243] [Para 1-2]

[0244] The semiconductor device 1 according to para 1-1, wherein

[0245] The first element region 24 is formed on one side and the other side across the extension electrode 33 in the second direction Y,

[0246] Further comprising a first trench electrode structure 27 formed on the first main face 3 of the chip 2, traversing the extension electrode 33, spanning a plurality of the first element regions 24 adjacent across the extension electrode 33, physically and electrically separated from the second trench electrode structure 29,

[0247] The extension electrode 33 selectively has a laminated structure of the first electrode layer 34 and the second electrode layer 35 electrically connected to the first trench electrode structure 27 directly above the first trench electrode structure 27.

[0248] [Para 1-3]

[0249] The semiconductor device 1 according to para 1-2, wherein

[0250] A plurality of the first element regions 24 and a plurality of the second element regions 25 are alternately arranged in the first direction X,

[0251] The extension electrode 33 comprises one of the second electrode layer 35 continuously extending across the plurality of the first element regions 24 and the plurality of the second element regions 25, and a plurality of the first electrode layer 34 selectively divided by a non-contact interval 36 opposite the second element region 25 from the second electrode layer 35, thereby selectively arranged at a contact interval 37 opposite the first element region 24 from the second electrode layer 35.

[0252] [Para 1-4]

[0253] The semiconductor device 1 according to para 1-3, wherein

[0254] The first trench electrode structure 27 comprises a first trench 47 and a first buried electrode 49 buried in the first trench 47,

[0255] The second trench electrode structure 29 comprises a second trench 61 and a second buried electrode 63 buried in the second trench 61 and covered by the insulating layer 67,

[0256] The first electrode layer 34 comprises a first contact layer 38 integrally drawn from the first buried electrode 49 onto the first main face 3 and covering the plurality of the first trench electrode structures 27.

[0257] [Para 1-5]

[0258] The semiconductor device 1 according to Para 1-4,

[0259] Further comprising a second contact layer 39 formed adjacent to the extension electrode 33 in the second direction Y, integrally led out from the second buried electrode 63 onto the first main surface 3, and covering the plurality of second trench electrode structures 29.

[0260] [Para 1-6]

[0261] The semiconductor device 1 according to Para 1-5, wherein

[0262] The second contact layer 39 has a shape arranged with the extension electrode 33 and extending in a band shape in the first direction X.

[0263] [Para 1-7]

[0264] The semiconductor device 1 according to Para 1-5,

[0265] Further comprising a third trench electrode structure 28 extending in the first element region 24 side by side with the first trench electrode structure 27, not crossing the extension electrode 33, and having a terminal portion 31 on the inner side of the first element region 24 departing from the extension electrode 33 in the second direction Y.

[0266] [Para 1-8]

[0267] The semiconductor device 1 according to Para 1-7, wherein

[0268] The third trench electrode structure 28 includes a third trench 55, and a third buried electrode 57 buried in the third trench 55 and covered by the insulating layer 67,

[0269] Further comprising a third contact layer 40 integrally led out from the third buried electrode 57 onto the first main surface 3 in the terminal portion 31 of the third trench electrode structure 28, and a surface electrode layer 12 covering and connected to the second contact layer 39 and the third contact layer 40.

[0270] [Para 1-9]

[0271] The semiconductor device 1 according to Para 1-8, wherein

[0272] The plurality of extension electrodes 33 are formed at intervals in the second direction Y,

[0273] The surface electrode layer 12 covers each of the first element region 24 and the second element region 25 in the divided region 20 sandwiched by the adjacent extension electrodes 33.

[0274] [Para 1-10]

[0275] The semiconductor device 1 according to any one of Para 1-2 to Para 1-9, wherein

[0276] a drift region 41 of a first conductivity type formed in the chip 2,

[0277] The first element region 24 includes a body region 50 of a second conductivity type formed in the first main face 3, an emitter region 51 of the first conductivity type formed in a surface layer portion of the body region 50, a collector region 45 of the second conductivity type formed in the second main face 4, and an IGBT region 24 having the trench gate structure 27 as the first trench electrode structure 27,

[0278] The second element region 25 includes a first impurity region 64 of the second conductivity type formed in the first main face 3, a second impurity region 58 of the first conductivity type formed in the second main face 4, and a diode region 25 having a diode-side trench structure 29 as the second trench electrode structure 29 electrically connected to the emitter region 51,

[0279] The extension electrode 33 includes a gate extension electrode 33 electrically connected to the trench gate structure 27.

[0280] [Para 1-11]

[0281] The semiconductor device 1 according to Para 1-10,

[0282] a well region 87 of the second conductivity type formed in the first main face 3 directly below the gate extension electrode 33 deeper than the trench gate structure 27 and the diode-side trench structure 29.

[0283] [Para 1-12]

[0284] The semiconductor device 1 according to Para 1-11, wherein

[0285] The well region 87 straddles a boundary portion of the IGBT region 24 and the diode region 25 in the first direction X, and traverses the gate extension electrode 33 in the second direction Y, and is integrally connected to the body region 50 of the IGBT region 24 and the first impurity region 64 of the diode region 25.

[0286] [Para 1-13]

[0287] The semiconductor device 1 according to any one of the following Embodiments 1-10 to Embodiment 1-12,

[0288] Further comprising a fourth trench electrode structure 29 formed in the diode region 25A, not crossing the gate extension electrode 33, having a terminal portion 32 on an inner side of the diode region 25A away from the gate extension electrode 33 in the second direction Y,

[0289] The gate extension electrode 33 selectively has a gate resistor 108 in a portion adjacent to the fourth trench electrode structure 29.

[0290] [Embodiment 1-14]

[0291] The semiconductor device 1 according to Embodiment 1-13,

[0292] Further comprising a gate pad electrode 7 electrically connected to the gate extension electrode 33,

[0293] The diode region 25A includes a pad-adjacent diode region 25A adjacent to the gate pad electrode 7 in the first direction X and formed with the fourth trench electrode structure 29,

[0294] The gate extension electrode 33 includes a plurality of the second electrode layers 35, 109, 110 split in a portion crossing the pad-adjacent diode region 25A,

[0295] The gate resistor 108 is formed of a portion of the first electrode layer 34 sandwiched by the plurality of second electrode layers 35, 109, 110.

[0296] [Embodiment 1-15]

[0297] The semiconductor device 1 according to Embodiment 1-13,

[0298] Further comprising a gate pad electrode 7 electrically connected to the gate extension electrode 33,

[0299] The diode region 25 includes a pad-adjacent diode region 25 adjacent to the gate pad electrode 7 in the second direction Y and formed with the fourth trench electrode structure 29,

[0300] The gate extension electrode 33 includes a plurality of the second electrode layers 35, 109, 110 split in a portion crossing the pad-adjacent diode region 25,

[0301] The gate resistor 108 is formed by a portion of the first electrode layer 34 sandwiched by the plurality of second electrode layers 35, 109, 110.

[0302] [Para 2-1]

[0303] A semiconductor device 1 includes:

[0304] A chip 2 having a first main surface 3;

[0305] An IGBT region 24 formed on the first main surface 3 of the chip 2;

[0306] A diode region 25 formed on the first main surface 3 of the chip 2, adjacent to the IGBT region 24 in a first direction X;

[0307] A gate extension electrode 33 extending continuously across the IGBT region 24 and the diode region 25 in the first direction X in a region on the first main surface 3; and

[0308] A trench gate structure 27 formed on the first main surface 3 of the chip 2, extending across the gate extension electrode 33,

[0309] The gate extension electrode 33 avoids a portion directly above the trench gate structure 27, and selectively has a gate resistor 108 in a portion crossing the diode region 25.

[0310] According to this structure, the gate extension electrode 33 has the gate resistor 108. The gate resistor 108 constitutes a gate resistance for a gate of the IGBT. For example, the gate resistor 108 is effective in suppressing oscillation (noise) caused by a parasitic inductance at the time of turn-off. In addition, the gate resistor 108 avoids a portion directly above the trench gate structure 27, and is selectively disposed in a portion of the gate extension electrode 33 crossing the diode region 25. Therefore, an increase in area of the chip 2 can be avoided due to the gate resistor 108. Therefore, the semiconductor device 1 having the gate resistor 108 can be provided without impairing an effective area of the IGBT region 24.

[0311] [Para 2-2]

[0312] The semiconductor device 1 according to Para 2-1,

[0313] Further includes an insulating layer 67 covering the first main surface 3,

[0314] A plurality of the IGBT regions 24 sandwiching the diode region 25 in the first direction X are formed,

[0315] The gate extension electrode 33 includes a resistance layer 103 formed between the insulating layer 67 and the first main surface 3, extending continuously across the IGBT region 24 and the diode region 25 in the first direction X, and a plurality of wiring layers 104 formed on the insulating layer 67, portions thereof across the diode region 25 being divided, the resistance being lower than that of the resistance layer 103,

[0316] The gate resistor 108 is formed of a portion of the resistance layer 103 sandwiched by the plurality of wiring layers 104.

[0317] [Note 2-3]

[0318] The semiconductor device 1 according to Note 2-2,

[0319] The trench gate structure 27 includes a gate trench 47 and a gate buried electrode 49 buried in the gate trench 47,

[0320] The resistance layer 103 is formed into a constant-width planar band that is drawn out from the gate buried electrode 49 to the first main surface 3 integrally.

[0321] [Note 2-4]

[0322] The semiconductor device 1 according to Note 2-2,

[0323] The gate resistor 108 further includes a resistance trench 113 formed in the first main surface 3 of the chip 2 and a resistance electrode layer 115 buried in the resistance trench 113, which is integral with the resistance layer 103.

[0324] [Note 2-5]

[0325] The semiconductor device 1 according to Note 2-4,

[0326] The resistance trench 113 is formed into a planar band that is long in a direction across the gate extension electrode 33.

[0327] [Note 2-6]

[0328] The semiconductor device 1 according to any one of Note 2-1 to Note 2-5,

[0329] includes a gate pad electrode 7 electrically connected to the gate extension electrode 33,

[0330] The gate extension electrode 33 includes a ring-shaped peripheral portion 100 that surrounds the gate pad electrode 7 and an extension portion 101 extending in a band shape from the peripheral portion 100 in the first direction X,

[0331] The diode region 25 includes a pad-adjacent diode region 25A adjacent to the gate pad electrode 7 in the first direction X,

[0332] A diode-side trench structure 29 is further included, which is formed in the pad-adjacent diode region 25A, has a terminal portion 32 on an inner side of the pad-adjacent diode region 25A away from the extension portion 101 in a second direction Y intersecting the first direction X,

[0333] The gate resistor 108 is formed in the extension portion 101 adjacent to the terminal portion 32 of the diode-side trench structure 29.

[0334] [Para 2-7]

[0335] The semiconductor device 1 according to any one of Paras 2-6,

[0336] A plurality of the IGBT regions 24 and a plurality of the diode regions 25 are alternately arranged in the first direction X,

[0337] The pad-adjacent diode region 25A is selectively formed in a portion adjacent to the gate pad electrode 7 in the first direction X,

[0338] A diode-side second trench structure 29 is formed in the diode region 25 other than the pad-adjacent diode region 25A, which is formed in the first main face 3 of the chip 2, and which traverses the extension portion 101.

[0339] [Para 2-8]

[0340] The semiconductor device 1 according to Para 2-6 or Para 2-7,

[0341] The gate pad electrode 7 is disposed at a peripheral portion of the chip 2,

[0342] The gate extension electrode 33 includes an outer extension electrode 16 formed from the gate pad electrode 7 along a peripheral portion of the chip 2 so as to surround an active region 18, and inner extension electrodes 17, 33 traversing the active region 18, having one end portion and another end portion connected to different positions in the outer extension electrode 16,

[0343] The gate resistor 108 is formed in the inner extension electrodes 17, 33.

[0344] [Para 2-9]

[0345] The semiconductor device 1 according to any one of Paras 2-1 to 2-5,

[0346] a gate pad electrode 7 electrically connected to the gate extension electrode 33,

[0347] The gate extension electrode 33 includes a ring-shaped peripheral portion 100 that surrounds the gate pad electrode 7, and an extension portion 101 that extends in a band shape from the peripheral portion 100 in the first direction X,

[0348] The diode region 25 includes a pad-adjacent diode region 25A that is adjacent to the gate pad electrode 7 in a second direction Y that intersects the first direction X,

[0349] A diode-side trench structure 29 is further included, which is formed in the pad-adjacent diode region 25A, has a terminal portion 32 on an inner side of the pad-adjacent diode region 25A that is away from the peripheral portion 100 in the second direction Y,

[0350] The gate resistor 108 is formed in the peripheral portion 100 of the gate extension electrode 33 adjacent to the terminal portion 32 of the diode-side trench structure 29.

[0351] [Para 2-10]

[0352] The semiconductor device 1 according to Para 2-9, wherein

[0353] A plurality of the IGBT regions 24 and a plurality of the diode regions 25 are alternately arranged in the first direction X,

[0354] The pad-adjacent diode region 25A is selectively formed in a portion adjacent to the gate pad electrode 7 in the second direction Y,

[0355] A diode-side second trench structure 29 is formed in the diode region 25 other than the pad-adjacent diode region 25A, which is formed in the first main surface 3 of the chip 2, and which traverses the extension portion 101.

[0356] [Para 2-11]

[0357] The semiconductor device 1 according to any one of Paras 2-1 to 2-10, wherein

[0358] The gate resistor 108 is formed of polysilicon.

[0359] [Para 3-1]

[0360] A semiconductor device 1 includes:

[0361] a chip 2 having a first main surface 3 and a second main surface 4;

[0362] a first element region 24 formed on the first main face 3 of the chip 2;

[0363] a second element region 25 formed on the first main face 3 of the chip 2, adjacent to the first element region 24 in the first direction X;

[0364] a gate extension electrode 33 extending continuously across the first element region 24 and the second element region 25 in the first direction X in a region on the first main face 3;

[0365] a trench gate structure 27 formed on the first main face 3 of the first element region 24, extending across the gate extension electrode 33;

[0366] a second trench electrode structure 29 formed on the first main face 3 of the second element region 25, not extending across the gate extension electrode 33, having a terminal portion 32 on an inner side of the second element region 25 away from the gate extension electrode 33 in a second direction Y intersecting the first direction X;

[0367] a gate auxiliary trench 95 formed directly below the gate extension electrode 33 in a portion adjacent to the second element region 25 in the second direction Y; and

[0368] a gate auxiliary buried electrode 97 buried through a gate insulating film 96 in the gate auxiliary trench 95, electrically connected to the gate extension electrode 33.

[0369] According to this structure, the gate auxiliary buried electrode 97 electrically connected to the gate extension electrode 33 is formed. Thereby, the gate capacitance can be increased, and thus the ESD tolerance of the gate can be improved. In addition, the gate auxiliary buried electrode 97 is disposed in the free space directly below the gate extension electrode 33. Therefore, for the gate auxiliary buried electrode 97, an increase in the chip 2 area and an increase in the gate trench 47 density can be avoided. Thereby, an increase in the chip cost and an increase in the process difficulty can be suppressed.

[0370] [Note 3-2]

[0371] The semiconductor device 1 according to Note 3-1, in which

[0372] The gate auxiliary trench 95 is a trench longer in the second direction Y.

[0373] [Note 3-3]

[0374] The semiconductor device 1 according to Note 3-2, in which

[0375] The gate auxiliary trench 95 includes a plurality of elliptical trenches whose long diameter direction coincides with the second direction Y.

[0376] [Note 3-4]

[0377] The semiconductor device 1 according to Note 3-2,

[0378] The gate auxiliary trench 95 includes a plurality of strip-shaped trenches whose length direction coincides with the second direction Y.

[0379] [Note 3-5]

[0380] The semiconductor device 1 according to any one of Note 3-2 to Note 3-4,

[0381] The gate auxiliary trench 95 has an end portion 98 that protrudes outward beyond the gate extension electrode 33 in the second direction Y.

[0382] [Note 3-6]

[0383] The semiconductor device 1 according to any one of Note 3-1 to Note 3-5,

[0384] The trench gate structure 27 includes a gate trench 47 and a gate buried electrode 49 buried in the gate trench 47,

[0385] The gate extension electrode 33 includes a first electrode layer 34 that is integrally drawn out onto the first main surface 3 from the gate buried electrode 49 and the gate auxiliary buried electrode 97, covering the gate trench 47 and the gate auxiliary trench 95, and a second electrode layer 35 that is formed on the first electrode layer 34 with an insulating layer 67 interposed therebetween, extending across the gate trench 47 and the gate auxiliary trench 95 and in the first direction X.

[0386] [Note 3-7]

[0387] The semiconductor device 1 according to Note 3-6,

[0388] The first electrode layer 34 is strip-shaped and extends at a constant width in the first direction X.

[0389] The second electrode layer 35 is strip-shaped and extends at a constant width in the first direction X.

[0390] [Note 3-8]

[0391] The semiconductor device 1 according to any one of Note 3-1 to Note 3-7,

[0392] includes a drift region 41 of a first conductivity type formed in the chip 2,

[0393] The first element region 24 includes a body region 50 of the second conductivity type formed on the first main face 3, an emitter region 51 of the first conductivity type formed on a surface layer portion of the body region 50, a collector region 45 of the second conductivity type formed on the second main face 4, and an IGBT region 24 having the trench gate structure 27,

[0394] The second element region 25 includes a first impurity region 64 of the second conductivity type formed on the first main face 3, a second impurity region 58 of the first conductivity type formed on the second main face 4, and a diode region 25 having a diode side trench structure 29 as the second trench electrode structure 29 electrically connected to the emitter region 51.

[0395] [Note 3-9]

[0396] The semiconductor device 1 according to Note 3-8,

[0397] The diode side trench structure 29 and the gate auxiliary trench 95 are formed on the same imaginary straight line 99 extending along the second direction Y.

[0398] [Note 3-10]

[0399] The semiconductor device 1 according to Note 3-8 or 3-9,

[0400] The gate extension electrode 33 selectively has a gate resistor 108 in a portion avoiding directly above the trench gate structure 27 and in a portion crossing the diode region 25.

[0401] [Note 3-11]

[0402] The semiconductor device 1 according to Note 3-10,

[0403] includes an insulating layer 67 covering the first main face 3,

[0404] a plurality of the IGBT regions 24 sandwiching the diode region 25 in the first direction X are formed,

[0405] The gate extension electrode 33 includes a resistor layer 103 formed between the insulating layer 67 and the first main face 3, which extends continuously across the IGBT regions 24 and the diode region 25 in the first direction X, and a plurality of wiring layers 104 formed on the insulating layer 67, which are divided in a portion crossing the diode region 25, and have a lower resistance than the resistor layer 103,

[0406] The gate resistor 108 is formed of a portion of the resistance layer 103 sandwiched by the plurality of wiring layers 104.

[0407] [Para 3-12]

[0408] The semiconductor device 1 according to Para 3-11, wherein

[0409] The gate resistor 108 further includes a resistance trench 113 formed in the first main surface 3 of the chip 2, and a resistance buried electrode 115 buried in the resistance trench 113, integrated with the resistance layer 103.

[0410] [Para 3-13]

[0411] The semiconductor device 1 according to Para 3-12, wherein

[0412] The resistance trench 113 is formed in a top view as a band long in a direction crossing the gate extension electrode 33.

[0413] [Para 3-14]

[0414] The semiconductor device 1 according to any one of Paras 3-10 to 3-13,

[0415] Further including a gate pad electrode 7 electrically connected to the gate extension electrode 33,

[0416] The diode region 25 includes a pad-adjacent diode region 25A adjacent to the gate pad electrode 7 in the first direction X,

[0417] The gate resistor 108 is formed in the gate extension electrode 33 at a position in the vicinity of the pad-adjacent diode region 25A.

[0418] [Para 3-15]

[0419] The semiconductor device 1 according to any one of Paras 3-10 to 3-13,

[0420] Further including a gate pad electrode 7 electrically connected to the gate extension electrode 33,

[0421] The diode region 25 includes a pad-adjacent diode region 25A adjacent to the gate pad electrode 7 in the second direction Y,

[0422] The gate resistor 108 is formed in the gate extension electrode 33 at a position in the vicinity of the pad-adjacent diode region 25A.

[0423] Explanation of Symbols

[0424] 1 - semiconductor device, 2 - semiconductor chip, 3 - first main surface, 4 - second main surface, 5A - side surface, 5B - side surface, 5C - side surface, 5D - side surface, 6 - electrode film, 7 - gate terminal electrode, 8 - first sensing terminal electrode, 9 - second sensing terminal electrode, 10 - current detection terminal electrode, 11 - open terminal electrode, 12 - emitter terminal electrode, 13 - gate wiring, 14 - first sensing wiring, 15 - second sensing wiring, 16 - first portion, 17 - second portion, 18 - active region, 19 - peripheral region, 20 - division region, 21 - central wiring, 22 - side wiring, 23 - sensor region, 24 - IGBT region, 25 - diode region, 25A - pad-adjacent diode region, 26 - RC-IGBT arrangement, 27 - trench gate structure, 28 - emitter trench structure, 29 - diode side trench structure, 30 - termination portion, 31 - termination portion, 32 - termination portion, 33 - gate extension electrode, 34 - first electrode layer, 35 - second electrode layer, 36 - non-contact section, 37 - contact section, 38 - first contact layer, 39 - second contact layer, 40 - third contact layer, 41 - drift region, 42 - semiconductor substrate, 43 - collector terminal electrode, 44 - buffer layer, 45 - collector region, 46 - FET structure, 47 - gate trench, 48 - gate insulating layer, 49 - gate electrode layer, 50 - bulk region, 51 - emitter region, 52 - carrier storage region, 53 - contact trench, 54 - contact region, 55 - emitter trench, 56 - emitter insulating layer, 57 - emitter potential electrode layer, 58 - cathode region, 59 - diode cell region, 60 - cell separation structure, 61 - cell separation trench, 62 - cell separation insulating layer, 63 - cell separation electrode layer, 64 - anode region, 65 - pn junction portion, 66 - diode trench, 67 - interlayer insulating layer, 68 - first insulating layer, 69 - second insulating layer, 70 - third insulating layer, 71 - emitter opening, 72 - diode opening, 73 - emitter plug electrode, 74 - barrier electrode layer, 75 - main electrode layer, 76 - diode plug electrode, 77 - first electrode layer, 78 - second electrode layer, 79 - third electrode layer, 80 - lead-out electrode layer, 81 - first opening, 82 - first plug electrode, 83 - lead-out electrode layer, 84 - second opening, 85 - second plug electrode, 86 - boundary region, 87 - well region, 88 - lead-out portion, 89 - upper side protruding portion, 90 - lead-out electrode layer, 91 - gate opening, 92 - gate plug electrode, 93 - gate auxiliary trench structure, 94 - termination portion, 95 - gate auxiliary trench, 96 - gate auxiliary insulating layer, 97 - gate auxiliary electrode layer, 98 - termination portion, 99 - imaginary straight line, 100 - surrounding portion, 101 - extension portion, 102 - gap region, 103 - resistance layer, 104 - wiring layer, 105 - pad support layer, 106 - surrounding contact, 107 - pad contact108 - gate resistor, 109 - first extension, 110 - second extension, 111 - resistor contact, 112 - trench resistor structure, 113 - resistor trench, 114 - resistor insulation layer, 115 - resistor electrode layer, 116 - lead-out resistor layer, 117 - first surrounding portion, 118 - second surrounding portion.

Claims

1. A semiconductor device, characterized in that, Include: A chip, which has a first main surface; IGBT regions are formed on the first main surface of the chip; A diode region is formed on the first main surface of the chip and is adjacent to the IGBT region in a first direction; A gate extension electrode extends continuously across the IGBT region and the diode region along the first direction in a region on the first main surface. as well as A trench gate structure is formed on the first main surface of the chip and extends transversely through the gate extension electrode. The gate extension electrode avoids the portion directly above the trench gate structure and selectively has a gate resistor in the portion that traverses the diode region.

2. The semiconductor device according to claim 1, characterized in that, Includes an insulating layer covering the first main surface. A plurality of IGBT regions are formed with the diode region sandwiched between them in the first direction. The gate extension electrode includes a resistive layer formed between the insulating layer and the first main surface, extending continuously across the IGBT region and the diode region in the first direction; And multiple wiring layers, formed on the insulating layer, segmented in the portion traversing the diode region, with lower resistance than the resistive layer. The gate resistor is formed from a portion of the resistor layer sandwiched between the plurality of wiring layers.

3. The semiconductor device according to claim 2, characterized in that, The trench gate structure includes a gate trench and a gate embedded electrode buried in the gate trench. The resistive layer is formed as a top-view strip of constant width, integrally led out from the gate embedded electrode to the first main surface.

4. The semiconductor device according to claim 2, characterized in that, The gate resistor further includes: a resistor trench formed on the first main surface of the chip; and a resistor embedded electrode embedded in the resistor trench and integral with the resistor layer.

5. The semiconductor device according to claim 4, characterized in that, The resistive trench is formed as a long, top-view strip in the direction traversing the gate extension electrode.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, Includes a gate pad electrode electrically connected to the gate extension electrode. The gate extension electrode includes an annular peripheral portion surrounding the gate pad electrode and an extension portion extending in a strip shape from the peripheral portion along the first direction. The diode region is included in the pad-adjacent diode region adjacent to the gate pad electrode in the first direction. It also includes a diode-side trench structure formed in the pad-adjacent diode region, having a termination portion inside the pad-adjacent diode region extending from the extension along a second direction intersecting the first direction. The gate resistor is formed adjacent to the terminal portion of the diode-side trench structure in the extension.

7. The semiconductor device according to claim 6, characterized in that, Multiple IGBT regions and multiple diode regions are alternately arranged in the first direction. The pad-adjacent diode region is selectively formed in the portion adjacent to the gate pad electrode in the first direction. A diode-side second trench structure is formed in the diode region other than the diode region adjacent to the pad. This diode-side second trench structure is formed on the first main surface of the chip and traverses the extension.

8. The semiconductor device according to claim 6 or 7, characterized in that, The gate pad electrode is disposed at the periphery of the chip. The gate extension electrode includes: an outer extension electrode formed from the gate pad electrode along the periphery of the chip, surrounding the active region; and an inner extension electrode traversing the active region, having one end and another end connected to different positions within the outer extension electrode. The gate resistor is formed on the inner extended electrode.

9. The semiconductor device according to any one of claims 1 to 5, characterized in that, Includes a gate pad electrode electrically connected to the gate extension electrode. The gate extension electrode includes an annular peripheral portion surrounding the gate pad electrode and an extension portion extending in a strip shape from the peripheral portion along the first direction. The diode region is included in the pad-adjacent diode region adjacent to the gate pad electrode in a second direction intersecting the first direction. It also includes a diode-side trench structure formed in the diode region adjacent to the pad, having a termination portion on the inner side of the diode region adjacent to the pad, which extends from the surrounding portion along the second direction. The gate resistor is formed adjacent to the terminal portion of the diode-side trench structure at the periphery of the gate extension electrode.

10. The semiconductor device according to claim 9, characterized in that, Multiple IGBT regions and multiple diode regions are alternately arranged in the first direction. The pad-adjacent diode region is selectively formed in the portion adjacent to the gate pad electrode in the second direction. A diode-side second trench structure is formed in the diode region other than the diode region adjacent to the pad. This diode-side second trench structure is formed on the first main surface of the chip and traverses the extension.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The gate resistor is formed of polysilicon.

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