Semiconductor device, display device, display module, and electronic apparatus

Abstract

Provided is a novel semiconductor device having excellent convenience, practicality, and reliability. The semiconductor device includes a first functional layer, a second functional layer overlapping the first functional layer and including a functional element including a first electrode, and a first conductive layer. The first functional layer includes a first layer, a spacer and a transistor, and is sandwiched between the second functional layer and the spacer. The first layer includes a first opening, and the first layer has insulating properties. The spacer includes a first surface, a second surface, a third surface, and a second opening. The first surface, the second surface, and the third surface have insulating properties. The second surface faces the first surface, and the second surface is closer to the first layer than the first surface. The third surface connects the first surface and the second surface and is located on a side surface of the second opening. The transistor includes a second electrode, a third electrode, a fourth electrode, a semiconductor layer and an insulating layer. The first conductive layer electrically connects the third electrode and the first electrode through the first opening.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device, a display device, a display module, or an electronic device.

[0002] Note that one embodiment of the present application is not limited to the technical field described above. The technical field of one embodiment of the present application disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present application relates to a process, a machine, a manufacture, or a composition of matter. Thus, more specifically, examples of the technical field of one embodiment of the application disclosed in this specification are a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. BACKGROUND

[0003] As one of display devices, there is a liquid crystal display device in which a liquid crystal element is used as a display element. For example, an active matrix liquid crystal display device in which pixel electrodes are arranged in a matrix shape and each pixel electrode is connected to a switching element is used for various devices such as a smartphone, a tablet terminal, a display device, a television device, a digital signage, and the like.

[0004] It is known that a liquid crystal display device is roughly classified into two types of a transmissive type and a reflective type. When the effective light-emitting area ratio (also referred to as an aperture ratio) of a pixel in a liquid crystal display device is higher, brighter display can be achieved, and power consumption can be reduced, and thus improvement in the aperture ratio is required.

[0005] For example, it is known that an active matrix liquid crystal display device in which a transistor in which a metal oxide is used for a channel formation region is used as a switching element connected to each pixel electrode. Patent Document 1 discloses a liquid crystal display device in which a transistor in which a metal oxide is used for a channel formation region is used to improve the aperture ratio.

[0006] [Prior Art Documents]

[0007] [Patent Documents]

[0008] [Patent Document 1] Japanese Published Patent Application No. 2018-189938 SUMMARY

[0009] PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] As described above, various inventions are disclosed in prior art documents, but there are many problems in convenience, practicality, or reliability, and thus they are not satisfactory. Thus, one of the objects of one embodiment of the present application is to provide a novel semiconductor device which is excellent in convenience, practicality, or reliability. Another object of the present application is to provide a novel display device which is excellent in convenience, practicality, or reliability. Another object of the present application is to provide a novel display module which is excellent in convenience, practicality, or reliability. Another object of the present application is to provide a novel electronic device which is excellent in convenience, practicality, or reliability. Another object of the present application is to provide a novel semiconductor device, a novel display device, a novel display module, and a novel electronic device.

[0011] Note that the description of these objects does not preclude the existence of other objects. Note that one embodiment of the present application does not need to achieve all the above-described objects. Note that objects other than the above can be derived from the description of the specification, the drawings, the claims, and the like.

[0012] Means for solving the technical problem

[0013] (1) One embodiment of the present application is a semiconductor device including a first functional layer, a second functional layer, and a first conductive layer.

[0014] The second functional layer overlaps with the first functional layer, and the second functional layer includes a functional element, and the functional element includes a first electrode.

[0015] The first functional layer includes a first layer, a spacer, and a transistor. The first layer is interposed between the second functional layer and the spacer, the first layer includes a first opening portion, and the first layer has an insulating property.

[0016] The spacer includes a first surface, a second surface, a third surface, and a second opening portion, and the first surface, the second surface, and the third surface have an insulating property. The second surface faces the first surface, and the second surface is closer to the first layer than the first surface. The third surface connects the first surface and the second surface, and the third surface is positioned on a side surface of the second opening portion.

[0017] The transistor includes a second electrode, a third electrode, a fourth electrode, a semiconductor layer, and an insulating layer. The second electrode includes a region in contact with the first surface and a region overlapping with the second opening portion. The third electrode includes a region in contact with the second surface, a third opening portion, and a fourth surface, the fourth surface is positioned on a side surface of the third opening portion, and the third opening portion overlaps with the second opening portion. The fourth electrode includes a region facing the third surface, and the insulating layer includes a region interposed between the third surface and the fourth electrode. The semiconductor layer includes a region interposed between the third surface and the insulating layer, the semiconductor layer is in contact with the second electrode in the second opening portion, and the semiconductor layer is in contact with the third electrode in the fourth surface.

[0018] The first conductive layer electrically connects the third electrode and the first electrode through the first opening portion.

[0019] (2) In addition, one embodiment of the present application is the above-described semiconductor device including a second conductive layer.

[0020] The second conductive layer is electrically connected to the second electrode, has light-blocking properties, and overlaps with the first opening portion.

[0021] Thus, a step formed on the first opening portion can overlap with the second conductive layer. Further, a flat region can be formed in a region which does not overlap with the second conductive layer. Further, an electrode of a functional element can be formed in the flat region. Further, a flat region can be formed in the electrode. Further, a layer containing liquid crystal can be formed on the flat region of the electrode, for example. The second conductive layer can be arranged between the layer containing liquid crystal and the backlight, for example. In addition, the second conductive layer can be used to block light in order to prevent light of the backlight from reaching a region of alignment disorder formed in the layer containing liquid crystal due to the step on the first opening portion. In addition, the aperture ratio of a liquid crystal device can be improved. In addition, the luminance of a display device can be improved. In addition, power consumption can be reduced. As a result, a novel semiconductor device with high convenience, utility, or reliability can be provided.

[0022] (3) In addition, one embodiment of the present application is the above-described semiconductor device including a third conductive layer.

[0023] The first functional layer includes a second layer, the second layer is interposed between the first layer and the spacer, the second layer includes a fourth opening portion, and the second layer has insulating properties.

[0024] The third conductive layer is interposed between the first layer and the second layer, overlaps with the first opening portion and the fourth opening portion, electrically connects the first conductive layer and the third electrode, and has light-transmitting properties.

[0025] Further, the third electrode has light-transmitting properties.

[0026] (4) In addition, one embodiment of the present application is the above-described semiconductor device including a fourth conductive layer.

[0027] The fourth conductive layer is interposed between the first layer and the third conductive layer. In addition, the fourth conductive layer has light-transmitting properties.

[0028] Thus, a capacitor can be formed using the fourth conductive layer, the third conductive layer, and the first layer. Further, the potential of the third conductive layer can be held at a prescribed potential when the transistor is in a non-conductive state. Further, the potential of the first electrode of the functional element can be held at a prescribed potential. For example, an electric field of a prescribed strength can be continuously applied to a layer including liquid crystal. As a result, a novel semiconductor device with high convenience, utility, or reliability can be provided.

[0029] (5) In addition, one embodiment of the present application is the above-described semiconductor device including a third conductive layer.

[0030] The first functional layer includes a second layer, the second layer is interposed between the first layer and the spacer, the second layer includes a fourth opening portion, and the second layer has an insulating property.

[0031] The third conductive layer is interposed between the first layer and the second layer, the third conductive layer overlaps the first opening portion and the fourth opening portion, the third conductive layer electrically connects the first conductive layer and the third electrode, and the third conductive layer has a light-transmitting property.

[0032] In addition, the second electrode has a light-blocking property, and the first opening portion overlaps the second electrode.

[0033] Thus, a step formed on the first opening portion can overlap the second electrode of the transistor. Further, a flat region can be formed in a region which does not overlap the second electrode. Further, an electrode of a functional element can be formed in the flat region. Further, a flat region can be formed in the electrode. Further, a layer including liquid crystal can be formed on the flat region of the electrode, for example. For example, the second electrode can be positioned between the layer including liquid crystal and a backlight. In addition, the second electrode can be used to block light from the backlight so that an alignment disordered region formed in the layer including liquid crystal due to a step on the first opening portion can be prevented. In addition, the aperture ratio of a liquid crystal device can be increased. In addition, the luminance of a display device can be increased. In addition, power consumption can be reduced. As a result, a novel semiconductor device with high convenience, utility, or reliability can be provided.

[0034] (6) In addition, one embodiment of the present application is the above-described semiconductor device including a third conductive layer and a fifth conductive layer.

[0035] The first functional layer includes a second layer, the second layer is interposed between the first layer and the spacer, the second layer includes a fourth opening portion, and the second layer has an insulating property.

[0036] The third conductive layer is interposed between the first layer and the second layer, the third conductive layer overlaps the first opening portion and the fourth opening portion, the third conductive layer electrically connects the first conductive layer and the third electrode, and the third conductive layer has a light-transmitting property.

[0037] The fifth conductive layer is electrically connected to the fourth electrode, overlaps with the first opening portion, and has light-blocking properties.

[0038] Thus, a step formed on the first opening portion can overlap with the seventh conductive layer. Further, a flat region can be formed in a region that does not overlap with the seventh conductive layer. Furthermore, an electrode of a functional element can be formed in the flat region. Moreover, a flat region can be formed in the electrode. Furthermore, a layer containing liquid crystal, for example, can be formed on the flat region of the electrode. For example, the seventh conductive layer can be arranged between the layer containing liquid crystal and the backlight. Further, in order to prevent light of the backlight from reaching a region of alignment disorder formed in the layer containing liquid crystal due to the step on the first opening portion, the seventh conductive layer can be used to block light. Further, the aperture ratio of the liquid crystal device can be improved. Further, the luminance of the display device can be improved. Further, power consumption can be reduced. As a result, a novel semiconductor device excellent in convenience, practicality, or reliability can be provided.

[0039] (7) Further, one embodiment of the present application is a display device in which the functional element is a liquid crystal device.

[0040] (8) Further, one embodiment of the present application is a display module including the above display device and at least one of a connector and an integrated circuit.

[0041] (9) Further, one embodiment of the present application is an electronic device including the above display device and at least one of a battery, a camera, a speaker, and a microphone.

[0042] In the drawings of this specification, a block diagram in which constituent elements are shown as blocks independent of one another according to their functions is shown, but actual constituent elements are difficult to be completely classified according to their functions, and one constituent element can involve a plurality of functions.

[0043] In this specification, a light-emitting device includes an image display device using a light-emitting element. Further, the light-emitting device sometimes includes a module in which a light-emitting element is mounted on a connector such as an anisotropic conductive film or a TCP (Tape Carrier Package); a module in which a printed wiring board is provided at an end portion of a TCP; or a module in which an IC (Integrated Circuit) is directly mounted on a light-emitting element by a COG (Chip On Glass) method. Furthermore, an illumination device or the like sometimes includes a light-emitting device.

[0044] Effects of Invention

[0045] According to one embodiment of the present application, a novel semiconductor device excellent in convenience, practicality, or reliability can be provided. According to one embodiment of the present application, a novel display device excellent in convenience, practicality, or reliability can be provided. According to one embodiment of the present application, a novel display module excellent in convenience, practicality, or reliability can be provided. According to one embodiment of the present application, a novel electronic device excellent in convenience, practicality, or reliability can be provided. According to the present application, a novel semiconductor device can be provided. According to the present application, a novel display device can be provided. According to the present application, a novel display module can be provided. According to the present application, a novel electronic device can be provided.

[0046] Note that the description of these effects does not preclude the presence of other effects. One embodiment of the present application does not necessarily achieve all the effects described above. Note that an effect other than those described above can be derived from the description, the drawings, the claims, and the like. BRIEF DESCRIPTION OF DRAWINGS

[0047] FIGS. 1A-1C is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0048] FIG. 2A and FIG. 2B is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0049] FIG. 3 is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0050] FIG. 4 is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0051] FIGS. 5A-5C is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0052] FIG. 6A and FIG. 6B is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0053] FIG. 7 is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0054] FIG. 8 is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0055] FIGS. 9A-9C is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0056] FIG. 10A and FIG. 10B is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0057] FIG. 11 FIG. 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0058] FIG. 12 FIG. 2 is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0059] FIGS. 13A-13C FIG. 3 is a diagram illustrating a structure of a semiconductor device according to an embodiment.

[0060] FIG. 14A FIG. 4 is a diagram illustrating a structure of a semiconductor device according to an embodiment. FIG. 14B

[0061] FIG. 5 is a diagram illustrating a structure of a semiconductor device according to an embodiment. FIG. 15

[0062] FIG. 6 is a diagram illustrating a structure of a semiconductor device according to an embodiment. FIG. 16

[0063] FIG. 7 is a diagram illustrating a structure of a display device according to an embodiment. FIG. 17

[0064] FIG. 8 is a diagram illustrating a structure of a display device according to an embodiment. FIG. 18

[0065] FIG. 9 is a diagram illustrating a structure of a display device according to an embodiment. FIG. 19

[0066] FIG. 10 is a diagram illustrating a structure of a display device according to an embodiment. FIG. 20

[0067] FIG. 11 is a diagram illustrating a structure of a display device according to an embodiment. FIG. 21

[0068] FIG. 12 is a diagram illustrating a structure of a transistor according to an embodiment. FIGS. 22A-22D

[0069] FIG. 13 is a diagram illustrating a structure of a transistor according to an embodiment. FIGS. 23A-23F

[0070] FIG. 14 is a diagram illustrating a structure of a transistor according to an embodiment. FIG. 24A FIG. 24B FIG. 15 is a diagram illustrating a structure of a transistor according to an embodiment.

[0071] FIG. 25A FIG. 25B FIG. 16 is a diagram illustrating a structure of a transistor according to an embodiment.

[0072] FIGS. 26A-26C FIG. 17 is a diagram illustrating a structure of a display device according to an embodiment. ​​

[0073] FIGS. 27A-27D FIG. 1 is a diagram illustrating a driving method of a display device according to an embodiment.

[0074] FIG. 28 FIG. 2 is a diagram illustrating a structure of a display device according to an embodiment.

[0075] FIGS. 29A-29C FIG. 3 is a diagram illustrating a structure of a display module according to an embodiment.

[0076] FIGS. 30A-30F FIG. 4 is a diagram illustrating a structure of an electronic device according to an embodiment. DETAILED DESCRIPTION

[0077] A semiconductor device of one embodiment of the present application includes a first functional layer, a second functional layer, and a first conductive layer. The second functional layer overlaps with the first functional layer, and the second functional layer includes a functional element including a first electrode. The first functional layer includes a first layer, a spacer, and a transistor, the first layer is interposed between the second functional layer and the spacer, the first layer includes a first opening portion, and the first layer is insulative. The spacer includes a first surface, a second surface, a third surface, and a second opening portion, the first surface, the second surface, and the third surface are insulative, the second surface faces the first surface, and the second surface is closer to the first layer than the first surface. Further, the third surface connects the first surface and the second surface, and the third surface is positioned on a side surface of the second opening portion. The transistor includes a second electrode, a third electrode, a fourth electrode, a semiconductor layer, and an insulating layer, the second electrode includes a region in contact with the first surface and a region overlapping with the second opening portion, the third electrode includes a region in contact with the second surface, a third opening portion, and a fourth surface, the fourth surface is positioned on a side surface of the third opening portion, and the third opening portion overlaps with the second opening portion. The fourth electrode includes a region facing the third surface, and the insulating layer includes a region interposed between the third surface and the fourth electrode. The semiconductor layer includes a region interposed between the third surface and the insulating layer, the semiconductor layer is in contact with the second electrode in the second opening portion, the semiconductor layer is in contact with the third electrode at the fourth surface, and the first conductive layer electrically connects the third electrode and the first electrode through the first opening portion.

[0078] Therefore, the step formed on the first opening can overlap with the second conductive layer. Furthermore, a flat region can be formed in the area that does not overlap with the second conductive layer. Furthermore, electrodes for functional elements can be formed in this flat region. Furthermore, a flat region can be formed in this electrode. Furthermore, a liquid crystal-containing layer can be formed, for example, on the flat region of the electrode. For example, the second conductive layer can be disposed between the liquid crystal-containing layer and the backlight. To prevent backlight light from reaching the disordered region in the liquid crystal-containing layer formed due to the step on the first opening, the second conductive layer can be used to block light. Furthermore, the aperture ratio of the liquid crystal device can be increased. Furthermore, the brightness of the display device can be increased. Furthermore, power consumption can be reduced. As a result, a novel semiconductor device with excellent convenience, practicality, and reliability can be provided.

[0079] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below. Note that in the inventive structures described below, the same reference numerals are used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted.

[0080] (Implementation Method 1)

[0081] In this embodiment, refer to Figures 1 to 12. FIG. 16 The structure of a semiconductor device according to one aspect of the present invention is described.

[0082] FIG. 1A This is a perspective view schematically illustrating the structure of a semiconductor device according to one aspect of the present invention. FIG. 1B This is a cross-sectional view schematically illustrating the structure of a semiconductor device according to one embodiment of the present invention. Furthermore, FIG. 1C This is a top view illustrating an example of a semiconductor device according to one aspect of the present invention.

[0083] FIG. 2A This is an explanation FIG. 1C The image shows a front view of a portion of a semiconductor device according to one aspect of the present invention. FIG. 2B It is along FIG. 2A The cross-sectional view of the cut-off line P1-P2 is shown.

[0084] FIG. 3 This is a detailed explanation. FIG. 2B A diagram showing a portion of the structure. Note that, for simplicity, the shading lines of some constituent elements have been omitted.

[0085] FIG. 4 is a cross-sectional view of a structure of a semiconductor device of one embodiment of the present application, which is different from that of the semiconductor device illustrated in FIG. 1. FIG. 2B

[0086] FIG. 5A is a perspective view schematically illustrating a structure of a semiconductor device of one embodiment of the present application, FIG. 5B is a cross-sectional view schematically illustrating a structure of a semiconductor device of one embodiment of the present application. In addition, FIG. 5C is a top view of one example of a semiconductor device of one embodiment of the present application.

[0087] FIG. 6A is a front view of a part of a semiconductor device of one embodiment of the present application, FIG. 5C is a cross-sectional view along the cut line P1-P2 in FIG. 6B. FIG. 6B FIG. 6A

[0088] FIG. 7 is a cross-sectional view of a structure of a semiconductor device of one embodiment of the present application, which is different from that of the semiconductor device illustrated in FIG. 1. FIG. 6B

[0089] FIG. 8 is a cross-sectional view of a structure of a semiconductor device of one embodiment of the present application, which is different from that of the semiconductor device illustrated in FIG. 1. FIG. 7

[0090] FIG. 9A is a perspective view schematically illustrating a structure of a semiconductor device of one embodiment of the present application, FIG. 9B is a cross-sectional view schematically illustrating a structure of a semiconductor device of one embodiment of the present application. In addition, FIG. 9C is a top view of one example of a semiconductor device of one embodiment of the present application.

[0091] FIG. 10A is a front view of a part of a semiconductor device of one embodiment of the present application, FIG. 9C is a cross-sectional view along the cut line P1-P2 in FIG. 6B. FIG. 10B FIG. 10A

[0092] FIG. 11 is a cross-sectional view of a structure of a semiconductor device of one embodiment of the present application, which is different from that of the semiconductor device illustrated in FIG. 1. FIG. 10B

[0093] FIG. 12 is a cross-sectional view of a structure of a semiconductor device of one embodiment of the present application, which is different from that of the semiconductor device illustrated in​​​​​​​​FIG. 11 The semiconductor device illustrated in FIG. 1A is different from the semiconductor device illustrated in FIG. 1B.

[0094] FIG. 13A is a perspective view schematically illustrating a structure of a semiconductor device of one embodiment of the present application, FIG. 13B is a cross-sectional view schematically illustrating a structure of a semiconductor device of one embodiment of the present application. Note that FIG. 13C is a top view of one example of a semiconductor device of one embodiment of the present application.

[0095] FIG. 14A is a cross-sectional view of a portion of a semiconductor device of one embodiment of the present application, FIG. 13C is a front view of a portion of a semiconductor device of one embodiment of the present application, FIG. 14B is a cross-sectional view taken along FIG. 14A the broken line P1-P2.

[0096] FIG. 15 is a cross-sectional view schematically illustrating a structure of a semiconductor device of one embodiment of the present application, which is different from the semiconductor device illustrated in FIG. 1A. FIG. 14B

[0097] FIG. 16 is a cross-sectional view schematically illustrating a structure of a semiconductor device of one embodiment of the present application, which is different from the semiconductor device illustrated in FIG. 1B. FIG. 15

[0098] <Structure Example 1 of Semiconductor Device>

[0099] One embodiment of the present application is a semiconductor device including a functional layer 510, a functional layer 520, and a conductive layer 519A (see FIG. 1A ).

[0100] <Structure Example 1 of Functional Layer 520>

[0101] The functional layer 520 overlaps with the functional layer 510, and the functional layer 520 includes a functional element 550 (see FIG. 1A and FIG. 1B ).

[0102] <Structure Example of Functional Element 550>

[0103] For example, a liquid crystal device 550LC can be used as the functional element 550 (see FIG. 1C , FIG. 2B or FIG. 4 ​​). The liquid crystal device 550LC includes an electrode 551LC. In addition, the liquid crystal device 550LC includes an electrode 552LC and a layer 553LC including liquid crystal. The electrode 552LC is arranged so as to form an electric field that controls the alignment of the liquid crystal material with the electrode 551LC. Note that a variety of functional elements can be used for the semiconductor device of one embodiment of the present application, not limited to a liquid crystal device. For example, a light-emitting device, an optical conversion device, or a memory device can be used, and a flat region of an electrode can be effectively used.

[0104] For example, the electrode 551LC can have a comb-tooth shape, and the electrode 552LC can be arranged so as to form a horizontal electric field or an edge electric field with the electrode 551LC (see FIG. 5B). FIG. 1C and FIG. 2B Note that the electrode 551LC is interposed between the layer 553LC including liquid crystal and the electrode 552LC.

[0105] For example, the electrode 551LC can be arranged so as to form a vertical electric field with the electrode 552LC (see FIG. 5A). FIG. 4 In addition, the layer 553LC including liquid crystal is interposed between the electrode 551LC and the electrode 552LC.

[0106] In addition, the liquid crystal device 550LC includes an alignment film AF1 and an alignment film AF2. The alignment film AF1 is interposed between the layer 553LC including liquid crystal and the electrode 551LC, and the layer 553LC including liquid crystal is interposed between the alignment film AF2 and the alignment film AF1.

[0107] For example, a transmissive liquid crystal device using a vertical alignment (VA) mode can be used for the liquid crystal device 550LC. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

[0108] Further, the operation mode is not limited to the VA mode, and a liquid crystal device that operates in various modes can be used as the liquid crystal device 550LC. For example, the liquid crystal device 550LC can employ an FFS mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a guest-host mode, or the like.

[0109] Here, the liquid crystal device controls the transmission or non-transmission of light by the optical modulation of liquid crystal using polarized light. The optical modulation of liquid crystal is controlled by an electric field (including a lateral electric field, a longitudinal electric field, or a tilted direction electric field) applied to the liquid crystal. As the liquid crystal that can be used for the liquid crystal device, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a high-molecular dispersion type liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), a high-molecular network type liquid crystal (PNLC (Polymer Network Liquid Crystal)), a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. The above-described liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on the conditions. In addition, as the liquid crystal material, either a positive type liquid crystal or a negative type liquid crystal can be used, and an appropriate liquid crystal material can be used depending on the mode or design.

[0110] <<Structure Example 2 of Functional Layer 520>>

[0111] The functional layer 520 includes a light-blocking film BM, a coloring layer CF, a layer 522, and a layer KB. The light-blocking film BM includes an opening, and the coloring layer CF overlaps the opening of the light-blocking film BM. The layer 522 is interposed between the coloring layer CF and the layer 553LC including liquid crystal, and has insulating properties. The layer KB is interposed between the opening 518_4 and the light-blocking film BM, and the layer KB controls the thickness of the layer 553LC including liquid crystal. Further, the functional layer 520 includes a layer 521. The layer 521 is interposed between the layer 553LC including liquid crystal and the functional layer 510.

[0112] <<Structure Example 1 of Functional Layer 510>>

[0113] Functional layer 510 includes layer 518, spacer 110, and transistor 100 (see reference). FIG. 2B In addition, functional layer 510 includes layer 516.

[0114] [Structure examples of layers 518 and 516]

[0115] Layer 518 is sandwiched between functional layer 520 and spacer 110. Layer 518 includes an opening 518_4 and is insulating. Layer 516 is sandwiched between layer 518 and spacer 110 and overlaps with transistor 100.

[0116] For example, insulating inorganic materials, insulating organic materials, or insulating composite materials containing both inorganic and organic materials can be used for layer 518.

[0117] Specifically, inorganic oxides, inorganic nitrides, or inorganic oxynitrides can be used for layer 518. Alternatively, a laminated material selected from multiple inorganic oxides, inorganic nitrides, and inorganic oxynitrides can be used for layer 518.

[0118] Specifically, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc., can be used for layer 518. Because the silicon nitride film is a dense film, it has excellent impurity diffusion suppression capabilities. Additionally, a film with excellent impurity diffusion suppression capabilities can be appropriately used for layer 516. This prevents impurities that cause a deterioration in the operating characteristics of the transistor 100 from diffusing from the outside of the transistor 100 to the inside.

[0119] Furthermore, for example, polyester, polyolefin, polyamide, polyimide, polycarbonate, polysiloxane, or acrylic resin can be used for layer 518. Additionally, a photosensitive material can be used to form layer 518. Moreover, polyimide possesses superior thermal stability, insulation, toughness, low dielectric constant, low coefficient of thermal expansion, and chemical resistance compared to other organic materials.

[0120] In addition, when layer 518 is formed on the substrate, layer 518 can flatten the steps of the structure originating from the substrate.

[0121] [Structural example of spacer 110]

[0122] Spacer 110 includes surface 110_1, surface 110_2, surface 110_3 and opening 110_4 (see reference). FIG. 3 ). Surfaces 110_1, 110_2 and 110_3 are insulating.

[0123] Face 110_2 is opposite to face 110_1, and face 110_2 is closer to layer 518 than face 110_1.

[0124] For example, the structure of the stacked layer 110A, the layer 110B, and the layer 110C can be used for the spacer 110. When the layer 110C is located between the layer 110A and the layer 110B, for example, the layer 110A constitutes the surface 110_1 and the layer 110B constitutes the surface 110_2.

[0125] The surface 110_3 connects the surface 110_1 and the surface 110_2, and the surface 110_3 is located on a side surface of the opening portion 110_4.

[0126] For example, in the case where the structure of the stacked layer 110A, the layer 110B, and the layer 110C is used for the spacer 110, the surface 110_3 is constituted by a side surface of the opening portion of the layer 110A, a side surface of the opening portion of the layer 110B, and a side surface of the opening portion of the layer 110C.

[0127] [Structure Example of Transistor 100]

[0128] The transistor 100 includes the electrode 112A, the electrode 112B, the electrode 104, the semiconductor layer 108, and the insulating layer 106 (see FIG. 1). FIG. 2B ).

[0129] The electrode 112A includes a region in contact with the surface 110_1 and a region overlapping with the opening portion 110_4.

[0130] The electrode 112B includes a region in contact with the surface 110_2, the opening portion 112B_4, and the surface 112B_3. The surface 112B_3 is located on a side surface of the opening portion 112B_4, and the opening portion 112B_4 overlaps with the opening portion 110_4.

[0131] The electrode 104 includes a region facing the surface 110_3. In addition, the electrode 104 is used as a gate electrode of the transistor 100.

[0132] The insulating layer 106 includes a region sandwiched between the surface 110_3 and the electrode 104. In addition, the insulating layer 106 is used as a gate insulating film of the transistor 100.

[0133] The semiconductor layer 108 includes a region sandwiched between the surface 110_3 and the insulating layer 106. Note that a channel of the transistor 100 is formed in the semiconductor layer 108.

[0134] The semiconductor layer 108 is in contact with the electrode 112A in the opening portion 110_4, and the semiconductor layer 108 is in contact with the electrode 112B in the surface 112B_3. In addition, the electrode 112A is used as one of a source electrode and a drain electrode of the transistor 100, and the electrode 112B is used as the other of the source electrode and the drain electrode of the transistor 100. Further, structures that can be used for the transistor 100 are described in detail in Embodiment 3.

[0135] Structure example of conductive layer 519A

[0136] The conductive layer 519A electrically connects the electrode 112B and the electrode 551LC through the opening portion 518_4.

[0137] For example, a conductive film is formed on the layer 518 in which the opening portion 518_4 overlaps with the electrode 112B, whereby the conductive film can be electrically connected to the electrode 112B in the opening portion 518_4. Further, the conductive film can be processed into a prescribed shape to form the conductive layer 519A and the electrode 551LC. In the case where the conductive layer 519A and the electrode 551LC are formed of the same conductive layer, a portion of the conductive layer which overlaps with the opening portion 518_4 of the layer 518 is used as the conductive layer 519A and a portion of the conductive layer which overlaps with a flat region of the layer 518 is used as the electrode 551LC.

[0138] As the conductive layer 519A, an inorganic conductive material, an organic conductive material, a metal, a conductive oxide, or the like can be used.

[0139] Specifically, a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, and manganese can be used for the conductive layer 519A. Alternatively, an alloy or the like including the above metal element can be used for the conductive layer 519A.

[0140] Specifically, as the conductive layer 519A, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are sequentially stacked, or the like can be used.

[0141] For example, a conductive oxide including indium can be used for the conductive layer 519A. Specifically, indium oxide, indium tin oxide (abbreviation: ITO), indium tin oxide including silicon or silicon oxide (abbreviation: ITSO), indium zinc oxide, indium oxide including tungsten oxide and zinc oxide (abbreviation: IWZO), or the like can be used.

[0142] Further, for example, a conductive oxide including zinc can be used for the conductive layer 519A. Specifically, zinc oxide, zinc oxide to which gallium is added, zinc oxide to which aluminum is added, or the like can be used.

[0143] Structure example 2 of semiconductor device

[0144] The semiconductor device of one embodiment of the present application includes a conductive layer S (see FIG. 1A). FIG. 1C FIG. 2B ).

[0145] Structure example of conductive layer S​

[0146] The conductive layer S is electrically connected to the electrode 112A, and has light-blocking properties. For example, a wiring used to supply a signal to the liquid crystal device 550LC can be used for the conductive layer S. Note that in the case where the conductive layer S and the electrode 112A are formed of the same conductive layer, a portion of the conductive layer overlapping with the opening portion 110_4 of the spacer 110 is used as the electrode 112A and a portion of the conductive layer overlapping with the flat region of the spacer 110 is used as the conductive layer S. In addition, a material that can be used for the conductive layer 519A can be used for the conductive layer S, and in particular, a metal or an alloy can be suitably used.

[0147] The opening portion 518_4 overlaps with the conductive layer S. In other words, the opening portion 518_4 overlaps with the electrode 112B and the conductive layer S.

[0148] Thus, a step formed on the opening portion 518_4 can overlap with the conductive layer S. In addition, a flat region can be formed in a region that does not overlap with the conductive layer S. Furthermore, an electrode of the functional element 550 can be formed in the flat region. Furthermore, a flat region can be formed in the electrode. Furthermore, a layer containing liquid crystal can be formed on the flat region of the electrode, for example. Furthermore, the conductive layer S can be arranged between the layer containing liquid crystal and the backlight, for example. Furthermore, in order to prevent light of the backlight from reaching a region of alignment disorder formed in the layer containing liquid crystal due to the step on the opening portion 518_4, the conductive layer S can be used to block light. In addition, the aperture ratio of the liquid crystal device can be increased. In addition, the luminance of the display device can be increased. In addition, power consumption can be reduced. As a result, a novel semiconductor device with high convenience, utility, or reliability can be provided.

[0149] <Structure Example 3 of Semiconductor Device>

[0150] The semiconductor device of one embodiment of the present application includes a conductive layer 519B (see FIG. 5A and FIG. 5B ). Note that the semiconductor device described with reference to FIG. 5A and FIG. 5B is different from the semiconductor device described with reference to FIG. 1A and FIG. 1B in that the former includes the conductive layer 519B and in that the functional layer 510 includes the layer 517.

[0151] <<Structure Example 2 of Functional Layer 510>

[0152] The functional layer 510 includes the layer 517. The layer 517 is interposed between the layer 518 and the spacer 110 (see FIG. 5A , FIG. 5B and FIG. 6B ).

[0153] [Structure Example 1 of Layer 517]

[0154] Layer 517 includes an opening portion 517_4, and has insulating properties (see FIG. 6B For example, a material that can be used for layer 518 can be used for layer 517.

[0155] [Structure Example 1 of Conductive Layer 519B]

[0156] Conductive layer 519B is interposed between layer 518 and layer 517. For example, a material that can be used for conductive layer 519A can be used for conductive layer 519B.

[0157] Conductive layer 519B overlaps with opening portion 518_4 and opening portion 517_4. Conductive layer 519B electrically connects conductive layer 519A and electrode 112B.

[0158] For example, a conductive film is formed on layer 517 in which opening portion 517_4 is formed at a position overlapping with electrode 112B, whereby the conductive film can be electrically connected to electrode 112B in opening portion 517_4. Further, the conductive film can be processed into a prescribed shape to form conductive layer 519B.

[0159] For example, by forming layer 518 in which opening portion 518_4 is formed at a position overlapping with conductive layer 519B, and forming a conductive film on layer 518, the conductive film can be electrically connected to electrode 112B in opening portion 518_4. Further, the conductive film can be processed into a prescribed shape to form conductive layer 519A and electrode 551LC.

[0160] Further, conductive layer 519B has light-transmitting properties, and electrode 112B also has light-transmitting properties. Thus, for example, the aperture ratio of the liquid crystal device can be improved.

[0161] [Structure Example 4 of Semiconductor Device]

[0162] The semiconductor device of one embodiment of the present application includes conductive layer 519C (see FIG. 7 Further, the semiconductor device described with reference to FIG. 7 differs from the semiconductor device described with reference to FIG. 5C , FIG. 6A and FIG. 6B in that, in the former, functional layer 510 includes layer 517 and layer 553LC containing liquid crystal is interposed between electrode 551LC and electrode 552LC.

[0163] [Structure Example 3 of Functional Layer 510]

[0164] The functional layer 510 includes the conductive layer 519C, and includes the layer 518 between the conductive layer 519C and the conductive layer 519B. Thus, a capacitor can be formed using the conductive layer 519C, the conductive layer 519B, and the layer 518. For example, a power supply potential or a ground potential can be supplied to the conductive layer 519C.

[0165] [Structure Example 1 of Conductive Layer 519C]

[0166] The conductive layer 519C has a light-transmitting property. For example, a material that can be used for the conductive layer 519A can be used for the conductive layer 519C.

[0167] [Structure Example 5 of Semiconductor Device]

[0168] The semiconductor device of one embodiment of the present application includes the conductive layer 519C (see FIG. 8 ). Note that the semiconductor device described with reference to FIG. 8 is different from the semiconductor device described with reference to FIG. 7 in that the layer 517 includes the layer 517A and the layer 517B and the conductive layer 519C is interposed between the layer 517A and the layer 517B.

[0169] [Structure Example 4 of Functional Layer 510]

[0170] The functional layer 510 includes the conductive layer 519C (see FIG. 8 ).

[0171] [Structure Example 2 of Layer 517]

[0172] The layer 517 includes the layer 517A and the layer 517B. The layer 517B is interposed between the layer 518 and the layer 517A. For example, a material that can be used for the layer 518 can be used for the layer 517A and the layer 517B.

[0173] [Structure Example 2 of Conductive Layer 519C]

[0174] The conductive layer 519C is interposed between the layer 517B and the layer 517A. In addition, the conductive layer 519C has a light-transmitting property. Thus, a capacitor can be formed using the conductive layer 519C, the conductive layer 519B, and the layer 517B. For example, a power supply potential or a ground potential can be supplied to the conductive layer 519C.

[0175] Thus, a capacitor can be formed using the conductive layer 519C, the conductive layer 519B, and the layer 518. Furthermore, the potential of the conductive layer 519B can be held at a predetermined potential when the transistor 100 is in an off state. Furthermore, the potential of an electrode of the functional element 550 can be held at a predetermined potential. Furthermore, for example, an electric field of a predetermined strength can be continuously applied to a layer including liquid crystal. As a result, a novel semiconductor device which is excellent in convenience, utility, or reliability can be provided.

[0176] <Structure example 6 of semiconductor device>

[0177] The semiconductor device of one embodiment of the present application includes a conductive layer 519B (see FIG. 9A and FIG. 9B ). Note that the semiconductor device described with reference to FIG. 9A and FIG. 9B is different from the semiconductor device described with reference to FIG. 5A and FIG. 5B in that the opening 518_4 overlaps with the opening 110_4 of the spacer 110 in the former.

[0178] <<Structure example 5 of functional layer 510>

[0179] The functional layer 510 includes a layer 517. The layer 517 is interposed between the layer 518 and the spacer 110 (see FIG. 9A , FIG. 9B and FIG. 10B ).

[0180] [Structure example 3 of layer 517]

[0181] The layer 517 includes an opening 517_4, and the layer 517 has an insulating property (see FIG. 10B ). For example, a material that can be used for the layer 518 can be used for the layer 517.

[0182] <<Structure example 2 of conductive layer 519B>

[0183] The conductive layer 519B is interposed between the layer 518 and the layer 517. For example, a material that can be used for the conductive layer 519A can be used for the conductive layer 519B.

[0184] The conductive layer 519B overlaps with the opening 518_4 and the opening 517_4. The conductive layer 519B electrically connects the conductive layer 519A and the electrode 112B.

[0185] For example, a conductive film is formed over the layer 517 including the opening 517_4 formed at a position overlapping with the electrode 112B, whereby the conductive film can be electrically connected to the electrode 112B in the opening 517_4. Further, the conductive film can be processed into a prescribed shape to form the conductive layer 519B.

[0186] For example, by forming the layer 518 including the opening 518_4 formed at a position overlapping with the conductive layer 519B over the conductive layer 519B and forming a conductive film over the layer 518, the conductive film can be electrically connected to the electrode 112B in the opening 518_4. Further, the conductive film can be processed into a prescribed shape to form the conductive layer 519A and the electrode 551LC.

[0187] Further, the conductive layer 519B has a light-transmitting property.

[0188] Further, the electrode 112A has a light-blocking property, and the opening portion 518_4 overlaps with the electrode 112A.

[0189] <Structure Example 7 of Semiconductor Device>

[0190] The semiconductor device of one embodiment of the present application includes a conductive layer 519C (see FIG. 11 ). Further, the semiconductor device described with reference to FIG. 11 is different from the semiconductor device described with reference to FIG. 9C , FIG. 10A and FIG. 10B in that the functional layer 510 includes the layer 517 and the layer 553LC including liquid crystal is interposed between the electrode 551LC and the electrode 552LC in the former.

[0191] <<Structure Example 6 of Functional Layer 510>>

[0192] The functional layer 510 includes the conductive layer 519C which is interposed between the conductive layer 519B and the layer 518 (see FIG. 11 ). Thus, a capacitor can be formed using the conductive layer 519C, the conductive layer 519B, and the layer 518. For example, a power supply potential or a ground potential can be supplied to the conductive layer 519C.

[0193] [Structure Example 3 of Conductive Layer 519C]

[0194] The conductive layer 519C has a light-transmitting property. For example, a material that can be used for the conductive layer 519A can be used for the conductive layer 519C.

[0195] <Structure Example 8 of Semiconductor Device>

[0196] The semiconductor device of one embodiment of the present application includes a conductive layer 519C (see FIG. 12 ). Further, the semiconductor device described with reference to FIG. 12 is different from the semiconductor device described with reference to FIG. 11 in that the layer 517 includes the layer 517A and the layer 517B and the conductive layer 519C is interposed between the layer 517A and the layer 517B in the former.

[0197] <<Structure Example 7 of Functional Layer 510>>

[0198] The functional layer 510 includes the conductive layer 519C (see FIG. 12 ).

[0199] [Structure Example 4 of Layer 517]

[0200] The layer 517 includes a layer 517A and a layer 517B. The layer 517B is interposed between the layer 518 and the layer 517A. For example, a material that can be used for the layer 518 can be used for the layer 517A and the layer 517B.

[0201] [Structure Example 4 of Conductive Layer 519C]

[0202] The conductive layer 519C is interposed between the layer 517B and the layer 517A. Further, the conductive layer 519C has a light-transmitting property. Thus, a capacitor can be formed using the conductive layer 519C, the conductive layer 519B, and the layer 517B. For example, a power supply potential or a ground potential can be supplied to the conductive layer 519C.

[0203] Thus, a step formed on the opening portion 518_4 can overlap with the electrode 112A of the transistor 100. In addition, a flat region can be formed in a region which does not overlap with the electrode 112A. Further, an electrode of the functional element 550 can be formed in the flat region. Further, a flat region can be formed in the electrode. Further, a layer including liquid crystal can be formed on the flat region of the electrode, for example. For example, the electrode 112A can be arranged between the layer including liquid crystal and the backlight. In addition, in order to prevent light of the backlight from reaching a region of alignment disorder formed in the layer including liquid crystal due to the step on the opening portion 518_4, the electrode 112A can be used to block light. In addition, the aperture ratio of the liquid crystal device can be increased. In addition, the luminance of the display device can be increased. In addition, power consumption can be reduced. As a result, a novel semiconductor device with high convenience, utility, or reliability can be provided.

[0204] [Structure Example 9 of Semiconductor Device]

[0205] The semiconductor device of one embodiment of the present application includes the conductive layer 519B and the conductive layer G (see FIG. 13A FIG. 13B FIG. 14B The semiconductor device described with reference to FIG. 13A and FIG. 13B is different from the semiconductor device described with reference to FIG. 9A and FIG. 9B in that the functional layer 510 includes the conductive layer G and the opening portion 518_4 overlaps with the conductive layer G in the former.

[0206] [Structure Example 8 of Functional Layer 510]

[0207] The functional layer 510 includes the layer 517. The layer 517 is interposed between the layer 518 and the spacer 110 (see FIG. 13A FIG. 13B FIG. 14B ).

[0208] [Structure Example 5 of Layer 517]​​​​

[0209] The layer 517 includes an opening portion 517_4 and has an insulating property. For example, a material that can be used for the layer 518 can be used for the layer 517.

[0210] Structure Example 3 of Conductive Layer 519B

[0211] The conductive layer 519B is interposed between the layer 518 and the layer 517. For example, a material that can be used for the conductive layer 519A can be used for the conductive layer 519B.

[0212] The conductive layer 519B overlaps the opening portion 518_4 and the opening portion 517_4. The conductive layer 519B electrically connects the conductive layer 519A and the electrode 112B.

[0213] For example, a conductive film is formed over the layer 517 including the opening portion 517_4 overlapping the electrode 112B, whereby the conductive film can be electrically connected to the electrode 112B in the opening portion 517_4. Further, the conductive film can be processed into a predetermined shape to form the conductive layer 519B.

[0214] Further, for example, by forming the layer 518 including the opening portion 518_4 overlapping the position where the conductive layer 519B is formed over the layer 518 and forming a conductive film over the layer 518, the conductive film can be electrically connected to the electrode 112B in the opening portion 518_4. Further, the conductive film can be processed into a predetermined shape to form the conductive layer 519A and the electrode 551LC.

[0215] Further, the conductive layer 519B has a light-transmitting property.

[0216] Structure Example of Conductive Layer G

[0217] The conductive layer G is electrically connected to the electrode 104 and has a light-blocking property. For example, a wiring for supplying a control signal to the transistor 100 can be used for the conductive layer G.

[0218] The conductive layer G overlaps the opening portion 518_4. In other words, the opening portion 518_4 overlaps the conductive layer 519B and the conductive layer G.

[0219] Structure Example 10 of Semiconductor Device

[0220] The semiconductor device of one embodiment of the present application includes a conductive layer 519C (see FIG. 5B). FIG. 15 Further, the semiconductor device described with reference to FIG. 15 is different from the semiconductor device described with reference to FIG. 13C , FIG. 14A and FIG. 14BThe semiconductor device described in the description differs from the semiconductor device described in the description in that: in the former, the functional layer 510 includes the layer 517 and the layer 553 LC containing liquid crystal is interposed between the electrode 551 LC and the electrode 552 LC.

[0221] <<Structure Example 9 of Functional Layer 510>>

[0222] The functional layer 510 includes the conductive layer 519C interposed between the conductive layer 519B and the layer 518 (see FIG. 15 ). Thus, a capacitor can be formed using the conductive layer 519C, the conductive layer 519B, and the layer 518. For example, a power supply potential or a ground potential can be supplied to the conductive layer 519C.

[0223] [Structure Example 5 of Conductive Layer 519C]

[0224] The conductive layer 519C has a light-transmitting property. For example, a material that can be used for the conductive layer 519A can be used for the conductive layer 519C.

[0225] <Structure Example 11 of Semiconductor Device>

[0226] The semiconductor device of one embodiment of the present application includes the conductive layer 519C (see FIG. 16 ). The semiconductor device described in the description differs from the semiconductor device described in the description in that: in the former, the layer 517 includes the layer 517A and the layer 517B and the conductive layer 519C is interposed between the layer 517A and the layer 517B. FIG. 16 FIG. 15 <Structure Example 10 of Functional Layer 510>

[0227] <<Structure Example 10 of Functional Layer 510>>

[0228] The functional layer 510 includes the conductive layer 519C (see FIG. 16 ).

[0229] [Structure Example 6 of Layer 517]

[0230] The layer 517 includes the layer 517A and the layer 517B. The layer 517B is interposed between the layer 518 and the layer 517A. For example, a material that can be used for the layer 518 can be used for the layer 517A and the layer 517B.

[0231] [Structure Example 6 of Conductive Layer 519C]

[0232] The conductive layer 519C is interposed between the layer 517B and the layer 517A. Further, the conductive layer 519C has a light-transmitting property. Thus, a capacitor can be formed using the conductive layer 519C, the conductive layer 519B, and the layer 517B. For example, a power supply potential or a ground potential can be supplied to the conductive layer 519C.

[0233] ​Thus, a step formed on the opening portion 518_4 can be overlapped with the conductive layer G. Further, a flat region can be formed in a region not overlapped with the conductive layer G. Further, an electrode of the functional element 550 can be formed in the flat region. Further, a flat region can be formed in the electrode. Further, a layer containing liquid crystal, for example, can be formed on the flat region of the electrode. For example, the conductive layer G can be arranged between the layer containing liquid crystal and the backlight. In addition, in order to prevent light of the backlight from reaching a region of alignment disorder formed in the layer containing liquid crystal due to the step on the opening portion 518_4, the conductive layer G can be used to shield light. In addition, the aperture ratio of the liquid crystal device can be improved. In addition, the luminance of the display device can be improved. In addition, power consumption can be reduced. As a result, a novel semiconductor device excellent in convenience, utility, or reliability can be provided.

[0234] Note that the present embodiment can be combined as appropriate with other embodiments shown in the present specification.

[0235] (Embodiment 2)

[0236] In this embodiment, a structure example of a display device of one embodiment of the present application is described.

[0237] The display device of the present embodiment can be a high-resolution display device or a large display device. Thus, for example, the display device of the present embodiment can be used as a display portion of an electronic device such as a television device, a desktop or a notebook personal computer, a display for a computer or the like, a digital sign, a large game machine such as a pachinko machine, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, or a sound reproduction device, which has a larger screen.

[0238] In addition, the display device of the present embodiment can be a high-definition display device. Thus, for example, the display device of the present embodiment can be used as a display portion of an information terminal device (wearable device) such as a watch-type and a bracelet-type, and a display portion of a wearable device such as a head-mounted display (HMD) and a pair of glasses-type AR device, which can be mounted on the head.

[0239] The semiconductor device of one embodiment of the present application can be used for a display device or a module including the display device. As the module including the display device, a module in which a flexible printed circuit (FPC) or a tape carrier package (TCP) or the like is connected to the display device, a module in which an integrated circuit (IC) is mounted by a chip on glass (COG) method or a chip on film (COF) method, or the like can be given.

[0240] FIG. 17 A perspective view of the display device 5050A is shown.

[0241] Display device 5050A has a structure that bonds substrate 5152 and substrate 5151. FIG. 17 In the image, substrate 5152 is represented by a dashed line.

[0242] The display device 5050A includes a display section 5162, a connection section 5140, a circuit section 5164, wiring 5165, etc. FIG. 17 An example is shown where display device 5050A is equipped with IC5173 and FPC5172. Therefore, it is also possible to... FIG. 17 The structure shown is called a display module including display device 5050A, IC and FPC.

[0243] The connecting portion 5140 is provided on the outer side of the display portion 5162. The connecting portion 5140 may be provided along one or more sides of the display portion 5162. There may also be one or more connecting portions 5140. FIG. 17 An example is shown where the connection portions 5140 are arranged around the four sides of the display section. In the connection portions 5140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode. When the common electrode is disposed on one side of the substrate 5151, the connection portions 5140 may be omitted if not needed.

[0244] The circuit section 5164 may include, for example, a scan line driving circuit (also known as a gate driver). Alternatively, the circuit section 5164 may include both a scan line driving circuit and a signal line driving circuit (also known as a source driver).

[0245] Wiring 5165 has the function of supplying signals and power to display unit 5162 and circuit unit 5164. The signals and power are input to wiring 5165 from the outside via FPC 5172 or from IC 5173.

[0246] FIG. 17 An example is shown where IC 5173 is mounted on substrate 5151 using a COG or COF method. IC 5173 can be, for example, an IC that includes one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 5050A and the display module can also be configured without an IC. Alternatively, the IC can be mounted on an FPC using a COF method or the like.

[0247] The vertical transistor of one embodiment of the present application can be used in one or both of the display portion 5162 and the circuit portion 5164 of the display device 5050A, for example. The vertical transistor of one embodiment of the present application can also be used for the IC 5173.

[0248] For example, when the vertical transistor of one embodiment of the present application is used for a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be achieved. Further, for example, when the vertical transistor of one embodiment of the present application is used for a driver circuit (e.g., one or both of a gate line driver circuit and a source line driver circuit) of a display device, the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be achieved. Furthermore, the vertical transistor of one embodiment of the present application has favorable electrical characteristics, and by using the vertical transistor for a display device, the reliability of the display device can be improved.

[0249] The display portion 5162 is an image display region in the display device 5050A and includes a plurality of pixels 5210 arranged periodically. FIG. 17 An enlarged view of one pixel 5210 is shown.

[0250] There is no particular limitation on the arrangement of pixels in the display device of this embodiment, and various methods can be employed. As the arrangement of pixels, for example, a stripe arrangement, an S stripe arrangement, a matrix arrangement, a Delta arrangement, a Bayer arrangement, and a Pentile arrangement can be given.

[0251] FIG. 17 The pixel 5210 shown includes a sub-pixel 5210R which emits red light, a sub-pixel 5210G which emits green light, and a sub-pixel 5210B which emits blue light. Each of the sub-pixel 5210R, the sub-pixel 5210G, and the sub-pixel 5210B includes a display element and a circuit which controls driving of the display element.

[0252] As the display element, a liquid crystal element can be used, for example. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, or a semi-transmissive liquid crystal element can be given, for example.

[0253] Note that a variety of elements (e.g., a light-emitting element) other than a liquid crystal element can be used as the display element. As the light-emitting element, a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a semiconductor laser, or the like can be given, for example. As the LED, a small-size LED, a micro LED, or the like can be used, for example.

[0254] In addition to the above, a MEMS (Micro Electro Mechanical Systems) element of a shutter mode or an optical interference mode, or a display element using a microcapsule method, an electrophoretic method, an electro-wetting method or the like, or the like can be used. In addition, a light source and a QLED (Quantum-dot LED) using a color conversion technology of a quantum dot material can be used.

[0255] [Structure Example 1 of Display Device]

[0256] FIG. 18 One example of a cross section of a portion of a region including the FPC 5172, a portion of the circuit portion 5164, a portion of the display portion 5162, a portion of the connection portion 5140, and a portion of a region including an end portion of the display device 5050A is shown.

[0257] FIG. 18 The display device shown includes a liquid crystal device operating in a VA mode.

[0258] The substrate 5151 is attached to the substrate 5152 with an adhesive layer. A liquid crystal is sealed in a region surrounded by the substrate 5151, the substrate 5152, and the adhesive layer. In addition, a polarizing plate POL2 is provided on a side of the substrate 5152. A polarizing plate POL1 is provided on a side of the substrate 5151.

[0259] Although not shown, a backlight can be provided on the outside of the polarizing plate POL2 or the outside of the polarizing plate POL1.

[0260] The transistor included in the circuit portion 5164 and the transistor included in the display portion 5162 can have the same structure or different structures. In addition, as the plurality of transistors included in the circuit portion 5164, transistors having the same structure can be used, or transistors having different structures can be used in combination.

[0261] The conductive particles CP are electrically connected to a conductive layer provided on the side of the substrate 5151 in the connection portion 5140. Thus, a potential or a signal can be supplied from an FPC or an IC provided on the side of the substrate 5151.

[0262] As the conductive particles CP, particles on the surface of which an organic resin or silica or the like is covered with a metal material can be used. As the metal material, nickel or gold is preferably used because it can reduce contact resistance. In addition, particles on which two or more metal materials are covered in layers such as gold on nickel are preferably used. In addition, the conductive particles CP preferably use a material that generates elastic deformation or plastic deformation. At this time, the conductive particles CP sometimes have a shape in which they are flattened in the longitudinal direction. By having this shape, the contact area of the conductive particles CP with the conductive layer electrically connected to the conductive particles CP can be increased, and thus contact resistance can be reduced and problems such as connection failure can be suppressed from occurring.

[0263] [Structure Example 2 of Display Device]

[0264] FIG. 19 The display device illustrated includes a liquid crystal device that operates in an FFS mode. The pixel electrode has a comb-tooth shape or a shape provided with a slit when viewed from a planar surface. In addition, the common electrode is disposed so as to overlap the pixel electrode.

[0265] FIG. 20 is an example in which the upper and lower relationship of the pixel electrode and the common electrode is reversed. The common electrode has a comb-tooth shape or a shape provided with a slit when viewed from a planar surface and is disposed on the pixel electrode with the insulating layer interposed therebetween.

[0266] [Structure Example 3 of Display Device]

[0267] FIG. 21 The display device illustrated includes a liquid crystal device that operates in an IPS mode.

[0268] The pixel electrode and the common electrode are both disposed on the same insulating layer. The pixel electrode and the common electrode both have a comb-tooth shape when viewed from a planar surface and are disposed so as to engage with each other. The pixel electrode and the common electrode are preferably formed by processing the same conductive film.

[0269] At least a part of the present embodiment can be implemented in appropriate combination with other embodiments described in the present specification.

[0270] (Embodiment 3)

[0271] In the present embodiment, the structure of a transistor of a semiconductor device which can be used in one embodiment of the present application will be described with reference to FIGS. 22 to 25.

[0272] FIG. 22A is a plan view of the transistor 10. FIG. 22B is a cross-sectional view of a portion along the dot-dash line A1-A2 of FIG. 22A FIG. 22C is a perspective view of the transistor 10 with a part of the transistor 10 removed. FIG. 22D is an equivalent circuit diagram of the transistor 10. ​

[0273] FIG. 23A and FIG. 23B yes FIG. 22B An enlarged view of transistor 10 is shown. Additionally, FIG. 23C This is a diagram showing the opening at 159° when viewed from the Z direction.

[0274] FIG. 24A and FIG. 24B This is a plan view of transistor 10.

[0275] FIG. 25A This is a cross-sectional view of transistor 10. FIG. 25B yes FIG. 25A The equivalent circuit diagram of transistor 10 is shown.

[0276] <Example of transistor structure>

[0277] An example of the structure of a transistor in a semiconductor device that can be used in one aspect of the present invention will be described. Note that, for ease of understanding the structure of transistor 10, [further details are provided]. FIG. 22A and FIG. 22C A portion of the description of the constituent elements of transistor 10 is omitted. For example, in FIG. 22A and FIG. 22C omitted in FIG. 22B The description of insulating layer 164, etc., is shown.

[0278] In transistor 10, an insulating layer 154 is included on substrate 153, and a conductive layer 155 is included on insulating layer 154. Furthermore, an insulating layer 156 is included on conductive layer 155, an insulating layer 157 is included on insulating layer 156, and an insulating layer 158 is included on insulating layer 157. Additionally, a conductive layer 160 is included on insulating layer 158.

[0279] In the region overlapping a portion of the conductive layer 155, openings 159 are provided in the conductive layer 160, insulating layer 158, insulating layer 157, and insulating layer 156 (see reference). FIG. 22B and FIG. 23A Furthermore, a semiconductor layer 161 is included in the opening 159. The semiconductor layer 161 has a region overlapping the bottom of the opening 159 and a region overlapping the sides of the opening 159. The semiconductor layer 161 has regions contacting the sides of the insulating layer 158, the insulating layer 157, and the insulating layer 156. Additionally, a portion of the semiconductor layer 161 is electrically connected to the conductive layer 160, and another portion of the semiconductor layer 161 is electrically connected to the conductive layer 155.

[0280] Further, the transistor 10 includes an insulating layer 162 over the insulating layer 158, the conductive layer 160, and the semiconductor layer 161, and includes a conductive layer 163 over the insulating layer 162. Further, an insulating layer 164 is included over the insulating layer 162 and the conductive layer 163. The insulating layer 162 has a region overlapping with a side surface of the opening 159 with the semiconductor layer 161 interposed therebetween. The conductive layer 163 is provided so as to cover the semiconductor layer 161. Thus, the conductive layer 163 has a region extending beyond an end portion of the semiconductor layer 161. Further, the conductive layer 163 has a region overlapping with a side surface of the opening 159 with the insulating layer 162 and the semiconductor layer 161 interposed therebetween.

[0281] The conductive layer 155 has a region serving as one of a source electrode and a drain electrode of the transistor 10. Further, the conductive layer 160 has a region serving as the other of the source electrode and the drain electrode of the transistor 10. For example, when the conductive layer 155 is used as the drain electrode of the transistor 10, the conductive layer 160 is used as the source electrode of the transistor 10.

[0282] The semiconductor layer 161 has a region serving as a channel-forming semiconductor layer of the transistor 10, the insulating layer 162 has a region serving as a gate insulating layer, and the conductive layer 163 has a region serving as a gate electrode. Thus, the transistor 10 is provided in a region including the opening 159.

[0283] The source electrode and the drain electrode of the transistor 10 are arranged in the Z direction. Thus, the source and the drain of the transistor 10 are arranged at different positions in the Z direction, respectively. For example, with the top surface of the substrate 153 as a reference, the source and the drain of the transistor 10 are arranged so as to have different distances from the reference top surface of the substrate 153. Such a transistor is sometimes referred to as a "vertical channel transistor", a "vertical type channel transistor", a "vertical transistor", or a "VFET (Vertical Field Effect Transistor)". In the vertical channel transistor, a direction in which a drain current Id flows includes a component in the Z direction (vertical direction). For example, in the transistor 10 which is a vertical channel transistor, when a cross section passing through the center (or the barycenter) of the opening 159 seen in the Z direction is seen in the X direction or the Y direction, an angle θ (see FIG. 1B) formed by a formed surface of the semiconductor layer 161 over the conductive layer 155 and a direction in which the drain current Id flows is 5 degrees or more and 110 degrees or less, 10 degrees or more and 90 degrees or less, 30 degrees or more and 90 degrees or less, or 60 degrees or more and 90 degrees or less. FIG. 23A

[0284] ​In addition, as described above, the semiconductor layer 161 has a region in contact with the side surface of the insulating layer 157. Thus, the drain current Id flows along the side surface of the insulating layer 157. By this, the angle θ formed by the formed surface of the semiconductor layer 161 on the conductive layer 155 and the direction in which the drain current Id flows can be replaced with the angle θ formed by the formed surface of the semiconductor layer 161 on the conductive layer 155 and the side surface of the insulating layer 157.

[0285] The longitudinal channel transistor can reduce the occupied area of the transistor because the source electrode and the drain electrode are arranged in the Z direction. The occupied area of the semiconductor device can be significantly reduced by using the longitudinal channel transistor as the semiconductor device.

[0286] Here, one example of a material that can be used for the transistor 10 or the semiconductor device according to one embodiment of the present application will be described.

[0287] [Conductive layer]

[0288] As the conductive material that can be used for the gate electrode, the source electrode, and the drain electrode of the transistor 10, various wirings and electrodes included in the semiconductor device, and the like, a metal element selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), and the like, an alloy including the above metal elements, an alloy in which the above metal elements are combined, and the like can be used. In addition, a semiconductor typified by polysilicon including an impurity element such as phosphorus, a silicide such as nickel silicide, and the like can be used. There is no particular limitation on a method for forming the conductive material, and various formation methods such as an evaporation method, an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, a sputtering method, a spin coating method, and the like can be used.

[0289] In addition, as the conductive material, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be used. A layer formed using the Cu-X alloy can be processed with a wet etching process, so that manufacturing cost can be reduced. In addition, as the conductive material, an aluminum alloy including one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can be used.

[0290] As the conductive material that can be used for the conductive layer, a conductive material containing oxygen such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, and the like can also be used. Further, a conductive material containing nitrogen such as titanium nitride, tantalum nitride, tungsten nitride, and the like can also be used. In addition, the conductive layer can also adopt a stacked structure of a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above metal elements in combination.

[0291] For example, the conductive layer can adopt a single-layer structure of an aluminum layer containing silicon, a two-layer structure of a titanium layer stacked on an aluminum layer, a two-layer structure of a titanium layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a tantalum nitride layer, and a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer stacked in this order.

[0292] In addition, a plurality of conductive layers formed of the above conductive materials can also be stacked. For example, the conductive layer can also adopt a stacked structure of a material containing the above metal elements and a conductive material containing oxygen in combination. In addition, a stacked structure of a material containing the above metal elements and a conductive material containing nitrogen in combination can also be adopted. In addition, a stacked structure of a material containing the above metal elements, a conductive material containing oxygen, and a conductive material containing nitrogen in combination can also be adopted.

[0293] For example, the conductive layer can also adopt a three-layer structure of a conductive layer containing at least one of indium and zinc and oxygen, a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen stacked in this order. At this time, it is preferable that the side surface of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. In addition, for example, a plurality of conductive layers containing at least one of indium and zinc and oxygen can also be stacked as the conductive layer.

[0294] [Insulating layer]

[0295] As each insulating layer, a single layer or a stack selected from the following insulating materials can be adopted: aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminosilicate, and the like. In addition, a plurality of kinds of oxide materials, nitride materials, oxynitride materials, and nitroxide materials can also be used.

[0296] There is no particular limitation on the formation method of the insulating material, and various formation methods such as an evaporation method, an ALD method, a CVD method, a sputtering method, a spin coating method, and the like can be used.

[0297] In this specification and the like, an oxynitride refers to a material containing nitrogen at a higher content than oxygen. In addition, an oxynitride refers to a material containing oxygen at a higher content than nitrogen. Note that the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS) or secondary ion mass spectrometry (SIMS).

[0298] For example, the insulating layer 154 and the insulating layer 164 are preferably formed using an insulating material which is less likely to transmit impurities. For example, a single layer or a stack of insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. As an example of an insulating material which is less likely to transmit impurities, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon nitride, or the like can be given.

[0299] By using an insulating material which is less likely to transmit impurities as the insulating layer 154, diffusion of impurities from the substrate 153 side can be suppressed, and the reliability of the transistor 10 can be improved. That is, the reliability of a semiconductor device including the transistor 10 can be improved. By using an insulating material which is less likely to transmit impurities as the insulating layer 164, diffusion of impurities from above the insulating layer 164 can be suppressed, and the reliability of the transistor 10 can be improved. That is, the reliability of a semiconductor device including the transistor 10 can be improved.

[0300] In addition, an insulating layer which can be used as a planarization layer can be used as the insulating layer. As a material of an insulating layer which can be used as a planarization layer, an acrylic resin, a polyimide, an epoxy resin, a polyamide, a polyimide amide, a siloxane resin, a benzocyclobutene resin, a phenol resin, a precursor thereof, and the like can be given. In addition to the above-described organic materials, a low-k material, a siloxane resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like can be used. In addition, a plurality of insulating layers formed of these materials can be stacked.

[0301] In addition, a siloxane resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane-based material as a starting material. A siloxane resin can have an organic group (e.g., an alkyl group or an aryl group) or a fluorine group as a substituent. Note that the organic group can include a fluorine group.

[0302] In addition, the surface of the insulating layer or the like can be subjected to CMP treatment. By performing CMP treatment, the unevenness of the surface of the insulating layer or the like can be reduced, and thus the coverage of the insulating layer and the conductive layer formed later can be improved.

[0303] [Semiconductor Layer]

[0304] As the semiconductor layer 161, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor, or the like can be used alone or in combination. As a semiconductor material, a semiconductor material having a band gap (a semiconductor material other than a zero band gap semiconductor), such as silicon, germanium, or the like can be used, for example. For example, a single-element semiconductor, a compound semiconductor, or a layered substance (also referred to as an atomic layered substance, a two-dimensional material, or the like), or the like is preferably used as a semiconductor material. As a compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials can also contain impurities as dopants.

[0305] For example, as the semiconductor layer 161, a single crystal silicon, a polycrystalline silicon, a microcrystalline silicon, or an amorphous silicon can be used. As the polycrystalline silicon, a low-temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be used, for example.

[0306] A transistor in which an amorphous silicon is used for the semiconductor layer 161 can be formed over a large-sized glass substrate and can be manufactured at low cost. A transistor in which a polycrystalline silicon is used for the semiconductor layer 161 has high field-effect mobility and can operate at high speed. Further, a transistor in which a microcrystalline silicon is used for the semiconductor layer 161 has high field-effect mobility and can operate at high speed as compared with a transistor in which an amorphous silicon is used.

[0307] As a compound semiconductor that can be used for a semiconductor material, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, boron arsenide, and the like can be given. The boron nitride used for a semiconductor layer preferably has an amorphous structure. The boron arsenide used for a semiconductor layer preferably includes a crystal having a cubic crystal structure.

[0308] The semiconductor layer 161 can also include a layered substance used as a semiconductor. The layered substance is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by a bond such as a van der Waals force, which is weaker than a covalent bond and an ionic bond. The layered substance has high conductivity in a unit layer, i.e., has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity for a channel formation region, a transistor with high on-state current can be provided.

[0309] As a layered substance, for example, graphene, silicene, boron nitride, a chalcogenide, and the like can be given. In boron nitride as a layered substance, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. A chalcogenide is a compound containing an oxygen group element. Further, an oxygen group element is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and astatine. Further, as a chalcogenide, a transition metal chalcogenide, a Group 13 chalcogenide, and the like can be given. As a transition metal chalcogenide which can be used for a semiconductor layer of a transistor, specifically, molybdenum sulfide (typically, MoS2), molybdenum selenide (typically, MoSe2), molybdenum telluride (typically, MoTe2), tungsten sulfide (typically, WS2), tungsten selenide (typically, WSe2), tungsten telluride (typically, WTe2), hafnium sulfide (typically, HfS2), hafnium selenide (typically, HfSe2), zirconium sulfide (typically, ZrS2), zirconium selenide (typically, ZrSe2), and the like can be given. By using the above-described transition metal chalcogenide for a semiconductor layer, a storage device with a large on-state current can be provided.

[0310] The oxide semiconductor has a band gap of 2 eV or more, and thus a transistor using an oxide semiconductor, which is one of metal oxides, as a semiconductor layer in which a channel is formed (also referred to as an "OS transistor") has extremely small off-state current. Thus, power consumption of a semiconductor device including an OS transistor can be reduced. Furthermore, an OS transistor is stable in a high-temperature environment and has little variation in characteristics. For example, even in a high-temperature environment, the off-state current is hardly increased. Specifically, even in an environment at a temperature higher than or equal to room temperature and lower than or equal to 200 °C, the off-state current is hardly increased. Furthermore, even in a high-temperature environment, the on-state current is not easily decreased. Thus, a semiconductor device including an OS transistor is stable in a high-temperature environment and has high reliability.

[0311] In this embodiment and the like, an OS transistor is preferably used as the transistor 10. Since an OS transistor has high withstand voltage between a source and a drain, the channel length can be shortened. Thus, the on-state current can be increased. An OS transistor is suitable for a vertical channel transistor.

[0312] The channel length L can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and smaller than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L can be set to be 100 nm or more and 1 μm or less.

[0313] As the metal oxide that can be used as the semiconductor layer of the OS transistor, for example, an indium oxide, a gallium oxide, and a zinc oxide can be given. The metal oxide preferably contains at least indium (In) or zinc (Zn). Further, the metal oxide preferably contains two or three of indium, an element M, and zinc. Note that the element M is a metal element or a semi-metal element having a high bonding energy with oxygen, for example, a metal element or a semi-metal element having a higher bonding energy with oxygen than indium.

[0314] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or a plurality of the above elements, more preferably one or a plurality of elements selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. Note that in this specification and the like, a metal element and a semi-metal element are collectively referred to as a "metal element", and the "metal element" described in this specification and the like includes a semi-metal element in some cases.

[0315] For example, an indium zinc oxide (In-Zn oxide), an indium tin oxide (In-Sn oxide), an indium titanium oxide (In-Ti oxide), an indium gallium oxide (In-Ga oxide), an indium gallium aluminum oxide (In-Ga-Al oxide), an indium gallium tin oxide (In-Ga-Sn oxide), a gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), an aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), an indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), an indium tin zinc oxide (In-Sn-Zn oxide), an indium titanium zinc oxide (In-Ti-Zn oxide), an indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), an indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), an indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), or the like can be used. Alternatively, an indium tin oxide including silicon, a gallium tin oxide (Ga-Sn oxide), an aluminum tin oxide (Al-Sn oxide), or the like can be used.

[0316] By increasing the proportion of the number of atoms of indium to the sum of the numbers of atoms of all metal elements included in the metal oxide, the field-effect mobility of the transistor can be increased.

[0317] One or more of metal elements having a large number of periods can be contained instead of indium or in addition to indium. The larger the overlap of the orbits of the metal elements, the greater the tendency of the carrier conduction in the metal oxide. Therefore, the field-effect mobility of the transistor can be increased in some cases when a metal element having a large number of periods is contained. As the metal element having a large number of periods, a metal element belonging to the 5th period and a metal element belonging to the 6th period, and the like can be given. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, and the like can be given. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0318] In addition, the metal oxide can contain one or more of non-metal elements. The field-effect mobility of the transistor can be increased in some cases when the metal oxide contains a non-metal element. As the non-metal element, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, hydrogen, and the like can be given, for example.

[0319] By increasing the proportion of the number of atoms of zinc to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, a metal oxide with high crystallinity is obtained, whereby diffusion of impurities in the metal oxide can be suppressed. Thus, variation in electrical characteristics of the transistor is suppressed, and reliability can be improved.

[0320] By increasing the proportion of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, formation of oxygen vacancies in the metal oxide can be suppressed. Thus, generation of carriers due to oxygen vacancies is suppressed, whereby a transistor with a small off-state current can be achieved. Furthermore, variation in electrical characteristics of the transistor is suppressed, and reliability can be improved.

[0321] The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer. Thus, by changing the composition of the metal oxide depending on the electrical characteristics and reliability required for the transistor, a semiconductor device with excellent electrical characteristics and high reliability can be achieved.

[0322] In the case where an In-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide whose proportion of the number of atoms of indium is higher than that of zinc is preferably used. For example, a metal oxide whose proportion of the number of atoms of metal elements is In:Zn = 1 : 1, In:Zn = 2 : 1, In:Zn = 3 : 1, In:Zn = 4 : 1, In:Zn = 5 : 1, In:Zn = 7 : 1, In:Zn = 10 : 1, or the like can be used.

[0323] In the case where an In-Sn oxide is used for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of tin is preferably used. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn = 1 : 1, In:Sn = 2: 1, In:Sn = 3: 1, In:Sn = 4: 1, In:Sn = 5: 1, In:Sn = 7: 1, In:Sn = 10: 1, or the like can be used.

[0324] In the case where an In-Sn-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of tin can be used. Further, a metal oxide in which the atomic ratio of zinc is higher than that of tin is preferably used. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn:Zn = 2: 1:3, In:Sn:Zn = 3: 1:2, In:Sn:Zn = 4:2:3, In:Sn:Zn = 4:2:4.1, In:Sn:Zn = 5: 1:3, In:Sn:Zn = 5: 1:6, In:Sn:Zn = 5: 1:7, In:Sn:Zn = 5: 1:8, In:Sn:Zn = 6: 1:6, In:Sn:Zn = 10: 1:3, In:Sn:Zn = 10: 1:6, In:Sn:Zn = 10: 1:7, In:Sn:Zn = 10: 1:8, In:Sn:Zn = 5:2:5, In:Sn:Zn = 10: 1:10, In:Sn:Zn = 20: 1:10, In:Sn:Zn = 40: 1:10, or the like can be used.

[0325] In the case where an In-Al-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of aluminum can be used. Further, a metal oxide in which the atomic ratio of zinc is higher than that of aluminum is preferably used. For example, a metal oxide in which the atomic ratio of metal elements is In:Al:Zn = 2: 1:3, In:Al:Zn = 3: 1:2, In:Al:Zn = 4:2:3, In:Al:Zn = 4:2:4.1, In:Al:Zn = 5: 1:3, In:Al:Zn = 5: 1:6, In:Al:Zn = 5: 1:7, In:Al:Zn = 5: 1:8, In:Al:Zn = 6: 1:6, In:Al:Zn = 10: 1:3, In:Al:Zn = 10: 1:6, In:Al:Zn = 10: 1:7, In:Al:Zn = 10: 1:8, In:Al:Zn = 5:2:5, In:Al:Zn = 10: 1:10, In:Al:Zn = 20: 1:10, In:Al:Zn = 40: 1:10, or the like can be used.

[0326] When an In-Ga-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium to the atomic ratio of gallium is higher than that of metal elements can be used. Further, a metal oxide in which the atomic ratio of zinc to the atomic ratio of gallium is higher than that of metal elements is further preferable. For example, a metal oxide in which the atomic ratio of metal elements is In:Ga:Zn = 2:1:3, In:Ga:Zn = 3:1:2, In:Ga:Zn = 4:2:3, In:Ga:Zn = 4:2:4.1, In:Ga:Zn = 5:1:3, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:7, In:Ga:Zn = 5:1:8, In:Ga:Zn = 6:1:6, In:Ga:Zn = 10:1:3, In:Ga:Zn = 10:1:6, In:Ga:Zn = 10:1:7, In:Ga:Zn = 10:1:8, In:Ga:Zn = 5:2:5, In:Ga:Zn = 10:1:10, In:Ga:Zn = 20:1:10, In:Ga:Zn = 40:1:10, or the like can be used.

[0327] When an In-M-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium to the atomic ratio of element M is higher than that of metal elements can be used. Further, a metal oxide in which the atomic ratio of zinc to the atomic ratio of element M is higher than that of metal elements is further preferable. For example, a metal oxide in which the atomic ratio of metal elements is In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, or the like can be used.

[0328] Note that in the case where a plurality of metal elements are included as element M, the total of the atomic ratios of the metal elements can be the atomic ratio of element M. For example, in the case of using an In-Ga-Al-Zn oxide including gallium and aluminum as element M, the total of the atomic ratio of gallium and the atomic ratio of aluminum can be the atomic ratio of element M. Further, the atomic ratios of indium, element M, and zinc are preferably in the above ranges.

[0329] It is preferable to use a metal oxide in which the proportion of the number of atoms of indium to the sum of the number of atoms of metal elements among the primary component elements contained in the metal oxide is higher than or equal to 30 at.% and lower than or equal to 100 at.%, preferably higher than or equal to 30 at.% and lower than or equal to 95 at.%, more preferably higher than or equal to 35 at.% and lower than or equal to 95 at.%, more preferably higher than or equal to 35 at.% and lower than or equal to 90 at.%, more preferably higher than or equal to 40 at.% and lower than or equal to 90 at.%, more preferably higher than or equal to 45 at.% and lower than or equal to 90 at.%, more preferably higher than or equal to 50 at.% and lower than or equal to 80 at.%, more preferably higher than or equal to 60 at.% and lower than or equal to 80 at.%, more preferably higher than or equal to 70 at.% and lower than or equal to 80 at.%. For example, in the case where an In-M-Zn oxide is used as a semiconductor layer, the proportion of the number of atoms of indium to the total of the number of atoms of indium, element M, and zinc is preferably within the above range.

[0330] As described above, when the proportion of the number of atoms of indium to the sum of the number of atoms of metal elements among the primary component elements contained in the metal oxide is increased, the field-effect mobility of the transistor can be increased. With the use of the transistor, a circuit which can operate at high speed can be manufactured. Furthermore, the area occupied by the circuit can be reduced. For example, even when the transistor is used for a large display device or a high-definition display device, the signal delay of each wiring can be reduced even when the number of wirings is increased, and thus display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be reduced.

[0331] The analysis of the composition of the metal oxide can be performed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a plurality of the above methods can be combined and used for the analysis. Note that the actual content of an element with a low content ratio is sometimes different from the content ratio obtained by analysis due to the analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0332] Metal oxides are preferably formed using sputtering or ALD methods. Note that when forming metal oxides using sputtering, the atomic ratio of the target material may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes lower than the atomic ratio of zinc in the target material. Specifically, this zinc atomic ratio is sometimes about 40% to 90% of the zinc atomic ratio in the target material.

[0333] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability under forward bias can be realized. In other words, a transistor with small variations in threshold voltage during PBTS testing can be achieved. Furthermore, when using a gallium-containing metal oxide, the gallium content is preferably lower than the indium content. This results in a transistor with high reliability.

[0334] One reason for the variation in threshold voltage during PBTS testing can be the presence of defect states at or near the interface between the semiconductor layer and the gate insulating layer. A higher defect state density results in more significant degradation during PBTS testing. The formation of these defect states can be suppressed by reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0335] The rationale for suppressing threshold voltage variations in PBTS testing by using metal oxides with little or no gallium content in the semiconductor layer can be considered, for example, as follows: Gallium contained in metal oxides is more likely to draw oxygen than other metals (such as indium or zinc). Therefore, it can be inferred that carrier (electron) trap sites are easily created at the interface between the gallium-containing metal oxide and the gate insulating layer, where gallium bonds with excess oxygen in the gate insulating layer. Consequently, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing a change in the threshold voltage.

[0336] More specifically, when using In-Ga-Zn oxide as the semiconductor layer, a metal oxide with an indium atomic ratio higher than that of gallium can be used. More preferably, a metal oxide with a zinc atomic ratio greater than that of gallium is used. In other words, a metal oxide with a metal element atomic ratio satisfying In>Ga and Zn>Ga is used as the semiconductor layer.

[0337] For example, the semiconductor layer of the OS transistor can use a metal oxide in which the atomic ratio of the metal elements is In:Ga:Zn = 2:1:3, In:Ga:Zn = 3:1:2, In:Ga:Zn = 4:2:3, In:Ga:Zn = 4:2:4.1, In:Ga:Zn = 5:1:3, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:7, In:Ga:Zn = 5:1:8, In:Ga:Zn = 6:1:6, In:Ga:Zn = 10:1:3, In:Ga:Zn = 10:1:6, In:Ga:Zn = 10:1:7, In:Ga:Zn = 10:1:8, In:Ga:Zn = 5:2:5, In:Ga:Zn = 10:1:10, In:Ga:Zn = 20:1:10, In:Ga:Zn = 40:1:10, or the like.

[0338] The semiconductor layer of the OS transistor preferably uses a metal oxide in which the atomic percentage of gallium with respect to the atomic number of the metal elements contained is higher than 0 atomic % and lower than or equal to 50 atomic %, preferably higher than or equal to 0.1 atomic % and lower than or equal to 40 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 35 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 30 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 25 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 20 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 15 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 10 atomic %. By reducing the atomic percentage of gallium with respect to the atomic number of the metal elements in the semiconductor layer, a transistor with high resistance to PBTS testing can be achieved. Note that by containing gallium in the metal oxide, an effect of not easily generating oxygen vacancies (V O : Oxygen Vacancy) in the metal oxide is obtained.

[0339] A metal oxide not containing gallium can also be used as the semiconductor layer of the OS transistor. For example, an In-Zn oxide can be used for the semiconductor layer. In this case, when the atomic percentage of indium with respect to the atomic number of the metal elements contained in the metal oxide is increased, the field-effect mobility of the transistor can be increased. On the other hand, when the atomic percentage of zinc with respect to the atomic number of the metal elements contained in the metal oxide is increased, the metal oxide has high crystallinity, so that variation in electrical characteristics of the transistor is suppressed and reliability can be increased. Furthermore, a metal oxide not containing gallium and zinc such as indium oxide can also be used as the semiconductor layer. By using a metal oxide not containing gallium, particularly, variation in threshold voltage in PBTS testing can be extremely small.

[0340] For example, an oxide containing indium and zinc can be used as the semiconductor layer. In that case, a metal oxide in which the atomic ratio of the metal elements is, for example, In:Zn = 2:3, In:Zn = 4:1, or the like can be used.

[0341] Note that the above description is given based on the case where gallium is used, but the above description can be applied to the case where element M is used instead of gallium. As the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of element M is preferably used. Further, a metal oxide in which the atomic ratio of zinc is higher than that of element M is preferably used.

[0342] By using a metal oxide in which the content of element M is low as the semiconductor layer, a transistor with high reliability to a positive voltage application can be realized. By using such a transistor as a transistor which needs to have high reliability to a positive voltage application, a semiconductor device with high reliability can be realized.

[0343] Next, the reliability of a transistor to light is described.

[0344] The electrical characteristics of a transistor sometimes fluctuate due to light incident on the transistor. It is particularly preferable that a transistor used for a region where light is likely to be incident have small fluctuation in electrical characteristics under light irradiation and have high reliability to light. The reliability to light can be evaluated by, for example, the amount of fluctuation in threshold voltage in an NBTI S test.

[0345] By increasing the content of element M of a metal oxide used for a semiconductor layer, a transistor with high reliability to light can be realized. That is, a transistor with small amount of fluctuation in threshold voltage in an NBTI S test can be realized. Specifically, a metal oxide in which the atomic ratio of element M is higher than or equal to that of indium has a larger band gap, and thus the amount of fluctuation in threshold voltage in an NBTI S test of a transistor can be reduced. The band gap of a metal oxide included in a semiconductor layer is preferably higher than or equal to 2.0 eV, further preferably higher than or equal to 2.5 eV, still further preferably higher than or equal to 3.0 eV, yet further preferably higher than or equal to 3.2 eV, yet further preferably higher than or equal to 3.3 eV, yet further preferably higher than or equal to 3.4 eV, and yet further preferably higher than or equal to 3.5 eV.

[0346] For example, a metal oxide in which the atomic ratio of the metal elements is In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or the like can be used as the semiconductor layer.

[0347] The semiconductor layer particularly preferably uses a metal oxide in which the proportion of the number of atoms of element M to the number of atoms of the metal elements contained is greater than or equal to 20 at.% and less than or equal to 70 at.%, preferably greater than or equal to 30 at.% and less than or equal to 70 at.%, more preferably greater than or equal to 30 at.% and less than or equal to 60 at.%, more preferably greater than or equal to 40 at.% and less than or equal to 60 at.%, more preferably greater than or equal to 50 at.% and less than or equal to 60 at.%.

[0348] When an In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the proportion of the number of atoms of indium to the number of atoms of gallium is lower than or equal to 1 can be used. For example, a metal oxide in which the proportion of the number of atoms of metal elements is In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:1.2, In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:3, In:Ga:Zn = 1:3:4, or the like can be used.

[0349] The semiconductor layer particularly preferably uses a metal oxide in which the proportion of the number of atoms of gallium to the number of atoms of the metal elements contained is greater than or equal to 20 at.% and less than or equal to 60 at.%, preferably greater than or equal to 20 at.% and less than or equal to 50 at.%, more preferably greater than or equal to 30 at.% and less than or equal to 50 at.%, more preferably greater than or equal to 40 at.% and less than or equal to 60 at.%, more preferably greater than or equal to 50 at.% and less than or equal to 60 at.%.

[0350] By using a metal oxide with a high content of element M for the semiconductor layer, a transistor with high reliability with respect to light can be realized. By using such a transistor as a transistor that needs to have high reliability with respect to light, a semiconductor device with high reliability can be realized.

[0351] The semiconductor layer can also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer can be the same or substantially the same as each other. By employing a stacked structure of metal oxide layers with the same composition, the same sputtering target can be used, for example, so that manufacturing costs can be reduced.

[0352] The compositions of the two or more metal oxide layers included in the semiconductor layer can be different from each other. For example, a two-layer stacked structure of a first metal oxide layer with a composition of In:M:Zn = 1:3:4 [atomic ratio] or the like and a second metal oxide layer with a composition of In:M:Zn = 1:1:1 [atomic ratio] or the like overlapping the first metal oxide layer can be used. Further, gallium or aluminum is particularly preferably used as element M. For example, a stacked structure selected from any one of an indium oxide, an indium gallium oxide, and IGZO and any one of IAZO, IAGZO, and ITZO (registered trademark), and the like can be used.

[0353] For example, a first metal oxide layer of a composition of In:M:Zn = 1:1:1 [atomic ratio] or its neighborhood and a second metal oxide layer of a composition of In:Zn = 4:1 [atomic ratio] or its neighborhood provided over the first metal oxide layer can be used.

[0354] For example, a three-layer stacked structure in which a semiconductor layer of a metal element atomic ratio of In:Ga:Zn = 1:1:1 is used as a first layer, a semiconductor layer of a metal element atomic ratio of In:Zn = 4:1 is used as a second layer, and a semiconductor layer of a metal element atomic ratio of In:Ga:Zn = 1:1:1 is used as a third layer can be used. The band gap of the semiconductor layer of the first layer and the third layer is preferably larger than that of the semiconductor layer of the second layer. With this structure, the second layer can be used as a main current path, and thus a so-called buried channel structure can be achieved.

[0355] A metal oxide layer having crystallinity is preferably used as the semiconductor layer. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a poly-crystal structure, an nc (nano-crystal) structure, or the like can be used. By using a metal oxide layer having crystallinity for the semiconductor layer, the density of defect states in the semiconductor layer can be reduced, and thus a display device with high reliability can be achieved. Note that the CAAC structure refers to a crystal structure in which a plurality of microcrystals (typically, a plurality of IGZO microcrystals) have c-axis alignment and the plurality of microcrystals are connected without being aligned in the a-b plane. The CAAC structure has fewer grain boundaries and crystal grains in the a-b plane than the poly-crystal structure, and thus a display device with high reliability can be achieved.

[0356] The higher the crystallinity of the metal oxide layer used for the semiconductor layer, the lower the density of defect states in the semiconductor layer can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of flowing a large current can be achieved.

[0357] In the case where a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (temperature of a stage) at the time of formation, the higher the crystallinity of the metal oxide layer can be. Further, the higher the flow rate ratio of an oxygen gas (hereinafter also referred to as an oxygen flow rate) to the entire deposition gas used at the time of formation, the higher the crystallinity of the metal oxide layer can be.

[0358] The semiconductor layer of the OS transistor can also have a stacked-layer structure of two or more metal oxide layers having different crystallinity. For example, the semiconductor layer can have a stacked-layer structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer, and the second metal oxide layer can include a region whose crystallinity is higher than that of the first metal oxide layer. Alternatively, the second metal oxide layer can include a region whose crystallinity is lower than that of the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer can also have the same or approximately the same composition. By using a stacked-layer structure of metal oxide layers having the same composition, the same sputtering target can be used, for example, so that the manufacturing cost can be reduced. For example, a stacked-layer structure of two or more metal oxide layers having different crystallinity can be formed by using the same sputtering target while changing the flow rate of oxygen. Note that the two or more metal oxide layers included in the semiconductor layer can also have different compositions.

[0359] The transistor 10 described in this embodiment can have a channel length L determined by the thickness of the insulating layer provided between the conductive layer 160 and the conductive layer 155. Thus, a transistor with a short channel length L can be manufactured with high precision. Further, the variation in characteristics among a plurality of transistors 10 can be reduced. Thus, the operation of a semiconductor device including the transistor 10 is stable, and the reliability can be improved. Further, when the variation in characteristics is reduced, the degree of freedom in circuit design of a semiconductor device is increased, and thus the operating voltage can be reduced. Thus, the power consumption of a semiconductor device can be reduced.

[0360] When the semiconductor layer 161 includes an oxide semiconductor, the insulating layer 156 and the insulating layer 158 are preferably formed using a material containing hydrogen. The oxide semiconductor in a region where the insulating layer is in contact with the oxide semiconductor is n-type by the contact with the insulating layer containing hydrogen, and thus can be used as a source region or a drain region. As the insulating layer, a material containing silicon, nitrogen, and hydrogen can be used, for example. Specifically, silicon nitride containing hydrogen, silicon oxynitride containing hydrogen, or the like can be used.

[0361] When the semiconductor layer 161 includes an oxide semiconductor, the conductive layer 155 in contact with the semiconductor layer 161 and the conductive layer 160 in contact with the semiconductor layer 161 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen can be used. For example, a conductive material containing titanium or tantalum and nitrogen can be used. Alternatively, another conductive material can be provided so as to overlap with the conductive material containing nitrogen.

[0362] On the other hand, the insulating layer 157 is preferably formed using a material in which hydrogen is reduced and oxygen is contained. For example, a material containing silicon and oxygen can be used. Specifically, silicon oxide, silicon oxynitride, or the like can be used. Since hydrogen is an impurity element in an oxide semiconductor, when the semiconductor layer 161 functioning as an oxide semiconductor is in contact with the insulating layer 157 in which hydrogen is reduced, the semiconductor layer 161 is not easily n-type. When the semiconductor layer 161 functioning as an oxide semiconductor is in contact with the insulating layer 157 containing oxygen, oxygen vacancies in the semiconductor layer 161 are reduced, the characteristics of the transistor 10 are stable, and thus the reliability is improved.

[0363] When the semiconductor layer 161 includes an oxide semiconductor, the insulating layer 157 preferably contains excess oxygen. In this specification and the like, "excess oxygen" refers to oxygen which is released by heating. Further, when the insulating layer 157 includes a material containing excess oxygen, the insulating layer 156 and the insulating layer 158 are preferably formed using a material which is less likely to transmit oxygen. As the material which is less likely to transmit oxygen, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used. By using a material which is less likely to transmit oxygen for the insulating layer 156 and the insulating layer 158, excess oxygen contained in the insulating layer 157 is less likely to be released to the lower layer or the upper layer. Thus, the oxide semiconductor can be sufficiently supplied with oxygen. For example, an insulating layer containing silicon and oxygen (the insulating layer 157) can be included between two insulating layers containing silicon and nitrogen (the insulating layer 156 and the insulating layer 158).

[0364] When the semiconductor layer 161 includes an oxide semiconductor and the insulating layer 156 and the insulating layer 158 include a material containing hydrogen, a region of the semiconductor layer 161 in contact with the conductive layer 160 and a region of the semiconductor layer 161 in contact with the insulating layer 158 are used as one of a source (a source region) and a drain (a drain region). Further, a region of the semiconductor layer 161 in contact with the conductive layer 155 and a region of the semiconductor layer 161 in contact with the insulating layer 156 are used as the other of the source (the source region) and the drain (the drain region). Thus, the channel length L of the transistor 10 is determined depending on the thickness t of the insulating layer 157 (see FIG. 1B). FIG. 23A ).

[0365] The insulating layer 156 and the insulating layer 158 can also be formed using a material containing no hydrogen or little hydrogen. For example, a silicon nitride containing little hydrogen or a silicon oxynitride containing little hydrogen can be used. In this case, the region of the semiconductor layer 161 in contact with the insulating layer 156 and the region of the semiconductor layer 161 in contact with the insulating layer 158 are not n-type. Thus, the region of the semiconductor layer 161 in contact with the conductive layer 160 is used as one of the source (source region) and the drain (drain region). Further, the region of the semiconductor layer 161 in contact with the conductive layer 155 is used as the other of the source (source region) and the drain (drain region). In this case, the thickness ts of the sum of the thicknesses of the insulating layer 156, the insulating layer 157, and the insulating layer 158 corresponds to the channel length L of the transistor 10 (see FIG. 1B). FIG. 23A

[0366] The channel length L can be controlled by adjusting the thicknesses of the insulating layer 156, the insulating layer 157, and the insulating layer 158. The channel length L can be, for example, greater than or equal to 5 nm, greater than or equal to 7 nm, or greater than or equal to 10 nm and less than 3 μm, less than or equal to 2.5 μm, less than or equal to 2 μm, less than or equal to 1.5 μm, less than or equal to 1.2 μm, less than or equal to 1 μm, less than or equal to 500 nm, less than or equal to 300 nm, less than or equal to 200 nm, less than or equal to 100 nm, less than or equal to 50 nm, less than or equal to 30 nm, or less than or equal to 20 nm. For example, the channel length L can be set to be greater than or equal to 100 nm and less than or equal to 1 μm.

[0367] In this embodiment, three insulating layers (the insulating layer 156, the insulating layer 157, and the insulating layer 158) are included between the conductive layer 155 and the conductive layer 160, but the number of layers of the insulating layer between the conductive layer 155 and the conductive layer 160 is not limited thereto. The insulating layer between the conductive layer 155 and the conductive layer 160 can be one layer or two layers. Further, it can be four or more layers.

[0368] The circumference p of the opening 159 is the channel width W of the transistor 10 (see FIG. 1B) by the provision of the semiconductor layer 161 in the opening 159. FIG. 23C The circumference p can be calculated, for example, from the position of half (t / 2) of the thickness t of the insulating layer 157 or the position of half (ts / 2) of the thickness ts. Note that the circumference at an arbitrary position of the opening 159 can be set to the channel width W as needed. For example, the circumference p of the lowermost portion of the opening 159 can be set to the channel width W or the circumference p of the uppermost portion of the opening 159 can be set to the channel width W.

[0369] In FIG. 23C , the outline (planar shape) of the opening 159 viewed in the Z direction is illustrated as a circle, but is not limited thereto. For example, the outline of the opening 159 viewed in the Z direction can be an ellipse (see FIG. 23D ). Further, it can be a rectangle (see FIG. 23E ). Note that,​FIG. 23E A rectangle in which the corner is bent is shown. Further, for example, the outline of the opening 159 viewed from the Z direction can also be a shape including one or both of a straight portion and a curved portion (see FIG. 1B). FIG. 23F ).

[0370] In the transistor 10 according to one embodiment of the present application, the capacitance value of the parasitic capacitance generated between the gate and the source is different from the capacitance value of the parasitic capacitance generated between the gate and the drain. Specifically, of the capacitor Cl formed in the region in which the conductive layer 160 and the conductive layer 163 overlap over the insulating layer 154 and the capacitor C2 formed in the region in which the conductive layer 155 and the conductive layer 163 overlap in the opening 159, the capacitance value of the capacitor Cl is larger than the capacitance value of the capacitor C2 (see FIGS. 1B and 1C). FIG. 22D and FIG. 23B ).

[0371] In the transistor 10 according to one embodiment of the present application viewed from the Z direction, the conductive layer 163 overlaps with the conductive layer 160 in a manner that surrounds the opening 159 at the peripheral portion of the opening 159 and overlaps with the conductive layer 155 at the bottom portion of the opening 159 (see FIGS. 1B and 1C). FIG. 24A and FIG. 24B ).

[0372] In FIG. 24A , the region used as the capacitor Cl viewed from the Z direction is hatched. The region in which the conductive layer 160 and the conductive layer 163 overlap with each other with the semiconductor layer 161 and the insulating layer 162 interposed therebetween over the insulating layer 154 is used as the capacitor Cl (see FIGS. 1B and 1C). FIG. 23B and FIG. 24A ). Note that the insulating layer 154 and the insulating layer 162 are omitted in FIG. 24A .

[0373] In FIG. 24B , the region used as the capacitor C2 viewed from the Z direction is hatched. The region in which the conductive layer 155 and the conductive layer 163 overlap with each other with the semiconductor layer 161 and the insulating layer 162 interposed therebetween at the bottom portion of the opening 159 is used as the capacitor C2 (see FIGS. 1B and 1C). FIG. 23B and FIG. 24B ). Note that the insulating layer 154 and the insulating layer 162 are omitted in FIG. 24B .

[0374] It is known from FIG. 24A and FIG. 24B that the area of the region used as the capacitor C2 is larger than the area of the region used as the capacitor Cl. When the area of the region used as the capacitor C2 is larger than the area of the region used as the capacitor Cl, the capacitance value of the capacitor Cl is larger than that of the capacitor C2.

[0375] When the overlapping area of the conductive layer 155 and the conductive layer 163 is changed to change the capacitance value of the capacitor C2, the shape of the opening 159 is changed, and thus the perimeter p of the opening 159 is changed. Since the change in the perimeter p directly affects the electrical characteristics of the transistor 10, it is difficult to adjust the capacitance value of the capacitor C2.

[0376] On the other hand, the adjustment of the overlapping area of the conductive layer 163 and the conductive layer 160 is easy, and it is also difficult to affect the electrical characteristics of the transistor 10. For example, by increasing the overlapping area of the conductive layer 163 and the conductive layer 160, the capacitance value of the capacitor Cl can be increased.

[0377] As FIG. 25A As shown in a cross-sectional view of FIG. 17, a conductive layer 166 which is close to the semiconductor layer 161 can be provided in the insulating layer 157. Further, the conductive layer 166 is provided so as not to be in contact with the semiconductor layer 161. Further, the conductive layer 166 is preferably provided so as to surround the semiconductor layer 161. By providing the conductive layer 166 so as to be close to the semiconductor layer 161 without being in contact with the semiconductor layer 161, the conductive layer 166 can be used as a back gate electrode of the transistor 10. Thus, the transistor 10 shown in FIG. 17 is used as a transistor including a back gate (back gate electrode). Further, the transistor 10 shown in FIG. 17 is used as a transistor including a back gate (back gate electrode) and a gate electrode. FIG. 25A As shown in a cross-sectional view of FIG. 17, a conductive layer 166 which is close to the semiconductor layer 161 can be provided in the insulating layer 157. Further, the conductive layer 166 is provided so as not to be in contact with the semiconductor layer 161. Further, the conductive layer 166 is preferably provided so as to surround the semiconductor layer 161. By providing the conductive layer 166 so as to be close to the semiconductor layer 161 without being in contact with the semiconductor layer 161, the conductive layer 166 can be used as a back gate electrode of the transistor 10. Thus, the transistor 10 shown in FIG. 17 is used as a transistor including a back gate (back gate electrode). Further, the transistor 10 shown in FIG. 17 is used as a transistor including a back gate (back gate electrode) and a gate electrode. FIG. 25B is FIG. 25A is an equivalent circuit diagram of the transistor 10 shown in FIG. 17.

[0378] Here, the back gate electrode is described. Generally, the back gate electrode is formed of a conductive layer and is arranged so that the channel formation region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Thus, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be the same as that of the gate electrode, or can be a GND potential or an arbitrary potential. By electrically connecting the gate electrode and the back gate electrode, the on-state current of the transistor can be increased. Further, by changing the potential of the back gate electrode independently of the gate electrode, the threshold voltage of the transistor can be changed.

[0379] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, the transistor has a function of preventing an electric field generated outside the transistor from affecting the channel formation region of the semiconductor layer (especially, an electric field shielding function against static electricity or the like). As a result, the variation in characteristics of the transistors is reduced. Further, the deterioration of the transistor characteristics caused by GBTS testing is suppressed. For example, by including the back gate electrode, the variation in threshold voltage before and after GBTS testing can be suppressed. In addition, the variation in threshold voltage of the transistor including the back gate electrode before and after GBTS testing is smaller than that of the transistor not including the back gate electrode.

[0380] The GBTS (NBTS and PBTS) test is a kind of accelerated test, which can evaluate the change in characteristics of the transistor (change over time) due to long-term use in a short time. In particular, the amount of change in threshold voltage of the transistor before and after the GBTS test is an important index for checking reliability. It can be said that the less the amount of change in threshold voltage before and after the GBTS test, the higher the reliability of the transistor.

[0381] In addition, when light is incident from the back gate electrode side, by forming the back gate electrode using a conductive film having light shielding properties, it is possible to prevent light from being incident on the semiconductor layer from the back gate electrode side. Similarly, by forming the gate electrode using a conductive film having light shielding properties, it is possible to prevent light from being incident on the semiconductor layer from the gate electrode side. By forming one or both of the gate electrode and the back gate electrode using a conductive film having light shielding properties, it is possible to prevent light degradation of the semiconductor layer and prevent degradation of electrical characteristics such as threshold voltage shift of the transistor.

[0382] Further, the gate electrode and the back gate electrode can shield the electric field generated by the drain electrode from affecting the semiconductor layer. Therefore, it is possible to suppress the variation in the rise voltage of the on-state current due to the variation in the drain voltage. Note that this effect is significant when the gate electrode and the back gate electrode are supplied with potentials.

[0383] By connecting a plurality of transistors 10 in parallel, the channel width W of the transistor 10 in appearance can be increased. By increasing the channel width W, the resistance value between the source and the drain when the transistor 10 is in the on state becomes small, and the drain current Id when the transistor 10 is in the on state can be increased.

[0384] [Substrate]

[0385] There is no particular limitation on the material used for the substrate. Depending on the purpose, the material used for the substrate can be determined in consideration of, for example, the presence or absence of light transmittance and heat resistance that can withstand heat treatment. For example, an insulating substrate such as a glass substrate of barium borosilicate glass or aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a semiconductor substrate, a flexible substrate, a bonding film, a base material film, or the like can be used.

[0386] For example, as the semiconductor substrate, a semiconductor substrate composed of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, or the like can be used. Alternatively, the semiconductor substrate can be a single-crystal semiconductor or a polycrystal semiconductor.

[0387] As a substrate when the transistor 10 and the like according to one embodiment of the present application is used for a display device, for example, a glass substrate having a large area such as the sixth generation (1500 mm x 1850 mm), the seventh generation (1870 mm x 2200 mm), the eighth generation (2200 mm x 2400 mm), the ninth generation (2400 mm x 2800 mm), the tenth generation (2950 mm x 3400 mm), or the like can be used. Thus, a large display device can be manufactured. By making the substrate large, more display devices can be manufactured using one substrate, so that the manufacturing cost can be reduced.

[0388] As a material of a flexible substrate, a bonding film, a base film, and the like, for example, a polyester such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, an acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), a polyamide (nylon, aramid, or the like), polysiloxane, a cyclic olefin resin, polystyrene, a polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), an ABS resin, and a cellulose nanofiber, or the like can be used.

[0389] By using the above material as a substrate, a light-weight semiconductor device including the transistor 10 can be provided. Further, by using the above material as a substrate, a semiconductor device with high impact resistance can be provided. Further, by using the above material as a substrate, a semiconductor device which is less likely to be broken can be provided.

[0390] The lower the linear expansion coefficient of the flexible substrate used as a substrate, the more the deformation due to the environment can be suppressed, and thus is preferable. For example, the flexible substrate used as a substrate can use a material having a linear expansion coefficient of 1 x 10 -3 / K or lower, 5 x 10 -5 / K or lower, or 1 x 10 -5 / K or lower. In particular, the linear expansion coefficient of aramid is low, and thus is suitable for a flexible substrate.

[0391] Note that this embodiment mode can be combined as appropriate with other embodiment modes described in this specification.

[0392] (Embodiment 4)

[0393] In this embodiment, a display device of one embodiment of the present application is described. The semiconductor device of one embodiment of the present application can be used for a display device.

[0394] FIG. 26A The display device illustrated in FIG. 45 includes a pixel portion 4502, a driver circuit portion 4504, a protection circuit 4506, and a terminal portion 4507. Alternatively, a structure in which the protection circuit 4506 is not provided can be employed.

[0395] The pixel portion 4502 includes a plurality of pixel circuits 4501 configured in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each of the pixel circuits 4501 includes a circuit that drives a display element.

[0396] The driver circuit portion 4504 includes a driver circuit such as a gate driver 4504a that outputs a scan signal to the gate lines GL_1 to GL_X, and a source driver 4504b that supplies a data signal to the data lines DL_1 to DL_Y. The gate driver 4504a can have a structure including at least a shift register. Further, the source driver 4504b can be formed of a shift register, a digital-analog conversion circuit, a latch circuit, and the like.

[0397] The terminal portion 4507 refers to a portion provided with a terminal for inputting a power supply, a control signal, an image signal, and the like from an external circuit to the display device.

[0398] The protection circuit 4506 is a circuit that places a wiring to which the protection circuit 4506 is connected in an open state with respect to another wiring when a potential outside a certain range is supplied to the wiring. FIG. 26A The protection circuit 4506 illustrated in the drawing can be connected to various wirings such as the gate lines, the data lines, and the like, for example. Further, in the FIG. 26A In the drawing, the protection circuit 4506 is provided with hatching in order to distinguish the protection circuit 4506 from the pixel circuit 4501.

[0399] Further, the gate driver 4504a and the source driver 4504b and the pixel portion 4502 can be provided over the same substrate, or an IC in which the gate driver circuit or the source driver circuit is separately formed can be mounted on a substrate provided with the pixel portion 4502 by a COG (Chip on glass) method or the like. Alternatively, an FPC (Flexible Printed Circuit) in which an IC is mounted can be attached to a substrate by an ACF (Anisotropic Conductive Film) or the like.

[0400] In particular, it is preferable that the pixel portion 4502 and the gate driver 4504a be manufactured over the same substrate by the same process. At this time, it is preferable that a transistor of one embodiment of the present application be provided in each of the pixel portion 4502 and the gate driver 4504a. Further, when the source driver 4504b uses an IC, it is preferable that a demultiplexer circuit be provided over the substrate, which can reduce the number of terminals of the IC. At this time, it is preferable that a transistor of one embodiment of the present application be used for the demultiplexer circuit.

[0401] FIG. 26B An example of a structure of a pixel circuit that can be used for the pixel circuit 4501 is described.

[0402] FIG. 26B The pixel circuit 4501 illustrated includes a liquid crystal element 4570, a transistor 4550, and a capacitor 4560. Further, the pixel circuit 4501 is connected to a data line DL_n, a gate line GL_m, a potential supply line, and the like.

[0403] As the transistor 4550, a vertical transistor of one embodiment of the present application can be used.

[0404] The potential of one of a pair of electrodes of the liquid crystal element 4570 is set in accordance with the specifications of the pixel circuit 4501. The alignment state of the liquid crystal element 4570 is set in accordance with data written. Further, a common potential can be supplied to one of a pair of electrodes of the liquid crystal element 4570 included in each of a plurality of pixel circuits 4501. Further, different potentials can be supplied to one of a pair of electrodes of the liquid crystal element 4570 in the pixel circuits 4501 of each row.

[0405] In addition, FIG. 26C The pixel circuit 4501 illustrated includes a transistor 4552, a transistor 4554, a capacitor 4562, and a light-emitting element 4572. Further, the pixel circuit 4501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, and a potential supply line VL_b, and the like.

[0406] Further, one of the potential supply line VL_a and the potential supply line VL_b is supplied with a high power supply potential VDD and the other is supplied with a low power supply potential VSS. The current flowing through the light-emitting element 4572 is controlled in accordance with the potential applied to the gate of the transistor 4554, and thus the luminance of light emission from the light-emitting element 4572 is controlled.

[0407] Next, a pixel circuit provided with a memory for correcting the gray scale displayed by a pixel and a display device including the pixel circuit are described.

[0408] FIG. 27A A circuit diagram of the pixel circuit 4400 is shown. The pixel circuit 4400 includes a transistor Ml, a transistor M2, a capacitor Cl, and a circuit 4401. Further, the pixel circuit 4400 is connected to a wiring SI, a wiring S2, a wiring Gl, and a wiring G2.

[0409] As the transistor Ml and the transistor M2, a vertical transistor of one embodiment of the present application can be used.

[0410] The gate of transistor M1 is connected to wiring G1, one of its source and drain is connected to wiring S1, and the other of its source and drain is connected to one electrode of capacitor C1. The gate of transistor M2 is connected to wiring G2, one of its source and drain is connected to wiring S2, and the other of its source and drain is connected to the other electrode of capacitor C1 and circuit 4401.

[0411] Circuit 4401 includes at least one display element. Here, the display element includes a liquid crystal device. However, it is not limited to this, and the display element can be a variety of components, typically including light-emitting elements such as organic EL elements, LED elements, or MEMS (Micro Electro Mechanical Systems) elements.

[0412] The node connecting transistor M1 and capacitor C1 is denoted as node N1, and the node connecting transistor M2 and circuit 4401 is denoted as node N2.

[0413] The pixel circuit 4400 can maintain the potential of node N1 by turning transistor M1 off. Furthermore, it can maintain the potential of node N2 by turning transistor M2 off. Moreover, by writing a predetermined potential to node N1 through transistor M1 while transistor M2 is off, the potential of node N2 can change in response to changes in the potential of node N1 due to capacitive coupling through capacitor C1.

[0414] Here, one or both of transistors M1 and M2 can be an oxide semiconductor transistor as illustrated in Embodiment 3. Because this transistor has extremely low off-state current, the potential of node N1 or node N2 can be maintained for a long time. Furthermore, when the potential maintenance period of each node is short (specifically, when the frame rate is 30Hz or higher, etc.), a transistor using a semiconductor such as silicon can also be used.

[0415] [Example of driver method]

[0416] Next, refer to FIG. 27B An example illustrating the operation of the pixel circuit 4400 is provided. FIG. 27B This is a timing diagram of the operation of the pixel circuit 4400. Note that, for ease of explanation, the effects of various resistors such as wiring resistors, parasitic capacitances, and transistor threshold voltages are not considered here.

[0417] exist FIG. 27B In the work shown, a frame period is divided into period T1 and period T2. Period T1 is the period for writing potential to node N2, and period T2 is the period for writing potential to node N1.

[0418] [Period T1]

[0419] During the period T1, both the wiring Gl and the wiring G2 are supplied with a potential that makes the transistor become in an on state. Further, the wiring Sl is supplied with a fixed potential V ref , the wiring S2 is supplied with a first data potential V w .

[0420] The node Nl is supplied with the potential V ref from the wiring Sl through the transistor Ml. Further, the node N2 is supplied with the first data potential V w from the wiring S2 through the transistor M2. Thus, the capacitor Cl becomes in a state of holding a potential difference V w -V ref .

[0421] [Period T2]

[0422] Next, during the period T2, the wiring Gl is supplied with a potential that makes the transistor Ml become in an on state, the wiring G2 is supplied with a potential that makes the transistor M2 become in an off state, and the wiring Sl is supplied with a second data potential V data . Further, the wiring S2 can be supplied with a predetermined constant potential or made to be in a floating state.

[0423] The node Nl is supplied with the second data potential V data from the wiring Sl through the transistor Ml. At this time, due to the capacitive coupling through the capacitor Cl, the potential of the node N2 changes by an amount of a potential dV with respect to the second data potential V data . That is, the circuit 4401 is input with a potential in which the first data potential V w and the potential dV are added together. Note that, although FIG. 27B the potential dV is shown as a positive value, it can also be a negative value. That is, the second data potential V data may also be lower than the potential V ref .

[0424] Here, the potential dV is substantially determined by the capacitance value of the capacitor Cl and the capacitance value of the circuit 4401. When the capacitance value of the capacitor Cl is sufficiently larger than the capacitance value of the circuit 4401, the potential dV becomes a potential close to the second data potential V data .

[0425] As described above, since the pixel circuit 4400 can combine two kinds of data signals to generate a potential supplied to the circuit 4401 including the display element, it is possible to perform gradation correction within the pixel circuit 4400.

[0426] Further, the pixel circuit 4400 can generate a potential exceeding the maximum potential supplyable to the source driver connected to the wiring S1 and the wiring S2. For example, in the case of using a light emitting element, high dynamic range (HDR) display or the like can be performed. Further, in the case of using a liquid crystal device, overdrive or the like can be implemented.

[0427] [Application Example]

[0428] [Example of Using a Liquid Crystal Device]

[0429] FIG. 27C The pixel circuit 4400LC illustrated includes a circuit 4401LC. The circuit 4401LC includes a liquid crystal device LC and a capacitor C2.

[0430] One electrode of the liquid crystal device LC is connected to the node N2 and one electrode of the capacitor C2, and the other electrode is connected to a wiring to which a potential V com2 is supplied. The other electrode of the capacitor C2 is connected to a wiring to which a potential V com1 is supplied.

[0431] The capacitor C2 is used as a storage capacitor. Further, the capacitor C2 can be omitted when not needed.

[0432] Since the pixel circuit 4400LC can supply a high voltage to the liquid crystal device LC, high-speed display can be implemented by overdrive, for example, and a liquid crystal material with a high driving voltage can be used. Further, by supplying a correction signal to the wiring S1 or the wiring S2, gradation correction can be performed in accordance with the use temperature, the deterioration state of the liquid crystal device LC, or the like.

[0433] [Example of Using a Light Emitting Element]

[0434] FIG. 27D The pixel circuit 4400EL illustrated includes a circuit 4401EL. The circuit 4401EL includes a light emitting element EL, a transistor M3, and a capacitor C2.

[0435] The gate of the transistor M3 is connected to the node N2 and one electrode of the capacitor C2, one of the source and the drain is connected to a wiring to which a potential V H is supplied, and the other of the source and the drain is connected to one electrode of the light emitting element EL. The other electrode of the capacitor C2 is connected to a wiring to which a potential V com is supplied. The other electrode of the light emitting element EL is connected to a wiring to which a potential V L is supplied.

[0436] The transistor M3 has a function of controlling a current supplied to the light emitting element EL. The capacitor C2 is used as a storage capacitor. The capacitor C2 can be omitted when not needed.

[0437] Further, although a structure in which the anode side of the light emitting element EL is connected to the transistor M3 is shown here, a structure in which the cathode side is connected to the transistor M3 can also be employed. At this time, the potential V H may be changed as appropriate. L

[0438] The pixel circuit 4400EL can cause a large current to flow through the light emitting element EL by applying a high potential to the gate of the transistor M3, and thus, for example, HDR display or the like can be implemented. Further, by supplying a correction signal to the wiring S1 or the wiring S2, the electrical characteristics of the transistor M3, the light emitting element EL, and the like can be corrected.

[0439] Further, the circuit shown in FIGS. 17A and 17B is not limiting, and a structure in which a transistor, a capacitor, or the like is additionally added can also be employed. FIG. 27C FIG. 27D

[0440] At least a part of this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0441] (Embodiment 5)

[0442] In this embodiment mode, a structure example of a touch panel module including a touch panel and an IC is described.

[0443] FIG. 28 A block diagram of a touch panel module 6500 is shown. The touch panel module 6500 includes a touch panel 6510 and an IC 6520.

[0444] The touch panel 6510 includes a display portion 6511, an input portion 6512, a scan line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504. The display portion 6511 includes a plurality of pixels, a plurality of signal lines, and a plurality of scan lines, and can display an image. The input portion 6512 includes a plurality of sensor elements which sense contact or proximity to the touch panel 6510 by a sensing object, and can be used as a touch sensor. The scan line driver circuit 6513 can output a scan signal to the scan lines in the display portion 6511.

[0445] The sensor driver circuit 6503 can output a signal which drives the sensor elements in the input portion 6512. The sensor driver circuit 6503 can have a structure in which a shift register circuit and a buffer circuit are combined, for example.

[0446] The detection circuit 6504 can amplify and output an output signal from the sensor elements in the input portion 6512 to an AD conversion circuit 6507.

[0447] ​​​Here, although the display portion 6511 and the input portion 6512 are separately shown as the structure of the touch panel 6510 for convenience of explanation, a so-called In-Cell type touch panel that has both a function of displaying an image and a function of a touch sensor can also be employed.

[0448] As a manner of the touch sensor that can be used as the input portion 6512, for example, an electrostatic capacitive type can be used. As the electrostatic capacitive type, there are a surface type electrostatic capacitive type, a projection type electrostatic capacitive type, and the like. As the projection type electrostatic capacitive type, there are a self-capacitance type, a mutual-capacitance type, and the like. The mutual-capacitance type is preferably used, whereby multi-point detection can be performed at the same time.

[0449] Note that, not being limited thereto, various types of sensors that can sense the approach, contact, or press of a sensing object such as a finger or a stylus pen can also be used for the input portion 6512. As a manner of the sensor, in addition to the electrostatic capacitive type, various types such as a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and the like can be used.

[0450] As the In-Cell type touch panel, there are typically a Hybrid-In-Cell type and a Full-In-Cell type. The Hybrid-In-Cell type refers to a structure in which an electrode or the like that constitutes a touch sensor is provided on both a substrate that supports a display element and an opposing substrate or on the opposing substrate. The Full-In-Cell type refers to a structure in which an electrode or the like that constitutes a touch sensor is provided on a substrate that supports a display element. By employing the Full-In-Cell type touch panel, the structure of the opposing substrate can be simplified, and thus the Full-In-Cell type is preferable. In particular, in the Full-In-Cell type, by using an electrode that constitutes a display element as an electrode that constitutes a touch sensor, the manufacturing process can be simplified, and thus the manufacturing cost can be reduced, and thus the Full-In-Cell type is preferable.

[0451] The display portion 6511 preferably has an extremely high resolution of HD (number of pixels: 1280 x 720), FHD (number of pixels: 1920 x 1080), WQHD (number of pixels: 2560 x 1440), WQXGA (number of pixels: 2560 x 1600), 4K (number of pixels: 3840 x 2160), 8K (number of pixels: 7680 x 4320), or the like. In particular, a resolution of 4K, 8K, or higher is preferable. In addition, the pixel density (definition) of the pixels provided in the display portion 6511 is preferably 300 ppi or higher, more preferably 500 ppi or higher, still more preferably 800 ppi or higher, further more preferably 1000 ppi or higher, and yet further more preferably 1200 ppi or higher. Such a display portion 6511 having a high resolution and high definition can further improve the sense of reality, the sense of depth, and the like.

[0452] The IC 6520 includes a circuit unit 6501, a signal line drive circuit 6502, and an AD conversion circuit 6507. The circuit unit 6501 includes a timing controller 6505, an image processing circuit 6506, and the like.

[0453] The signal line drive circuit 6502 is capable of outputting an image signal (also referred to as a video signal) as an analog signal to the signal lines in the display portion 6511. For example, the signal line drive circuit 6502 can include a shift register, a digital-analog conversion circuit (DAC), a latch circuit, a buffer circuit, and the like. In addition, the touch panel 6510 can also include a demultiplexer circuit connected to the signal lines.

[0454] The AD conversion circuit 6507 has a function of converting an analog signal input from the detection circuit 6504 into a digital signal and outputting the same to the circuit unit 6501. For example, the AD conversion circuit 6507 can include an analog-digital conversion circuit (ADC) and an amplification circuit.

[0455] The image processing circuit 6506 in the circuit unit 6501 has a function of generating and outputting a signal for driving the display portion 6511 of the touch panel 6510, generating and outputting a signal for driving the input portion 6512, and analyzing a signal output from the input portion 6512 and outputting the same to the CPU 6540.

[0456] More specifically, the image processing circuit 6506 is capable of generating an image signal, for example, in accordance with an instruction of the CPU 6540. In addition, the image processing circuit 6506 is capable of performing signal processing on the image signal in accordance with the specifications of the display portion 6511 to convert the same into an analog image signal, and supplying the same to the signal line drive circuit 6502. In addition, the image processing circuit 6506 is capable of generating a drive signal output to the sensor drive circuit 6503 in accordance with an instruction of the CPU 6540. The image processing circuit 6506 is also capable of analyzing a signal input from the detection circuit 6504 via the AD conversion circuit 6507, and outputting the same as position information to the CPU 6540.

[0457] The timing controller 6505 can generate and output a signal (a clock signal, a start pulse signal, and the like) to the scan line drive circuit 6513 and the sensor drive circuit 6503 in accordance with a synchronization signal in the image signal and the like processed by the image processing circuit 6506. The timing controller 6505 can also have a function of generating and outputting a signal that defines the timing of the output signal of the detection circuit 6504. Here, the timing controller 6505 preferably outputs signals that are synchronized with the signals output to the scan line drive circuit 6513 and the signals output to the sensor drive circuit 6503, respectively. In particular, it is preferable to separate the period in which data rewriting the pixels of the display portion 6511 is performed and the period in which sensing is performed in the input portion 6512. For example, the touch panel 6510 can be driven in a manner in which one frame period is divided into a period in which data rewriting the pixels is performed and a sensing period. In addition, for example, by providing two or more sensing periods in one frame period, the detection sensitivity and the detection accuracy can be improved.

[0458] The image processing circuit 6506 can include, for example, a processor. For example, a microprocessor such as a DSP (Digital Signal Processor), a GPU (Graphics Processing Unit), or the like can be used. The microprocessor can also be constituted by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array). The image processing circuit 6506 performs various data processing, program control, and the like by interpreting and executing instructions from various programs by the processor. The program that can be executed by the processor can be stored in a memory region in the processor or in a storage device provided separately.

[0459] Further, it is preferable that one or more of the display portion 6511, the input portion 6512, the scan line driver circuit 6513, the sensor driver circuit 6503, and the detection circuit 6504 included in the touch panel 6510 each include a transistor in which an oxide semiconductor is used for a channel formation region, which has extremely low off-state current. Since the off-state current of the transistor is extremely low, long-term retention of data can be ensured by using the transistor as a switch for holding charges (data) flowing into a capacitor serving as a storage element. Further, the transistor can be used in the circuit unit 6501 included in the IC 6520, the signal line driver circuit 6502, the AD conversion circuit 6507, or the like provided outside the CPU 6540 and the like. For example, by applying this characteristic to a register or a cache memory or the like of the image processing circuit 6506, the image processing circuit 6506 can be operated only when necessary, and in other cases, previous processing information can be stored in the storage element, whereby so-called normally off computing in which power supply to the image processing circuit 6506 is turned off when the image processing circuit 6506 is not used can be achieved, and low power consumption of the touch panel module 6500 and an electronic device provided with the touch panel module 6500 can be achieved.

[0460] Note that, although a structure in which the circuit unit 6501 includes the timing controller 6505 and the image processing circuit 6506 is described here, the image processing circuit 6506 itself or a circuit having part of the functions of the image processing circuit 6506 can be provided outside the IC 6520. Alternatively, the CPU 6540 can be provided with all or part of the functions of the image processing circuit 6506. For example, a structure in which the circuit unit 6501 includes the signal line driver circuit 6502, the timing controller 6505, and the AD conversion circuit 6507 can be employed.

[0461] Further, although an example in which the IC 6520 includes the circuit unit 6501 is described here, the circuit unit 6501 can not be included in the IC 6520. In that case, the IC 6520 can have a structure including the signal line driver circuit 6502 and the AD conversion circuit 6507. For example, when a plurality of ICs are mounted in the touch panel module 6500, a plurality of ICs 6520 which do not include the circuit unit 6501 can be arranged by additionally providing an IC including the circuit unit 6501, or an IC including only the IC 6520 and the signal line driver circuit 6502 can be combined.

[0462] Thus, by assembling the function of driving the display portion 6511 of the touch panel 6510 and the function of driving the input portion 6512 in one IC, the number of ICs mounted in the touch panel module 6500 can be reduced, and thus cost can be reduced.

[0463] FIG. 29A ,FIG. 29B and FIG. 29C is a schematic view of a touch panel module 6500 in which an IC 6520 is mounted.

[0464] In FIG. 29A , the touch panel module 6500 includes a substrate 6531, a counter substrate 6532, a plurality of FPCs 6533, the IC 6520, and an IC 6530, and the like. Between the substrate 6531 and the counter substrate 6532, a display portion 6511, an input portion 6512, a scan line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504 are included. The IC 6520 and the IC 6530 are mounted on the substrate 6531 by a COG (Chip On Glass) method or the like.

[0465] The IC 6530 is an IC that includes only the signal line driver circuit 6502 or includes the signal line driver circuit 6502 and the circuit unit 6501 in the above-described IC 6520. The IC 6520 and the IC 6530 are supplied with signals from the outside through the FPC 6533. In addition, it is also possible to output signals from the IC 6520 or the IC 6530 to the outside through the FPC 6533.

[0466] FIG. 29A A structure in which two scan line driver circuits 6513 are provided in a manner of sandwiching the display portion 6511 is exemplified. Also, a structure in which the IC 6530 is included in addition to the IC 6520 is shown. Such a structure can be applied to a case where the resolution of the display portion 6511 is extremely high.

[0467] FIG. 29B An example in which one IC 6520 and one FPC 6533 are mounted is shown. In this way, by concentrating functions in one IC 6520, the number of components can be reduced, so it is preferable. In addition, in FIG. 29B , an example in which the scan line driver circuit 6513 is arranged along the side of the two short sides of the display portion 6511 that is closer to the FPC 6533 is shown.

[0468] FIG. 29C A structure including a PCB (Printed Circuit Board) 6534 in which an image processing circuit 6506 or the like is mounted is exemplified. The IC 6520 and the IC 6530 on the substrate 6531 are electrically connected to the PCB 6534 by the FPC 6533. Here, the IC 6520 can also not include the above-described image processing circuit 6506.

[0469] Further, in FIG. 29A , FIG. 29B and FIG. 29CIn this case, the ICs 6520 and 6520 can also be mounted on the FPC 6533 without being mounted on the substrate 6531. For example, the ICs 6520 and 6520 can be mounted on the FPC 6533 in a COF manner or a TAB manner or the like.

[0470] As FIG. 29A and FIG. 29B indicated, a structure in which the FPC 6533, the ICs 6520 (and 6530), and the like are arranged on the short side of the display portion 6511 can realize a narrow frame, and thus can be applied to electronic devices such as smartphones, mobile phones, or tablet terminals, for example. In addition, a structure using the PCB 6534 as indicated in FIG. 29C , for example, can be applied to television devices, display devices, tablet terminals, or notebook personal computers, and the like.

[0471] At least a part of this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0472] (Embodiment 6)

[0473] In this embodiment mode, an electronic device of one embodiment of the present application is described.

[0474] The electronic device of this embodiment mode includes a display device of one embodiment of the present application in a display portion. The display device of one embodiment of the present application is easy to realize high definition and high resolution. Thus, it can be used for a display portion of various electronic devices.

[0475] In addition, the semiconductor device of one embodiment of the present application can also be used for a portion other than the display portion of an electronic device. For example, when the semiconductor device of one embodiment of the present application is used for a control portion or the like of an electronic device, low power consumption can be realized, and thus it is preferable.

[0476] As the electronic device, for example, in addition to a television device, a desktop or notebook personal computer, a display for a computer or the like, a digital sign, a large game machine such as a pachinko machine, and the like, an electronic device having a large screen can be given. Further, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, a sound reproduction device, and the like can be given.

[0477] In particular, since the display device of one embodiment of the present application can improve definition, it can be used for an electronic device including a small display portion. As such an electronic device, for example, a watch-type and bracelet-type information terminal device (wearable device), a wearable device that can be worn on the head, a VR device such as a head-mounted display, a glasses-type AR device, and a MR device, and the like can be given.

[0478] The electronic device of this embodiment can also include a sensor having a function of detecting, sensing, or measuring a force, a displacement, a position, a velocity, an acceleration, an angular velocity, a rotational frequency, a distance, light, liquid, magnetism, a temperature, a chemical substance, a sound, time, hardness, an electric field, an electric current, an electric voltage, an electric power, a radiation line, a flow rate, humidity, an inclination, a vibration, an odor, or infrared rays.

[0479] The electronic device of this embodiment can have various functions. For example, it can have a function of displaying various information (still images, moving images, character images, and the like) on the display portion, a function of a touch panel, a function of displaying a calendar, a date, or a time, a function of executing various kinds of software (programs), a function of performing wireless communication, a function of reading out a program or data stored in a storage medium, and the like.

[0480] FIG. 30A The electronic device 7500 shown is a portable information terminal device that can be used as a smartphone.

[0481] The electronic device 7500 includes a housing 7001, a display portion 7002, a power button 7003, a button 7004, a speaker 7005, a microphone 7006, a camera 7007, a light source 7008, and the like. The display portion 7002 has a function of a touch panel.

[0482] The display portion 7002 can apply the display device of one embodiment of the present application.

[0483] FIG. 30B FIG. 7B is a cross-sectional view of an end portion of the microphone 7006 side of the housing 7001.

[0484] The display surface side of the housing 7001 is provided with a protective member 7010 having a light-transmitting property, and a space surrounded by the housing 7001 and the protective member 7010 is provided with a display panel 7011, an optical member 7012, a touch sensor panel 7013, a printed circuit board 7017, a battery 7018, and the like.

[0485] The display panel 7011, the optical member 7012, and the touch sensor panel 7013 are fixed to the protective member 7010 with an adhesive layer (not shown).

[0486] In a region on the outer side of the display portion 7002, part of the display panel 7011 is folded, and the folded portion is connected to an FPC 7015. The FPC 7015 is provided with an IC 7016. The FPC 7015 is connected to a terminal provided in the printed circuit board 7017.

[0487] The display panel 7011 can use the display device of one embodiment of the present application. With this, an electronic device that is extremely lightweight can be implemented. Further, since the display panel 7011 is extremely thin, a large-capacity battery 7018 can be mounted with the thickness of the electronic device suppressed. Further, by folding a portion of the display panel 7011 to provide a connection portion with the FPC 7015 on the back of the pixel portion, an electronic device with narrow frame can be implemented.

[0488] FIG. 30C An example of a television device is shown. In the television device 7100, a housing 7101 has incorporated therein a display portion 7000. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

[0489] The display portion 7000 can apply the display device of one embodiment of the present application.

[0490] The operation of the television device 7100 shown in FIG. 8 can be performed by operating switches provided in the housing 7101 and a remote control 7111 provided separately. FIG. 30C The display portion 7000 can apply the display device of one embodiment of the present application.

[0491] Further, the television device 7100 includes a receiver and a modem, and the like. With the receiver, general television broadcasts can be received. Furthermore, with the modem connected to a communication network by a wired or wireless method, one-way (from a sender to a receiver) or two-way (between senders, between receivers, or the like) information communication can be performed.

[0492] FIG. 30D An example of a notebook personal computer is shown. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The display portion 7000 is incorporated in the housing 7211.

[0493] The display portion 7000 can apply the display device of one embodiment of the present application.

[0494] FIG. 30E The display portion 7000 can apply the display device of one embodiment of the present application. FIG. 30F An example of a digital sign is shown.

[0495] FIG. 30EThe digital sign 7300 illustrated includes a housing 7301, the display portion 7000, a speaker 7303, and the like. Further, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.

[0496] FIG. 30F A digital sign 7400 provided on a cylindrical column 7401 is illustrated. The digital sign 7400 includes the display portion 7000 provided along the curved surface of the column 7401.

[0497] In FIG. 30E and FIG. 30F , the display device of one embodiment of the present application can be used for the display portion 7000.

[0498] The larger the display portion 7000 is, the more information can be provided at a time. The larger the display portion 7000 is, the more likely it is to attract attention, and for example, the effect of advertisement can be improved.

[0499] It is preferable to use a touch panel for the display portion 7000 because not only a still image or a moving image can be displayed on the display portion 7000 but also a user can intuitively operate the display portion 7000. In the case of use for providing information such as route information or traffic information, the ease of use can be improved by intuitive operation.

[0500] As illustrated in FIG. 30E and FIG. 30F , the digital sign 7300 or the digital sign 7400 can be linked to an information terminal device 7311 or an information terminal device 7411 carried by a user through wireless communication. For example, advertisement information displayed on the display portion 7000 can be displayed on the screen of the information terminal device 7311 or the information terminal device 7411. Further, the display of the display portion 7000 can be switched by operating the information terminal device 7311 or the information terminal device 7411.

[0501] A game can be played on the digital sign 7300 or the digital sign 7400 with the screen of the information terminal device 7311 or the information terminal device 7411 as an operation unit (controller). Thus, a plurality of users can participate in the game at the same time and enjoy the game.

[0502] At least a part of the present embodiment can be implemented in appropriate combination with the other embodiments described in this specification.

[0503] [Explanation of Symbols]

[0504] AF1: alignment film, AF2: alignment film, BM: light shielding film, CF: coloring layer, DL_1: data line, DL_n: data line, DL_Y: data line, GL_1: gate line, GL_m: gate line, GL_X: gate line, KB: layer, LC: liquid crystal device, VL_a: potential supply line, VL_b: potential supply line, 10: transistor, 100: transistor, 104: electrode, 106: insulating layer, 108: semiconductor layer, 110_1: surface, 110_2: surface, 110_3: surface, 110_4: opening, 110A: layer, 110B: layer, 110C: layer, 112A: electrode, 112B: electrode, 112B_3: surface, 112B_4: opening, 153: substrate, 154: insulating layer, 155: conductive layer, 156: insulating layer, 157: insulating layer, 158: insulating layer, 159: opening, 160: conductive layer, 161: semiconductor layer, 162: insulating layer, 163: conductive layer, 164: insulating layer, 166: conductive layer, 510: functional layer, 516: layer, 517_4: opening, 517A: layer, 517B: layer, 517: layer, 518_4: opening, 518: layer, 519A: conductive layer, 519B: conductive layer, 519C: conductive layer, 520: functional layer, 521: layer, 522: layer, 550LC: liquid crystal device, 550: functional element, 551LC: electrode, 552LC: electrode, 553LC: layer, 4400EL: pixel circuit, 4400LC: pixel circuit, 4400: pixel circuit, 4401EL: circuit, 4401LC: circuit, 4401: circuit, 4501: pixel circuit, 4502: pixel portion, 4504a: gate driver, 4504b: source driver, 4504: drive circuit portion, 4506: protection circuit, 4507: terminal portion, 4550: transistor, 4552: transistor, 4554: transistor, 4560: capacitor, 4562: capacitor, 4570: liquid crystal device, 4572: light emitting element, 5050A: display device, 5140: connection portion, 5151: substrate, 5152: substrate, 5162: display portion, 5164: circuit portion, 5165: wiring, 5172: FPC, 5173: IC, 5210B: sub-pixel, 5210G: sub-pixel, 5210R: sub-pixel, 5210: pixel, 6500: touch panel module, 6501: circuit unit, 6502: signal line driver circuit, 6503: sensor driver circuit, 6504: detection circuit, 6505: timing controller, 6506: image processing circuit, 6507: AD conversion circuit, 6510: touch panel, 6511: display portion, 6512: input portion, 6513: scanning line driver circuit, 6520: IC, 6530: IC, 6531: substrate, 6532: counter substrate, 6533: FPC,6534: PCB, 6540: CPU, 7000: display portion, 7001: housing, 7002: display portion, 7003: power button, 7004: button, 7005: speaker, 7006: microphone, 7007: camera, 7008: light source, 7010: protection member, 7011: display panel, 7012: optical member, 7013: touch sensor panel, 7015: FPC, 7016: IC, 7017: printed circuit board, 7018: battery, 7100: television device, 7101: housing, 7103: stand, 7111: remote control, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital sign, 7301: housing, 7303: speaker, 7311: information terminal device, 7400: digital sign, 7401: column, 7411: information terminal device, 7500: electronic device.

Claims

1. A semiconductor device, comprising: First functional layer; Second functional layer; as well as First conductive layer, The second functional layer overlaps with the first functional layer. The second functional layer includes functional elements. The functional element includes a first electrode. The first functional layer includes a first layer, spacers, and transistors. The first layer is sandwiched between the second functional layer and the spacer. The first layer includes a first opening. The first layer is insulating. The spacer includes a first surface, a second surface, a third surface, and a second opening. The first surface, the second surface, and the third surface are insulating. The second surface is opposite to the first surface. The second surface is closer to the first layer than the first surface. The third surface connects the first surface and the second surface. The third surface is located on the side of the second opening. The transistor includes a second electrode, a third electrode, a fourth electrode, a semiconductor layer, and an insulating layer. The second electrode includes a region that contacts the first surface and a region that overlaps with the second opening. The third electrode includes a region in contact with the second surface, a third opening, and a fourth surface. The fourth surface is located on the side of the third opening. The third opening overlaps with the second opening. The fourth electrode includes a region facing the third electrode. The insulating layer includes the region sandwiched between the third surface and the fourth electrode. The semiconductor layer includes a region sandwiched between the third surface and the insulating layer. The semiconductor layer is in contact with the second electrode in the second opening. The semiconductor layer is in contact with the third electrode on the fourth surface. Furthermore, the first conductive layer electrically connects the third electrode to the first electrode through the first opening.

2. The semiconductor device according to claim 1, further comprising: Second conductive layer, The second conductive layer is electrically connected to the second electrode. The second conductive layer has light-shielding properties. Furthermore, the first opening overlaps with the second conductive layer.

3. The semiconductor device according to claim 2, further comprising: Third conductive layer, The first functional layer includes a second layer. The second layer is sandwiched between the first layer and the spacer. The second layer includes a fourth opening. The second layer is insulating. The third conductive layer is sandwiched between the first layer and the second layer. The third conductive layer overlaps with the first opening and the fourth opening. The third conductive layer electrically connects the first conductive layer to the third electrode. The third conductive layer is transparent. Furthermore, the third electrode is transparent.

4. The semiconductor device according to claim 3, The first functional layer includes a fourth conductive layer. The first layer is sandwiched between the fourth conductive layer and the third conductive layer. Furthermore, the fourth conductive layer is transparent.

5. The semiconductor device according to claim 1, further comprising: Third conductive layer, The first functional layer includes a second layer. The second layer is sandwiched between the first layer and the spacer. The second layer includes a fourth opening. The second layer is insulating. The third conductive layer is sandwiched between the first layer and the second layer. The third conductive layer overlaps with the first opening and the fourth opening. The third conductive layer electrically connects the first conductive layer to the third electrode. The third conductive layer is transparent. The second electrode has light-shielding properties. Furthermore, the first opening overlaps with the second electrode.

6. The semiconductor device according to claim 1, further comprising: Third conductive layer; as well as Fifth conductive layer, The first functional layer includes a second layer. The second layer is sandwiched between the first layer and the spacer. The second layer includes a fourth opening. The second layer is insulating. The third conductive layer is sandwiched between the first layer and the second layer. The third conductive layer overlaps with the first opening and the fourth opening. The third conductive layer electrically connects the first conductive layer to the third electrode. The third conductive layer is transparent. The fifth conductive layer is electrically connected to the fourth electrode. The fifth conductive layer overlaps with the first opening. Furthermore, the fifth conductive layer has light-shielding properties.

7. A display device, in, The functional element in the semiconductor device according to any one of claims 1 to 6 is a liquid crystal device.

8. A display module, comprising: The display device according to claim 7; as well as At least one of a connector and an integrated circuit.

9. An electronic device, comprising: The display device according to claim 7; as well as At least one of a battery, camera, speaker, and microphone.

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