A low-temperature failure test system and test method for a chip under test

Abstract

The application discloses a kind of to be measured chip low temperature failure test system and test method, system includes refrigeration module, leakage current acquisition module, image acquisition module and control module;Refrigeration module makes to be measured chip from first temperature state cooling and maintain second temperature state;Image acquisition module obtains the first image information of to be measured chip at first temperature state, second image information at second temperature state;Leakage current acquisition module obtains first leakage current and second leakage current;Control module is electrically connected with image acquisition module and leakage current acquisition module respectively, for capturing first leakage current compound generated first photon, determine the initial bright spot of first photon on first image information;Capture second leakage current compound generated second photon, determine the failure bright spot of second photon on second image information;According to initial bright spot and failure bright spot, determine the failure position of to be measured chip.Using the above system, the failure position of low temperature failure to be measured chip under room temperature is quickly determined.

Description

Technical Field

[0001] This invention relates to the technical field of low-temperature failure testing, and more particularly to a low-temperature failure testing device and method for a chip under test. Background Technology

[0002] With the further maturation of chip technology and the diversification of chip usage environments, chip failures in different environments are increasing, leading to a growing demand for chip failure analysis. Common failure analyses include room-temperature electrical failure analysis, high-temperature electrical failure analysis, and low-temperature electrical failure analysis. For room-temperature failure analysis, the failure analysis laboratory temperature can be maintained at 20℃±5℃ and humidity at 40%~60% for testing. High-temperature failure analysis can be performed using heating. However, low-temperature failure localization presents many challenges because the low-temperature environment cannot be maintained at room temperature. Therefore, a method for failure analysis of chips that fail at low temperatures at room temperature is urgently needed. Summary of the Invention

[0003] This invention provides a low-temperature failure testing device and method for chips under test. By cooling the chip under test at room temperature and maintaining it at a low temperature, the failure location of the chip under test that fails at low temperature can be quickly and accurately determined under room temperature conditions. The method is low-cost and easy to operate.

[0004] In a first aspect, the present invention provides a low-temperature failure testing system for a chip under test, including a cooling module, a leakage current acquisition module, an image acquisition module, and a control module;

[0005] The cooling module is used to cool the chip under test from a first temperature state and maintain it at a second temperature state for a preset time period.

[0006] The image acquisition module is used to acquire first image information of the chip under test under a first temperature state and second image information of the chip under test under a second temperature state;

[0007] The leakage current acquisition module is used to acquire the first leakage current of the chip under test when it is in a first temperature state, and to acquire the second leakage current of the chip under test when it is in a second temperature state.

[0008] The control module is electrically connected to the image acquisition module and the leakage current acquisition module, respectively. It is used to receive the first image information and the first leakage current. Based on the first leakage current, it captures the first photon generated by the recombination of the first leakage current with the charge carriers in the chip under test. Based on the first photon, it determines the position point corresponding to the first photon on the first image information, forming an initial bright spot. It receives the second image information and the second leakage current. Based on the second leakage current, it captures the second photon generated by the recombination of the second leakage current with the charge carriers in the chip under test. Based on the second photon, it determines the position point corresponding to the second photon on the second image information, forming a failure bright spot. Based on the initial bright spot and the failure bright spot, it determines the failure location of the chip under test.

[0009] Optionally, the system also includes a stage; the stage has a through hole at its center; the stage is located on the side of the chip under test away from the image acquisition module, and the chip under test is directly opposite the through hole;

[0010] The cooling module is used to cool the chip under test from a first temperature state and maintain it at a second temperature state for a preset time period from the side of the stage away from the image acquisition module.

[0011] Optionally, the system also includes a first glass slide and a second glass slide; the chip under test is attached between the first carrier slide and the second glass slide;

[0012] The first glass slide is located on the side of the chip under test closer to the image acquisition module, and the second glass slide is located on the side of the chip under test away from the image acquisition module, in order to keep the surface of the chip under test clean.

[0013] The cooling module is used to cool the chip under test from a first temperature state to a second temperature state from the side of the first glass slide near the image acquisition module and maintain it for a preset time period.

[0014] Optionally, the thickness H of the first glass slide satisfies: 0.15mm≤H≤0.17mm.

[0015] Optionally, the preset time period is 5s-10s, and / or the second temperature state is -35℃ to -45℃.

[0016] Optionally, the refrigeration module includes a C2H2F4 rapid cooler.

[0017] Optionally, the image acquisition module includes an enhanced low-light microscope.

[0018] Secondly, the present invention provides a method for low-temperature failure testing of a chip under test, comprising:

[0019] The image acquisition module receives the first image information of the chip under test under the first temperature state, and the leakage current acquisition module receives the first leakage current of the chip under test under the first temperature state.

[0020] Based on the first leakage current, capture the first photon generated by the recombination of the first leakage current with the charge carriers in the chip under test;

[0021] Based on the first photon, the position point corresponding to the first photon on the first image information is determined, forming the initial bright spot;

[0022] The image acquisition module receives the second image information of the chip under test under the second temperature state, and the leakage current acquisition module receives the second leakage current of the chip under test under the second temperature state.

[0023] Based on the second leakage current, capture the second photon generated by the recombination of the second leakage current with the charge carriers in the chip under test;

[0024] Based on the second photon, the position point corresponding to the second photon on the second image information is determined, forming a failure bright spot;

[0025] Based on the initial bright spot and the failed bright spot, the failure location of the chip under test is determined.

[0026] Optionally, a protective layer is provided on the surface of the chip under test;

[0027] Before receiving the first image information of the chip under test in a first temperature state obtained by the image acquisition module, and the first leakage current of the chip under test in a first temperature state obtained by the leakage current acquisition module, the method further includes:

[0028] An acidic solution is used to remove the protective layer on the surface of the chip under test.

[0029] Optionally, based on the initial bright spot and the failed bright spot, the failure location of the chip under test can be determined, including:

[0030] Compare failed bright spots with initial bright spots to determine the locations of bright spots where there are more failed bright spots than initial bright spots;

[0031] Based on the locations of the extra bright spots and the design drawings, the failure location of the chip under test can be determined.

[0032] The technical solution of this invention involves electrically connecting a control module to an image acquisition module and a leakage current acquisition module. When the chip under test (DUT) is at a first temperature state, the image acquisition module acquires the first image information of the DUT, and the leakage current acquisition module acquires the first leakage current of the DUT. Upon receiving the first image information and the first leakage current, the control module detects that the first leakage current generates electron-hole pairs (i.e., charge carriers) when flowing through optical devices such as diodes on the DUT. These first leakage currents recombine with the charge carriers to generate first photons. The control module captures these first photons, converts the optical signal into an electrical signal, and combines this with the received first image information to determine the location of the first photon in the first image information, i.e., the initial bright spot. After determining the initial bright spot, a cooling module is used to cool the DUT from the first temperature state to a second temperature state, maintaining this temperature for a preset time period to ensure the DUT remains at the second temperature state throughout this preset time. When the DUT is powered on, the image acquisition module acquires the second image information of the DUT, and the leakage current acquisition module acquires the second leakage current of the DUT. The control module receives the second image information and the second leakage current. The second leakage current recombines with charge carrier radiation to generate a second photon. The control module captures the generated second photon and converts the optical signal into an electrical signal. Combined with the received second image information, it determines the location of the generated second photon within the second image information, i.e., the failure bright spot. Finally, the control module compares the initial bright spot with the failure bright spot. This can be understood as subtracting the initial bright spot from the failure bright spot; the resulting bright spot is the bright spot generated at the failure location. Therefore, by further magnifying the design drawings, it can be determined which component generated the extra bright spot, thus identifying the failure location of the chip under test (DUT), i.e., identifying the component that experienced low-temperature failure. Using the above system, by cooling the DUT at room temperature and maintaining it at a low second temperature state, rapid and accurate determination of the failure location of a low-temperature failed DUT is achieved under room temperature conditions. This method is low-cost and easy to operate.

[0033] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1This is a schematic diagram of a low-temperature failure testing system for a chip under test provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of another low-temperature failure testing system for a chip under test provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the structure of another low-temperature failure testing system for a chip under test provided in an embodiment of the present invention;

[0038] Figure 4 This is a flowchart of a low-temperature failure test method for a chip under test provided in an embodiment of the present invention. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] In one embodiment, Figure 1 This is a schematic diagram of a low-temperature failure testing system for a chip under test provided in an embodiment of the present invention. This embodiment is applicable to determining the failure location of a chip under test that has failed at low temperatures in a room temperature environment. (Refer to...) Figure 1As shown, the test system includes a cooling module 1, a leakage current acquisition module 2, an image acquisition module 3, and a control module 4. The cooling module 1 is used to cool the chip under test 5 from a first temperature state and maintain it at a second temperature state for a preset time period. The image acquisition module 3 is used to acquire first image information of the chip under test 5 at the first temperature state and second image information of the chip under test 5 at the second temperature state. The leakage current acquisition module 2 is used to acquire the first leakage current of the chip under test 5 at the first temperature state and the second leakage current of the chip under test 5 at the second temperature state. The control module 4 is connected to the image acquisition module 3 and the leakage current acquisition module 4 respectively. The current acquisition module 2 is electrically connected and is used to receive first image information and first leakage current. Based on the first leakage current, it captures the first photon generated by the recombination of the first leakage current with the charge carriers in the chip under test 5. Based on the first photon, it determines the position point corresponding to the first photon on the first image information, forming an initial bright spot. It also receives second image information and second leakage current. Based on the second leakage current, it captures the second photon generated by the recombination of the second leakage current with the charge carriers in the chip under test 5. Based on the second photon, it determines the position point corresponding to the second photon on the second image information, forming a failure bright spot. Based on the initial bright spot and the failure bright spot, it determines the failure location of the chip under test 5.

[0042] The cooling module 1 is used to cool the chip under test 5, so that the chip under test 5 cools down from a first temperature state to a second temperature state, and maintains the second temperature state for a preset time period. In this embodiment, the first temperature state can be room temperature, and the second temperature state can be a low temperature. In addition, the cooling module 1 may include a rapid cooler, which may include a C2H2F4 rapid cooler. Furthermore, provided that the chip under test 5 can be cooled down from the first temperature state to the second temperature state, this embodiment does not limit the specific structure and type of the cooling module 1. The leakage current acquisition module 2 is used to acquire the leakage current of the chip under test 5 when the chip under test 5 is powered on. That is, the leakage current acquisition module 2 can acquire the first leakage current of the chip under test 5 when it is in the first temperature state, and the second leakage current of the chip under test 5 when it is in the second temperature state. Typically, the first leakage current in the first temperature state is small, such as 1uA. The second leakage current in the second temperature state is large, such as 50uA. In this embodiment, the leakage current acquisition module 2 may include, but is not limited to, a power meter, or any electronic instrument that can be used to measure leakage current, and is not limited here. Image acquisition module 3 is used to acquire first image information of the chip under test 5 at a first temperature state and second image information of the chip under test 5 at a second temperature state, and sends the first and second image information to control module 4. In this embodiment, image acquisition module 3 may include, but is not limited to, an enhanced microscopy (EMMI) microscope. Specifically, the enhanced microscopy microscope may be an indium gallium arsenide (InGaAs) lens, which is a high-sensitivity detector that can accurately acquire image information of the chip under test 5. Control module 4 is the core control module of this embodiment, used to receive the first image information, the second image information, the first leakage current, and the second leakage current to determine the low-temperature failure location of the chip under test 5.

[0043] Specifically, by electrically connecting the control module 4 to the image acquisition module 3 and the leakage current acquisition module 2 respectively, when the chip under test 5 is in a first temperature state, i.e., at room temperature, by powering on the chip under test 5, the image acquisition module 3 will acquire the first image information of the chip under test 5 at this time, and the leakage current acquisition module 2 will acquire the first leakage current of the chip under test 5. The image acquisition module 3 will send the acquired first image information and the first leakage current acquired by the leakage current acquisition module 2 to the control module 4. After receiving the first image information and the first leakage current, the control module 4 will detect that the first leakage current generates electron-hole pairs, i.e., charge carriers, when it flows through the diodes and other optical devices of the chip under test 5. The first leakage current will recombine with the charge carriers to generate the first photon. The control module 4 will capture the generated first photon and convert the optical signal into an electrical signal. Combined with the received first image information, the control module 4 will determine the position of the generated first photon in the first image information, i.e., the initial bright spot. It is understandable that the first photon captured by the control module 4 is essentially a photon generated by leakage current at a certain location on the chip under test 5. Since the exact location of the first photon on the chip under test 5 is unknown, the control module 4 can gradually acquire image information by scanning the first image information line by line or point by point. Based on precise control during the scanning process, the location of the first photon can be mapped to a specific location in the first image information, thus determining the initial bright spot. Alternatively, the control module 4 can also directly use algorithmic logic to overlap the first photon with the first image information, thereby quickly comparing and determining the location of the first photon in the first image information.

[0044] After the control module 4 identifies the initial bright spot, the chip under test 5 can be cooled using the cooling module 1. This cooling process lowers the chip under test 5 from a first temperature state to a second temperature state, i.e., from room temperature to a preset low temperature, and continues for a preset time period to ensure the chip under test 5 remains at the second temperature state throughout this time. At this point, the chip under test 5 is powered on. The image acquisition module 3 acquires the second image information of the chip under test 5, and the leakage current acquisition module 2 acquires the second leakage current of the chip under test 5. The image acquisition module 3 sends the acquired second image information and the leakage current acquired by the leakage current acquisition module 2 to the control module 4. Upon receiving the second image information and the second leakage current, the control module 4 recognizes that the second leakage current generates electron-hole pairs (charge carriers) when flowing through the diodes and other optical components of the chip under test 5. These second leakage currents recombine with the charge carriers to generate second photons. The control module 4 captures these second photons, converts the optical signal into an electrical signal, and combines this with the received second image information to determine the location of the generated second photon in the second image information, i.e., the failure bright spot. It is understandable that the second photon captured by the control module 4 is essentially a photon generated by leakage current at a certain location on the chip under test 5. Since the exact location of the second photon on the chip under test 5 is unknown, the control module 4 can gradually acquire image information by scanning the second image information line by line or point by point. Based on precise control during the scanning process, the position of the second photon can be mapped to the second image information to determine the initial bright spot. Alternatively, the control module 4 can also directly use algorithmic logic to overlap the second photon with the second image information, thus quickly comparing and determining the position of the second photon in the second image information.

[0045] Finally, after the control module 4 determines the initial bright spot and the failed bright spot, it compares the initial bright spot and the failed bright spot. This can be understood as subtracting the initial bright spot from the failed bright spot. The extra bright spot is the bright spot generated at the failure location. Therefore, by further enlarging the design drawings, it can be determined which component generated the extra bright spot, thus determining the failure location of the chip under test 5, which is the component that caused the low-temperature failure.

[0046] The technical solution of this invention involves electrically connecting a control module to an image acquisition module and a leakage current acquisition module. When the chip under test (DUT) is in a first temperature state, the image acquisition module acquires the first image information of the DUT, and the leakage current acquisition module acquires the first leakage current of the DUT. Upon receiving the first image information and the first leakage current, the control module detects that the first leakage current generates electron-hole pairs (i.e., charge carriers) when flowing through the diodes or other optical devices of the DUT. These first leakage currents recombine with the charge carriers to generate first photons. The control module captures these first photons, converts the optical signal into an electrical signal, and combines this with the received first image information to determine the location of the first photon in the first image information, i.e., the initial bright spot. After determining the initial bright spot, a cooling module is used to cool the DUT from the first temperature state to a second temperature state, maintaining this temperature for a preset time period to ensure the DUT remains in the second temperature state throughout the preset time period. When the DUT is powered on, the image acquisition module acquires the second image information of the DUT, and the leakage current acquisition module acquires the second leakage current of the DUT. The control module receives the second image information and the second leakage current. The second leakage current recombines with charge carrier radiation to generate a second photon. The control module captures the generated second photon and converts the optical signal into an electrical signal. Combined with the received second image information, it determines the location of the generated second photon within the second image information, i.e., the failure bright spot. Finally, the control module compares the initial bright spot with the failure bright spot. This can be understood as subtracting the initial bright spot from the failure bright spot; the resulting bright spot is the bright spot generated at the failure location. Therefore, by further magnifying the design drawings, it can be determined which component generated the extra bright spot, thus identifying the failure location of the chip under test (DUT), i.e., identifying the component that experienced low-temperature failure. Using the above system, by cooling the DUT at room temperature and maintaining it at a low second temperature state, rapid and accurate determination of the failure location of a low-temperature failed DUT is achieved under room temperature conditions. This method is low-cost and easy to operate.

[0047] Optionally, the preset time period is 5s-10s, and / or the second temperature state is -35℃ to -45℃.

[0048] In this embodiment, to ensure that the acquisition of the second image information and the second leakage current is achieved at a preset low temperature, the surface temperature of the chip under test 5 needs to be maintained at a second temperature state, i.e., a low temperature state, for at least a preset time period. This preset time period is 5s-10s, meaning the cooling module 1 needs to continuously cool the chip under test 5 after its surface temperature reaches the second temperature state, maintaining the surface temperature for at least 5s-10s. During this time period, the acquisition of the second image information and the second leakage current of the chip under test 5 is completed. Furthermore, to determine whether the surface temperature of the chip under test 5 is maintained at the second temperature state within the preset time period, a high-precision temperature gun can be used to detect the surface temperature of the chip under test 5 in real time within that preset time period. The high-precision temperature gun has a measurement range of -50℃ to 950℃.

[0049] In addition, the second temperature state in this embodiment is -35℃ to -45℃. Even if the surface of the chip 5 under test is maintained in the above range for a preset time period, for example, the second temperature state can be -35℃, -40℃ or -45℃. The specific temperature state can be determined according to the actual situation and is not limited here.

[0050] Optional, Figure 2 This is a schematic diagram of another low-temperature failure testing system for a chip under test provided in an embodiment of the present invention, with reference to... Figure 2 As shown, the system also includes a stage 6; a through hole 61 is provided at the center of the stage 6; the stage 6 is located on the side of the chip under test 5 away from the image acquisition module 3, and the chip under test 5 is directly facing the through hole 61; the cooling module 1 is used to cool the chip under test 5 from the side of the stage 6 away from the image acquisition module 3 from the first temperature state and maintain the second temperature state within a preset time period.

[0051] The stage 6 is used to place the chip under test 5. In this embodiment, one end of the stage 6 can be fixed to a fixing member to ensure that the stage 6 is in a suspended state. A through hole 61 is provided in the center of the stage 6 to place the chip under test 5, so that the chip under test 5 is directly facing the through hole 61. In this state, the chip under test 5 is above the stage 6, and there is no structure below it. The back of the chip under test 5 can be observed through the through hole 61 below the stage 6. Therefore, when the cooling module 1 is used to cool the chip under test 5, the cooling can be performed from the side of the stage 6 away from the image acquisition module 3, that is, from below the stage 6. Essentially, the cooling of the chip under test 5 is achieved through the through hole 61 of the stage 6, causing the temperature of the chip under test 5 to drop from a first temperature state and maintain a second temperature state for a preset time period.

[0052] Optional, Figure 3 This is a schematic diagram of another low-temperature failure testing system for a chip under test provided in an embodiment of the present invention, with reference to... Figure 3As shown, the system also includes a first glass slide 7 and a second glass slide 8; the chip under test 5 is attached between the first glass slide 7 and the second glass slide 8; the first glass slide 7 is located on the side of the chip under test 5 closer to the image acquisition module 3, and the second glass slide 8 is located on the side of the chip under test 5 away from the image acquisition module 3, for keeping the surface of the chip under test 5 clean; the cooling module 1 is used to cool the chip under test 5 from the first temperature state from the side of the first glass slide 7 closer to the image acquisition module 3 and maintain the second temperature state for a preset time period.

[0053] In this embodiment, the first glass slide 7 and the second glass slide 8 are located on both sides of the chip under test 5 and are attached to the chip under test 5. The first glass slide 7 is attached to the front of the chip under test 5, and the second glass slide 8 is attached to the back of the chip under test 5. This effectively prevents liquefied water vapor and dirt from entering the chip under test 5, keeping the surface of the chip under test 5 clean. In this embodiment, the materials of the first glass slide 7 and the second glass slide 8 can be transparent materials, including but not limited to glass. At this time, after the first glass slide 7 and the second glass slide 8 are set on both sides of the chip under test 5, with the first glass slide 7 located on the side of the chip under test 5 closer to the image acquisition module 3 and the second glass slide 8 located on the side of the chip under test 5 away from the image acquisition module 3, that is, the first glass slide 7 is located between the chip under test 5 and the image acquisition module 3, when the cooling module 1 cools down the chip under test 5, it can choose to cool down from the front of the chip under test 5, that is, from the side of the first glass slide 7, so that the temperature of the chip under test 5 drops from the first temperature state and is maintained in the second temperature state for a preset time period.

[0054] It should be noted that when attaching the first glass slide 7 to the front of the chip under test 5, insulating and high and low temperature resistant tape can be used to fix the first glass slide 7. When applying the tape, only the outer edge of the first glass slide 7 should be adhered, and the center of the first glass slide 7 should not be adhered, so as to prevent the front of the chip under test 5 from being blocked by the tape, which would affect the clarity of the image acquisition module 3 in acquiring the image of the surface of the chip under test 5.

[0055] Optional, continue to refer to Figure 2 and Figure 3 The thickness H of the first glass slide 7 satisfies: 0.15mm≤H≤0.17mm.

[0056] In this embodiment, when selecting the first glass slide 7, a thickness of 0.15mm-0.17mm can be selected. For example, the thickness H of the first glass slide 7 can be 0.15mm, 0.16mm, or 0.17mm. Without affecting the cooling of the chip under test 5 and the acquisition of the surface image of the chip under test 5, the thickness of the first glass slide 7 can be determined according to the actual situation and is not limited here. In addition, the length and width of the first glass slide 7 can be selected as needed. For example, the length and width of the first glass slide 7 are both 24mm ± 1mm.

[0057] It should be noted that, for the second glass slide 8, in this application, it can be selected within the range of 76±1mm in length, 25±1mm in width, and 1±0.1mm in thickness, and there is no limitation.

[0058] Based on the same inventive concept, this invention provides a method for low-temperature failure testing of a chip under test. Figure 4 A flowchart of a low-temperature failure test method for a chip under test provided in an embodiment of the present invention is shown below. Figure 4 As shown, the method includes:

[0059] S110: Receive the first image information of the chip under test under the first temperature state obtained by the image acquisition module, and the first leakage current of the chip under test under the first temperature state obtained by the leakage current acquisition module.

[0060] Specifically, when the chip under test is in the first temperature state, i.e. at room temperature, by powering on the chip under test, the image acquisition module will acquire the first image information of the chip under test at this time, and the leakage current acquisition module will acquire the first leakage current of the chip under test.

[0061] S120. Based on the first leakage current, capture the first photon generated by the recombination of the first leakage current and the charge carriers in the chip under test.

[0062] S130. Based on the first photon, determine the position point corresponding to the first photon on the first image information to form an initial bright spot.

[0063] Specifically, after receiving the first image information and the first leakage current, the first leakage current generates electron-hole pairs (i.e., charge carriers) when flowing through the diodes and other optical components of the chip under test (DUT). These carriers recombine with the leakage current to generate the first photon. The system captures this first photon, converts the optical signal into an electrical signal, and combines this signal with the received first image information to determine the location of the first photon within the image information—the initial bright spot. Essentially, the captured first photon is a photon generated by leakage current at a specific location on the DUT. Since the exact location of the first photon on the DUT is unknown, the first image information can be scanned line by line or point by point to gradually acquire image information in sections. Precise control during the scanning process allows the location of the first photon to be mapped to a specific position in the first image information, thus determining the initial bright spot. Alternatively, algorithms can be used to directly overlap the first photon with the first image information, enabling rapid comparison and determination of the first photon's location within the first image information.

[0064] S140: Receive the second image information of the chip under test under the second temperature state obtained by the image acquisition module, and the second leakage current of the chip under test under the second temperature state obtained by the leakage current acquisition module.

[0065] Specifically, after identifying the initial bright spot, the chip under test can be cooled using a cooling module. This cools the chip from a first temperature state to a second temperature state, i.e., from room temperature to a preset low temperature, and maintains this temperature for a preset time period, ensuring that the chip remains at the second temperature state throughout the preset time period. At this point, the chip is powered on, and the image acquisition module acquires the second image information of the chip under test, while the leakage current acquisition module acquires the second leakage current of the chip under test.

[0066] S150. Based on the second leakage current, capture the second photon generated by the recombination of the second leakage current and the charge carriers in the chip under test.

[0067] S160. Based on the second photon, determine the position point corresponding to the second photon on the second image information, forming a failure bright spot.

[0068] Specifically, after receiving the second image information and the second leakage current, the second leakage current generates electron-hole pairs (i.e., charge carriers) when flowing through the diodes and other optical components of the chip under test (DUT). These carriers recombine to generate a second photon. The system captures this second photon, converts the optical signal into an electrical signal, and combines this signal with the received second image information to determine the location of the second photon within the image information—the failure bright spot. Essentially, the captured second photon is a photon generated at a specific location on the DUT due to leakage. Since the exact location of the second photon on the DUT is unknown, the second image information can be scanned line by line or point by point to gradually acquire image information in sections. Precise control during the scanning process allows the location of the second photon to be mapped to the second image information, thus identifying the initial bright spot. Alternatively, algorithms can be used to directly overlap the second photon with the second image information, enabling rapid comparison and determination of the second photon's location within the second image information.

[0069] S170. Based on the initial bright spot and the failed bright spot, determine the failure location of the chip under test.

[0070] This step can be further broken down into: comparing the failed bright spots with the initial bright spots, determining the locations of bright spots where the number of failed bright spots exceeds the number of initial bright spots, and thus determining the location of the failure in the chip under test.

[0071] Specifically, after identifying the initial bright spot and the failed bright spot, the two are compared. This can be understood as subtracting the initial bright spot from the failed bright spot. The extra bright spot is the bright spot generated at the failure location. Therefore, by further enlarging the design drawings, we can determine which component generated the extra bright spot, thus identifying the failure location of the chip under test, which is the component that caused the low-temperature failure.

[0072] The technical solution of this invention involves receiving first image information of the chip under test (DUT) at a first temperature state acquired by an image acquisition module, and first leakage current of the DUT at the first temperature state acquired by a leakage current acquisition module; capturing first photons generated by the recombination of the first leakage current with charge carriers in the DUT based on the first leakage current; determining the position point corresponding to the first photon on the first image information based on the first photon, forming an initial bright spot; receiving second image information of the DUT at a second temperature state acquired by the image acquisition module, and second leakage current of the DUT at the second temperature state acquired by the leakage current acquisition module; capturing second photons generated by the recombination of the second leakage current with charge carriers in the DUT based on the second leakage current; determining the position point corresponding to the second photon on the second image information based on the second photon, forming a failure bright spot; and determining the failure location of the DUT based on the initial bright spot and the failure bright spot. Using this method, rapid and accurate determination of the failure location of a DUT that fails at low temperatures is achieved under room temperature conditions, with low cost and ease of operation.

[0073] Optionally, a protective layer is provided on the surface of the chip under test; before S110, receiving the first image information of the chip under test under the first temperature state acquired by the image acquisition module, and the first leakage current of the chip under test under the first temperature state acquired by the leakage current acquisition module, the method further includes:

[0074] S100. Use an acidic solution to remove the protective layer on the surface of the chip under test.

[0075] The protective layer on the surface of the chip to be tested after sample preparation is usually a layer of black glue.

[0076] Specifically, when removing the protective layer on the surface of the chip under test, an acidic solution, such as a solution of nitric acid or hydrochloric acid with a certain concentration, can be used. Through the chemical reaction between the acidic solution and the protective layer, the protective layer is removed, exposing the surface of the chip under test and the silicon substrate and other materials on the back of the chip under test, in preparation for subsequent failure testing.

[0077] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0078] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A low-temperature failure testing system for a chip under test, characterized in that, It includes a cooling module, a leakage current acquisition module, an image acquisition module, and a control module; The cooling module is used to cool the chip under test from a first temperature state and maintain it at a second temperature state for a preset time period. The image acquisition module is used to acquire first image information of the chip under test under the first temperature state and second image information of the chip under test under the second temperature state; The leakage current acquisition module is used to acquire the first leakage current of the chip under test when it is in the first temperature state, and to acquire the second leakage current of the chip under test when it is in the second temperature state. The control module is electrically connected to the image acquisition module and the leakage current acquisition module respectively, and is used to receive the first image information and the first leakage current, capture the first photon generated by the recombination of the first leakage current and the charge carriers in the chip under test according to the first leakage current, and determine the position point of the first photon on the first image information according to the first photon to form an initial bright spot. The system receives the second image information and the second leakage current. Based on the second leakage current, it captures the second photon generated by the recombination of the second leakage current with the charge carriers in the chip under test. Based on the second photon, it determines the position point corresponding to the second photon on the second image information, forming a failure bright spot. Based on the initial bright spot and the failure bright spot, it determines the failure location of the chip under test.

2. The low temperature failure test system for a chip under test according to claim 1, wherein, It also includes a stage; the stage has a through hole at its center; the stage is located on the side of the chip under test away from the image acquisition module, and the chip under test is directly opposite the through hole; The cooling module is used to cool the chip under test from the first temperature state and maintain the second temperature state for a preset time period from the side of the stage away from the image acquisition module.

3. The low temperature failure test system for a chip under test according to claim 1, wherein, It also includes a first glass slide and a second glass slide; the chip under test is attached between the first carrier slide and the second glass slide; The first glass slide is located on the side of the chip under test closer to the image acquisition module, and the second glass slide is located on the side of the chip under test away from the image acquisition module, in order to keep the surface of the chip under test clean; The cooling module is used to cool the chip under test from the first temperature state and maintain the second temperature state for a preset time period from the side of the first glass slide closest to the image acquisition module.

4. The low temperature failure test system for a chip under test according to claim 3, wherein, The thickness H of the first glass slide satisfies: 0.15mm≤H≤0.17mm.

5. The low temperature failure test system for a chip under test of claim 1, wherein, The preset time period is 5s-10s, and / or the second temperature state is -35℃ to -45℃.

6. The low temperature failure test system of a die under test as recited in claim 1, wherein, The refrigeration module includes a C2H2F4 rapid cooler.

7. The low temperature failure test system of a die under test as recited in claim 1, wherein, The image acquisition module includes an enhanced low-light microscope.

8. A method for low temperature failure test of a chip to be tested, characterized by, include: The image acquisition module receives first image information of the chip under test being in a first temperature state, and the leakage current acquisition module receives first leakage current of the chip under test being in the first temperature state. Based on the first leakage current, capture the first photon generated by the recombination of the first leakage current with the charge carriers in the chip under test; According to the first photon, a corresponding position point of the first photon on the first image information is determined to form an initial bright spot; receiving second image information of the to-be-tested chip in a second temperature state acquired by the image acquisition module and second leakage current of the to-be-tested chip in the second temperature state acquired by the leakage current acquisition module; According to the second leakage current, a second photon generated by the recombination of the second leakage current and the carrier in the to-be-tested chip is captured; According to the second photon, a corresponding position point of the second photon on the second image information is determined to form a failure bright spot; According to the initial bright spot and the failure bright spot, the failure position of the to-be-tested chip is determined.

9. The method of claim 8, wherein the low temperature failure test of the die under test is performed at a temperature of about - 40°C. The surface of the to-be-tested chip is provided with a protective layer; Before receiving the first image information of the to-be-tested chip in a first temperature state acquired by the image acquisition module and the first leakage current of the to-be-tested chip in the first temperature state acquired by the leakage current acquisition module, the method further comprises: Using an acidic solution, the protective layer on the surface of the to-be-tested chip is removed.

10. The method of claim 8, wherein the low temperature failure test of the die under test is performed at a temperature of about - 40°C. According to the initial bright spot and the failure bright spot, the failure position of the to-be-tested chip is determined, comprising: Comparing the failure bright spot with the initial bright spot to determine the bright spot positions that the failure bright spot has more than the initial bright spot; According to the extra bright spot positions, the failure position of the to-be-tested chip is determined in combination with a design drawing.

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