Voltage regulator with aging mitigation

Abstract

The present disclosure relates to a voltage regulator comprising: an error amplifier having a first output, a first non-inverting input, and a first inverting input, wherein the error amplifier is configured to generate a signal based on a first voltage at the first non-inverting input and a second voltage at the first inverting input; and circuitry coupled to the error amplifier and to an output of the voltage regulator. The circuitry may be configured to: in a first mode, cause a voltage to be applied at a predefined voltage level between the first inverting input and the first non-inverting input of the error amplifier; and in a second mode, coupling the first inverting input of the error amplifier to a first reference voltage source and coupling the first non-inverting input of the error amplifier to the output of the voltage regulator.

Description

TECHNICAL FIELD

[0001] Embodiments of the subject matter described herein relate generally to voltage regulators, such as voltage regulators including a boost converter. BACKGROUND

[0002] Automotive systems often require voltage regulation to accommodate sudden changes in battery voltage, which can occur, for example, during cold start. Such voltage regulation is generally intended to prevent the voltage supplied to the automotive system from falling below a target voltage level, such as a target voltage level that can be required to maintain operation of various electrical systems of the automotive system. Over time, aging and degradation of circuitry used to provide such voltage regulation can negatively impact the accuracy and robustness of the automotive system. SUMMARY

[0003] In an example embodiment, a voltage regulator includes an error amplifier having a first output, a first non-inverting input, and a first inverting input, where the error amplifier is configured to generate a signal based on a first voltage at the first non-inverting input and a second voltage at the first inverting input; and circuitry coupled to the error amplifier and to an output of the voltage regulator. The circuitry can be configured to, in a first mode, cause a voltage to be applied at a predefined voltage level between the first inverting input and the first non-inverting input of the error amplifier; and in a second mode, cause the first inverting input of the error amplifier to be coupled to a first reference voltage source and the first non-inverting input of the error amplifier to be coupled to the output of the voltage regulator.

[0004] In one or more embodiments, the voltage regulator additionally includes boost converter circuitry having a second output and configured to generate an output voltage at the second output, where the output voltage of the boost converter circuitry is controlled based on the signal generated by the error amplifier.

[0005] In one or more embodiments, the circuitry includes a first switch coupled between the first inverting input of the error amplifier and the first non-inverting input of the error amplifier; a second switch coupled to the first inverting input of the error amplifier; a comparator having a second inverting input, a second non-inverting input, and a third output, where the second inverting input is coupled to a second reference voltage source, the second non-inverting input is coupled to the output voltage of the boost converter circuitry, and the third output is coupled to respective control terminals of the first switch and the second switch; and a source selectively coupled to at least one of the first inverting input of the error amplifier or the first non-inverting input of the error amplifier via the first switch, where the source is a current source or a voltage source.

[0006] In one or more embodiments, the source is a voltage source including a first terminal connected to a first non-inverting input of an error amplifier, and including a second terminal selectively coupled to a first inverting input via a first switch.

[0007] In one or more embodiments, the voltage regulator additionally includes at least one voltage divider coupled to the second output of the boost converter circuitry. A second non-inverting input of the comparator can be coupled to the second output of the boost converter circuitry via a first node of the at least one voltage divider, and the second switch can selectively couple the first inverting input of the error amplifier to the boost converter circuitry via a second node of the at least one voltage divider.

[0008] In one or more embodiments, the comparator is configured to close the first switch and open the second switch in a first mode, and to close the second switch and open the first switch in a second mode.

[0009] In one or more embodiments, the circuitry additionally includes an inverter coupled between a third output of the comparator and a control terminal of the second switch.

[0010] In one or more embodiments, the voltage regulator additionally includes a signal path coupled to the first output of the error amplifier, integrator circuitry coupled along the signal path, and pulse width modulation circuitry coupled between the signal path and the boost converter circuitry. The pulse width modulation circuitry can be configured to generate a modulated signal based on the signal output by the error amplifier, and to provide the modulated signal to control a transistor of the boost converter circuitry.

[0011] In an example embodiment, an automotive system includes a voltage regulator having an error amplifier having a first output, a first non-inverting input, and a first inverting input, where the error amplifier is configured to generate a signal based on a first voltage at the first non-inverting input and a second voltage at the first inverting input; a boost converter circuitry having a second output and configured to generate an output voltage at the second output, where the output voltage of the boost converter circuitry is controlled based on the signal generated by the error amplifier; and circuitry coupled to the error amplifier and to the second output of the boost converter circuitry. The circuitry can be configured to, in a first mode, cause a voltage to be applied at a predefined voltage level between the first inverting input and the first non-inverting input of the error amplifier, and in a second mode, couple the first inverting input of the error amplifier to a first reference voltage source and the first non-inverting input of the error amplifier to the second output of the boost converter circuitry.

[0012] In one or more embodiments, the circuitry includes a first switch coupled between a first inverting input of an error amplifier and a first non-inverting input of the error amplifier, a second switch coupled to the first inverting input of the error amplifier, a comparator having a second inverting input, a second non-inverting input, and a third output, wherein the second inverting input is coupled to a second reference voltage source, the second non-inverting input is coupled to an output voltage of the boost converter circuitry, and the third output is coupled to respective control terminals of the first switch and the second switch, and a source selectively coupled to at least one of the first inverting input of the error amplifier or the first non-inverting input of the error amplifier via the first switch. The source can be a current source or a voltage source.

[0013] In one or more embodiments, the source is a voltage source including a first terminal connected to the first non-inverting input of the error amplifier and including a second terminal selectively coupled to the first inverting input via the first switch.

[0014] In one or more embodiments, the automotive system additionally includes at least one voltage divider coupled to the second output of the boost converter circuitry. The second non-inverting input of the comparator can be coupled to the second output of the boost converter circuitry via a first node of the at least one voltage divider, and the second switch can selectively couple the first inverting input of the error amplifier to the boost converter circuitry via a second node of the at least one voltage divider.

[0015] In one or more embodiments, the comparator is configured to close the first switch and open the second switch in a first mode, and to close the second switch and open the first switch in a second mode.

[0016] In one or more embodiments, the circuitry additionally includes an inverter coupled between the third output of the comparator and a control terminal of the second switch.

[0017] In one or more embodiments, the automotive system additionally includes a signal path coupled to a first output of the error amplifier, integrator circuitry coupled along the signal path, and pulse width modulation circuitry coupled between the signal path and the boost converter circuitry. The pulse width modulation circuitry can be configured to generate a modulated signal based on a signal output by the error amplifier, and to provide the modulated signal to control a transistor of the boost converter circuitry.

[0018] In an example embodiment, a method includes causing, by circuitry of a voltage regulator, a voltage difference to be applied across a first input and a second input of an error amplifier at a predefined voltage level in response to an output voltage of the voltage regulator being above a threshold voltage level; and causing, by the circuitry of the voltage regulator, the first input of the error amplifier to be coupled to a reference voltage source and the second input of the error amplifier to be coupled to the output of the voltage regulator in response to the output voltage being below the threshold voltage level.

[0019] In one or more embodiments, causing the voltage difference to be applied across the first input and the second input of the error amplifier at the predefined voltage level includes causing, by a comparator of the circuitry, a first switch of the circuitry to be closed, wherein the first switch is coupled between the first input and the second input of the error amplifier; and causing, by the comparator, a second switch of the circuitry to be opened, wherein the second switch is coupled between the second input of the error amplifier and the output of the voltage regulator.

[0020] In one or more embodiments, causing the first input of the error amplifier to be coupled to the reference voltage source and the second input of the error amplifier to be coupled to the output of the voltage regulator includes causing, by the comparator, the first switch of the circuitry to be opened; and causing, by the comparator, the second switch of the circuitry to be closed.

[0021] In one or more embodiments, the method further includes receiving, at a first input of the comparator, a voltage based on the output voltage of the voltage regulator, and receiving, at a second input of the comparator, a second reference voltage.

[0022] In one or more embodiments, the method further includes controlling a transistor of a boost converter circuitry of the voltage regulator based on an output signal generated by the error amplifier, wherein an output of the boost converter circuitry corresponds to the output of the voltage regulator. BRIEF DESCRIPTION OF DRAWINGS

[0023] A more complete understanding of the subject matter can be obtained by referring to the following detailed description and claims, considered in connection with the accompanying drawings, in which like reference symbols indicate similar elements throughout the several views. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. The figures, together with the detailed description, are incorporated in and form part of the specification, and serve to further illustrate examples, embodiments, and the like, and explain various principles and advantages in accordance with the present disclosure, in which:

[0024] Figure 1 An illustrative block diagram showing an automotive system including a voltage regulator with aging mitigation circuitry is shown in accordance with various embodiments;

[0025] Figure 2 An illustrative block diagram showing an automotive system including a voltage regulator with aging mitigation circuitry is shown in accordance with various embodiments; Figure 1a block diagram of a voltage regulator with aging mitigation circuitry in an automotive system;

[0026] Figure 3 illustrate a method for operating aging mitigation circuitry in a voltage regulator (e.g., Figure 2 various voltage levels during startup of a voltage regulator of

[0027] Figure 4 illustrate a method for operating aging mitigation circuitry in a voltage regulator (e.g., Figure 1 or Figure 2 a voltage regulator) according to various embodiments. DETAILED DESCRIPTION

[0028] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments described herein and the uses of such embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.

[0029] For the sake of explanation, general configurations are illustrated. Descriptions and details of well-known features and techniques can be omitted in order to avoid unnecessarily obscuring the present disclosure. For example, the sizes and relative sizes of some elements or regions in the figures can be exaggerated relative to other elements or regions to help improve the understanding of the embodiments described herein.

[0030] The terms “first,” “second,” “third,” “fourth,” and the like, if any, as used in the description and the claims, can be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in other sequences than described or otherwise illustrated herein. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, includes, or has a list of elements can include additional elements not expressly listed or inherent to such process, method, article, or apparatus. As used herein, the terms “approximately,” “substantially,” “about,” and “nearly” mean to an extent that a stated purpose is met by a reasonable amount of deviation, and slight deviations, if any, are immaterial to the stated purpose.

[0031] According to these principles, when used in reference to a measurable quantity, such as an amount of material, these terms mean that the quantity is equal to the stated value, within acceptable tolerances, given the manufacturing methodology / technology used to manufacture the described structure or measure the described quantity or dimension. Unless otherwise stated, directional references, such as "top," "bottom," "left," "right," "upper," "lower," and the like, are made for purposes of illustration and description and are not intended to be limiting, unless otherwise indicated. As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration." Any implementation described herein as exemplary or as an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, certain terminology can also be used in the present description for the purpose of reference only, and, thus, is not intended to be limiting.

[0032] In this document, elements or nodes or features are sometimes referred to as "connected" or "coupled" together. As used herein, unless expressly stated to the contrary, "connected" means that one element is directly or indirectly in electrical or non-electrical communication with (or is directly or indirectly communicative with) another element, and not necessarily mechanically or physically. Similarly, unless expressly stated to the contrary, "coupled" means that one element is directly or indirectly in electrical or non-electrical communication (or is directly or indirectly communicative) with another element, not necessarily mechanically or physically. Accordingly, although the schematic diagrams shown in the figures depict exemplary arrangements of elements, additional intervening elements, devices, features, or components can be present in one or more embodiments of the depicted subject matter.

[0033] Various embodiments described herein relate to voltage regulators, such as boost regulators (sometimes referred to herein as "boost voltage regulators" or "boost regulator circuitry"), having aging mitigation circuitry, as well as corresponding systems (e.g., automotive systems) and methods. As used herein, "boost regulator" refers to voltage regulator circuitry that includes boost converter circuitry.

[0034] Conventional automotive systems often use voltage regulators to prevent the voltage output from a battery to other automotive system components from dropping below a threshold voltage level when the battery voltage suddenly drops, for example, during engine startup. In one conventional approach, such voltage regulators include an operational amplifier that receives a feedback voltage based on the battery at a first input and a reference voltage at a second input, where the difference between the feedback voltage and the reference voltage controls the output of the operational amplifier, which in turn attempts to maintain the voltage output by the voltage regulator above the threshold voltage level. The voltage across the inputs of the operational amplifier in such conventional voltage regulators is relatively high during normal operation and relatively low during voltage regulation. The amount of time that conventional voltage regulators are in a normal operating state is typically significantly greater than the amount of time that they are in a voltage regulation state, such that the relatively high voltage across the inputs of the operational amplifier is maintained during a majority of the operating time of the automotive system that includes the voltage regulator. Maintaining this relatively high voltage level across the inputs of the operational amplifier in this way can be undesirable because it causes relatively faster aging of the operational amplifier (i.e., compared to when a lower voltage is used), and this accelerated aging negatively impacts the accuracy and robustness of the voltage regulator.

[0035] In one or more embodiments, an automotive system includes a voltage regulator, such as a boost voltage regulator, coupled to a battery, where the voltage regulator includes aging mitigation circuitry. The aging mitigation circuitry can include a comparator, a first switch, and a voltage source (or a current source according to one or more other embodiments). The first switch can be coupled between a first input and a second input of an error amplifier (e.g., an operational transconductance amplifier (OTA)). The first input of the error amplifier can be coupled to receive a first reference voltage from a first reference voltage source. The second input of the error amplifier can be coupled to an output of the voltage regulator via a feedback path that includes, for example, a voltage divider. A second switch can be coupled between the second input of the error amplifier and the output of the voltage regulator (e.g., via a first node of the voltage divider that is part of the feedback path).

[0036] The comparator can include first and second inputs and an output, where the first input of the comparator is coupled to the output of the voltage regulator via the second node of the voltage divider, the second input of the comparator is coupled to receive the second reference voltage from the second reference voltage source, and the output of the comparator is coupled to control terminals of the first and second switches. The resistances of the voltage divider and the values of the first and second reference voltages can be selected such that when the output voltage of the voltage regulator falls below a first threshold voltage level (e.g., indicating a start of a voltage regulation state), the comparator is configured to open the first switch and close the second switch, thereby disconnecting the first and second inputs of the error amplifier from each other and connecting the second input of the error amplifier to the feedback path. When the output voltage of the voltage regulator is above the first threshold voltage level (e.g., indicating that the voltage regulator is in a normal operating state), the comparator is configured to close the first switch and open the second switch, thereby connecting the first and second inputs of the error amplifier (via the voltage source) and disconnecting the second input of the error amplifier from the feedback path.

[0037] In this way, in the normal operating state, the voltage across the first and second inputs of the error amplifier can be set to a relatively low value, thereby mitigating an aging of the error amplifier that would otherwise occur due to maintaining a higher voltage level across the inputs of the amplifier. This aging mitigation can in turn advantageously improve accuracy (e.g., by reducing an associated shift in DC accuracy) and robustness of the voltage regulator.

[0038] Figure 1 An automotive system 100 (sometimes referred to herein as “system 100”) is shown that includes a voltage regulator 106 having an aging mitigation circuitry 108. The aging mitigation circuitry 108 can be configured to reduce a voltage offset between inputs of an error amplifier (e.g., which can be implemented as an operational transconductance amplifier (OTA)) of the voltage regulator 106 to mitigate an aging of the error amplifier, as described in more detail below.

[0039] As shown, the automotive system 100 includes a power management integrated circuit (PMIC) 102, a battery 104, a system on a chip (SOC) 116, one or more sensors 132, and a motor driver 134. The PMIC 102 can include the voltage regulator 106, a direct current (DC)-DC converter 110, one or more additional DC-DC converters 128, a memory 112, control logic 114, and one or more low dropout (LDO) regulators 130. The SOC 116 can include one or more processor cores 118, a memory 120, one or more input / output (I / O) devices 122, one or more peripheral devices 124, and one or more subsystems 126.

[0040] The battery 104 can be coupled to an input of a voltage regulator 106, which can provide a battery voltage VBAT at the input. In one or more embodiments, the battery voltage VBAT can be nominally between about 12V and about 14V, as non-limiting examples. The voltage regulator 106 can be coupled between the battery 104 and a DC-DC converter 110. In one or more embodiments, the DC-DC converter 110 can be a synchronous buck converter.

[0041] The voltage regulator 106 can be configured to generate an output voltage VBST, which can be provided to the DC-DC converter 110. During a normal operating state, the output voltage VBST can equal or approximately equal VBAT minus an offset (e.g., about 0.7V corresponding to a voltage drop across a diode of the voltage regulator 106). During a voltage regulation state (e.g., occurring when VBST falls below a threshold voltage level), the voltage regulator 106 can be configured to maintain a voltage level of the output voltage VBST at or above a target voltage level VTRGT. For example, the target voltage level VTRGT corresponds to a voltage level at or above which an interruption in operation of other “downstream” components or subsystems of the system 100 (e.g., the SOC 116, the sensor 132, and the motor driver 134) can be prevented or mitigated. In one or more embodiments, the target voltage level VTRGT can be about 6V, as non-limiting examples.

[0042] The DC-DC converter 110 can be configured to step down the voltage VBST and provide the resulting stepped-down voltage to an additional DC-DC converter 128 and an LDO regulator 130. In one or more embodiments, the DC-DC converter 110 can be a DC-DC step-down buck converter.

[0043] The additional DC-DC converter 128 can receive a voltage output by the DC-DC converter 110, which can step up or step down the voltage to generate one or more additional voltages. The additional DC-DC converter 128 can then provide these generated voltages to the SOC 116 (e.g., to one or more of the processor core 118, the memory 120, the I / O device 122, the peripheral device 124, or the subsystem 126), the sensor 132, or the motor driver 134.

[0044] The LDO regulator 130 can receive and regulate a voltage output by the DC-DC converter 110, and can provide the resulting one or more regulated voltages to the SOC 116 (e.g., to one or both of the I / O device 122 or the peripheral device 124) and, in one or more embodiments, to a driver of the additional DC-DC converter 128.

[0045] In one or more embodiments, control logic 114 can communicate with SOC 116 through an interface (not shown) and can control DC-DC converter 110 to scale up or scale down a voltage output by DC-DC converter 110 based on instructions received from SOC 116. In one or more embodiments, memory 112 includes a one-time programmable (OTP) memory that can provide preset limits for voltage ranges and other parameters to be used by various devices or subsystems of automotive system 100. In one or more embodiments, the preset limits of the OTP memory of memory 112 can be stored by a manufacturer of PMIC 102 or by a manufacturer of a vehicle in which system 100 is disposed.

[0046] Each of processor cores 118 of SOC 116 can include at least one central processing unit (CPU) and a local cache. In one or more embodiments, memory 120 can be a system memory of SOC 116 connected to one or more of processor cores 118, I / O devices 122, peripheral devices 124, or subsystems 126 via one or more interconnects or communication buses (not shown). Memory 120 can include computer-readable instructions for an operating system executable by processor cores 118 and other software associated with tasks performed by SOC 116.

[0047] As a non-limiting example, I / O devices 122 can include I / O devices for applications provided by SOC 116, such as a display, a touchscreen input device, and one or more network ports. As a non-limiting example, peripheral devices 124 can include circuitry configured to perform flash memory management, power management, interconnect management, and physical layer tasks (e.g., universal serial bus (USB) functionality).

[0048] As a non-limiting example, sensors 132 can include one or more airflow sensors, pressure sensors, temperature sensors, fuel sensors, speed sensors, voltage sensors, or proximity sensors. Motor drivers 134 can be configured to drive one or more electric motors configured to convert electrical power to torque in order to turn wheels of a vehicle including system 100. Sensors 132 and motor drivers 134 can receive electrical power from one or more of DC-DC converters 128.

[0049] Figure 2 A voltage regulator 200 is shown that includes an error amplifier 240 and aging mitigation circuitry configured and arranged to prevent or mitigate aging of error amplifier 240. In one or more embodiments, voltage regulator 200 can correspond to or can be implemented asFigure 1 Voltage regulator 106.

[0050] As shown in the figure, the voltage regulator 200 may include an aging mitigation circuit system 201, a boost converter circuit system 202, a voltage divider 216, an error amplifier 240, an integrator circuit system 244, and a pulse width modulation (PWM) circuit system 252. The boost converter circuit system 202 may draw power from the battery (e.g., at node 212). Figure 1 The battery 104 receives a battery voltage VBAT, can receive a PWM signal (e.g., sometimes referred to as a "modulated signal") output by the PWM circuit system 252, and can output an output voltage VBST at node 214. A voltage divider 216 may be coupled between node 214 and a ground or reference node, and may include coupling to the aging mitigation circuit system 201 and selectively coupled to an intermediate node of the error amplifier 240 via the aging mitigation circuit system 201. The aging mitigation circuit system may be coupled between the voltage divider 216 and the input of the error amplifier 240. The error amplifier 240 may be coupled between the aging mitigation circuit system 201 and the input of the PWM circuit system 252, can receive a first reference voltage VREF1 from a reference voltage source at a non-inverting input via node 242, and can be configured to output an error amplifier signal EA. An integrator circuit system 244 may be coupled along the signal path between the output of the error amplifier 240 and the input of the PWM circuit system 252.

[0051] The boost converter circuit system 202 may include an inductor 204, a diode 206, a capacitor 208, and a transistor 210. The inductor 204 may include a first terminal coupled to node 212 and a second terminal coupled to the input terminal of the diode 206 and the drain terminal of the transistor 210, at which the battery voltage VBAT (e.g., from...) can be provided. Figure 1 (Battery 104). Diode 206 may include an input terminal coupled to a second end of inductor 204 and to the drain terminal of transistor 210, and may include a first end coupled to a first end of capacitor 208 and to the output terminal of node 214, at which an output voltage VBST is provided. Capacitor 208 may include a first end coupled to node 214 and to the output terminal of diode 206, and may include a second end coupled to ground or a reference node. Transistor 210 may include a drain terminal coupled to the second end of inductor 204 and to the input terminal of diode 206, a source terminal coupled to ground or a reference node, and a gate terminal coupled to the output of PWM circuit system 252.

[0052] The PWM signal output by the PWM circuitry 252 can control the passage of current through the transistor 210 to boost or otherwise control the output voltage VBST. In one or more embodiments, in a "normal operation" mode of the voltage regulator 200, the output voltage VBST can equal or approximately equal the battery voltage VBAT minus the voltage drop across the diode 206 (e.g., about 0.6V to 0.7V). In a "voltage regulation" mode of the voltage regulator 200, the PWM 252 can be configured to control the transistor 210 to cause VBST to be limited to a target voltage level VTGT based on the output of the error amplifier 240.

[0053] The error amplifier 240 can be configured to generate an error amplifier signal EA, where a current of the error amplifier signal EA is determined based on a voltage difference across the inverting input and the non-inverting input of the error amplifier 240. In one or more embodiments, the error amplifier 240 is an operational transconductance amplifier (OTA) configured to output a current at its input terminals that is proportional to the voltage difference. The error amplifier signal EA can charge or discharge a capacitor of the integrator circuitry 244, and can be combined with the integrator circuitry 244 to control the PWM circuitry 252 via the signal path 245.

[0054] In one or more embodiments, the integrator circuitry 244 can include a capacitor 246 coupled between the signal path 245 and a ground or reference node, and can include a resistor 248 and a capacitor 250 coupled in series between the signal path 245 and the ground or reference node, where the resistor 248 and the capacitor 250 are coupled in parallel with the capacitor 246. It should be understood that this arrangement of the integrator circuitry 244 is intended to be illustrative and not limiting, such that other suitable integrator circuitry arrangements can be used in accordance with one or more other embodiments.

[0055] During a "normal operating state" of the voltage regulator 200, when the VBST is above the voltage threshold TH1, the aging mitigation circuitry 201 can be configured to cause the voltage difference between the inverting input and the non-inverting input of the error amplifier 240 to be at or about a predefined voltage level VOF (sometimes referred to as an "offset voltage level" VOF), which can be at or about the minimum voltage level required for the error amplifier 240 to generate an error amplifier signal EA having a certain current level (e.g., a negative current level) that disables the PWM circuitry 252 so that no boost occurs. In the normal operating state, the boost converter circuitry 202 generates the output voltage VBST at or about a voltage level that is VBAT minus the voltage drop across the diode 206. During a "voltage regulation state" of the voltage regulator 200, when the output voltage VBST drops below the voltage threshold TH1, the aging mitigation circuitry 201 can be configured to cause (e.g., by controlling the switches 234 and 236) the voltage difference across the inverting input and the non-inverting input of the error amplifier 240 to be at a voltage level of about VDIV1-VREF1, where VDIV1 is the voltage at the node 224 of the voltage divider 216 and is based on the output voltage VBST, and where VREF1 is the first reference voltage at the node 242. The voltage difference at the inputs of the error amplifier 240 in the voltage regulation mode causes the error amplifier 240 to generate an error amplifier signal EA having a current level that causes the PWM circuitry 252 to control the boost converter circuitry 202 to generate the output voltage VBST at or above a target voltage level VTGT, even when VBAT drops below VTGT. In one or more embodiments, the target voltage level VTGT can be about 6V as a non-limiting example. The control of the voltages supplied by the aging mitigation circuitry 201 at the inverting input and the non-inverting input of the error amplifier 240 is described in more detail below.

[0056] The voltage divider 216 can include resistors 218, 220, and 222 having respective resistance values R1, R2, and R3, and coupled in series between the node 214 and a ground or reference node. The node 224 is disposed at the connection point between the resistor 218 and the resistor 220. The voltage VDIV1 at the node 224 is nominally equal to VBST*(R2+R3) / (R1+R2+R3). The node 226 is disposed at the connection point between the resistor 220 and the resistor 222. The voltage VDIV2 at the node 226 is nominally equal to VBST*(R3) / (R1+R2+R3).

[0057] Aging mitigation circuitry 201 can include at least comparator 228, switches 234 and 236 (sometimes referred to herein as switch SW1 and switch SW2, respectively), and source 238. In one or more embodiments, aging mitigation circuitry 201 includes inverter 232. In one or more embodiments, aging mitigation circuitry 201 can correspond to or can be implemented as aging mitigation circuitry 108 of Figure 1 FIG. 1.

[0058] Comparator 228 includes an inverting input coupled to receive a second reference voltage VREF2 from a reference voltage source via node 230, and includes a non-inverting input coupled to receive voltage VDIV2 from node 226 of voltage divider 216. In one or more embodiments, first reference voltage VREF1 is equal to or approximately equal to second reference voltage VREF2. While voltage VDIV2 provided at the non-inverting input of comparator 228 is generated via the same voltage divider 216 used to generate voltage VDIV1 in this example, this is intended to be illustrative and not limiting. For example, in one or more other embodiments, VDIV1 and VDIV2 can be generated using two separate voltage dividers, each coupled to receive output voltage VBST from node 214.

[0059] The comparator 228 includes an output at which the comparator 228 is configured to provide an output voltage OVP. The output of the comparator 228 is coupled to respective control terminals of switches 234 and 236. A source 238 can be selectively coupled between the inverting and non-inverting inputs of the error amplifier 240 through the switch 234. For example, in response to VDIV2 being greater than VREF2 (corresponding to a normal operating state of the voltage regulator 200), the comparator 228 can be configured to produce the output voltage OVP at a voltage level sufficient to cause the switch 234 to close, thereby connecting the source 238 between the inverting and non-inverting inputs of the error amplifier 240, and sufficient to cause the switch 236 to open, thereby disconnecting the inverting input of the error amplifier 240 from the node 224 of the voltage divider 216. The inverter 232 can invert the output voltage OVP and provide the resulting inverted voltage to the control terminal of the switch SW2. In one or more embodiments, the output voltage OVP is a positive voltage (e.g., a logic low digital signal) in the normal operating state, and the inverter 232 reduces the output voltage OVP to a voltage level (e.g., a logic low digital signal) that is low enough to cause the switch 236 to open. In response to VDIV2 being less than VREF2 (corresponding to a voltage regulation state of the voltage regulator 200), the comparator 228 can be configured to produce the output voltage OVP at a voltage level sufficient to cause the switch 234 to open, thereby disconnecting the source 238 from the inverting input of the error amplifier 240, and sufficient to cause the switch 236 to close, thereby connecting the inverting input of the error amplifier 240 to the node 224 of the voltage divider 216.

[0060] By controlling the states of the switches 234 and 236 with the comparator 228 based on the output voltage VBST in this manner, the voltage VFB at the inverting input of the error amplifier 240 becomes dependent on the output voltage VBST. For example, in the voltage regulation state, the voltage VFB is equal to or approximately equal to VREF1, which occurs when VBST drops below the threshold voltage level due to a corresponding drop in the battery voltage VBAT. In the normal operating state, the voltage VFB is equal to or approximately equal to VREF1 + VOF, which occurs when VBST is above the threshold voltage level, where VOF is an offset voltage applied between the inputs of the error amplifier 240 by the source 238 when the switch 234 is closed. As a non-limiting example, the difference between VDIV1 during the voltage regulation state (when VBST is below the threshold) and VREF1 + VOF in the normal operating state (when VBST is above the threshold) can be relatively small, on the order of about 0.1 mV to about 0.9 mV. In contrast, conventional voltage regulators typically allow a voltage difference between the inputs of the error amplifier on the order of about 100 mV to about 1 V.

[0061] In this manner, the aging mitigation circuitry 201 can advantageously reduce the voltage differential VOF across the inputs of the error amplifier 240 during normal operating conditions, where the voltage regulator 200 remains for many applications, such as automotive applications, for a majority of its operational lifetime, thereby advantageously mitigating the effects of aging associated with the relatively higher voltage differentials typically applied in conventional approaches. Such aging mitigation can, for example, prevent or mitigate uncontrolled offset drifts (associated with a shift in DC accuracy of the voltage regulator) that can otherwise negatively impact the accuracy and robustness of the voltage regulator 200.

[0062] Figure 3 FIGS. 302, 304, and 306 show graphs illustrating various voltages and voltage thresholds of the voltage regulator 200 before, during, and after an example start-up event. Figure 2 Figure 2 Figure 3

[0063] As shown in graph 302, from time TO to time Tl and after time T4, the battery voltage VBAT and the output voltage VBST of the voltage regulator 200 are at respective nominal voltage levels (about 12 V and about 11.3 V, respectively, as non-limiting examples). Time Tl corresponds to an example start-up event of a vehicle system (e.g., a vehicle system including the voltage regulator 200) in which the battery voltage VBAT is initially at a relatively low voltage level (e.g., about 10 V) and then increases to a nominal voltage level (e.g., about 12 V) over a period of time (e.g., about 1 second). Figure 1 ​​​the initiation of a start event of the automotive system 100. From time Tl to time T2, the output voltage VBST begins to fall along with the battery voltage VBAT. At time T2, the output voltage VBST falls below the predetermined threshold voltage level THl, in response to which the voltage regulator 200 transitions from the normal operating state to the voltage regulation state. For example, as shown in the graph 306, at time T2, the output voltage OVP of the comparator 228 can fall by an amount sufficient to cause the switch 236 to close and the switch 234 to open. In one or more embodiments, this fall in the output voltage OVP can correspond to a change in OVP from a digital logic high level to a digital logic low level. While the voltage regulator 200 is in the voltage regulation state from time T2 to time T3, the error amplifier 240 regulates the output voltage VBST to remain at or above the target voltage level VTGT. As shown, THl is set to a voltage level greater than the voltage level of VTGT, such that the voltage regulator 200 transitions to the voltage regulation state before VBAT and VBST fall below VTGT. As shown in the graph 304, after the switch 236 closes and the switch 234 opens at time T2, the voltage FB provided at the inverting input of the error amplifier 240 experiences a relatively small voltage change AV as the voltage VFB transitions from (VREF1 + VOF) to VDIV1. Here, AV is equal to or approximately equal to (VREF1 + VOF) - VDIV1. In one or more embodiments, AV can be about 0.1 mV to about 0.9 mV, as a non-limiting example.

[0064] At time T3, VBST rises above the threshold THl, and the voltage regulator 200 enters the normal operating state. As shown in the graph 306, at time T3, the output voltage OVP increases back to the previous voltage level (e.g., the voltage level of OVP between TO and T2) sufficient to cause the switch 236 to open and the switch 234 to close. In one or more embodiments, this fall in the output voltage OVP can correspond to a change in OVP from a digital logic low level to a digital logic high level. At time T3, due to the change in state of the switches 234 and 236, the voltage FB at the inverting input of the error amplifier 240 transitions back to (VREF1 + VOF), such that the voltage drop across the inputs of the error amplifier 240 is at or about VOF. After time T3, the voltage levels of VBAT and VBST continue to rise until they reach the nominal levels associated with the normal operating state at time T4.

[0065] Controlling switches 234 and 236 by using the output voltage OVP limits the voltage across the input of error amplifier 240 during normal operation (before time T2 and after time T3), and allows error amplifier 240 to perform its intended voltage regulation function during voltage regulation (from time T2 to time T3). In this way, applying OVP to control switches 234 and 236 mitigates aging of error amplifier 240 without significantly affecting its voltage regulation function.

[0066] Figure 4 A voltage regulator (e.g.) is shown. Figure 1 Voltage regulator 106 or Figure 2 The aging mitigation circuit system (e.g., aging mitigation circuit system 108) of the voltage regulator 200 can be described by the illustrative process flow of its operation in normal operating state and voltage regulation state. (See reference...) Figure 2 The voltage regulator 200 is described in method 400, and for the sake of brevity, aspects of such components already described above are not necessarily repeated here. It should be understood that references to the components of the voltage regulator 200 are illustrative and not limiting, and other suitable circuit systems may be used, at least when method 400 is practiced in one or more other embodiments.

[0067] At block 402, in normal operation, the output voltage OVP from comparator 228 causes switch SW2 (i.e., switch 236) to open and switch SW1 (i.e., switch 234) to close. This connects source 238 between the inverting and non-inverting inputs of error amplifier 240, and source 238 is configured to limit the voltage between the inverting and non-inverting inputs to an offset voltage VOF. The offset voltage VOF can be set to the minimum offset voltage level (e.g., less than 10mV) required to compensate for the inherent offset of the error amplifier. For example, the offset voltage VOF can be set such that the inherent offset of the error amplifier minus VOF is negative, thereby forcing a negative current at the output of error amplifier 240, thus disabling PWM.

[0068] At block 404, if the voltage VDIV2 at the non-inverting input of comparator 228 is greater than the reference voltage VREF2 at the inverting input of comparator 228, then method 400 proceeds to block 402, where voltage regulator 200 is in normal operation and comparator 228 generates output voltage OVP at a voltage level sufficient to open switch SW2 and close switch SW1. Otherwise (i.e., if voltage DIV2 is less than the reference voltage VREF2), then method 400 proceeds to block 406, where voltage regulator 200 is in voltage regulation mode and comparator 228 generates output voltage OVP at a voltage level sufficient to close switch SW2 and open switch SW1.

[0069] At block 406, in the voltage regulation state, the output voltage OVP output by the comparator 228 causes the switch SW2 to close and the switch SWl to open. This causes the source 238 to disconnect between the inverting and non-inverting inputs of the error amplifier 240 and causes the voltage VDIVl to be connected to the inverting input of the error amplifier 240. The voltage VDIV2 is periodically checked at the comparator 228 for the reference voltage VREF2 (corresponding to a return to block 404).

[0070] Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method can be altered so that certain operations can be performed in an inverse order or so that certain operations can be performed, at least in part, concurrently with other operations. In one or more other embodiments, instructions or sub-operations of distinct operations can be implemented in an intermittent and / or alternating manner.

[0071] It should also be noted that at least some of the operations of the methods described herein can be implemented using software instructions stored on a computer usable storage medium for execution by a computer. As an example, an embodiment of a computer program product includes a computer-usable storage medium having computer-readable program code stored therein. The computer-usable or computer-readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device). Examples of a non-transitory computer-usable and computer-readable storage medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and an optical disk.

[0072] Alternatively, embodiments herein can be implemented entirely in hardware or in an implementation that includes both hardware and software elements. In embodiments using software, the software can include but is not limited to firmware, resident software, microcode, or other suitable software.

[0073] As used herein, the terms "circuit" and "circuitry," including the term "processing circuitry" and related terms, mean any suitable combination of analog or digital circuitry, hardware, firmware, software, and / or the like; including, but not limited to, one or more of application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, and / or microprocessors. It will be appreciated that the term "circuitry" encompasses both non- transitory and transitory memory devices, including, but not limited to, random access memory (RAM), read-only memory (ROM), and the like, which can be implemented using any suitable technology, such as SRAM, DRAM, or magnetic storage devices, as non-limiting examples. In accordance with these principles, it will be appreciated that a reference to a "processor" or "processing circuitry" can include a device in which a general purpose computing device includes or otherwise is coupled to memory that stores machine-readable instructions that are configured to cause the processing circuitry to perform the actions described. Such instructions can be stored as instructions of a human-readable high-level programming language that are interpreted or compiled to object code or machine language, as non-limiting examples, or they can be stored directly in a lower-level language such as object code or machine language or another suitable representation, as non-limiting examples.

[0074] It will be further appreciated that features such as processing circuitry, memory, and related circuitry and devices can be implemented by any suitable combination of one or more localized devices, including but not limited to distributed systems formed of multiple different devices in communication with each other via direct electrical communication, wireless communication, and via public or private communication networks including the Internet, unless otherwise explicitly stated. It will be further appreciated that processing circuitry and related devices can be implemented by one or more physical machines or by virtual machines, including but not limited to virtualized computing environments provided within "cloud" computing environments or other virtualization systems.

[0075] While at least one exemplary embodiment has been presented in the foregoing detailed description of specific embodiments, it should be appreciated that a multitude of modifications can be made. It should also be appreciated that the exemplary embodiments described herein are not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing one or more embodiments of the described application. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the claimed subject matter, which is defined by the appended claims including their equivalents.

Claims

1. A voltage regulator, characterized in that, include: An error amplifier having a first output, a first non-inverting input, and a first inverting input, wherein the error amplifier is configured to generate a signal based on a first voltage at the first non-inverting input and a second voltage at the first inverting input; as well as A circuit system coupled to the error amplifier and the output of the voltage regulator, wherein the circuit system is configured to: In the first mode, a voltage is applied between the first inverting input and the first non-inverting input of the error amplifier at a predefined voltage level; as well as In the second mode, the first inverting input of the error amplifier is coupled to a first reference voltage source and the first non-inverting input of the error amplifier is coupled to the output of the voltage regulator.

2. The voltage regulator according to claim 1, characterized in that, In addition, including: A boost converter circuit system having a second output and configured to generate an output voltage at the second output, wherein the output voltage of the boost converter circuit system is controlled based on the signal generated by the error amplifier.

3. The voltage regulator according to claim 2, characterized in that, The circuit system includes: A first switch is coupled between the first inverting input of the error amplifier and the first non-inverting input of the error amplifier. A second switch, the second switch being coupled to the first inverting input of the error amplifier; A comparator having a second inverting input, a second non-inverting input, and a third output, wherein the second inverting input is coupled to a second reference voltage source, the second non-inverting input is coupled to the output voltage of the boost converter circuit system, and the third output is coupled to corresponding control terminals of the first and second switches; and A source, which is selectively coupled via the first switch to at least one of the first inverting input or the first non-inverting input of the error amplifier, wherein the source is a current source or a voltage source.

4. The voltage regulator according to claim 3, characterized in that, The source is a voltage source, which includes a first terminal connected to the first non-inverting input of the error amplifier and a second terminal selectively coupled to the first inverting input via the first switch.

5. The voltage regulator according to claim 3 or 4, characterized in that, Additionally, at least one voltage divider is included, coupled to the second output of the boost converter circuit system, wherein the second non-inverting input of the comparator is coupled to the second output of the boost converter circuit system via a first node of the at least one voltage divider, and wherein the second switch selectively couples the first inverting input of the error amplifier to the boost converter circuit system via a second node of the at least one voltage divider.

6. The voltage regulator according to claim 5, characterized in that, The comparator is configured to: In the first mode, the first switch is closed and the second switch is opened; and In the second mode, the second switch is closed and the first switch is opened.

7. The voltage regulator according to claim 6, characterized in that, The circuit system further includes an inverter coupled between the third output of the comparator and the control terminal of the second switch.

8. The voltage regulator according to claim 7, characterized in that, In addition, including: A signal path, the signal path being coupled to the first output of the error amplifier; An integrator circuit system coupled along the signal path; as well as A pulse width modulation circuit system coupled between the signal path and the boost converter circuit system, wherein the pulse width modulation circuit system is configured to generate a modulated signal based on the signal output by the error amplifier and to provide the modulated signal to control the transistors of the boost converter circuit system.

9. A vehicle system, characterized in that, Includes the voltage regulator according to any of the preceding claims.

10. A method, characterized in that, include: The circuit system of the voltage regulator responds to the output voltage of the voltage regulator being higher than a threshold voltage level by applying the voltage difference between the first and second inputs of the error amplifier at a predefined voltage level; as well as The circuitry of the voltage regulator, in response to the output voltage being lower than the threshold voltage level, couples the first input of the error amplifier to a reference voltage source and the second input of the error amplifier to the output of the voltage regulator.

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