Memory management method and apparatus for heterogeneous environment, electronic device, and medium

Abstract

The application relates to the chip technical field, in particular to a memory management method and device for a heterogeneous environment, electronic equipment and medium, the method comprises the following steps: creating a double address domain intelligent pointer based on a memory access request; completing target memory allocation and establishing a page table mapping in a target address space based on the address allocation field; if the data access length is greater than a corresponding preset threshold value, selecting a DMA transmission mechanism to access the target memory based on the page table mapping, the target virtual address and the target process number, otherwise, selecting a HAG transmission mechanism to access the target memory based on the page table mapping, the target virtual address and the target process number; if the target memory is GPU memory and the selected transmission mechanism is the HAG transmission mechanism, automatically triggering a target memory synchronization operation after the target memory is accessed, so as to guarantee data consistency. The application reduces the complexity of memory management in a heterogeneous environment, improves the safety and consistency of memory management, and improves the data transmission performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chips, and in particular to a memory management method and device for a heterogeneous environment, electronic equipment and medium. BACKGROUND

[0002] With the rapid development of artificial intelligence, high-performance computing and graphics processing technology, heterogeneous environment architecture is widely used in various computing tasks. In the heterogeneous environment architecture, the central processing unit (CPU) and the graphics processing unit (GPU) work together to fully exert their respective computing advantages. However, since the CPU and the GPU usually have independent memory systems and addressing spaces, the exchange of data between the CPU and the GPU becomes a key bottleneck affecting the overall performance of the system. In traditional heterogeneous environment memory management, the CPU and the GPU use different address spaces, which requires manual tracking and conversion of addresses, increasing the development complexity and the possibility of errors. In languages such as C / C++ that do not have memory safety guarantees, manual memory management can easily lead to buffer overflow, memory leakage and other problems, with poor security and poor data transmission performance. Therefore, how to reduce the complexity of memory management in a heterogeneous environment, improve the security of memory management and enhance the data transmission performance has become a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a memory management method and device for a heterogeneous environment, electronic equipment and medium, which reduces the complexity of memory management in a heterogeneous environment, improves the security and consistency of memory management, and enhances the data transmission performance.

[0004] According to a first aspect of the present application, a memory management method for a heterogeneous environment is provided, comprising:

[0005] Creating a dual address domain smart pointer based on a memory access request, the dual address domain smart pointer being a smart pointer with dual address domains that carries a system virtual address for CPU access and a device virtual address for GPU access, the dual address domain smart pointer including an address allocation field, a virtual address field and a process number field, the virtual address field being used to set a target virtual address, and the process number field being used to set a target process number;

[0006] Completing target memory allocation in a target address space based on the address allocation field and establishing a page table mapping, the target memory being GPU memory or CPU memory, and the page table mapping being used to set the mapping relationship between the virtual address and the physical address;

[0007] If the data access length is greater than a corresponding preset threshold, a DMA transmission mechanism is selected to access the target memory based on the page table mapping, the target virtual address and the target process number, otherwise, a HAG transmission mechanism is selected to access the target memory based on the page table mapping, the target virtual address and the target process number, the DMA transmission mechanism is an access mechanism for transmitting data between GPU memory and CPU memory using a GPU internal streaming DMA controller, and the HAG transmission mechanism is a mechanism for allowing the CPU to directly access the GPU memory through a PCIe interface;

[0008] If the target memory is GPU memory and the selected transmission mechanism is the HAG transmission mechanism, a target memory synchronization operation is automatically triggered after the target memory is accessed.

[0009] According to the second aspect of the present application, a memory management device for a heterogeneous environment is provided, comprising:

[0010] An intelligent pointer creation module is configured to create a dual address domain intelligent pointer based on a memory access request, the dual address domain intelligent pointer being a dual address domain intelligent pointer carrying a system virtual address for CPU access and a device virtual address for GPU access, the dual address domain intelligent pointer comprising an address allocation field, a virtual address field and a process number field, the virtual address field being configured to set a target virtual address, and the process number field being configured to set a target process number.

[0011] A target memory allocation module is configured to complete target memory allocation in a target address space and establish a page table mapping based on the address allocation field, the target memory being GPU memory or CPU memory, and the page table mapping being configured to set a mapping relationship between a virtual address and a physical address.

[0012] A target memory access module is configured to select a DMA transmission mechanism to access the target memory based on the page table mapping, the target virtual address and the target process number when a data access length is greater than a corresponding preset threshold, and select a HAG transmission mechanism to access the target memory based on the page table mapping, the target virtual address and the target process number when the data access length is not greater than the corresponding preset threshold, the DMA transmission mechanism being an access mechanism for transmitting data between GPU memory and CPU memory using a GPU internal streaming DMA controller, and the HAG transmission mechanism being a mechanism for allowing the CPU to directly access the GPU memory through a PCIe interface.

[0013] A target memory synchronization module is configured to automatically trigger a target memory synchronization operation after the target memory is accessed if the target memory is GPU memory and the selected transmission mechanism is the HAG transmission mechanism.

[0014] According to a third aspect of the present application, an electronic device is provided, comprising at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to perform the method according to the first aspect of the present application.

[0015] According to a fourth aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions for performing the method according to the first aspect of the present application.

[0016] Compared with the prior art, the present application has obvious advantages and beneficial effects. By means of the above technical solutions, the present application provides a memory management method, device, electronic device and medium for a heterogeneous environment, which can achieve considerable technical progress and practicability, and has wide industrial utilization value, and at least has the following beneficial effects:

[0017] The present application creates a double address domain intelligent pointer, which simultaneously maintains a pointer type of a CPU addressing space and a pointer type of a GPU addressing space, completes target memory allocation and establishes a page table mapping in a target address space based on an address allocation field in the double address domain intelligent pointer, selects a DMA transmission mechanism or a HAG transmission mechanism according to a data access length, accesses the target memory based on the page table mapping, a target virtual address and a target process number, and finally realizes target memory synchronization. The present application can automatically select an optimal data path under a unified abstraction, reduces the complexity of memory management in a heterogeneous environment, improves the security and consistency of memory management, and improves data transmission performance. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0019] Figure 1 A flowchart of the memory management method for a heterogeneous environment provided by the embodiment of the present application is provided.

[0020] Figure 2 A flowchart of the sub-step of step S3 provided by the embodiment of the present application is provided.

[0021] Figure 3 A schematic diagram of the memory management device for a heterogeneous environment provided by the embodiment of the present application is provided.

[0022] Figure 4 A schematic diagram of the electronic device provided by the embodiment of the present application is provided. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0024] Embodiment one,

[0025] Embodiment one provides a memory management method for a heterogeneous environment, as shown in the formula (I), comprising: Figure 1

[0026] Step S1, creating a dual address domain smart pointer based on a memory access request, the dual address domain smart pointer is a dual address domain smart pointer carrying a system virtual address for CPU access and a device virtual address for GPU access, the dual address domain smart pointer includes an address allocation field, a virtual address field and a process number field, the virtual address field is used to set a target virtual address, and the process number field is used to set a target process number.

[0027] Among them, the dual address domain smart pointer can be set as VmBox, and the VmBox can realize dual address domain smart pointer management through three fields, which are specifically set as inner field, xva field and Process_id field. The address allocation field is specifically the inner field, which encapsulates a Box of address allocator, can apply for T type memory on the device (Device) side or the host (Host) side, and both adopt address translation module (ATU) for page table mapping. The system side corresponds to CPU, and the device side corresponds to GPU. For CPU, CPU access can be performed through Rust Deref / DerefMut. In Rust, Deref and DerefMut are two important interfaces (traits) for realizing dereference coercion. For GPU operation, the corresponding xva address and chip hardware process number (xpid) can be obtained through xva() and xpid(). The virtual address field is specifically the xva field, which is used to store the corresponding GPU virtual address. GPU can access memory through the address. The process number field is specifically the Process_id field, which is used to identify the GPU process ID number, and ensure that the memory operation is executed in the correct context.

[0028] ​Step S2, target memory allocation is completed in a target address space based on the address allocation field, and a page table mapping is established, the target memory being GPU memory or CPU memory, and the page table mapping being used to set a mapping relationship between a virtual address and a physical address.

[0029] Step S3, if the data access length is greater than a corresponding preset threshold, a DMA (Direct Memory Access) transmission mechanism is selected to access the target memory based on the page table mapping, the target virtual address, and the target process number, otherwise, a HAG (Host Access Gateway) transmission mechanism is selected to access the target memory based on the page table mapping, the target virtual address, and the target process number, the DMA transmission mechanism being an access mechanism for transmitting data between GPU memory and CPU memory using a GPU internal streaming DMA controller, and the HAG transmission mechanism allowing CPU to directly access GPU memory through a PCIe interface.

[0030] It should be noted that the target process number is required only when the target memory is GPU memory. The target process number is not required when the target memory is CPU memory. The GPU is internally provided with a preset IP capable of directly reading and writing GPU memory, and the preset IP can directly read and write GPU memory to implement the HAG transmission mechanism.

[0031] Step S4, if the target memory is GPU memory and the selected transmission mechanism is the HAG transmission mechanism, a target memory synchronization operation is automatically triggered after the target memory is accessed.

[0032] It should be noted that when the target memory is CPU memory, no additional target memory synchronization operation is required. When the target memory is GPU memory, a target memory synchronization operation is required. Since the DMA transmission mechanism provides built-in memory synchronization guarantee, but the HAG transmission mechanism cannot determine when the write operation is completed after operation, which can easily cause memory consistency problems, therefore, only when the target memory is GPU memory and the selected transmission mechanism is the HAG transmission mechanism, a target memory synchronization operation is automatically triggered after the target memory is accessed to ensure correct data transmission.

[0033] It should be noted that after the step S4 is executed, the corresponding allocated memory resource can be automatically released.

[0034] As an example, the application defines a unified preset interface, supports multiple transmission scenarios, and adapts to different data transmission scenarios. In step S1, the memory access request can be obtained based on the preset interface, and the preset access interface includes a system side to device side access interface (sys_to_dev), a device side to system side access interface (dev_to_sys), and a device side to device side access interface (sys_to_sys). The system side corresponds to the CPU, and the device side corresponds to the GPU. If the memory access request is obtained based on the system side to device side access interface or the device side to device side access interface, the corresponding target memory is the GPU memory, and if the memory access request is obtained based on the device side to system side access interface, the corresponding target memory is the CPU memory. The data transmission direction corresponding to the memory access request corresponding to the system side to device side access interface is from the system side to the device side. The data transmission direction corresponding to the memory access request corresponding to the device side to system side access interface is from the device side to the system side. The data transmission direction corresponding to the memory access request corresponding to the device side to device side access interface is from the device side to the device side. By defining a unified preset interface, the heterogeneous programming model is simplified, and the user can operate the CPU memory and the GPU memory using a unified preset interface without worrying about the underlying address conversion and data transmission details.

[0035] It should be noted that the application selects different transmission mechanisms according to the data access length, and through benchmark testing of different transmission directions, it is found that for different directions, when the data length exceeds a certain value, the performance of the DMA transmission mechanism is higher, and otherwise, the performance of the HAG transmission mechanism is higher. As a preferred example, if the data transmission direction is from the system side to the device side, the preset threshold is set to 2MB, and if the data transmission direction is from the device side to the system side or from the device side to the device side, the preset threshold is set to 32KB. By setting the preset threshold in different cases, different transmission mechanisms are selected, and the data transmission performance in the memory access process is improved.

[0036] As an example, in step S3, if the data access length is greater than the corresponding preset threshold, the DMA transmission mechanism is selected to access the target memory based on the page table mapping, the target virtual address, and the target process number, as shown in Figure 2 As shown in the figure, it can specifically include:

[0037] Step S31, if the data access length is greater than the corresponding preset threshold, it is judged whether the access data meets the DMA transmission alignment requirement, if it meets, all the access data is determined as the first access data, otherwise, the part of the access data that meets the DMA transmission alignment requirement is determined as the first access data, and the part of the access data that does not meet the DMA transmission alignment requirement is determined as the second access data.

[0038] Step S32, based on the page table mapping, the target virtual address, and the target process number, select a DMA transfer mechanism to access the target memory for the first access data; and based on the page table mapping, the target virtual address, and the target process number, select a HAG transfer mechanism to access the target memory for the second access data.

[0039] It should be noted that through steps S31-S32, the data transmission can meet the data alignment requirement of DMA and improve the data transmission performance.

[0040] It should be noted that there are two ways for data copying in all directions in the present application, one is a DMA transfer mechanism, and the other is a HAG transfer mechanism. Unlike the DMA transfer mechanism, the HAG transfer mechanism may not be able to ensure that the data has landed on the target memory immediately after operation, and therefore a Flush operation is needed to ensure correct data transmission. At the same time, in order to automate the memory flush, the present application adopts a RAII style VmBoxGuard, which automatically calls hag_flush when the Guard object is destructed, to ensure the consistency of the memory after modification, without the need for the developer to manually call a synchronization function, making the use more simple and intuitive. As an example, the dual address domain smart pointer is set to VmBox, and in step S4, the target memory synchronization operation is automatically triggered after the target memory is accessed, including:

[0041] Step S41, using a VmBoxGuard to manage the Guard object of the temporary access permission of the target memory pointed to by the VmBox.

[0042] Step S42, calling a mut_guard function to create a Guard object to obtain variable access permission to the target memory managed by the VmBox, allowing modification operations on the target memory.

[0043] Step S43, obtaining the Guard object in the target memory for modification.

[0044] Step S44, modifying the target memory based on the modified Guard object.

[0045] Step S45, automatically calling hag_flush to synchronize the GPU memory state.

[0046] It should be noted that in order to further ensure the synchronization of the cache states of the CPU and GPU memories, a manual synchronization path can also be set to realize the synchronization of the cache states of the CPU and GPU memories by directly calling hag_flush.

[0047] To avoid reference invalidation during memory access operations, prevent unsafe memory operations at compile time, the application ensures that only types that meet safety conditions can perform data transfer operations through a special marker feature. As an example, the method further includes:

[0048] Step S10, determine whether the data type of the memory access has a static lifetime. If so, mark the memory access request with a safe access identifier and execute the memory access flow of the method. Otherwise, do not mark the memory access request with a safe access identifier and do not execute the memory access flow of the method.

[0049] As an example, step S10 can be implemented using Rust's type system and ownership model to detect and prevent memory errors such as dangling pointers, memory leaks, etc. at compile time.

[0050] It should be noted that some example embodiments are described as processes or methods depicted as flow diagrams. Although each step of the flow diagrams is depicted as occurring sequentially, many of the steps can occur concurrently, in parallel, or simultaneously. In addition, the order of the steps can be re-arranged. A process can be terminated when its operations are completed, but can also have additional steps not included in the figure. A process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0051] Embodiment two,

[0052] Embodiment two provides a memory management device for a heterogeneous environment, as shown in Figure 3 comprising:

[0053] An intelligent pointer creation module is configured to create a dual address domain intelligent pointer based on a memory access request. The dual address domain intelligent pointer is a dual address domain intelligent pointer that carries both a system virtual address for CPU access and a device virtual address for GPU access. The dual address domain intelligent pointer includes an address allocation field, a virtual address field, and a process number field. The virtual address field is used to set a target virtual address, and the process number field is used to set a target process number.

[0054] The double address domain smart pointer can be specifically set as a VmBox, and the VmBox can specifically implement double address domain smart pointer management through three fields, which are specifically set as an inner field, an xva field and a Process_id field. The address allocation field is specifically the inner field, which internally encapsulates a Box of an address allocator, and can apply for T type memory on the device side or the host side, and both adopt an address translation module (ATU) for page table mapping. The system side corresponds to a CPU, and the device side corresponds to a GPU. For the CPU, CPU access can be performed through Rust Deref / DerefMut, and in Rust, Deref and DerefMut are two important interfaces (traits) for implementing dereference conversion. For GPU operation, the corresponding xva address and chip hardware process number (xpid) can be obtained through xva() and xpid(). The virtual address field is specifically the xva field, which is used to store the corresponding GPU virtual address. The GPU can access the memory through the address. The process number field is specifically the Process_id field, which is used to identify the GPU process ID number, and ensures that the memory operation is performed in the correct context.

[0055] A target memory allocation module is configured to complete target memory allocation in a target address space based on the address allocation field and establish page table mapping, the target memory is GPU memory or CPU memory, and the page table mapping is used to set the mapping relationship between the virtual address and the physical address.

[0056] A target memory access module is configured to select a DMA transmission mechanism to access the target memory based on the page table mapping, the target virtual address and the target process number when the data access length is greater than a corresponding preset threshold, and select a HAG transmission mechanism to access the target memory based on the page table mapping, the target virtual address and the target process number when the data access length is not greater than the corresponding preset threshold, the DMA transmission mechanism is an access mechanism for transmitting data between the GPU memory and the CPU memory using the internal streaming DMA controller of the GPU, and the HAG transmission mechanism is a mechanism allowing the CPU to directly access the GPU memory through the PCIe interface.

[0057] It should be noted that the target process number is required only when the target memory is GPU memory. The target process number is not required when the target memory is CPU memory. The GPU is internally provided with a preset IP capable of directly reading and writing the GPU memory, and the preset IP can directly read and write the GPU memory, thereby implementing the HAG transmission mechanism.

[0058] a target memory synchronization module, configured to automatically trigger a target memory synchronization operation after the target memory is accessed if the target memory is GPU memory and the selected transfer mechanism is the HAG transfer mechanism.

[0059] It should be noted that when the target memory is CPU memory, no additional target memory synchronization operation is required. When the target memory is GPU memory, a target memory synchronization operation is required. Since the DMA transfer mechanism provides built-in memory synchronization guarantee, but the HAG transfer mechanism cannot determine when the write operation is completed after operation, which can easily lead to memory consistency problems, therefore, only in the case where the target memory is GPU memory and the selected transfer mechanism is the HAG transfer mechanism, a target memory synchronization operation is required to be automatically triggered after the target memory is accessed to ensure correct data transmission.

[0060] It should be noted that the device can further include an internal resource release module, configured to automatically release the corresponding allocated memory resource after the target memory synchronization module is executed.

[0061] As an example, the present application defines a unified preset interface, supports multiple transfer scenarios, and adapts to different data transfer scenarios. The device further includes a preset access interface, the preset access interface includes a system side to device side access interface (sys_to_dev), a device side to system side access interface (dev_to_sys) and a device side to device side access interface (sys_to_sys), the system side corresponds to CPU, and the device side corresponds to GPU. The smart pointer creation module obtains the memory access request based on the preset interface. If the memory access request is obtained based on the system side to device side access interface or the device side to device side access interface, the corresponding target memory is GPU memory, and if the memory access request is obtained based on the device side to system side access interface, the corresponding target memory is CPU memory. The data transfer direction corresponding to the memory access request corresponding to the system side to device side access interface is from the system side to the device side. The data transfer direction corresponding to the memory access request corresponding to the device side to system side access interface is from the device side to the system side. The data transfer direction corresponding to the memory access request corresponding to the device side to device side access interface is from the device side to the device side. By defining a unified preset interface, the heterogeneous programming model is simplified, and users can use a unified preset interface to operate CPU memory and GPU memory without worrying about the details of the underlying address conversion and data transmission.

[0062] It should be noted that the application selects different transmission mechanisms according to the data access length, and through benchmark tests in different transmission directions, it is found that for different directions, when the data length exceeds a certain value, the performance of the selected DMA transmission mechanism is higher, and vice versa, the performance of the selected HAG transmission mechanism is higher. As a preferred example, if the data transmission direction is from the system side to the device side, the preset threshold is set to 2MB, and if the data transmission direction is from the device side to the system side or from the device side to the device side, the preset threshold is set to 32KB. By setting the preset threshold in different cases, different transmission mechanisms are selected, and the data transmission performance in the memory access process is improved.

[0063] As an example, the target memory access module is specifically configured to: when the data access length meets the corresponding preset threshold, judge whether the accessed data meets the DMA transmission alignment requirement, if it meets, determine all the accessed data as the first access data, otherwise, determine the part of the accessed data that meets the DMA transmission alignment requirement as the first access data, and determine the part of the accessed data that does not meet the DMA transmission alignment requirement as the second access data. Based on the page table mapping, the target virtual address and the target process number, the DMA transmission mechanism is selected to access the target memory for the first access data; based on the page table mapping, the target virtual address and the target process number, the HAG transmission mechanism is selected to access the target memory for the second access data. The above specific processing makes the data transmission meet the data alignment requirement of DMA and improves the data transmission performance.

[0064] It should be noted that in the application, there are two ways for data copying in all directions, one is the DMA transmission mechanism, and the other is the HAG transmission mechanism. Unlike the DMA transmission mechanism, the HAG transmission mechanism may not be able to ensure that the data has fallen on the target memory immediately after operation, so the Flush operation is needed to ensure correct data transmission. At the same time, in order to automate the memory flush, the application adopts the RAII style VmBoxGuard, which automatically calls hag_flush when the Guard object is destructed, to ensure the consistency of the modified memory, without the need for the developer to manually call the synchronization function, which is more simple and intuitive in use. As an example, the double address domain smart pointer is set to VmBox, and the target memory synchronization module is specifically configured to execute: using the Guard object of the VmBoxGuard to manage the temporary access permission of the target memory pointed to by the VmBox. The mut_guard function is called to create the Guard object, and the variable access permission of the target memory managed by the VmBox is obtained, allowing the target memory to be modified. The Guard object is obtained in the target memory for modification. The target memory is modified based on the modified Guard object.

[0065] The hag_flush is automatically called to synchronize the GPU memory state.

[0066] It should be noted that, in order to further ensure the synchronization of the cache states of the CPU and GPU memories, a manual synchronization path can also be set to realize the synchronization of the cache states of the CPU and GPU memories by directly calling hag_flush.

[0067] In order to avoid reference invalidation in the memory access operation process, prevent unsafe memory operations at the time of compilation, and ensure that only types meeting safety conditions can perform data transmission operations through a special marker feature, as an example, the device further includes a safety setting module configured to judge whether a static life cycle exists for a data type of memory access, and if so, mark a safety access identifier for a memory access request, and apply the device to perform a memory access process, otherwise, do not mark a safety access identifier for the memory access request, and do not apply the device to perform the memory access process. As an example, the safety setting module can be implemented by a Rust type system and an ownership model, and can detect and prevent memory errors such as dangling pointers and memory leaks at the time of compilation.

[0068] Embodiment three,

[0069] Embodiment three provides an electronic device, such as Figure 4 As shown in the figure, comprising: at least one processor;And, the memory connected with the at least one processor;Wherein, the memory stores the instruction that the at least one processor executes, the instruction is set to be used for executing the method described in the embodiment of the application.

[0070] Embodiment four,

[0071] Embodiment four provides a computer readable storage medium, which stores computer executable instructions, and the computer instructions are used to execute the method described in the embodiment of the application.

[0072] The embodiment of the application creates a double address domain intelligent pointer, simultaneously maintains a pointer type of a CPU addressing space and a pointer type of a GPU addressing space, completes target memory allocation and establishes a page table mapping in a target address space based on an address allocation field in the double address domain intelligent pointer, selects a DMA transmission mechanism or a HAG transmission mechanism according to a data access length, accesses target memory based on the page table mapping, a target virtual address and a target process number, and finally realizes target memory synchronization. The embodiment of the application reduces the complexity of memory management in a heterogeneous environment, improves the safety and consistency of memory management, and improves data transmission performance.

[0073] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, as long as it does not deviate from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A memory management method for a heterogeneous environment, characterized by, The method comprises the steps of: creating a dual address domain smart pointer based on a memory access request, the dual address domain smart pointer being a dual address domain smart pointer carrying a system virtual address for CPU access and a device virtual address for GPU access, the dual address domain smart pointer comprising an address allocation field, a virtual address field and a process number field, the virtual address field being used to set a target virtual address, and the process number field being used to set a target process number; completing target memory allocation in a target address space based on the address allocation field and establishing a page table mapping, the target memory being GPU memory or CPU memory, and the page table mapping being used to set a mapping relationship between a virtual address and a physical address; if the data access length is greater than a corresponding preset threshold, selecting a DMA transmission mechanism based on the page table mapping, the target virtual address and the target process number to access the target memory, otherwise, selecting a HAG transmission mechanism based on the page table mapping, the target virtual address and the target process number to access the target memory, the DMA transmission mechanism being a data transmission mechanism using a GPU internal streaming DMA controller to transmit data between GPU memory and CPU memory, and the HAG transmission mechanism being a mechanism allowing the CPU to directly access the GPU memory through a PCIe interface; if the target memory is GPU memory and the selected transmission mechanism is the HAG transmission mechanism, automatically triggering a target memory synchronization operation after the target memory is accessed.

2. The method of claim 1, wherein: the GPU is provided with a preset IP capable of directly reading and writing the GPU memory, and the HAG transmission mechanism is realized by directly reading and writing the GPU memory through the preset IP.

3. The method of claim 1, further comprising: obtaining the memory access request based on a preset access interface, the preset access interface comprising a system side to device side access interface, a device side to system side access interface and a device side to device side access interface, the system side corresponding to the CPU, and the device side corresponding to the GPU; if the memory access request is obtained based on the system side to device side access interface or the device side to device side access interface, the corresponding target memory is GPU memory, and if the memory access request is obtained based on the device side to system side access interface, the corresponding target memory is CPU memory.

4. The method of claim 3, wherein: if the data transmission direction is from the system side to the device side, the preset threshold is set to 2MB, and if the data transmission direction is from the device side to the system side or from the device side to the device side, the preset threshold is set to 32KB.

5. The method of claim 1, wherein if the data access length is greater than a corresponding preset threshold, selecting a DMA transmission mechanism based on the page table mapping, the target virtual address and the target process number to access the target memory, comprises: ​ ​ If the data access length is greater than the corresponding preset threshold, it is determined whether the accessed data meets the DMA transmission alignment requirement. If yes, all the accessed data is determined as the first accessed data. Otherwise, the part of the accessed data meeting the DMA transmission alignment requirement is determined as the first accessed data, and the part of the accessed data not meeting the DMA transmission alignment requirement is determined as the second accessed data. The first accessed data is accessed to the target memory based on the page table mapping, the target virtual address, and the target process number by using a DMA transmission mechanism. The second accessed data is accessed to the target memory based on the page table mapping, the target virtual address, and the target process number by using a HAG transmission mechanism.

6. The method of claim 1, wherein the dual address domain smart pointer is set as VmBox, and the automatically triggering the target memory synchronization operation after the target memory is accessed comprises: using a Guard object of the VmBoxGuard to manage the temporary access permission of the target memory pointed by the VmBox; calling a mut_guard function to create the Guard object, obtaining the variable access permission of the target memory managed by the VmBox, and allowing the modification operation on the target memory; obtaining the Guard object in the target memory for modification; modifying the target memory based on the modified Guard object; automatically calling a hag_flush to synchronize the GPU memory state.

7. The method of claim 1, wherein the method further comprises: determining whether the data type of the memory access has a static life cycle, if yes, marking a safe access identifier for the memory access request, and executing the memory access process of the method, otherwise, not marking the safe access identifier for the memory access request, and not executing the memory access process of the method. comprising: a smart pointer creation module configured to create a dual address domain smart pointer based on a memory access request, the dual address domain smart pointer being a smart pointer with dual address domains carrying a system virtual address for CPU access and a device virtual address for GPU access, the dual address domain smart pointer comprising an address allocation field, a virtual address field, and a process number field, the virtual address field being configured to set a target virtual address, and the process number field being configured to set a target process number; 8. A memory management apparatus for a heterogeneous environment, comprising: a target memory allocation module configured to complete target memory allocation in a target address space based on the address allocation field and establish a page table mapping, the target memory being a GPU memory or a CPU memory, and the page table mapping being configured to set a mapping relationship between a virtual address and a physical address; ​ ​ The target memory access module is configured to: access the target memory based on a page table mapping, a target virtual address and a target process number by using a DMA transmission mechanism when a data access length is greater than a preset threshold; and access the target memory based on the page table mapping, the target virtual address and the target process number by using a HAG transmission mechanism when the data access length is not greater than the preset threshold, wherein the DMA transmission mechanism is a transmission mechanism for transmitting data between GPU memory and CPU memory by using a GPU internal streaming DMA controller, and the HAG transmission mechanism is a mechanism for allowing a CPU to directly access GPU memory through a PCIe interface. The target memory synchronization module is configured to automatically trigger a target memory synchronization operation after the target memory is accessed if the target memory is GPU memory and the selected transmission mechanism is the HAG transmission mechanism.

9. The apparatus of claim 8, wherein The target memory access module is specifically configured to: determine whether the accessed data meets DMA transmission alignment requirements when the data access length is greater than the preset threshold, and determine all of the accessed data as first access data if the accessed data meets the DMA transmission alignment requirements, or determine a part of the accessed data that meets the DMA transmission alignment requirements as the first access data and determine a part of the accessed data that does not meet the DMA transmission alignment requirements as second access data; access the target memory for the first access data based on the page table mapping, the target virtual address and the target process number by using the DMA transmission mechanism; and access the target memory for the second access data based on the page table mapping, the target virtual address and the target process number by using the HAG transmission mechanism.

10. The apparatus of claim 8, wherein The apparatus further comprises a preset access interface, wherein the preset access interface comprises a system-side-to-device-side access interface, a device-side-to-system-side access interface and a device-side-to-device-side access interface, the system side corresponds to a CPU, the device side corresponds to a GPU, and the memory access request is obtained based on the preset access interface; if the memory access request is obtained based on the system-side-to-device-side access interface or the device-side-to-device-side access interface, the corresponding target memory is GPU memory, and if the memory access request is obtained based on the device-side-to-system-side access interface, the corresponding target memory is CPU memory. The apparatus comprises: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method of any one of claims 1-7.

11. An electronic device, comprising: The computer executable instructions are stored in the memory and are configured to execute the method of any one of claims 1-7. The computer executable instructions are stored in the memory and are configured to execute the method of any one of claims 1-7. ​ ​ 12. A computer-readable storage medium, characterized in that, ​

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