Display panel, display method thereof and display device

Abstract

The invention relates to a display panel, a display method thereof and a display device.In the display panel, a scanning signal line comprises a first sub-scanning signal line segment which is located in a first sub-display area and electrically connected with a first gate drive circuit and a second sub-scanning signal line segment which is located in a second sub-display area and electrically connected with a second gate drive circuit; the control unit is located between the first sub-scanning signal line segment and the second sub-scanning signal line segment of the same scanning signal line; the control unit comprises a first control transistor and a second control transistor; the first control transistor and the second control transistor are connected in series between the first sub-scanning signal line segment and the second sub-scanning signal line segment; the first control signal line is electrically connected with at least one of the first driving chip and the second driving chip and the first control transistor; the second control signal line is electrically connected with at least the other one of the first driving chip and the second driving chip and the second control transistor. The quality of split-screen display can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, display method, and display device thereof. Background Technology

[0002] With the continuous development of display technology, liquid crystal display (LCD), organic light-emitting diode (OLED), mini light-emitting diode (Mini LED) and micro light-emitting diode (MicroLED) displays have been gradually applied to the display screens of electronic devices such as mobile phones, laptops, and televisions.

[0003] However, the relevant technologies suffer from a problem where only part of the screen is displayed or part of the driver chip is damaged, resulting in a decline in display quality. This is a problem that urgently needs to be solved. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and its display method and display device, which aims to solve the problem of decreased display quality when only part of the screen is displayed or part of the driver chip is damaged in the related technology.

[0005] In a first aspect, embodiments of this application provide a display panel, including a display area and a non-display area at least partially surrounding the display area. The non-display area includes a first sub-non-display area and a second sub-non-display area located on both sides of the display area. The display area includes a first sub-display area adjacent to the first sub-non-display area and a second sub-display area adjacent to the second sub-non-display area. The first sub-display area and the second sub-display area are adjacent to each other. The display panel includes:

[0006] The first gate driving circuit and the second gate driving circuit are located in the first sub-non-display area and the second sub-non-display area, respectively.

[0007] Multiple scan signal lines, the scan signal lines including a first sub-scan signal line segment located in the first sub-display area and electrically connected to the first gate driving circuit, and a second sub-scan signal line segment located in the second sub-display area and electrically connected to the second gate driving circuit;

[0008] The first binding part and the second binding part are located in the non-display area;

[0009] The first driver chip and the second driver chip are electrically connected to the first bonding part and the second bonding part, respectively.

[0010] Multiple control units are respectively located between the first sub-scan signal segment and the second sub-scan signal segment of the same scan signal line;

[0011] First control signal line and second control signal line;

[0012] The control unit includes a first control transistor and a second control transistor, which are connected in series between the first sub-scan signal segment and the second sub-scan signal segment.

[0013] The first control signal line is electrically connected to at least one of the first driving chip and the second driving chip, as well as the gate of the first control transistor;

[0014] The second control signal line is electrically connected to at least one of the first driver chip and the second driver chip, as well as the gate of the second control transistor.

[0015] Secondly, based on the same concept, this application also provides a display method for a display panel, applied to the display panel described in the first aspect, the display method comprising:

[0016] When both the first sub-display area and the second sub-display area display images, both the first control transistor and the second control transistor are turned on, and the first sub-scan signal segment and the second scan signal segment in the same scan signal line are turned on;

[0017] The control unit is turned off only when the first sub-display area displays an image;

[0018] The control unit is turned off only when the second sub-display area displays an image.

[0019] Thirdly, based on the same concept, embodiments of this application also provide a display device, which includes the display panel provided in the first aspect.

[0020] In this embodiment, the first gate driving circuit and the second gate driving circuit are located in the first sub-display area and the second sub-display area, respectively; the scan signal line includes a first sub-scan signal line segment located in the first sub-display area and electrically connected to the first gate driving circuit, and a second sub-scan signal line segment located in the second sub-display area and electrically connected to the second gate driving circuit; a first bonding portion and a second bonding portion are located in the non-display area; a first driving chip and a second driving chip are electrically connected to the first bonding portion and the second bonding portion, respectively; a plurality of control units are located between the first sub-scan signal line segment and the second sub-scan signal line segment of the same scan signal line; a first control signal line and a second control signal line; wherein, the control unit includes a first control transistor and a second control transistor, the first control transistor and the second control transistor being connected in series between the first sub-scan signal line segment and the second sub-scan signal line segment; the first control signal line is electrically connected to at least one of the first driving chip and the second driving chip, and the gate of the first control transistor; the second control signal line is electrically connected to at least another of the first driving chip and the second driving chip, and the gate of the second control transistor. Firstly, the first and second sub-scan signal segments are electrically connected or electrically isolated through the control unit, eliminating the problem of tip discharge on electrodes or traces and preventing electrostatic damage to the first and second sub-scan signal segments. Secondly, during full-screen display, the first and corresponding second sub-scan signal segments are electrically connected through the control unit, preventing signal differences between them and improving the display uniformity of the first and second sub-display areas. Thirdly, when either the first or second driver chip fails, or when either the first or second sub-display area fails, and only one sub-display area is displayed (either the first or second sub-display area is displayed), the undisplayed sub-display area and its corresponding driver chip are completely shut down (no signal transmission), without affecting the normally displayed sub-display area. This improves the image quality of the normally displayed sub-display area and reduces the power consumption of the display panel. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A display panel with split-screen display function is provided in the related technology of the embodiments of this application.

[0023] Figure 2 This is a schematic diagram of a first type of display panel provided in an embodiment of this application.

[0024] Figure 3 This is a schematic diagram of a second type of display panel provided in an embodiment of this application.

[0025] Figure 4 This is a schematic diagram of a third type of display panel provided in an embodiment of this application.

[0026] Figure 5 This is a schematic diagram of a fourth type of display panel provided in an embodiment of this application.

[0027] Figure 6 This is a schematic diagram of a film layer structure in a display panel provided in an embodiment of this application.

[0028] Figure 7 This is a schematic diagram illustrating a first configuration of a first control transistor and a second control transistor in a display panel, as provided in an embodiment of this application.

[0029] Figure 8 This is a schematic diagram illustrating a second configuration of a first control transistor and a second control transistor in a display panel, as provided in an embodiment of this application.

[0030] Figure 9 This is a schematic diagram of a display device provided in an embodiment of this application.

[0031] Reference numerals: Display device 200; Display panel 100; Display area AA; Non-display area BB; First sub-non-display area BB1; Third sub-non-display area BB3; Second sub-non-display area BB2; Fourth sub-non-display area BB4; First sub-display area AA1; Second sub-display area AA2; First gate drive circuit Go1; Second gate drive circuit Go2; Scan signal line Sca1; First bonding part Bo1; Second bonding part Bo2; First driver chip Ci1; Second driver chip Ci2; Control unit k1; First control signal line kx1; Second control signal line kx2; First sub-scan signal line segment Sca1 1; Second sub-scan signal segment Sca12; First control transistor T1; Second control transistor T2; First dashed line 101; First connecting line L1; Second connecting line L2; Third connecting line L3; First resistor R1; Fourth connecting line L4; Second resistor R2; First direction X; Second direction Y; First sub-segment Sca01; Extension kx01; Substrate 11; Light-shielding metal layer 12; First insulating layer 13; Semiconductor layer 14; Gate insulating layer 15; First metal layer 16; Second insulating layer 17; Second metal layer 18; Active part 141; Gate 161; Source 181; Drain 182; Light-shielding part 121. Detailed Implementation

[0032] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0035] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0036] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0037] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0038] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0039] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0040] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0041] As described in the background section, with the development of display technology and the expansion of display panel application scenarios, the demand for split-screen or zoned display is increasing. For example, display panels used in vehicles need to have split-screen display functionality for the driver and passenger, and display panels used in gyms need to have split-screen display functionality for different exercisers. However, related technologies suffer from the problem of degraded display quality when only part of the screen is displayed or when part of the driver chip is damaged. Please refer to... Figure 1 , Figure 1A display panel with split-screen display function provided in the related technology of this application embodiment includes a non-display area BB comprising a first sub-non-display area BB1 and a second sub-non-display area BB2 located on both sides of the display area AA. The display area AA includes a first sub-display area AA1 adjacent to the first sub-non-display area BB1 and a second sub-display area AA2 adjacent to the second sub-non-display area BB2. The first sub-display area AA1 and the second sub-display area AA2 are adjacent. A first gate driving circuit Go1 and a second gate driving circuit Go2 are located in the first sub-non-display area BB1 and the second sub-non-display area BB2, respectively. A scan signal line Sca1 includes a line located in the first sub-display area AA1 and electrically connected to the first sub-non-display area BB2. A first sub-scan signal line segment Sca11 of a gate driving circuit Go1, and a second sub-scan signal line segment Sca12 located in the second sub-display area AA2 and electrically connected to the second gate driving circuit Go2; a first driving chip Ci1 drives the first sub-display area AA1 to display (driving the first gate driving circuit Go1 and the first sub-scan signal line segment Sca11, etc.), and a second driving chip Ci2 drives the second sub-display area AA2 to display (driving the second gate driving circuit Go2 and the second sub-scan signal line segment Sca12, etc.), and the first sub-scan signal line segment Sca11 and the second sub-scan signal line segment Sca12 in the same scan signal line Sca1 are disconnected. The related technology suffers from a decline in display quality when only part of the screen is displayed or when part of the driver chip is damaged. Specifically, this includes: 1) the presence of tip discharge at the break point between the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12, which can easily cause electrostatic discharge damage to both segments; 2) during full-screen display, signal differences can easily exist between the first sub-scan signal segment Sca11 and the corresponding second sub-scan signal segment Sca12, leading to a decrease in display quality in the first sub-display area A. 3) When one of the first driver chip Ci1 and the second driver chip Ci2 is damaged, or when one of the first sub-display area AA1 and the second sub-display area AA2 is damaged, only one sub-display area is displayed (one of the first sub-display area AA1 and the second sub-display area AA2 is displayed). The undisplayed sub-display area and / or the corresponding driver chip Ci2 cannot be completely turned off, which will continue to affect the normally displayed sub-display area, resulting in a decrease in the display quality of the normally displayed sub-display area and an increase in the power consumption of the display panel.

[0042] Based on the aforementioned technical problems, the inventors discovered that the first gate driving circuit and the second gate driving circuit are respectively located in the first sub-display area and the second sub-display area; the scan signal line includes a first sub-scan signal line segment located in the first sub-display area and electrically connected to the first gate driving circuit, and a second sub-scan signal line segment located in the second sub-display area and electrically connected to the second gate driving circuit; a first bonding portion and a second bonding portion are located in the non-display area; a first driving chip and a second driving chip are respectively electrically connected to the first bonding portion and the second bonding portion; multiple control units are respectively located between the first sub-scan signal line segment and the second sub-scan signal line segment of the same scan signal line; a first control signal line and a second control signal line; wherein, the control unit includes a first control transistor and a second control transistor, the first control transistor and the second control transistor being connected in series between the first sub-scan signal line segment and the second sub-scan signal line segment; the first control signal line is electrically connected to at least one of the first driving chip and the second driving chip, and the gate of the first control transistor; the second control signal line is electrically connected to at least the other of the first driving chip and the second driving chip, and the gate of the second control transistor. Firstly, the first and second sub-scan signal segments are electrically connected or electrically isolated through the control unit, eliminating the problem of tip discharge on electrodes or traces and preventing electrostatic damage to the first and second sub-scan signal segments. Secondly, during full-screen display, the first and corresponding second sub-scan signal segments are electrically connected through the control unit, preventing signal differences between them and improving the display uniformity of the first and second sub-display areas. Thirdly, when either the first or second driver chip fails, or when either the first or second sub-display area fails, and only one sub-display area is displayed (either the first or second sub-display area is displayed), the undisplayed sub-display area and its corresponding driver chip are completely shut down (no signal transmission), without affecting the normally displayed sub-display area. This improves the image quality of the normally displayed sub-display area and reduces the power consumption of the display panel.

[0043] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] Please see Figures 2 to 8 . Figure 2 This is a schematic diagram of a first type of display panel provided in an embodiment of this application. Figure 3 This is a schematic diagram of a second type of display panel provided in an embodiment of this application. Figure 4This is a schematic diagram of a third type of display panel provided in an embodiment of this application. Figure 5 This is a schematic diagram of a fourth type of display panel provided in an embodiment of this application.

[0045] Figure 6 This is a schematic diagram of a film layer structure in a display panel provided in an embodiment of this application. Figure 7 This is a schematic diagram illustrating a first configuration of a first control transistor and a second control transistor in a display panel, as provided in an embodiment of this application. Figure 8 This is a schematic diagram illustrating a second configuration of a first control transistor and a second control transistor in a display panel, as provided in an embodiment of this application. Figure 7 and Figure 8 A top-down view of the map layout.

[0046] This application provides a display panel 100, which includes a display area AA and a non-display area BB that at least partially surrounds the display area AA. The non-display area BB includes a first sub-non-display area BB1 and a second sub-non-display area BB2 located on both sides of the display area AA. The display area AA includes a first sub-display area AA1 adjacent to the first sub-non-display area BB1 and a second sub-display area AA2 adjacent to the second sub-non-display area BB2. The first sub-display area AA1 and the second sub-display area AA2 are adjacent to each other. The display panel 100 includes a first gate driving circuit Go1 and a second gate driving circuit Go2, multiple scan signal lines Sca1, a first bonding portion Bo1 and a second bonding portion Bo2, a first driving chip Ci1 and a second driving chip Ci2, multiple control units k1, a first control signal line kx1 and a second control signal line kx2. The first gate driving circuit Go1 and the second gate driving circuit Go2 are located in the first sub-non-display area BB1 and the second sub-non-display area BB2, respectively; the scan signal line Sca1 includes a first sub-scan signal line segment Sca11 located in the first sub-display area AA1 and electrically connected to the first gate driving circuit Go1, and a second sub-scan signal line segment Sca12 located in the second sub-display area AA2 and electrically connected to the second gate driving circuit Go2; the first binding part Bo1 and the second binding part Bo2 are located in the non-display area BB; the first driving chip Ci1 and the second driving chip Ci2 are electrically connected to the first binding part Bo1 and the second binding part Bo2, respectively; a plurality of control units k1 are located between the first sub-scan signal line segment Sca11 and the second sub-scan signal line segment Sca12 of the same scan signal line Sca1. The control unit k1 includes a first control transistor T1 and a second control transistor T2, which are connected in series between a first sub-scan signal line segment Sca11 and a second sub-scan signal line segment Sca12. A first control signal line kx1 is electrically connected to at least one of the first driving chip Ci1 and the second driving chip Ci2, and to the gate of the first control transistor T1. A second control signal line kx2 is electrically connected to at least another of the first driving chip Ci1 and the second driving chip Ci2, and to the gate of the second control transistor T2.

[0047] For example, such as Figures 2 to 5 As shown, the non-display area BB includes a first sub-non-display area BB1, a third sub-non-display area BB3, a second sub-non-display area BB2, and a fourth sub-non-display area BB4 connected in sequence.

[0048] For example, such as Figures 2 to 5 As shown, the display area AA includes a first sub-display area AA1 adjacent to the first sub-non-display area BB1, and a second sub-display area AA2 adjacent to the second sub-non-display area BB2. The first sub-display area AA1 and the second sub-display area AA2 are adjacent or connected. Figure 2The first dotted line 101 does not actually exist in the display panel 100. Figure 2 The first dashed line 101 in the middle distinguishes the position and relative position of the first sub-display area AA1 and the second sub-display area AA2.

[0049] For example, such as Figures 2 to 5 As shown, the first sub-non-display area BB1 and the second sub-non-display area BB2 are located on opposite sides of the display area AA, and the third sub-non-display area BB3 and the fourth sub-non-display area BB4 are located on opposite sides of the display area AA.

[0050] For example, such as Figures 2 to 5 As shown, in some embodiments, the non-display area BB includes a first sub-non-display area BB1, a third sub-non-display area BB3, a second sub-non-display area BB2, and a fourth sub-non-display area BB4 connected in sequence, and the non-display area BB surrounds the display area AA.

[0051] For example, in some other implementations, the non-display area BB includes portions of a first sub-non-display area BB1, a third sub-non-display area BB3, a second sub-non-display area BB2, and a fourth sub-non-display area BB4, with portions of the non-display area BB surrounding the display area AA.

[0052] For example, the first driver chip Ci1 and the second driver chip Ci2 are electrically connected to the first bonding portion Bo1 and the second bonding portion Bo2, respectively. In some embodiments, the first driver chip Ci1 and the second driver chip Ci2 are directly connected to the first bonding portion Bo1 and the second bonding portion Bo2, respectively. In other embodiments, the first driver chip Ci1 and the second driver chip Ci2 are electrically connected to the first bonding portion Bo1 and the second bonding portion Bo2 through corresponding circuit boards (flexible circuit boards, etc.).

[0053] For example, the first control signal line kx1 is electrically connected to at least one of the first driver chip Ci1 and the second driver chip Ci2, and the gate of the first control transistor T1; the second control signal line kx2 is electrically connected to at least another of the first driver chip Ci1 and the second driver chip Ci2, and the gate of the second control transistor T2. In some embodiments, such as Figure 2 As shown, the first control signal line kx1 is electrically connected to the gate of the first driving chip Ci1 and the first control transistor T1, and the first driving chip Ci1 can control the opening and closing of the first control transistor T1; the second control signal line kx2 is electrically connected to the gate of the second driving chip Ci2 and the second control transistor T2, and the second driving chip Ci2 can control the opening and closing of the second control transistor T2. This will be described in detail in subsequent embodiments. In other embodiments, such as... Figure 3As shown, the first control signal line kx1 is electrically connected to the gate of the second driving chip Ci2 and the first control transistor T1, and the second driving chip Ci2 can control the opening of the first control transistor T1; the second control signal line kx2 is electrically connected to the gate of the first driving chip Ci1 and the second control transistor T2, and the first driving chip Ci1 can control the opening of the second control transistor T2, which will be described in detail in subsequent embodiments. In some other embodiments, such as Figure 4 As shown, compared to Figure 3 For example, the first control signal line kx1 is also electrically connected to the gate of the first driver chip Ci1 and the first control transistor T1, and the first driver chip Ci1 can control the first control transistor T1 to turn off; the second control signal line kx2 is also electrically connected to the gate of the second driver chip Ci2 and the second control transistor T2, and the second driver chip Ci2 can control the second control transistor T2 to turn off, which will be described in detail in subsequent embodiments.

[0054] In this embodiment, the first gate driving circuit Go1 and the second gate driving circuit Go2 are located in the first sub-non-display area BB1 and the second sub-non-display area BB2, respectively; the scan signal line Sca1 includes a first sub-scan signal line segment Sca11 located in the first sub-display area AA1 and electrically connected to the first gate driving circuit Go1, and a second sub-scan signal line segment Sca12 located in the second sub-display area AA2 and electrically connected to the second gate driving circuit Go2; the first binding part Bo1 and the second binding part Bo2 are located in the non-display area BB; the first driving chip Ci1 and the second driving chip Ci2 are electrically connected to the first binding part Bo1 and the second binding part Bo2, respectively; and multiple control units k1 are located on the same scan signal line Sca1. Between the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12; a first control signal line kx1 and a second control signal line kx2; wherein, the control unit k1 includes a first control transistor T1 and a second control transistor T2, the first control transistor T1 and the second control transistor T2 being connected in series between the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12; the first control signal line kx1 is electrically connected to at least one of the first driving chip Ci1 and the second driving chip Ci2, and the gate of the first control transistor T1; the second control signal line kx2 is electrically connected to at least another of the first driving chip Ci1 and the second driving chip Ci2, and the gate of the second control transistor T2. In a first aspect, the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12 are electrically connected or electrically isolated by the control unit k1, eliminating the problem of tip discharge of electrodes or traces, and avoiding electrostatic damage to the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12. Secondly, during full-screen display, the first sub-scan signal segment Sca11 and the corresponding second sub-scan signal segment Sca12 can be electrically connected through the control unit k1, avoiding signal differences between them and improving the display uniformity of the first sub-display area AA1 and the second sub-display area AA2. Thirdly, when either the first driver chip Ci1 or the second driver chip Ci2 is damaged, or when either the first sub-display area AA1 or the second sub-display area AA2 is damaged, only one sub-display area is displayed (either the first sub-display area AA1 or the second sub-display area AA2 is displayed). The undisplayed sub-display area and its corresponding driver chip are completely shut down (no signal transmission), which does not affect the normally displayed sub-display area, improving the image quality of the normally displayed sub-display area and reducing the power consumption of the display panel 100.

[0055] In some implementations, such as Figure 2As shown, the first driving chip Ci1 can drive the first sub-display area AA1 to display an image, and the second driving chip Ci2 can drive the second sub-display area AA2 to display an image; the first control signal line kx1 is electrically connected to the gate of the first driving chip Ci1 and the first control transistor T1, and the first driving chip Ci1 can control the opening and closing of the first control transistor T1; the second control signal line kx2 is electrically connected to the gate of the second driving chip Ci2 and the second control transistor T2, and the second driving chip Ci2 can control the opening and closing of the second control transistor T2.

[0056] For example, such as Figure 2 As shown, when both the first sub-display area AA1 and the second sub-display area AA2 display images, both the first control transistor T1 and the second control transistor T2 are turned on, and the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12 in the same scan signal line Sca1 are conducted. When only the first sub-display area AA1 displays an image, the first driving chip Ci1 can control the first control transistor T1 to turn off, and / or the second driving chip Ci2 can control the second control transistor T2 to turn off, and the control unit k1 is turned off. When only the second sub-display area AA2 displays an image, the second driving chip Ci2 can control the second control transistor T2 to turn off, and / or the first driving chip Ci1 can control the first control transistor T1 to turn off, and the control unit k1 is turned off.

[0057] For example, such as Figure 2 As shown, when one of the first driver chip Ci1 and the second driver chip Ci2 is damaged, the other of the first driver chip Ci1 and the second driver chip Ci2 can control the control unit k1 to shut down. The sub-display area that is not displayed and the corresponding driver chip are completely shut down (no signal transmission), which will not affect the sub-display area that is displayed normally, improve the image quality of the sub-display area that is displayed normally, and also reduce the power consumption of the display panel 100.

[0058] In some implementations, such as Figure 3 As shown, the first driving chip Ci1 can drive the first sub-display area AA1 to display an image, and the second driving chip Ci2 can drive the second sub-display area AA2 to display an image; the first control signal line kx1 is electrically connected to the gate of the second driving chip Ci2 and the first control transistor T1, and the second driving chip Ci2 can control the first control transistor T1 to turn on; the second control signal line kx2 is electrically connected to the gate of the first driving chip Ci1 and the second control transistor T2, and the first driving chip Ci1 can control the second control transistor T2 to turn on.

[0059] For example, such as Figure 3As shown, when both the first sub-display area AA1 and the second sub-display area AA2 display images, both the first control transistor T1 and the second control transistor T2 are turned on, and the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12 in the same scan signal line Sca1 are conducted. When only the first sub-display area AA1 displays an image, the second driving chip Ci2 can control the first control transistor T1 to turn off, and / or the first driving chip Ci2 can control the second control transistor T2 to turn off, and the control unit k1 is turned off. When only the second sub-display area AA2 displays an image, the first driving chip Ci1 can control the second control transistor T2 to turn off, and / or the second driving chip Ci2 can control the first control transistor T1 to turn off, and the control unit k1 is turned off.

[0060] For example, such as Figure 3 As shown, in some embodiments, when one of the first driver chip Ci1 and the second driver chip Ci2 is damaged, since the damaged driver chip has no signal output, the control transistor controlled by the damaged driver chip can be directly turned off, thereby directly turning off the control unit k1.

[0061] For example, such as Figure 3 As shown, for example, when the first driver chip Ci1 is damaged, only the second sub-display area AA2 displays the image. Because the first driver chip Ci1 is damaged, it has no output signal to turn on the second control transistor T2, keeping it in a closed state. No additional signals or wiring are needed to control the control unit k1 to close, simplifying the control method for turning k1 on and off and reducing the cost of the driver chip. Simultaneously, the second driver chip Ci2 can output a DC signal to control the first control transistor T1 to open, and can also stop outputting a DC signal to control the first control transistor T1 to close. Similarly, the first driver chip Ci1 can output a DC signal to control the second control transistor T2 to open, and can also stop outputting a DC signal to control the second control transistor T2 to close. This simplifies the output signals in both the second and first driver chips Ci1, making the control method for turning k1 on and off simple and reducing the cost of the driver chip.

[0062] In some implementations, such as Figure 4 As shown, compared to Figure 3 For example, the first control signal line kx1 is also electrically connected to the gate of the first driver chip Ci1 and the first control transistor T1, and the first driver chip Ci1 can control the first control transistor T1 to turn off; the second control signal line kx2 is also electrically connected to the gate of the second driver chip Ci2 and the second control transistor T2, and the second driver chip Ci2 can control the second control transistor T2 to turn off.

[0063] For example, such as Figure 4 As shown, in Figure 3 Based on the example, the first control signal line kx1 is further configured to be electrically connected to the gate of the first driving chip Ci1 and the first control transistor T1, and the first driving chip Ci1 can control the first control transistor T1 to be turned off; the second control signal line kx2 is further configured to be electrically connected to the gate of the second driving chip Ci2 and the second control transistor T2, and the second driving chip Ci2 can control the second control transistor T2 to be turned off.

[0064] For example, such as Figure 4 As shown, in Figure 3 Based on the example, when one of the first driver chip Ci1 and the second driver chip Ci2 is damaged, since the damaged driver chip has no signal output, the control transistor controlled by the damaged driver chip can be directly turned off, causing the control unit k1 to be directly turned off. Furthermore, the undamaged driver chip controls its control transistor to be completely turned off. Since the undamaged driver chip outputs a signal to control its control transistor to be completely turned off, the control unit k1 is turned off more thoroughly, preventing leakage signals or small current transmission signals between the first sub-display area AA1 and the second sub-display area AA2.

[0065] For example, such as Figure 4 As shown, in Figure 3 Based on the example, for instance, when the first driver chip Ci1 is damaged, only the second sub-display area AA2 displays the image. Since the first driver chip Ci1 is damaged, it has no output signal to turn on the second control transistor T2, keeping it in the off state. There is no need to set up other signals or wiring to control the control unit k1 to turn off, making the control method of turning the control unit k1 on and off simple and reducing the cost of the driver chip. Furthermore, the second driver chip Ci2 outputs a signal to completely turn off the second control transistor T2, making the control unit k1 turn off more thoroughly, which can better prevent leakage signals or small current transmission signals between the first sub-display area AA1 and the second sub-display area AA2.

[0066] Simultaneously, the second driver chip Ci2 can output a DC signal to control the first control transistor T1 to turn on, and the second driver chip Ci2 can stop outputting a DC signal to control the first control transistor T1 to turn off. The first driver chip Ci1 can output another DC signal to control the second control transistor T2 to turn off completely. The first driver chip Ci1 can also output a DC signal to control the second control transistor T2 to turn on, and the first driver chip Ci1 can stop outputting a DC signal to control the second control transistor T2 to turn off, and the first driver chip Ci1 can output another DC signal to control the first control transistor T1 to turn off completely. This simplifies the output signals in the second driver chip Ci2 and the first driver chip Ci1, simplifies the control method for turning the control unit k1 on and off, and reduces the cost of the driver chips.

[0067] In some implementations, such as Figure 4 As shown, the display panel 100 also includes a first connecting line L1, a second connecting line L2, a third connecting line L3, a first resistor R1, a fourth connecting line L4, and a second resistor R2. The first connecting line L1 is electrically connected between the second driving chip Ci2 and the first control signal line kx1; the second connecting line L2 is electrically connected between the first driving chip Ci1 and the second control signal line kx2; the third connecting line L3 and the first resistor R1 are electrically connected between the first driving chip Ci1 and the first control signal line kx1; the fourth connecting line L4 and the second resistor R2 are electrically connected between the second driving chip Ci2 and the second control signal line kx2; wherein, the first connecting line L1 and the second connecting line L2 have a first potential signal, and the third connecting line L3 and the fourth connecting line L4 have a second potential signal; the first potential signal can turn on the first control transistor T1 and the second control transistor T2, and the second potential signal can turn off the first control transistor T1 and the second control transistor T2.

[0068] For example, such as Figure 4 As shown, the first connection line L1 and the second connection line L2 are connected to a first potential signal, and the third connection line L3 and the fourth connection line L4 are connected to a second potential signal. The first potential signal can turn on the first control transistor T1 and the second control transistor T2, and the second potential signal can turn off the first control transistor T1 and the second control transistor T2. The first potential signal and the second potential signal can be set according to the material type of the active part 141 in the first control transistor T1 and the second control transistor T2 and the characteristics of the thin-film transistor.

[0069] For example, by setting the first resistor R1, when the second driver chip Ci2 turns on the first control transistor T1 through the first connection line L1 and the first control signal line kx1, due to the voltage division of the first resistor R1 on the third connection line L3, the signal on the third connection line L3 cannot compete with the signal on the first connection line L1. The signal on the first connection line L1 plays a major control role, ensuring that the first control transistor T1 is turned on. That is, by setting the first resistor R1, the signal on the first connection line L1 plays a major control role when the first control transistor T1 is turned on, ensuring that the first control transistor T1 is turned on stably.

[0070] For example, by setting the second resistor R2, when the first driver chip Ci1 turns on the second control transistor T2 through the second connection line L2 and the second control signal line kx2, due to the voltage division of the second resistor R2 on the fourth connection line L4, the signal on the fourth connection line L4 cannot compete with the signal on the second connection line L2. The signal on the second connection line L2 plays a major control role, ensuring that the second control transistor T2 is turned on. That is, by setting the second resistor R2, the signal on the second connection line L2 plays a major control role when the second control transistor T2 is turned on, ensuring that the second control transistor T2 is turned on stably.

[0071] In some implementations, such as Figures 2 to 4 As shown, and in combination Figure 7 As shown, the scan signal line Sca1 extends along the first direction X, the first control signal line kx1 and the second control signal line kx2 both extend along the second direction Y, the first direction X intersects with the first direction X, the first sub-display area BB1 and the second sub-display area BB2 are located on both sides of the display area AA in the first direction X; the first control transistor T1 and the second control transistor T2 are located between the first sub-scan signal line segment Sca11 and the second sub-scan signal line segment Sca12 along the first direction X.

[0072] For example, such as Figures 2 to 4 As shown, and in combination Figure 7 As shown, the first direction X intersects the second direction Y, and the first direction X and the second direction Y can be perpendicular to each other.

[0073] For example, such as Figures 2 to 4 As shown, and in combination Figure 7 As shown, the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12 can extend along the same straight line, and the active portion 141 of the first control transistor T1 is perpendicular to the plane of the substrate 11. Figure 7Located on one side of the first control signal line kx1 in a direction perpendicular to the desktop or paper surface, the active part 141 of the second control transistor T2 is located on one side of the second control signal line kx2 in a direction perpendicular to the plane where the substrate 11 is located. The first control signal line kx1 directly acts as the gate of the first control transistor T1, and the second control signal line kx2 directly acts as the gate of the second control transistor T2. By making the first sub-scan signal line segment Sca11 and the second sub-scan signal line segment Sca12 extend on the same straight line, and by making the multiple sub-pixels controlled by the first sub-scan signal line segment Sca11 and the multiple sub-pixels controlled by the second sub-scan signal line segment Sca12 on the same straight line, the size of the control unit number k1 in the first direction X can be minimized to the greatest extent, so that the first sub-display area AA1 and the second sub-display area AA2 are adjacent or connected, thereby improving the display quality.

[0074] In some implementations, such as Figure 5 As shown, and in combination Figure 8 As shown, the scan signal line Sca1 extends along the first direction X, and the first control signal line kx1 and the second control signal line kx2 both extend along the second direction Y. The first direction X intersects with the first direction X. The first sub-display area BB1 and the second sub-display area BB2 are located on both sides of the display area AA in the first direction X. On the plane parallel to the display panel 100, the first sub-scan signal line segment Sca11 and the corresponding second sub-scan signal line segment Sca12 both include a first sub-segment Sca01 that is opposite to each other in the second direction Y. The first control transistor T1 and the second control transistor T2 are located in the second direction Y between the first sub-segment Sca01 of the first sub-scan signal line segment Sca11 and the first sub-segment Sca01 of the second sub-scan signal line segment Sca12.

[0075] For example, such as Figure 5 As shown, and in combination Figure 8 As shown, the first direction X intersects the second direction Y, and the first direction X and the second direction Y can be perpendicular to each other.

[0076] For example, such as Figure 5 As shown, and in combination Figure 8As shown, the first sub-scan signal line segment Sca11 and the second sub-scan signal line segment Sca12 can extend on different straight lines. The first control signal line kx1 has an extension kx01 as the gate of the first control transistor T1, and the second control signal line kx2 has an extension kx01 as the gate of the second control transistor T2. The active part 141 of the first control transistor T1 and the active part 141 of the second control transistor T2 are located between the first sub-scan signal line segment Sca11 and the corresponding second sub-scan signal line segment Sca12, which can minimize the layout space occupied by the control unit k1 in the first direction X (e.g., 0), thereby improving the display quality.

[0077] In some implementations, such as Figure 6 As shown, the display panel 100 includes a substrate 11, a light-shielding metal layer 12, a first insulating layer 13, a semiconductor layer 14, a gate insulating layer 15, a first metal layer 16, a second insulating layer 17, and a second metal layer 18. The light-shielding metal layer 12 is located on one side of the substrate 11; the first insulating layer 13 is located on the side of the light-shielding metal layer 12 away from the substrate 11; the semiconductor layer 14 is located on the side of the first insulating layer 13 away from the substrate 11; the gate insulating layer 15 is located on the side of the semiconductor layer 14 away from the substrate 11; the first metal layer 16 is located on the side of the gate insulating layer 15 away from the substrate 11; the second insulating layer 17 is located on the side of the first metal layer 16 away from the substrate 11; and the second metal layer 18 is located on the side of the second insulating layer 17 away from the substrate 11. The semiconductor layer 14... Layer 14 includes an active portion 141 of a thin-film transistor (e.g., a first control transistor T1 and a second control transistor T2), a first metal layer 16 includes a gate 161 of the thin-film transistor, a second metal layer 18 includes a source 181 and a drain 182 of the thin-film transistor, a light-shielding metal layer 12 includes a light-shielding portion 121, and the orthographic projection of the active portion 141 on the substrate 11 at least partially overlaps with the orthographic projection of the light-shielding portion 121 on the substrate 11. The light-shielding metal layer 12 also includes a first control signal line kx1 and a second control signal line kx2.

[0078] For example, the film structure of the display panel 100 is not limited to... Figure 6 As shown, for example, there may be other metal layers and insulating layers between the first metal layer 16 and the second metal layer 18, and the side of the second metal layer 18 away from the substrate 11 may also have other films and structures.

[0079] For example, the material of the semiconductor layer 14 can be low-temperature polycrystalline silicon. The light-shielding part 121 can block external light from entering the active part 141, or the light-shielding part 121 can block impurity ions (such as impurity ions in the substrate 11) from entering the active part 141, thereby improving the performance of the first thin film transistor. The function of the light-shielding part 121 is not limited to this.

[0080] For example, the light-shielding metal layer 12 also includes a first control signal line kx1 and a second control signal line kx2, which can make full use of the existing film layers of the display panel without adding additional processes and film layers, thus simplifying the manufacturing process and structure of the display panel 100. At the same time, the light-shielding metal layer 12 also includes the first control signal line kx1 and the second control signal line kx2, which can prevent the first control signal line kx1 and the second control signal line kx2 from interfering with the traces in other metal layers such as the first metal layer 16 and the second metal layer 18.

[0081] Secondly, based on the same concept, this application also provides a display method for a display panel. The display method can be applied to the display panel 100 described above. The display method includes: when both the first sub-display area AA1 and the second sub-display area AA2 display images, both the first control transistor T1 and the second control transistor T2 are turned on, and the first sub-scan signal segment Sca11 and the second sub-scan signal segment Sca12 in the same scan signal line Sca1 are turned on; when only the first sub-display area AA1 displays an image, the control unit k1 is turned off; when only the second sub-display area AA2 displays an image, the control unit k1 is turned off.

[0082] For example, for Figure 2 , Figure 3 and Figure 4 The display methods of the display panels in different embodiments have been described in detail above and will not be repeated here.

[0083] Please see Figure 9 , Figure 9 This is a schematic diagram of a display device provided in an embodiment of this application.

[0084] Thirdly, based on the same concept, this application also provides a display device 200, which includes a display panel 100 of any of the above features, or a display panel 100 that combines any of the above features.

[0085] For example, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 100 above, and will not be repeated below.

[0086] For example, the display device 200 provided in the embodiments of this application can be Figure 9 The vehicle shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc., and this application embodiment does not make any special limitation in this regard.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area at least partially surrounding the display area. The non-display area includes a first sub-non-display area and a second sub-non-display area located on both sides of the display area. The display area includes a first sub-display area adjacent to the first sub-non-display area and a second sub-display area adjacent to the second sub-non-display area. The first sub-display area and the second sub-display area are adjacent to each other. The display panel includes: The first gate driving circuit and the second gate driving circuit are located in the first sub-non-display area and the second sub-non-display area, respectively. Multiple scan signal lines, the scan signal lines including a first sub-scan signal line segment located in the first sub-display area and electrically connected to the first gate driving circuit, and a second sub-scan signal line segment located in the second sub-display area and electrically connected to the second gate driving circuit; The first binding part and the second binding part are located in the non-display area; The first driver chip and the second driver chip are electrically connected to the first bonding part and the second bonding part, respectively. Multiple control units are respectively located between the first sub-scan signal segment and the second sub-scan signal segment of the same scan signal line; First control signal line and second control signal line; The control unit includes a first control transistor and a second control transistor, which are connected in series between the first sub-scan signal segment and the second sub-scan signal segment. The first control signal line is electrically connected to at least one of the first driving chip and the second driving chip, as well as the gate of the first control transistor; The second control signal line is electrically connected to at least one of the first driver chip and the second driver chip, as well as the gate of the second control transistor.

2. The display panel according to claim 1, characterized in that, The first driver chip can drive the first sub-display area to display an image, and the second driver chip can drive the second sub-display area to display an image; The first control signal line is electrically connected to the gate of the first driving chip and the first control transistor, and the first driving chip can control the opening and closing of the first control transistor; The second control signal line is electrically connected to the gate of the second driving chip and the second control transistor, and the second driving chip can control the opening and closing of the second control transistor.

3. The display panel according to claim 1, characterized in that, The first driver chip can drive the first sub-display area to display an image, and the second driver chip can drive the second sub-display area to display an image; The first control signal line is electrically connected to the gate of the second driving chip and the first control transistor, and the second driving chip can control the opening of the first control transistor; The second control signal line is electrically connected to the gate of the first driver chip and the second control transistor, and the first driver chip can control the second control transistor to turn on.

4. The display panel according to claim 3, characterized in that, The first control signal line is also electrically connected to the gate of the first driver chip and the first control transistor, and the first driver chip can control the first control transistor to turn off; The second control signal line is also electrically connected to the gate of the second driver chip and the second control transistor, and the second driver chip can control the second control transistor to turn off.

5. The display panel according to claim 4, characterized in that, Also includes: The first connection line is electrically connected between the second driver chip and the first control signal line; The second connection line is electrically connected between the first driver chip and the second control signal line; The third connecting line and the first resistor are electrically connected between the first driver chip and the first control signal line; The fourth connecting line and the second resistor are electrically connected between the second driver chip and the second control signal line; Wherein, the first connecting line and the second connecting line are for a first potential signal, and the third connecting line and the fourth connecting line are for a second potential signal; The first potential signal can turn on the first control transistor and the second control transistor, and the second potential signal can turn off the first control transistor and the second control transistor.

6. The display panel according to claim 1, characterized in that, The scanning signal line extends along a first direction, and the first control signal line and the second control signal line both extend along a second direction. The first direction intersects with the first direction, and the first sub-display area and the second sub-display area are located on both sides of the display area in the first direction. The first control transistor and the second control transistor are located between the first sub-scan signal segment and the second sub-scan signal segment along the first direction.

7. The display panel according to claim 1, characterized in that, The scanning signal line extends along a first direction, and the first control signal line and the second control signal line both extend along a second direction. The first direction intersects with the first direction, and the first sub-display area and the second sub-display area are located on both sides of the display area in the first direction. On a plane parallel to the display panel, the first sub-scan signal segment and the corresponding second sub-scan signal segment each include a first sub-segment opposite each other along the second direction. The first control transistor and the second control transistor are located along the second direction between the first sub-segment of the first sub-scan signal segment and the first sub-segment of the second sub-scan signal segment.

8. The display panel according to claim 1, characterized in that, include: Base; A light-shielding metal layer is located on one side of the substrate; The first insulating layer is located on the side of the light-shielding metal layer away from the substrate; A semiconductor layer is located on the side of the first insulating layer away from the substrate; A gate insulating layer is located on the side of the semiconductor layer away from the substrate; A first metal layer is located on the side of the gate insulating layer away from the substrate; The second insulating layer is located on the side of the first metal layer away from the substrate; The second metal layer is located on the side of the second insulating layer away from the substrate; The semiconductor layer includes an active portion of a thin-film transistor, the first metal layer includes the gate of the thin-film transistor, the second metal layer includes the source and drain of the thin-film transistor, the light-shielding metal layer includes a light-shielding portion, the orthographic projection of the active portion on the substrate and the orthographic projection of the light-shielding portion on the substrate at least partially overlap, and the light-shielding metal layer also includes the first control signal line and the second control signal line.

9. A display method for a display panel, characterized in that, Applied to a display panel as described in any one of claims 1 to 8, the display method of the display panel includes: When both the first sub-display area and the second sub-display area display images, both the first control transistor and the second control transistor are turned on, and the first sub-scan signal segment and the second scan signal segment in the same scan signal line are turned on; The control unit is turned off only when the first sub-display area displays an image; The control unit is turned off only when the second sub-display area displays an image.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 8.

Images