RF semiconductor device and manufacturing method thereof

Abstract

The invention relates to an RF semiconductor device and a manufacturing method thereof. The invention relates to a radio frequency device. The radio frequency device includes a delivery device die and a multi-layer redistribution structure underlying the delivery device die. The transfer device die includes a device region having a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a transfer substrate. The FEOL portion includes an isolation region segment and an active layer, the active layer being surrounded by the isolation region segment. A top surface of the device region is planarized. The transfer substrate is located over the top surface of the device region. Herein, there is no silicon crystal within the transfer substrate or between the transfer substrate and the active layer. The multi-layer redistribution structure includes a plurality of raised structures at a bottom of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Description

[0001] This application is a divisional application of the Chinese Invention Patent Application No. 202080023383.8, filed on January 22, 2020, entered into Chinese National Phase on September 22, 2021, entitled “RF Semiconductor Device and Method of Manufacturing the Same”. TECHNICAL FIELD

[0002] The present disclosure relates to a radio frequency (RF) device and a manufacturing process thereof, and more particularly, to an RF device having enhanced thermal performance and enhanced electrical performance, and wafer level manufacturing and packaging processes that provide the RF device with enhanced performance. BACKGROUND

[0003] The widespread use of cellular devices and wireless devices has driven the rapid development of radio frequency (RF) technology. Substrates on which RF devices are manufactured play an important role in achieving high level performance of RF technology. Manufacturing RF devices on conventional silicon substrates can benefit from low cost silicon material, large scale wafer production capability, well-established semiconductor design tools, and well-established semiconductor manufacturing technology. Although using conventional silicon substrates is beneficial to RF device manufacturing, it is well known in the industry that conventional silicon substrates can have two undesirable properties for RF devices: harmonic distortion and low resistivity value. Harmonic distortion is a key obstacle to achieving high level linearity in RF devices built on silicon substrates.

[0004] In addition, high speed and high performance transistors are more densely integrated in RF devices. Therefore, as a large number of transistors are integrated on RF devices, a large amount of power passes through the transistors, and / or the transistors operate at high speed, the heat generated by the RF device will significantly increase. Therefore, it is desirable to package the RF device in a configuration for achieving better heat dissipation.

[0005] Wafer level fan-out (WLFO) and embedded wafer level ball grid array (eWLB) technologies are currently attracting wide attention in portable RF applications. WLFO and eWLB technologies are designed to provide high density input / output (I / O) ports without increasing the size of the package. This capability allows RF devices to be densely packaged within a single wafer.

[0006] In order to improve the operating speed and performance of RF devices, to adapt to the increase in heat generated by RF devices, to reduce the harmful harmonic distortion of RF devices, and to take advantage of WLFO / eWLB technology, it is therefore an object of the present disclosure to provide an improved wafer level manufacturing and packaging process for RF devices with enhanced performance. Further, there is also a need to enhance the performance of RF devices without increasing the size of the device. SUMMARY

[0007] The present disclosure relates to a radio frequency (RF) device with enhanced performance and a manufacturing process thereof. The disclosed RF device includes a transfer device die and a multi-layer redistribution structure. The transfer device die includes a device region and a transfer substrate. The device region has a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion. In this context, the FEOL portion is on top of the BEOL portion and includes an isolation section and an active layer surrounded by the isolation section and not vertically extended beyond the isolation section. The device region has a planarized top surface. The transfer substrate is on top of the top surface of the device region. There is no silicon crystal without germanium, nitrogen, or oxygen content within the transfer substrate or between the transfer substrate and the active layer within the device region. The multi-layer redistribution structure including a plurality of bump structures is formed under the BEOL portion of the transfer device die. The bump structures are on a bottom surface of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

[0008] In one embodiment of the RF device, the transfer substrate has a thermal conductivity greater than 10 W / m K and an electrical resistivity greater than 1E5 Ohm-cm.

[0009] In one embodiment of the RF device, the transfer substrate is formed from one of sapphire, heat conducting quartz, aluminum nitride, boron nitride, and beryllium oxide.

[0010] In one embodiment of the RF device, the transfer substrate has a thickness between 10 pm and 1000 pm.

[0011] In one embodiment of the RF device, the active layer is formed from a strained silicon epitaxial layer having a lattice constant of silicon therein greater than 5.461 at a temperature of 300 K.

[0012] In one embodiment of the RF device, the BEOL portion includes a connection layer, the FEOL portion further includes a contact layer, and the multi-layer redistribution structure further includes a redistribution interconnect. In this context, the active layer and the isolation section are on top of the contact layer, and the BEOL portion is under the contact layer. The bump structures are electrically coupled to the FEOL portion of the transfer device die through the redistribution interconnect within the multi-layer redistribution structure and the connection layer within the BEOL portion.

[0013] In one embodiment of the RF device, the device region further includes a passivation layer on top of the active layer and surrounded by the isolation sections. Herein, the passivation layer is formed of silicon dioxide. A top surface of each isolation section and a top surface of the passivation layer are coplanar and form the top surface of the device region.

[0014] In one embodiment of the RF device, a top surface of each isolation section and a top surface of the active layer are coplanar and form the top surface of the device region.

[0015] In one embodiment of the RF device, the pass-through device die further includes a barrier layer formed of silicon nitride coupled between the top surface of the device region and the pass-through substrate.

[0016] In one embodiment of the RF device, the FEOL portion is configured to provide at least one of a switch field effect transistor (FET), a diode, a capacitor, a resistor, or an inductor.

[0017] According to another embodiment, an alternative RF device includes a pass-through device die and a multi-layer redistribution structure. The pass-through device die includes a device region and a pass-through substrate. The device region has a FEOL portion and a BEOL portion. Herein, the FEOL portion is on top of the BEOL portion and includes isolation sections and an active layer surrounded by the isolation sections and not vertically extending beyond the isolation sections. The device region has a planarized top surface. The pass-through substrate is on top of the top surface of the device region. There is no silicon crystal without a germanium, nitrogen, or oxygen content within the pass-through substrate or between the pass-through substrate and the active layer within the device region. The multi-layer redistribution structure formed under the BEOL portion of the pass-through device die extends horizontally beyond the pass-through device die. The multi-layer redistribution structure includes a plurality of bump structures on a bottom surface of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the pass-through device die. The alternative RF device further includes a molding compound on top of the multi-layer redistribution structure to encapsulate the pass-through device die.

[0018] In one embodiment of the alternative RF device, the pass-through substrate has a thermal conductivity greater than 10 W / m-K and an electrical resistivity greater than 1E5 Ohm-cm.

[0019] In one embodiment of the alternative RF device, the pass-through substrate is formed of one of sapphire, heat conducting quartz, aluminum nitride, boron nitride, and beryllium oxide.

[0020] In one embodiment of the alternative RF device, a thickness of the transfer substrate is between 10 pm and 1000 pm.

[0021] In one embodiment of the alternative RF device, the active layer is formed of a strained silicon epitaxial layer, a lattice constant of silicon in the strained silicon epitaxial layer is greater than 5.461 at a temperature of 300 K.

[0022] In one embodiment of the alternative RF device, the BEOL portion includes a connection layer, the FEOL portion further includes a contact layer, and the multi-layer redistribution structure further includes a redistribution interconnect. Herein, the active layer and the isolation segments are located above the contact layer, and the BEOL portion is located below the contact layer. The bump structure is electrically coupled to the FEOL portion of the transfer device die through the redistribution interconnect within the multi-layer redistribution structure and the connection layer within the BEOL portion.

[0023] In one embodiment of the alternative RF device, the device region further includes a passivation layer located above the active layer and surrounded by the isolation segments. Herein, the passivation layer is formed of silicon dioxide. A top surface of each isolation segment and a top surface of the passivation layer are coplanar and form the top surface of the device region.

[0024] In one embodiment of the alternative RF device, a top surface of each isolation segment and a top surface of the active layer are coplanar and form the top surface of the device region.

[0025] In one embodiment of the alternative RF device, the transfer device die further includes a barrier layer formed of silicon nitride coupled between the top surface of the device region and the transfer substrate.

[0026] In one embodiment of the alternative RF device, the FEOL portion is configured to provide at least one of a switch FET, a diode, a capacitor, a resistor, or an inductor.

[0027] According to an example process, a precursor wafer is first provided, the precursor wafer including a plurality of complete device regions, a plurality of individual interface layers, and a silicon handling substrate. Each complete device region includes a BEOL portion and a complete FEOL portion located above the BEOL portion. The complete FEOL portion has an active layer and a complete isolation segment that extends vertically beyond the active layer and surrounds the active layer. Herein, each individual interface layer is located on one active layer and is surrounded by the complete isolation segment of a corresponding complete device region. Each individual interface layer is formed of SiGe. The silicon handling substrate is located on each complete isolation segment and each individual interface layer. Next, the silicon handling substrate is completely removed. The complete isolation segment is then thinned to provide a thinned wafer having a planarized top surface. The thinned wafer includes a plurality of device regions, and a combination of top surfaces of each device region forms the planarized top surface of the thinned wafer. Each device region includes the BEOL portion and a FEOL portion located above the BEOL portion. The FEOL portion has the active layer and the thinned isolation segment that surrounds the active layer. A transfer substrate is attached to the top surface of the thinned wafer to provide a transfer device wafer including a plurality of transfer device dies. Herein, there is no silicon crystal without a germanium, nitrogen, or oxygen content between the active layer of each device region and the transfer substrate, within the transfer substrate. Each transfer device die includes a corresponding device region and a portion of the transfer substrate located above the corresponding device region.

[0028] In one embodiment of the example process, the transfer substrate has a thermal conductivity greater than 10 W / m K and an electrical resistivity greater than 1E5 Ohm-cm.

[0029] In one embodiment of the example process, the transfer substrate is formed of one of: sapphire, heat conducting quartz, aluminum nitride, boron nitride, and beryllium oxide.

[0030] In one embodiment of the example process, the transfer substrate has a thickness between 10 pm and 1000 pm.

[0031] According to another embodiment, the example process further includes, prior to removing the silicon handling substrate, bonding the precursor wafer to a temporary carrier with a bonding layer; and after attaching the transfer substrate, debonding the temporary carrier from the transfer device wafer and cleaning the bonding layer from the transfer device wafer.

[0032] According to another embodiment, the exemplary process further includes forming a multi-layer redistribution structure under the transfer device wafer. Herein, the multi-layer redistribution structure includes a plurality of bump structures on a bottom surface of the multi-layer redistribution structure and redistribution interconnects within the multi-layer redistribution structure. Each bump structure is electrically coupled to one active layer of a corresponding transfer device die through the redistribution interconnects within the multi-layer redistribution structure and a connection layer within the BEOL portion of the corresponding transfer device die.

[0033] According to another embodiment, the exemplary process further includes singulating the transfer device wafer into a plurality of individual transfer device dies. A molding compound is then applied around and over each individual transfer device die to provide a molded device wafer. Herein, the molding compound encapsulates a top surface and side surfaces of each individual transfer device die, while a bottom surface of each individual transfer device die is exposed. A bottom surface of the molded device wafer is a combination of the bottom surface of each individual transfer device die and a bottom surface of the molding compound. Next, a multi-layer redistribution structure is formed under the molded device wafer. The multi-layer redistribution structure includes a plurality of bump structures on a bottom surface of the multi-layer redistribution structure and redistribution interconnects within the multi-layer redistribution structure. Each bump structure is electrically coupled to one active layer of a corresponding individual transfer device die through the redistribution interconnects within the multi-layer redistribution structure and a connection layer within the BEOL portion of the corresponding individual transfer device die.

[0034] According to another embodiment, the exemplary process further includes removing each individual interface layer after removing the silicon handle substrate and before thinning the complete isolation segments. As such, after the thinning step, the planarized top surface of each device region is formed by a top surface of a corresponding active layer and a top surface of a corresponding thinned isolation segment.

[0035] According to another embodiment, the exemplary process further includes removing each individual interface layer after removing the silicon handle substrate and before thinning the complete isolation segments and applying a passivation layer over a corresponding active layer. As such, after the thinning step, the planarized top surface of each device region is formed by a top surface of a corresponding passivation layer and a top surface of a corresponding thinned isolation segment.

[0036] In one embodiment of the exemplary process, the passivation layer is applied by one of a plasma-enhanced deposition process, an anodization process, and an ozone-based oxidation process.

[0037] According to another embodiment, the exemplary process further includes applying a barrier layer over the top surface of the thinned wafer prior to attaching the transfer substrate to the thinned wafer. Herein, the barrier layer is formed of silicon nitride.

[0038] In one embodiment of the exemplary process, providing the precursor wafer begins with providing a starting wafer that includes a common silicon epitaxial layer, a common interface layer located over the common silicon epitaxial layer, and a silicon handle substrate located over the common interface layer. A complementary metal-oxide-semiconductor (CMOS) process is then performed to provide the precursor wafer. Herein, the complete isolation segment extends through the common silicon epitaxial layer and the common interface layer and into the silicon handle substrate, such that the common interface layer separates into the individual interface layers and the common silicon epitaxial layer separates into a plurality of individual silicon epitaxial layers. Each active layer is formed of a corresponding individual silicon epitaxial layer.

[0039] In one embodiment of the exemplary process, the silicon handle substrate is removed by a mechanical grinding process, followed by an etching process.

[0040] In one embodiment of the exemplary process, the silicon handle substrate is removed by an etching process using an etchant chemical that is at least one of tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), acetylcholine (ACH), and xenon difluoride (XeF2).

[0041] In one embodiment of the exemplary process, the silicon handle substrate is removed by a reactive ion etching system having a chlorine-based gas chemical.

[0042] In one embodiment of the exemplary process, the transfer substrate is attached to the top surface of the thinned wafer by one of the group consisting of: anodic bonding, plasma bonding, and polymer adhesive bonding.

[0043] Those skilled in the art will appreciate the scope of the present disclosure and recognize additional aspects upon reading the following detailed description of the preferred embodiments in connection with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings incorporated in and forming a part of the specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0045] Figure 1 An exemplary radio frequency (RF) device having enhanced performance is shown in accordance with one embodiment of the present disclosure.

[0046] Figure 2An alternative RF device with enhanced thermal performance and enhanced electrical performance is shown in accordance with one embodiment of the present disclosure.

[0047] Figures 3A-15 An exemplary wafer-level manufacturing and packaging process showing steps of providing Figure 1 An exemplary wafer-level manufacturing and packaging process showing steps of providing

[0048] Figures 16-21 An exemplary wafer-level manufacturing and packaging process showing steps of providing Figure 2 An alternative wafer-level manufacturing and packaging process showing steps of providing

[0049] It is to be understood that the figures are shown by way of example, and Figures 1-21 may not be to scale. DETAILED DESCRIPTION

[0050] The embodiments set forth below represent the necessary information to enable those with ordinary skill in the art to practice the embodiments and demonstrate the best mode of practicing the embodiments. Upon reading the following description of the embodiments, one skilled in the art will understand how to implement the concepts in practice and will recognize that the concepts can be implemented in a variety of ways. The terminology used herein is for the purpose of describing the embodiments only and is not intended to limit the scope of the disclosure and the appended claims. The description below is not to be taken in a limiting sense, but is made merely for the purpose of providing

[0051] It is to be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] It will be understood that when an element as a layer, region or substrate or the like is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0053] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" or "over" or "under" can be used herein to describe one element's or portion's relationship to another element, layer or portion as illustrated in the Figures. It will be understood that such terms are intended to encompass different orientations of the device and its components in addition to the orientation depicted in the Figures.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] As conventional radio frequency silicon-on-insulator (RFSOI) wafers are expected to be in short supply in the coming years, alternative technologies are being designed to use silicon wafers, trap-rich layer formation, and smart-cut SOI wafer processes to meet high resistivity requirements. One alternative technology is based on using a silicon germanium (SiGe) interface layer between the silicon substrate and the silicon epitaxial layer instead of a buried oxide layer (BOX). However, this technology will still suffer from the deleterious distortion effects caused by the silicon substrate, similar to what is observed in RFSOI technology. The present disclosure relates to a radio frequency (RF) device with enhanced performance, and wafer-level manufacturing and packaging processes for manufacturing the device, which take advantage of the SiGe interface layer without the deleterious distortion effects from the silicon substrate.

[0057] Figure 1 An exemplary RF device 10 with enhanced performance according to one embodiment of the present disclosure is shown. For purposes of this illustration, the exemplary RF device 10 includes a transfer device die 12 having a device region 14 and a transfer substrate 16, and a multi-layer redistribution structure 18 formed under the device region 14 of the transfer device die 12.

[0058] In particular, the device region 14 includes a front end of line (FEOL) portion 20 and a back end of line (BEOL) portion 22 located under the FEOL portion 20. In one embodiment, the FEOL portion 20 can be configured to provide a switching field effect transistor (FET) and includes an active layer 24 and a contact layer 26. The active layer 24 can be formed of a relaxed silicon epitaxial layer or a strained silicon epitaxial layer and includes a source 28, a drain 30, and a channel 32 between the source 28 and the drain 30. Herein, a relaxed silicon epitaxial layer refers to a silicon epitaxial layer in which the lattice constant of the silicon is 5.431 at a temperature of 300 K. A strained silicon epitaxial layer refers to a silicon epitaxial layer in which the lattice constant of the silicon is greater than the lattice constant in a relaxed silicon epitaxial layer, such as greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515, at a temperature of 300 K. As such, the mobility of electrons in a strained silicon epitaxial layer can be enhanced compared to a relaxed silicon epitaxial layer. Thus, the switching speed of a FET formed of a strained silicon epitaxial layer can be faster compared to a FET formed of a relaxed silicon epitaxial layer.

[0059] A contact layer 26 is formed below the active layer 24 and includes a gate structure 34, a source contact 36, a drain contact 38, and a gate contact 40. The gate structure 34 can be formed of silicon oxide and extends horizontally below the channel 32 (e.g., from below the source 28 to below the drain 30). The source contact 36 is connected to and below the source 28, the drain contact 38 is connected to and below the drain 30, and the gate contact 40 is connected to and below the gate structure 34. An insulating material 42 can be formed around the source contact 36, the drain contact 38, the gate structure 34, and the gate contact 40 to electrically separate the source 28, the drain 30, and the gate structure 34. In different applications, the FEOL portion 20 can have different FET configurations or provide different device components, such as diodes, capacitors, resistors, and / or inductors.

[0060] Additionally, the FEOL portion 20 also includes an isolation section 44 that is above the insulating material 42 of the contact layer 26 and surrounds the active layer 24. The isolation section 44 is configured to electrically separate the RF device 10, particularly the active layer 24, from other devices (not shown) formed in a common wafer. The isolation section 44 can be formed of silicon dioxide that is resistant to etching chemicals, such as tetramethylammonium hydroxide (TMAH), xenon difluoride (XeF2), potassium hydroxide (KOH), sodium hydroxide (NaOH), or acetylcholine (ACH), and can be resistant to dry etching systems, such as a reactive ion etching (RIE) system with chlorine-based gas chemistry.

[0061] In some applications, the device region 14 further includes a passivation layer 48 that can be formed of silicon dioxide to passivate the active layer 24. The passivation layer 48 is deposited above a top surface of the active layer 24 and is surrounded by the isolation section 44. In one embodiment, a top surface of the passivation layer 48 and a top surface of the isolation section 44 are coplanar. The passivation layer 48 is configured to terminate surface junctions of the active layer 24, which can be a cause of unwanted leakage.

[0062] In some applications, device region 14 further includes an interface layer and / or buffer structure (not shown) formed of SiGe, located above the top surface of active layer 24 and surrounded by isolation segment 44 (described in the following paragraphs, not shown herein). If passivation layer 48, buffer structure, and interface layer are present, the interface layer and buffer structure are vertically positioned between active layer 24 and passivation layer 48. Hereinafter, the top surface of passivation layer 48 and the top surface of isolation segment 44 are coplanar. If passivation layer 48 is omitted, and interface layer and / or buffer structure are present, the top surface of interface layer (or the top surface of buffer structure) and the top surface of isolation segment 44 are coplanar (not shown). If passivation layer 48, buffer structure, and interface layer are omitted, the top surface of active layer 24 and the top surface of isolation segment 44 are coplanar (not shown). It should be noted that regardless of the presence of the passivation layer 48, the buffer structure, and / or the interface layer, the top surface of the device region 14 (the combination of the top surface of the isolation section 44 and the top surface of the passivation layer 48, the combination of the top surface of the isolation section 44 and the top surface of the interface layer, the combination of the top surface of the isolation section 44 and the top surface of the buffer structure, or the combination of the top surface of the isolation section 44 and the top surface of the active layer 24) is always planarized.

[0063] The transfer substrate 16 is located above the top surface of the device region 14. Heat generated in the device region 14 can travel upwards to the bottom portion of the transfer substrate 16 above the active layer 24, and then downwards through the device region 14 toward the multilayer redistribution structure 18, dissipating the heat. Therefore, it is highly desirable for the transfer substrate 16 to have high thermal conductivity, especially for the portion near the active layer 24. In this document, the high thermal conductivity of the transfer substrate 16 is between 2 W / m·K and 500 W / m·K (ideally above 10 W / m·K), and the high resistivity is between 1E5 Ohm-cm and 1E14 Ohm-cm. Suitable substrate materials for forming the transfer substrate 16 can include sapphire, thermally conductive quartz, and ceramic materials such as aluminum nitride, boron nitride, etc. The transfer substrate 16 can also be formed from beryllium oxide. The thickness of the transfer substrate 16 is based on the required thermal performance of the RF device 10, the device layout, the distance from the multilayer redistribution structure 18, and the details of the package and assembly. The thickness of the transfer substrate 16 can be between 10 μm and 1000 μm.

[0064] In some applications, the delivery device die 12 may further include a barrier layer coupled between the top surface of the device region 14 and the delivery substrate 16 (not shown). This barrier layer may be made of a material with a thickness between and silicon nitride formation between. The barrier layer is configured to provide excellent barrier to moisture and impurities that can diffuse into the channel 32 of the active layer 24 and cause reliability issues for the device. Additionally, the barrier layer can be configured to enhance adhesion between the device region 14 and the transfer substrate 16. It should be noted that regardless of the presence of the barrier layer, the passivation layer 48, or the interface layer, there is no silicon crystal without germanium, nitrogen, or oxygen content within the transfer substrate 16 or between the transfer substrate 16 and the top surface of the active layer 24. Each of the barrier layer, the passivation layer 48, and the interface layer are formed of a silicon composite.

[0065] The BEOL portion 22 is below the FEOL portion 20 and includes a plurality of connection layers 50 formed within a dielectric layer 52. Some of the connection layers 50 (for internal connections) are encapsulated by the dielectric layer 52 (not shown), while some of the connection layers 50 have a bottom portion that is not covered by the dielectric layer 52. Certain of the connection layers 50 are electrically connected to the FEOL portion 20. For purposes of this illustration, one of the connection layers 50 is connected to the source contact 36, and another of the connection layers 50 is connected to the drain contact 38.

[0066] The multilayer redistribution structure 18 formed below the BEOL portion 22 of the transfer device die 12 includes a plurality of redistribution interconnects 54, a dielectric pattern 56, and a plurality of bump structures 58. Herein, each of the redistribution interconnects 54 is connected to a corresponding connection layer 50 within the BEOL portion 22 and extends above a bottom surface of the BEOL portion 22. The connection between the redistribution interconnects 54 and the connection layers 50 is solderless. The dielectric pattern 56 is formed around and below each of the redistribution interconnects 54. Some of the redistribution interconnects 54 (connecting the transfer device die 12 to other device components formed from the same wafer) can be encapsulated by the dielectric pattern 56 (not shown), while some of the redistribution interconnects 54 have a bottom portion exposed through the dielectric pattern 56. Each of the bump structures 58 is formed at a bottom surface of the multilayer redistribution structure 18 and is electrically coupled to a corresponding redistribution interconnect 54 through the dielectric pattern 56. As such, the redistribution interconnects 54 are configured to connect the bump structures 58 to certain of the connection layers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. Thus, the bump structures 58 are electrically connected to the FEOL portion 20 through the corresponding redistribution interconnects 54 and the corresponding connection layers 50. Additionally, the bump structures 58 are separated from one another and protrude from the dielectric pattern 56.

[0067] In some applications, there can be additional redistribution interconnects (not shown) electrically coupled to redistribution interconnects 54 through dielectric pattern 56, and additional dielectric patterns (not shown) formed under dielectric pattern 56, such that a bottom portion of some additional redistribution interconnects can be exposed. Thus, each bump structure 58 is coupled to a corresponding additional redistribution interconnect through an additional dielectric pattern (not shown). Regardless of the number of layers of redistribution interconnects and / or dielectric patterns, multilayer redistribution structure 18 can be fiberglass-free or glass-free. In this context, fiberglass refers to individual glass filaments twisted into larger groupings. These glass filaments can then be woven into a fabric. Redistribution interconnects 54 can be formed of copper or other suitable metal. Dielectric pattern 56 can be formed of benzocyclobutene (BCB), polyimide, or other dielectric material. Bump structures 58 can be solder balls or copper pillars. Multilayer redistribution structure 18 has a thickness between 2 pm and 300 pm.

[0068] Figure 2 An alternative RF device 10A is shown that further includes a molding compound 60 compared to RF device 10 as shown in Figure 1 In this context, multilayer redistribution structure 18 can extend horizontally beyond delivery device die 12, and molding compound 60 is positioned over multilayer redistribution structure 18 to encapsulate delivery device die 12. In this embodiment, redistribution interconnects 54 of multilayer redistribution structure 18 can extend horizontally beyond delivery device die 12, and bump structures 58 of multilayer redistribution structure 18 can not be confined within a periphery of delivery device die 12. Molding compound 60 can be an organic epoxy resin system, among others.

[0069] Figures 3A-15 An exemplary wafer-level fabrication and packaging process is provided that demonstrates steps of fabricating an exemplary RF device 10 as shown in Figure 1 Although the exemplary steps are presented in a series, the exemplary steps do not necessarily depend on order. Some steps can be performed in a different order than presented. Further, processes within the scope of the present disclosure can include fewer or more steps than the steps presented. Figures 3A-15

[0070] First, as shown in Figure 3A and 3B ​As shown, a starting wafer 62 is provided. The starting wafer 62 includes a common silicon epitaxial layer 64, a common interface layer 66 on the common silicon epitaxial layer 64, and a silicon handle substrate 68 on the common interface layer 66. In this context, the common silicon epitaxial layer 64 is formed from a device grade silicon material having silicon epitaxial properties desired for forming electronic devices. The silicon handle substrate 68 can be composed of conventional low cost, low resistivity, and high dielectric constant silicon having a lattice constant of about 5.431 at a temperature of 300 K. The common interface layer 66 is formed from SiGe, which separates the common silicon epitaxial layer 64 from the silicon handle substrate 68.

[0071] The lattice constant of relaxed silicon is about 5.431 at a fixed temperature, such as 300 K. The lattice constant of relaxed Si 1-x Ge x depends on the germanium concentration, as The lattice constant of relaxed SiGe is greater than the lattice constant of relaxed silicon. If the common interface layer 66 is grown directly under the silicon handle substrate 68, the lattice constant in the common interface layer 66 will be strained (decreased) by the silicon handle substrate 68. If the common silicon epitaxial layer 64 is grown directly under the common interface layer 66, the lattice constant in the common silicon epitaxial layer 64 can remain in the original relaxed form (about the same as the lattice constant in a silicon substrate). Thus, the common silicon epitaxial layer 64 can not enhance electron mobility.

[0072] In one embodiment, a common buffer structure 70 can be formed between the silicon handle substrate 68 and the common interface layer 66, as shown. Figure 3A The common buffer structure 70 allows for a transition in the lattice constant from the silicon handle substrate 68 to the common interface layer 66. The common buffer structure 70 can include multiple layers and can be formed from SiGe having a vertically graded germanium concentration. The germanium concentration within the common buffer structure 70 can increase from 0% at the top side (near the silicon handle substrate 68) to X% at the bottom side (near the common interface layer 66). X% can depend on the germanium concentration within the common interface layer 66, such as 15%, or 25%, or 30%, or 40%, etc. In this context, the common interface layer 66 grown under the common buffer structure 70 can maintain its lattice constant in a relaxed form and can not be strained (decreased) to match the lattice constant of the silicon handle substrate 68. The germanium concentration can be uniform throughout the common interface layer 66 and greater than 15%, 25%, 30%, or 40% such that the lattice constant of relaxed SiGe in the common interface layer 66 is greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515 at a temperature of 300 K.

[0073] In this case, the common silicon epitaxial layer 64 is grown directly below the relaxed common interface layer 66, such that the lattice constant of the common silicon epitaxial layer 64 matches (is stretched to) the lattice constant in the relaxed common interface layer 66. Thus, the lattice constant in the strained common silicon epitaxial layer 64 can be greater than 5.461, or greater than 5.482, or greater than 5.493 or greater than 5.515, and thus greater than the lattice constant in the relaxed silicon epitaxial layer (e.g., 5.431 at a temperature of 300K) at a temperature of 300K. The electron mobility of the strained common silicon epitaxial layer 64 can be higher than the electron mobility of the relaxed silicon epitaxial layer. The thickness of the common silicon epitaxial layer 64 can be between 700 nm and 2000 nm, the thickness of the common interface layer 66 can be between and the thickness of the common buffer structure 70 can be between 100 nm and 1000 nm, and the thickness of the silicon handle substrate 68 can be between 200 pm and 700 pm.

[0074] In another embodiment, the common interface layer 66 can be formed directly below the silicon handle substrate 68, and the common buffer structure 70 can be formed between the common interface layer 66 and the common silicon epitaxial layer 64, as illustrated in Figure 3B In this case, the lattice constant of the common interface layer 66 is strained (decreased) by the silicon handle substrate 68. The common buffer structure 70 can still be formed of SiGe with a vertically graded germanium concentration. The germanium concentration within the common buffer structure 70 can increase from 0% at the top side (near the common interface layer 66) to X% at the bottom side (near the common silicon epitaxial layer 64). X% can be 15%, or 25%, or 30% or 40%. The lattice constant at the bottom side of the common buffer structure 70 is greater than the lattice constant at the top side of the common buffer structure 70. In this case, the lattice constant of the common silicon epitaxial layer 64 grown below the common buffer structure 70 matches (is stretched to) the lattice constant at the bottom side of the common buffer structure 70. Thus, the lattice constant in the strained common silicon epitaxial layer 64 is greater than the lattice constant in the relaxed silicon epitaxial layer (e.g., 5.431 at a temperature of 300K).

[0075] In some applications, the common buffer structure 70 is omitted (not shown). The common interface layer 66 is grown directly below the silicon handle substrate 68, and the common silicon epitaxial layer 64 is grown directly below the common interface layer 66. In this case, the lattice constant in the common interface layer 66 is strained (decreased) to match the lattice constant in the silicon handle substrate 68, and the lattice constant in the common silicon epitaxial layer 64 remains in the original relaxed form (approximately the same as the lattice constant in the silicon substrate).

[0076] Next, the starting wafer 62 (in Figure 3Aa complementary metal-oxide-semiconductor (CMOS) process is performed to provide a precursor wafer 72 having a plurality of complete device regions 14', as shown. Figure 4 Each complete device region 14' includes a complete FEOL portion 20' having an active layer 24, a contact layer 26, and a complete isolation section 44', and a BEOL portion 22 located below the complete FEOL portion 20'. For purposes of this illustration, the complete FEOL portion 20' is configured to provide a switching FET. In different applications, the complete FEOL portion 20' can have different FET configurations or provide different device components, such as diodes, capacitors, resistors, and / or inductors.

[0077] In one embodiment, the complete isolation section 44' of each complete device region 14' extends through the common silicon epitaxial layer 64, the common interface layer 66, and the common buffer structure 70 and into the silicon handle substrate 68. As such, the common buffer structure 70 separates into a plurality of individual buffer structures 70I, the common interface layer 66 separates into a plurality of individual interface layers 66I, and the common silicon epitaxial layer 64 separates into a plurality of individual silicon epitaxial layers 64I. Each individual silicon epitaxial layer 64I is used to form a corresponding active layer 24 in one complete device region 14'. The complete isolation section 44' can be formed by a shallow trench isolation (STI). If the active layer 24 is formed from one individual silicon epitaxial layer 64I having a strained (increased) lattice constant, the FET based on the active layer 24 can have a faster switching speed (lower on-resistance) than a FET formed from a relaxed silicon epitaxial layer having a relaxed lattice constant.

[0078] The top surface of the active layer 24 is in contact with the corresponding interface layer 66I located below the corresponding buffer structure 70I. The silicon handle substrate 68 is located above each individual buffer structure 70I, and a portion of the silicon handle substrate 68 can be located above the complete isolation section 44'. The BEOL portion 22 of the complete device region 14' including the plurality of connection layers 50 and the dielectric layers 52 is formed below the contact layer 26 of the complete FEOL portion 20'. A bottom portion of certain connection layers 50 is exposed through the dielectric layers 52 at a bottom surface of the BEOL portion 22.

[0079] After the precursor wafer 72 is completed, the precursor wafer 72 is then bonded with a temporary carrier 74, as shown. Figure 5The precursor wafer 72 can be bonded to the temporary carrier 74 by a bonding layer 76 that provides a planarized surface for the temporary carrier 74. The temporary carrier 74 can be a thick silicon wafer from a cost and thermal expansion perspective, but can also be constructed of glass, sapphire, or any other suitable carrier material. The bonding layer 76 can be a span-on polymeric adhesive film, such as the Brewer Science WaferBOND temporary adhesive material family.

[0080] The silicon handle substrate 68 is then selectively removed to provide an etched wafer 78, as shown. Figure 6 The selective removal is stopped at each individual buffer structure 70I or each interface layer 66I. The removal of the silicon handle substrate 68 can provide an opening 79 over each active layer 24 and within the full isolation section 44'. The removal of the silicon handle substrate 68 can be provided by a mechanical grinding process and an etching process, or by the etching process itself. As an example, the silicon handle substrate 68 can be ground to a thinner thickness to reduce the subsequent etching time. An etching process is then performed to at least completely remove the remaining silicon handle substrate 68. Since the silicon handle substrate 68, the individual buffer structure 70I, and the individual interface layer 66I have different germanium concentrations, they can have different reactions to the same etching technique (e.g., different etching speeds under the same etchant). Thus, the etching system can be able to identify the presence of the individual buffer structure 70I or the individual interface layer 66I (the presence of germanium), and be able to indicate when to stop the etching process. Generally, the higher the germanium concentration, the better the etching selectivity between the silicon handle substrate 68 and the individual buffer structure 70I (or between the silicon handle substrate 68 and the individual interface layer 66I). The etching process can be provided by a wet etching system with an etching chemistry that is at least one of TMAH, KOH, NaOH, ACH, and XeF2, or by a dry etching system such as a reactive ion etching system with a chlorine-based gas chemistry.

[0081] During the removal process, the complete isolation segments 44' are not removed and protect the sides of each active layer 24. The bonding layer 76 and the temporary carrier 74 protect the bottom surface of each BEOL portion 22. Here, after the removal step, the top surface of each complete isolation segment 44' and the top surface of each individual buffer structure 70I (or each individual interface layer 66I) are exposed. Due to the narrow gap nature of the SiGe material, the individual buffer structure 70I and / or the individual interface layer 66I can be conductive (for certain types of devices). The individual buffer structure 70I and / or the individual interface layer 66I can cause significant leakage between the source 28 and the drain 30 of the active layer 24. Therefore, in some applications such as FET switching applications, it is also desirable to remove the individual buffer structure 70I and the individual interface layer 66I, as Figure 7 illustrated. Each active layer 24 is exposed at the bottom of the corresponding opening 79. The individual buffer structure 70I and the individual interface layer 66I can be removed by the same etching process used to remove the silicon handle substrate 68, or can be removed by another etching process such as a chlorine-based dry etching system. Here, if each individual interface layer 66I is thin enough, it can not cause any significant leakage between the source 28 and the drain 30 of the FEOL portion 20. In that case, the individual interface layer 66I can be left behind (not shown). Similarly, if both the individual interface layer 66I and the individual buffer structure 70I are thin enough, it can not cause any significant leakage between the source 28 and the drain 30 of the FEOL portion 20. Such that the individual interface layer 66I and the individual buffer structure 70I can be left behind (not shown).

[0082] In some applications, after the silicon handle substrate 68, the individual buffer structure 70I, and the individual interface layer 66I are removed, each active layer 24 can be passivated to achieve a proper low level current leakage in the device. A passivation layer 48 can be formed over each active layer 24 and within the opening 79 of each complete FEOL portion 20', as Figure 8 illustrated. The passivation layer 48 can be formed of silicon dioxide by a plasma enhanced deposition process, an anodization process, an ozone-based oxidation process, and a variety of other suitable techniques. The passivation layer 48 is configured to terminate surface junctions at the top surface of the active layer 24, which can be the cause of unwanted leakage.

[0083] Next, the complete isolation segments 44' are thinned as isolation segments 44 to provide a thinned wafer 80 with planarized top surfaces, as Figure 9The thinned wafer 80 includes a plurality of device regions 14, and the combination of the top surfaces of each device region 14 forms a planarized top surface of the thinned wafer 80. In this context, the top surface of each passivation layer 48 and the top surface of each isolation segment 44 are coplanar if a passivation layer 48 is applied. If the passivation layer 48 is omitted, and a separate interface layer 66I (and / or a separate buffer structure 70I is present), the top surface of each isolation segment 44 and the top surface of each separate interface layer 66I (or the top surface of each separate buffer structure 70I) are coplanar (not shown). If the passivation layer 48, the separate buffer structure 70I, and the separate interface layer 66I are omitted, the top surface of each active layer 24 and the top surface of each isolation segment 44 are coplanar (not shown). Regardless of the presence of the passivation layer 48, the separate buffer structure 70I, and / or the separate interface layer 66I, the top surface of each device region 14 is always planarized. The planarization step can be accomplished by a chemical mechanical polishing (CMP) process using a suitable slurry and polishing wheel, etc.

[0084] The transfer substrate 16 is then bonded to the top surface of the thinned wafer 80 to provide a transfer device wafer 82, as shown in FIG. 4. Figure 10 Since the top surface of the thinned wafer 80 is planarized, the transfer device wafer 82 does not have any voids or defects at the bonding region. The transfer device wafer 82 includes a plurality of transfer device dies 12, each of which includes at least a device region 14 and a portion of the transfer substrate 16. The transfer substrate 16 has a high thermal conductivity between 2 W / m-K and 500 W / m-K, and a high electrical resistivity between 1E5 Ohm-cm and 1E14 Ohm-cm. The transfer substrate 16 can be formed of sapphire, heat conductive quartz, a ceramic material such as aluminum nitride, boron nitride, etc., or beryllium oxide. The thickness of the transfer substrate 16 can be between 10 pm and 1000 pm. A variety of suitable low temperature bonding processes can be employed in this step, such as anodic bonding, plasma bonding, polymer adhesive bonding, etc. The temporary carrier 74 provides mechanical strength and rigidity to the thinned wafer 80 during the bonding process of the transfer substrate 16.

[0085] In some applications, a barrier layer (not shown) can be formed over the top surface of the thinned wafer 80 prior to bonding the transfer substrate 16. This barrier layer can be formed of a material such as silicon dioxide, silicon nitride, etc., with a thickness between 1 pm and 100 pm. The barrier layer can be formed by a variety of suitable deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. And silicon nitride formation between. The barrier layer is configured to provide excellent barrier to moisture and impurities that can diffuse into the channel 32 of each active layer 24. Additionally, the barrier layer can be configured to enhance adhesion between the thinned wafer 80 and the transfer substrate 16. It should be noted that regardless of the presence of the barrier layer, the passivation layer 48, or the separate interface layer 66I, there is no silicon crystal without germanium, nitrogen, or oxygen content within the transfer substrate 16 or between the transfer substrate 16 and the top surface of each active layer 24. Each of the barrier layer, the passivation layer 48, and the separate interface layer 66I is formed of a silicon composite.

[0086] The temporary carrier 74 is then disengaged from the transfer device wafer 82 and the bonding layer 76 is removed from the transfer device wafer 82, as Figure 11 demonstrated. Depending on the properties of the temporary carrier 74 and the bonding layer 76 selected in the previous steps, a variety of disengagement and removal processes can be applied. For example, a lateral blade process can be used to mechanically disengage the temporary carrier 74 with the stack being heated to a suitable temperature. If the temporary carrier 74 is formed of a transparent material, other suitable processes involve UV light irradiation through the temporary carrier, or chemical disengagement using a suitable solvent. The bonding layer 76 can be removed by a wet etching or dry etching process, such as a proprietary solvent and plasma cleaning. After the disengagement and removal processes, some of the connection layers 50 can be exposed at the bottom surface of each BEOL portion 22 for use as a bottom portion of an input / output (I / O) port of each transfer device die 12. As such, at this point, each transfer device die 12 in each transfer device wafer 82 can be electrically verified to determine that the transfer device die is functioning properly.

[0087] Referring to Figures 12 to 14 , according to one embodiment of the present disclosure, a multilayer redistribution structure 18 is formed under the transfer device wafer 82. Although the redistribution steps are demonstrated in a series, the redistribution steps do not necessarily depend on the order. Some steps can be performed in a different order than presented. Further, the redistribution steps within the scope of the present disclosure can include fewer or more steps than Figures 12-14 demonstrated.

[0088] A plurality of redistribution interconnects 54 is first formed under each BEOL portion 22, as Figure 12exposed bottom portions of the corresponding connection tiers 50 within the BEOL portion 22, and can extend above the bottom surface of the BEOL portion 22. The connection between the redistribution interconnects 54 and the connection tiers 50 is solderless. A dielectric pattern 56 is then formed under each BEOL portion 22 to partially encapsulate each redistribution interconnect 54, as shown. Figure 13 As such, a bottom portion of each redistribution interconnect 54 is exposed by the dielectric pattern 56. In different applications, there can be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnects 54 through the dielectric pattern 56, and additional dielectric patterns (not shown) formed under the dielectric pattern 56 such that a bottom portion of each additional redistribution interconnect is exposed.

[0089] Next, a plurality of bump structures 58 are formed to complete the multilayer redistribution structure 18, and to provide wafer-level fan-out (WLFO) type packages 84, as shown. Figure 14 As shown, each bump structure 58 is formed at the bottom of the multilayer redistribution structure 18, and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 through the dielectric pattern 56. Thus, the redistribution interconnects 54 are configured to connect the bump structures 58 to certain connection tiers in the connection tiers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. As such, the bump structures 58 are electrically connected to the FEOL portion 20 through the corresponding redistribution interconnects 54 and the corresponding connection tiers 50. Additionally, the bump structures 58 are separated from each other, and vertically protrude from the dielectric pattern 56.

[0090] The multilayer redistribution structure 18 can be glass-fiber free or glass free. In this context, glass fiber refers to individual glass filaments twisted into larger groupings. These glass filaments can then be woven into a fabric. The redistribution interconnects 54 can be formed of copper or other suitable metal, the dielectric pattern 56 can be formed of BCB, polyimide, or other dielectric material, and the bump structures 58 can be solder balls or copper pillars. The thickness of the multilayer redistribution structure 18 is between 2 pm and 300 pm. Figure 15 The last step of singulating the WLFO packages 84 into individual RF devices 10 is shown. The singulation step can be provided by a probing and dicing process at certain isolation sections 44.

[0091] In another embodiment, Figures 16-21 An alternative process is provided that shows the steps of manufacturing Figure 2 An alternative process is provided that shows the steps of manufacturing an alternative RF device 10A, as shown. Although the example steps are shown in a series, the example steps do not necessarily depend on order. Some steps can be performed in a different order than presented. Further, processes within the scope of the present disclosure can contain more steps than presented.Figures 16-21 Fewer or more steps than shown can be performed.

[0092] As shown, after the de-bonding process and the cleaning process to provide the clean transfer device wafer 82, a singulation step is performed to singulate the transfer device wafer 82 into individual transfer device dies 12, as shown. This singulation step can be provided by a probing and dicing process at certain isolation sections 44. Herein, each transfer device die 12 can have the same height and contain at least a device region 14 having the FEOL portion 20 and the BEOL portion 22 and the transfer substrate 16. Figure 11 Figure 16 Next, a molding compound 60 is applied around and over the transfer device dies 12 to provide a molded device wafer 86, as shown. The molding compound 60 encapsulates the top and side surfaces of each transfer device die 12, while the bottom surface of each transfer device die 12, i.e., the bottom surface of the BEOL portion 22, is exposed. The bottom surface of the molded device wafer 86 is the combination of the bottom surface of each transfer device die 12 and the bottom surface of the molding compound 60. Herein, the bottom portion of certain ones of the connection layers 50 remains exposed at the bottom surface of each transfer device die 12. The molding compound 60 can be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dike fill encapsulation, or screen print encapsulation. Unlike the transfer substrate 16, the molding compound 60 has no thermal conductivity or resistivity requirements. The molding compound 60 can be an organic epoxy resin system, etc. A curing process (not shown) is then used to harden the molding compound 60. The curing temperature is between 100°C and 320°C, depending on which material is used as the molding compound 60. A grinding process (not shown) can be performed to provide a planarized top surface of the molding compound 60.

[0093] Next, a molding compound 60 is applied around and over the transfer device dies 12 to provide a molded device wafer 86, as shown. The molding compound 60 encapsulates the top and side surfaces of each transfer device die 12, while the bottom surface of each transfer device die 12, i.e., the bottom surface of the BEOL portion 22, is exposed. The bottom surface of the molded device wafer 86 is the combination of the bottom surface of each transfer device die 12 and the bottom surface of the molding compound 60. Herein, the bottom portion of certain ones of the connection layers 50 remains exposed at the bottom surface of each transfer device die 12. The molding compound 60 can be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dike fill encapsulation, or screen print encapsulation. Unlike the transfer substrate 16, the molding compound 60 has no thermal conductivity or resistivity requirements. The molding compound 60 can be an organic epoxy resin system, etc. A curing process (not shown) is then used to harden the molding compound 60. The curing temperature is between 100°C and 320°C, depending on which material is used as the molding compound 60. A grinding process (not shown) can be performed to provide a planarized top surface of the molding compound 60. Figure 17

[0094] The multi-layer redistribution structure 18 is formed according to one embodiment of the disclosure, with reference to Figures 18 to 20 Although the redistribution steps are shown in a series, the redistribution steps do not necessarily depend on the order. Some steps can be performed in a different order than presented. Further, the redistribution steps within the scope of the disclosure can contain fewer or more steps than shown. Figures 18-20

[0095] First, a plurality of redistribution interconnects 54 is formed under the molded device wafer 86, as shown. Figure 18 ​​​The redistribution interconnects 54 are electrically coupled to the corresponding connection tiers 50 within the BEOL portion 22, and can extend horizontally beyond the corresponding pass-through device dies 12 and under the molding compound 60. The connection between the redistribution interconnects 54 and the connection tiers 50 is solderless. The dielectric pattern 56 is then formed under the molding device wafer 86 to partially encapsulate each redistribution interconnect 54, as shown. Figure 19 As such, a bottom portion of each redistribution interconnect 54 is exposed by the dielectric pattern 56. In different applications, there can be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnects 54 through the dielectric pattern 56, and additional dielectric patterns (not shown) formed under the dielectric pattern 56 such that a bottom portion of each additional redistribution interconnect is exposed.

[0096] Next, a plurality of bump structures 58 are formed to complete the multilayer redistribution structure 18, and to provide the alternative WLFO package 84A, as shown. Figure 20 As shown, each bump structure 58 is formed at a bottom of the multilayer redistribution structure 18, and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 through the dielectric pattern 56. Thus, the redistribution interconnects 54 are configured to connect the bump structures 58 to certain connection tiers in the connection tiers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. As such, the bump structures 58 are electrically connected to the FEOL portion 20 through the corresponding redistribution interconnects 54 and the corresponding connection tiers 50. In this regard, the bump structures 58 can not be limited within the periphery of the corresponding pass-through device dies 12. Additionally, the bump structures 58 are separated from each other and vertically protrude from the dielectric pattern 56.

[0097] Figure 21 The last step of singulating the alternative WLFO package 84A into individual alternative RF devices 10A is shown. The singulation step can be provided by a probing and cutting process at portions of the molding compound 60 that are horizontally located between adjacent pass-through device dies 12.

[0098] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the following claims.

Claims

1. A method comprising: providing a precursor wafer comprising a plurality of complete device regions, a plurality of individual interface layers, and a silicon handling substrate, wherein: each of the plurality of complete device regions includes a back end of line (BEOL) portion and a complete front end of line (FEOL) portion located above the BEOL portion, wherein the complete FEOL portion includes an active layer and a complete isolation segment that extends vertically beyond and surrounds the active layer; each of the plurality of individual interface layers is located above one active layer and is surrounded by a complete isolation segment of a corresponding complete device region, wherein each of the plurality of individual interface layers is formed of silicon germanium (SiGe); and the silicon handling substrate is located above each complete isolation segment and each of the plurality of individual interface layers; completely removing the silicon handling substrate; after removing the silicon handling substrate, thinning the complete isolation segments to provide a thinned wafer having a planarized top surface, wherein: the thinned wafer includes a plurality of device regions, and a combination of top surfaces of each of the plurality of device regions forms the planarized top surface of the thinned wafer; and each of the plurality of device regions includes the BEOL portion and a FEOL portion located above the BEOL portion, wherein the FEOL portion includes an active layer and a thinned isolation segment that surrounds the active layer; and attaching a transfer substrate to the top surface of the thinned wafer to provide a transfer device wafer including a plurality of transfer device dies; wherein: there is no silicon crystal without a germanium, nitrogen, or oxygen content within the transfer substrate or between the active layer of each of the plurality of device regions and the transfer substrate; and each of the plurality of transfer device dies includes a corresponding device region and a portion of the transfer substrate located above the corresponding device region.

2. The method of claim 1, wherein the transfer substrate has a thermal conductivity greater than 10 W / m-K and an electrical resistivity greater than 1E5 Ohm-cm.

3. The method of claim 2, wherein the transfer substrate is formed of one of a group including sapphire, heat conducting quartz, aluminum nitride, boron nitride, and beryllium oxide.

4. The method of claim 2, wherein the transfer substrate has a thickness between 10 pm and 1000 pm.

5. The method of claim 1, further comprising: before removing the silicon handling substrate, bonding the precursor wafer to a temporary carrier with a bonding layer; and after attaching the transfer substrate, debonding the temporary carrier from the transfer device wafer and cleaning the bonding layer from the transfer device wafer.

6. The method of claim 1, further comprising forming a multi-layer redistribution structure under the transfer device wafer, wherein: the plurality of raised structures are electrically coupled to one active layer of the corresponding pass-through die through the redistribution interconnects within the multilayer redistribution structure and a connection layer within a BEOL portion of the corresponding pass-through die.

7. The method of claim 1, further comprising: singulating the pass-through die wafer into a plurality of individual pass-through dies; applying a molding compound around and over each of the plurality of individual pass-through dies to provide a molded die wafer, wherein: the molding compound encapsulates a top surface and side surfaces of each of the plurality of individual pass-through dies, while a bottom surface of each of the plurality of individual pass-through dies is exposed; and a bottom surface of the molded die wafer is a combination of the bottom surface of each of the plurality of individual pass-through dies and a bottom surface of the molding compound; and forming a multilayer redistribution structure under the molded die wafer, wherein: the multilayer redistribution structure includes a plurality of raised structures on a bottom surface of the multilayer redistribution structure and redistribution interconnects within the multilayer redistribution structure; and the plurality of raised structures are electrically coupled to one active layer of the corresponding individual pass-through die through the redistribution interconnects within the multilayer redistribution structure and a connection layer within a BEOL portion of the corresponding individual pass-through die.

8. The method of claim 1, further comprising, after removing the silicon handle substrate and before thinning the complete isolation segments, removing each of the plurality of individual interface layers such that, after the thinning step, a planarized top surface of each of the plurality of device regions is formed by a top surface of the corresponding active layer and a top surface of the corresponding thinned isolation segment.

9. The method of claim 1, further comprising, after removing the silicon handle substrate and before thinning the complete isolation segments, removing each of the plurality of individual interface layers and applying a passivation layer over the corresponding active layer such that, after the thinning step, a planarized top surface of each of the plurality of device regions is formed by a top surface of the corresponding passivation layer and a top surface of the corresponding thinned isolation segment.

10. The method of claim 9, wherein the passivation layer is applied by one process from a group comprising a plasma enhanced deposition process, an anodization process, and an ozone-based oxidation process.

11. The method of claim 1, further comprising, before attaching the pass-through substrate to the thinned wafer, applying a barrier layer over a top surface of the thinned wafer, wherein the barrier layer is formed from silicon nitride.

12. The method of claim 1, wherein providing the precursor wafer comprises: ​ A starting wafer is provided, the starting wafer including a common silicon epitaxial layer, a common interface layer located on the common silicon epitaxial layer, and a silicon handle substrate located on the common interface layer, wherein the common interface layer is formed of SiGe; and A complementary metal-oxide-semiconductor (CMOS) process is performed to provide the precursor wafer, wherein: the complete isolated section extends through the common silicon epitaxial layer and the common interface layer, and into the silicon handle substrate, such that the common interface layer is separated into a plurality of individual interface layers, and the common silicon epitaxial layer is separated into a plurality of individual silicon epitaxial layers; each active layer is formed of a corresponding individual silicon epitaxial layer; and each of the plurality of individual interface layers is located on a top surface of a corresponding active layer, and the silicon handle substrate is located on the plurality of individual interface layers.

13. The method of claim 1, wherein the silicon handle substrate is removed by a mechanical grinding process, followed by an etching process using an etchant chemical, the etchant chemical being at least one of a group including tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), acetylcholine (ACH), and xenon difluoride (XeF2).

14. The method of claim 1, wherein the silicon handle substrate is removed by an etching process using an etchant chemical, the etchant chemical being at least one of a group including TMAH, KOH, NaOH, ACH, and XeF2.

15. The method of claim 1, wherein the transfer substrate is attached to a top surface of the thinned wafer by one of a group including anodic bonding, plasma bonding, and polymer adhesive bonding.

16. The method of claim 1, wherein the precursor wafer further includes a plurality of individual buffer structures, wherein: each of the plurality of individual buffer structures is located between the silicon handle substrate and a corresponding individual interface layer; each of the plurality of individual buffer structures is formed of SiGe having a vertically graded germanium concentration; and the vertically graded germanium concentration within each of the plurality of individual buffer structures increases from the silicon handle substrate to the corresponding individual interface layer.

17. The method of claim 16, further comprising, after removing the silicon handle substrate and before thinning the complete isolated section, each of the plurality of individual buffer structures, removing each of the plurality of individual interface layers, and applying a passivation layer on a corresponding active layer, such that after the thinning step, a planarized top surface of each of the plurality of device regions is formed of a top surface of the corresponding passivation layer and a top surface of the corresponding thinned isolated section.

18. The method of claim 16, wherein providing the precursor wafer includes: providing a starting wafer including a common silicon epitaxial layer, a common interface layer located on the common silicon epitaxial layer, a common buffer structure located on the common interface layer, and a silicon handle substrate located on the common buffer structure, wherein: the common interface layer is formed of SiGe having a uniform germanium concentration, and the common buffer structure is formed of SiGe having a vertically staged germanium concentration, wherein the vertically staged germanium concentration within the common buffer structure increases from the silicon handle substrate to the common interface layer, such that the common interface layer is not strained by the silicon handle substrate and has a lattice constant greater than 5.461 at a temperature of 300 K; and a lattice constant of the silicon in the common silicon epitaxial layer is strained by the common interface layer and is greater than 5.461 at a temperature of 300 K; and performing a CMOS process to provide the precursor wafer, wherein: the complete isolation section extends through the common silicon epitaxial layer, the common interface layer, and the common buffer structure, and into the silicon handle substrate, such that the common buffer structure separates into a plurality of individual buffer structures, the common interface layer separates into a plurality of individual interface layers, and the common silicon epitaxial layer separates into a plurality of individual silicon epitaxial layers; each active layer is formed of a corresponding individual silicon epitaxial layer; and each of the plurality of individual interface layers is located over a top surface of a corresponding active layer, each of the plurality of individual buffer structures is located over a corresponding interface layer; and the silicon handle substrate is located over the plurality of individual buffer structures.

19. The method of claim 1, wherein the FEOL portion of each of the plurality of device regions is configured to provide at least one of a switching field effect transistor (FET), a diode, a capacitor, a resistor, or an inductor.

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