Method for evaluating semiconductor device feature size
By using partitioned chucks and temperature gradient evaluation methods in the self-aligned patterning process, the problems of long processing time and high cost are solved, and efficient IMB debugging and optimization are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INTEGRATED CIRCUIT EQUIPMENT INNOVATION CENTER CO LTD
- Filing Date
- 2025-08-19
- Publication Date
- 2026-05-12
AI Technical Summary
Existing methods for determining the feature size of semiconductor devices are time-consuming and costly, resulting in low efficiency in core-gap feature size balance (IMB) debugging.
A self-aligned patterning process using a partitioned chuck is employed. By setting a temperature gradient during the oxide etching step, feature size evaluation is performed to obtain feature size balance. The feature size relationship between the core and the gap is determined based on the temperature and size relationship.
It improves process debugging efficiency, reduces costs, minimizes errors, and enables rapid identification of IMB problems and optimization of process conditions.
Smart Images
Figure CN121149029B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of self-aligned patterning technology, and more specifically, to a method for evaluating the feature dimensions of semiconductor devices. Background Technology
[0002] SADP (Self-Aligned Double Patterning) and SAQP (Self-Aligned Quadruple Patterning) processes, as advanced multi-layer lithography technologies, can achieve high resolution and small feature sizes, thereby improving chip integration and performance. In actual process debugging, factors such as CD (feature size), Open ratio, and Etch amount can cause deviations between the Core CD and Gap CD, ultimately leading to a deterioration in the feature size imbalance (IMB) between the Core and Gap. Therefore, identifying CD issues during process debugging is crucial, as subsequent IMB improvements must be based on this condition.
[0003] In related technologies, the CD problem is determined by observing wafer slices using TEM (transmission electron microscopy). This method is not only time-consuming but also costly. Summary of the Invention
[0004] The purpose of this invention is to provide a method for evaluating the feature dimensions of semiconductor devices, so as to alleviate the technical problems of time-consuming and costly determination of CD in related technologies.
[0005] The method for evaluating the feature size of semiconductor devices provided by this invention includes:
[0006] In the processing step, the wafer is placed in a partitioned chuck, and the wafer is processed by a self-aligned patterning process to obtain multiple empty slots; in the oxide etching step of the self-aligned patterning process, the temperature difference between any two partitions of the partitioned chuck is greater than zero, the highest temperature of the partitioned chuck is higher than or equal to the reference temperature, and the lowest temperature of the partitioned chuck is lower than or equal to the reference temperature.
[0007] In the acquisition step, the feature size balance of each partition corresponding to the wafer is acquired; wherein, the feature size balance is the absolute value of the feature size difference between two adjacent slots, and the slot includes a core area and a gap;
[0008] In the determination step, based on the temperature of each partition of the partitioned chuck and the corresponding characteristic dimension balance, the size relationship between the characteristic dimension of the core area and the characteristic dimension of the gap is determined at the reference temperature.
[0009] Preferably, as one possible implementation, the plurality of partitions are radially distributed from the center of the partition chuck outwards, and the temperature of the plurality of partitions gradually decreases or increases from the inside outwards.
[0010] Preferably, as one possible implementation, the temperature of the innermost partition is consistent with the reference temperature.
[0011] Preferably, as one possible implementation, the determining step includes:
[0012] Under the condition that the temperature of the partition chuck gradually decreases from the inside to the outside, if the feature size balance gradually decreases or first decreases and then increases from the center of the wafer to the edge, it is determined that at the reference temperature, the feature size of the core region is smaller than the feature size of the gap; if the feature size balance gradually increases from the center of the wafer to the edge, it is determined that at the reference temperature, the feature size of the core region is larger than the feature size of the gap.
[0013] Under the condition that the temperature of the partition chuck gradually increases from the inside to the outside, if the feature size balance gradually decreases or first decreases and then increases from the center of the wafer to the edge, it is determined that at the reference temperature, the feature size of the core region is greater than the feature size of the gap; if the feature size balance gradually increases from the center of the wafer to the edge, it is determined that at the reference temperature, the feature size of the core region is greater than the feature size of the gap.
[0014] Preferably, as one possible implementation, the plurality of partitions include a central partition, an inner-middle partition, an outer-middle partition, and an edge partition, which are distributed radially from the center of the partition chuck in sequence from the inside to the outside.
[0015] Preferably, as one possible implementation, the temperature difference between two adjacent partitions of the partition chuck is less than or equal to 5°C.
[0016] Preferably, as one possible implementation, the temperature difference between two adjacent partitions of the partition chuck is 4°C.
[0017] Preferably, as one possible implementation, the acquisition step includes:
[0018] Measure the feature dimensions of multiple empty slots and determine the correspondence between the feature dimensions of each empty slot and the measurement position;
[0019] Based on the aforementioned correspondence, two adjacent empty slots are grouped together;
[0020] The difference between the characteristic dimensions of the two empty slots in each group is calculated and the absolute value is taken to obtain the balance of multiple characteristic dimensions and their corresponding positions.
[0021] Preferably, as one possible implementation, the acquisition step includes:
[0022] The characteristic dimensions of the empty slot were measured using a feature-dimension scanning electron microscope.
[0023] Another method for evaluating the feature dimensions of semiconductor devices provided by the present invention includes:
[0024] In the processing step, the wafer is placed in a chuck, and the wafer is processed by a self-aligned patterning process to obtain multiple empty slots; in the oxide etching step of the self-aligned patterning process, the temperature of the chuck is higher or lower than the reference temperature.
[0025] In the acquisition step, the feature size balance of the wafer is acquired; wherein, the feature size balance is the absolute value of the difference in feature size between two adjacent slots, and the slot includes the core region and the gap;
[0026] In the determination step, based on the temperature of the chuck and the balance of the feature dimensions, the size relationship between the feature dimensions of the core area and the feature dimensions of the gap is determined at the reference temperature.
[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0028] In this invention, during oxide etching of a wafer placed on a partitioned chuck, the temperature difference between any two partitions of the partitioned chuck is set to be greater than zero. After the wafer completes the self-aligned patterning process, the feature size of the gaps on the wafer is positively correlated with the temperature of the corresponding partition on the partitioned chuck, while the feature size of the core area of each region on the wafer is approximately the same, and is basically consistent with the feature size of the core area formed when the partitioned chuck is used at a reference temperature in the oxide etching step.
[0029] By analyzing IMB trends under different conditions through a single experiment, the characteristic dimensional relationship between the core region and gap of the wafer can be determined. This allows for rapid localization of IMB issues at the reference temperature, improving the efficiency of process debugging. Furthermore, without requiring wafer slicing observation, the experimental wafer can continue fabrication and be used for subsequent process debugging, reducing debugging costs. In addition, using a partitioned chuck and setting a temperature gradient can better reflect the IMB trend with temperature changes. Especially at the reference temperature, when the core CD and gap CD are not significantly different, it can identify the trend of IMB first decreasing and then increasing, greatly reducing the risk of errors introduced by IMB trend reversals and improving the accuracy of the conclusions. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0031] Figures 1a-1f A process flow diagram for self-aligned dual-graphics technology;
[0032] Figures 2a-2e A process flow diagram for self-aligned quadruple graphical technology;
[0033] Figure 3a This is a schematic diagram of the Core and Gap after oxide etching in a self-aligned dual patterning technique.
[0034] Figure 3b A schematic diagram of the Core and Gap after the completion of the self-aligned dual graphics technique;
[0035] Figures 4a-4b A schematic diagram and slice image of the top oxide removal process in a self-aligned quadruple patterning technique.
[0036] Figure 5 A first schematic flowchart of a method for evaluating the feature dimensions of semiconductor devices provided in an embodiment of the present invention;
[0037] Figure 6 This is a schematic diagram illustrating the effect of chuck temperature variation on feature size during the oxide etching step of a self-aligned patterning process.
[0038] Figure 7 This is a trend distribution diagram of IMB as a function of wafer radius in an embodiment of the present invention;
[0039] Figure 8This is a second schematic flowchart of a method for evaluating the feature size of a semiconductor device provided in an embodiment of the present invention. Detailed Implementation
[0040] The semiconductor industry has been constantly pursuing smaller, faster, and more energy-efficient chip manufacturing processes to meet the ever-increasing demands of modern electronic devices for performance and power consumption. As Moore's Law gradually approaches its limits, traditional photolithography techniques can no longer meet the needs of chip manufacturing. SADP and SAQP processes can achieve higher resolution and smaller feature sizes.
[0041] SADP (Self-Aligned Process) refers to the process of creating two distinct patterns in a single photolithography step using self-aligned technology. Its process flow is as follows: Figures 1a-1f As shown, Figure 1a The pattern is formed after a single litho-etch (photolithography-etching) process. Figure 1b This is a pattern formed after ALD oxide deposition (atomic layer deposition to form an oxide thin film). Figure 1c This is the pattern formed after ALD Ox etching (etching the oxide film generated by atomic layer deposition). Figure 1d The pattern formed after carbon stripping. Figure 1e The pattern formed after SiON etching. Figure 1f 2 nd The pattern is formed after carbon etching and top oxide removal. This technique allows for the simultaneous fabrication of dense lines and spaced lines on the chip, resulting in higher linewidth resolution. Therefore, compared to traditional multi-layer lithography processes, SADP significantly reduces cost and complexity.
[0042] SAQP process refers to the use of self-aligned technology to form four different patterns in a single photolithography step. Figure 1f Based on this, the wafer is further processed, and the subsequent process steps are as follows: Figures 2a-2e As shown, Figure 2a For ALD Oxide2 nd The pattern formed after deposition, Figure 2b This is the pattern formed after ALD Ox etching. Figure 2c The pattern formed after Carbon Stripping. Figure 2d The pattern formed after SiON etching. Figure 2e This is the pattern formed after Top Ox removal. This technique enables the creation of more complex structures and patterns on chips, thereby further improving chip integration and performance. It is commonly used in the manufacture of high-end chips, such as processors, memory, and graphics chips.
[0043] Taking SADP as an example, the Core and Gap are defined as follows: See Figure 3a After ALD Ox etching, the area containing Carbon is the Core, and the remaining areas are the Gap; see [link / reference]. Figure 3b After the SADP process, two adjacent spaces correspond to the Core and the Gap, respectively.
[0044] In related technologies, see Figure 4a and Figure 4b Before Top Ox removal, the wafer is sliced, and the Core CD and Gap CD are observed using transmission electron microscopy. The core and gap are distinguished based on the top oxide morphology to determine CD issues. On the one hand, slice identification is time-consuming and expensive; on the other hand, after wafer slicing, it's impossible to continue fabrication to observe the final CD, leading to significant errors. Furthermore, changes in experimental conditions may cause an IMB trend reversal. For example, the original conclusion was that the core CD was 1.5 nm smaller than the gap CD, resulting in an IMB of 1.5; after changing the experimental conditions, the core CD became 2 nm larger than the gap CD, resulting in an IMB of 2. The conclusion was that these experimental conditions were unfavorable for IMB optimization. However, the actual conclusion should be that these conditions significantly improve IMB optimization, and quantitative experiments can be used to achieve the goal of IMB optimization.
[0045] Based on this, the present invention provides a method and system for determining the balance of feature dimensions in a self-aligned patterning process. By using a 4-zone electrostatic adsorption chuck and setting a temperature gradient to change the distribution of core CD and gap CD, the IMB problem can be quickly located, improving the efficiency of process debugging and reducing the cost of process debugging. Moreover, the experimental wafer can continue to be fabricated and applied to subsequent process debugging, reducing errors caused by environmental factors such as sample preparation / measurement.
[0046] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0047] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.
[0048] Figure 5 An embodiment of the present invention provides a method for evaluating the feature dimensions of a semiconductor device, the method comprising:
[0049] S102, Processing step: The wafer is placed in a partitioned chuck, and the wafer is processed by a self-aligned patterning process to obtain multiple empty slots; In the oxide etching step of the self-aligned patterning process, the temperature difference between any two partitions of the partitioned chuck is greater than zero, the highest temperature of the partitioned chuck is higher than or equal to the reference temperature, and the lowest temperature of the partitioned chuck is lower than or equal to the reference temperature.
[0050] The oxide etching step is the Ox etching step (the step of etching the oxide film). Figure 1b The structure shown can be formed after this step. Figure 1c The structure shown; Figure 2a The structure shown can be formed after this step. Figure 2b The structure shown illustrates the ability to process wafers using a self-aligned patterning process via inductively coupled plasma etching (ICP), with the temperature of the partitioned chuck set in the process recipe. The reference temperature is the chuck temperature in the oxide etching step under the original process conditions.
[0051] S104, Acquisition step, acquire the feature size balance of each partition of the wafer; wherein, the feature size balance is the absolute value of the feature size difference between two adjacent slots, and the slots include the core area and the gaps;
[0052] S106, Determine the relationship between the feature dimensions of the core area and the feature dimensions of the gap at the reference temperature, based on the temperature of each partition of the partition chuck and the corresponding feature dimension balance.
[0053] During process debugging, a relatively linear relationship exists between temperature and the line diameter (CD) of the organic mask bottom: as temperature increases, sidewall adhesion decreases, lateral etching strengthens, and line CD decreases; conversely, as temperature decreases, sidewall adhesion increases, lateral etching weakens, and line CD increases. This qualitative relationship is applied to the oxide etching step in SADP or SAQP, as illustrated in the process diagram below. Figure 6 As shown, by Figure 6 The final morphology of the wafer leads to the following conclusions: as the temperature decreases, the Core CD remains unchanged, while the Gap CD decreases; correspondingly, as the temperature increases, the Core CD remains unchanged, while the Gap CD increases.
[0054] Based on the above conclusions, in this embodiment, when performing oxide etching on a wafer placed on a partitioned chuck, the temperature difference between any two partitions of the partitioned chuck is set to be greater than zero. After the wafer completes the self-aligned patterning process, the feature size of the gaps on the wafer will be positively correlated with the temperature of the corresponding partition on the partitioned chuck, while the feature size of the core area of each region on the wafer will be approximately the same, and basically consistent with the feature size of the core area formed when the partitioned chuck is used at the reference temperature in the oxide etching step.
[0055] The relationship between the characteristic dimensions of the core region and the characteristic dimensions of the gap at the reference temperature can be determined according to the following conditions:
[0056] A. When the highest temperature of the partition disk is equal to the base temperature, sort the partitions of the partition disk in order of decreasing temperature. The temperature gradually decreases, the core CD remains unchanged, while the gap CD gradually shrinks.
[0057] If the IMB gradually decreases, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots gradually decreases, it indicates that at the reference temperature, the core CD is smaller and the gap CD is larger. Therefore, the IMB is optimized after the gap CD decreases.
[0058] If the IMB gradually increases, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots gradually increases, it indicates that at the reference temperature, the core CD is larger and the gap CD is smaller. Therefore, as the gap CD decreases, the IMB deteriorates.
[0059] If the IMB first decreases and then increases, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots first decreases and then increases, it indicates that at the reference temperature, the core CD is smaller and the gap CD is larger, but the difference between the two is not significant. Therefore, after the gap CD decreases, the IMB is optimized. However, when the chuck temperature drops to a certain lower temperature, the gap CD becomes too small, causing the absolute value of the difference in characteristic dimensions between two adjacent empty slots to gradually increase, and the IMB will become worse and worse.
[0060] B. When the minimum temperature of the partition disk is equal to the reference temperature, sort the partitions of the partition disk in order of increasing temperature. The temperature gradually increases, the core CD remains unchanged while the gap CD gradually increases.
[0061] If the IMB gradually decreases, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots gradually decreases, it indicates that at the reference temperature, the core CD is large and the gap CD is small. Therefore, the IMB is optimized after the gap CD increases.
[0062] If the IMB gradually increases, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots becomes larger, it indicates that at the reference temperature, the core CD is smaller and the gap CD is larger. Therefore, as the gap CD increases, the IMB deteriorates.
[0063] If the IMB first decreases and then increases, that is, the absolute value of the difference in feature size between two adjacent empty slots first decreases and then increases, it indicates that at the reference temperature, the core CD is larger and the gap CD is smaller, but the difference between the two is not significant. Therefore, after the gap CD increases, the IMB is optimized. However, when the chuck temperature rises to a certain higher temperature, the gap CD becomes too large, causing the absolute value of the difference in feature size between two adjacent empty slots to gradually increase, and the IMB will become worse and worse.
[0064] C. When the reference temperature is between the lowest and highest temperatures, the partitions of the partition disk are sorted in order of increasing temperature. As the temperature gradually increases, the core CD remains unchanged while the gap CD gradually increases in size.
[0065] If the IMB gradually decreases, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots becomes smaller, it indicates that at the reference temperature, the core CD is larger and the gap CD is smaller. Therefore, the IMB is optimized after the gap CD increases.
[0066] If the IMB gradually increases, that is, the difference in characteristic dimensions between two adjacent empty slots becomes larger, it indicates that at the reference temperature, the core CD is smaller and the gap CD is larger. Therefore, as the gap CD increases, the IMB deteriorates.
[0067] If the IMB gradually decreases between the minimum and reference temperatures and gradually increases between the reference and maximum temperatures, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots gradually decreases between the minimum and reference temperatures and gradually increases between the reference and maximum temperatures, it indicates that at the reference temperature, the core CD and gap CD are of similar size. Therefore, regardless of whether the gap CD becomes larger or smaller, the IMB will deteriorate.
[0068] In summary, this embodiment, employing the aforementioned method, can determine the characteristic dimensional relationship between the core region and the gap of a wafer through a single experiment. This allows for rapid localization of IMB issues at the reference temperature, improving the efficiency of process debugging. Furthermore, it eliminates the need for wafer slicing observation; the experimental wafer can continue fabrication and be used for subsequent process debugging, reducing debugging costs. In addition, using a partitioned chuck and setting a temperature gradient better reflects the trend of IMB changes with temperature. Especially when the core CD and gap CD are not significantly different at the reference temperature, it can identify the trend of IMB first decreasing and then increasing, greatly reducing the risk of errors introduced by IMB trend reversals and improving the accuracy of the conclusions.
[0069] Once the relationship between Core CD and Gas CD is clarified, IMB performance can be optimized by adjusting the etching gas ratio and temperature. For example, after clarifying that the IMB issue is Core CD > Gap CD, the process tuning direction is to reduce Core CD or increase Gap CD. This can be achieved by reducing the sidewall shielding gas or increasing the temperature during the oxide etching step to increase Gap CD and thus optimize IMB.
[0070] Preferably, the partitions of the partitioned chuck are arranged radially from the center outwards, and the temperature of the partitions is set to gradually decrease or increase from the inside outwards. Thus, the trend of IMB variation with wafer radius can be analyzed based on the measured location of the slot, which facilitates the summary and analysis of the measurement data of the characteristic dimensions of the slot.
[0071] During photolithography, each chip has measurement patterns left in its corners for measuring the feature size and depth of the slots. This avoids directly measuring the device area and affecting chip yield. More data is available closer to the wafer edge, and less closer to the wafer center. Therefore, it is preferable to set the temperature of the innermost partition of the partitioned chuck to match the reference temperature. Only a small amount of measurement data is needed in the innermost partition for qualitative analysis to determine if the center's performance matches the reference. In other words, quantitative analysis of the measurement data in the innermost partition is unnecessary to determine the IMB (Integrated Motion Scale) trend, avoiding data errors due to insufficient measurement data. In contrast, more measurement data can be obtained in other partitions of the partitioned chuck, facilitating the acquisition of more significant IMB trends and enabling precise localization of IMB issues at the reference temperature.
[0072] The aforementioned determination steps may specifically include: under the condition that the temperature of the partitioned chuck gradually decreases from the inside to the outside, the feature dimensions of the core region in each part of the wafer are basically the same, while the feature dimensions of the gaps gradually decrease from the center to the edge of the wafer. If the feature dimension balance gradually decreases or first decreases and then increases from the center to the edge of the wafer, it can be determined that at the reference temperature, the feature dimensions of the core region are smaller than the feature dimensions of the gaps. Therefore, as the feature dimensions of the gaps decrease, the IMB is optimized. If the feature dimension balance gradually increases from the center to the edge of the wafer, it can be determined that at the reference temperature, the feature dimensions of the core region are larger than the feature dimensions of the gaps. Therefore, as the feature dimensions of the gaps decrease, the IMB deteriorates. In this way, the relationship between the feature dimensions of the core region and the gaps of the wafer can be quickly determined, thereby rapidly locating the IMB problem at the reference temperature.
[0073] The aforementioned determination step may further include: under the condition that the temperature of the partitioned chuck gradually increases from the inside to the outside, the feature dimensions of the core region in each part of the wafer are basically the same, while the feature dimensions of the gaps gradually increase from the center to the edge of the wafer. If the feature dimension balance gradually decreases or first decreases and then increases from the center to the edge of the wafer, it can be determined that at the reference temperature, the feature dimensions of the core region are larger than the feature dimensions of the gaps. Therefore, after the feature dimensions of the gaps increase, the IMB is optimized. If the feature dimension balance gradually increases from the center to the edge of the wafer, it can be determined that at the reference temperature, the feature dimensions of the core region are larger than the feature dimensions of the gaps. Therefore, after the feature dimensions of the gaps increase, the IMB deteriorates. In this way, the relationship between the feature dimensions of the core region and the gaps of the wafer can be quickly determined, thereby rapidly locating the IMB problem at the reference temperature.
[0074] The aforementioned partitioned chuck may include several partitions, such as the inner zone, middle inner zone, middle outer zone, and outer zone, which are distributed radially from the center outwards. This type of partitioned chuck can not only accurately locate IMB problems at the reference temperature, but also avoid interference between adjacent zones due to too many partitions. In addition, the hardware configuration is relatively simple and easy to mass-produce.
[0075] Typically, the central partition of a wafer corresponding to a partition chuck has only about 4 to 8 measurement patterns, the inner partition has about 6 to 15 measurement patterns, the outer partition has about 15 to 26 measurement patterns, and the edge partition has about 27 to 35 measurement patterns.
[0076] Specifically, the temperature difference between two adjacent partitions of a partitioned chuck can be set to less than or equal to 5°C to accommodate the chuck hardware configuration (such as electrostatic adsorption chuck heaters and cooling systems) in related technologies.
[0077] It is preferable to set the temperature difference between two adjacent partitions of the partitioned chuck to 4°C, so as to balance the actual capabilities of the chuck hardware with more significant experimental results. Figure 7 The following is a trend distribution chart of IMB under the following temperature conditions: The base temperature is 50°C; when using a partitioned chuck, the temperature of each partition is 50°C; the temperature of the center partition is 50°C, the temperature of the inner-middle partition is 46°C, the temperature of the outer-middle partition is 42°C, and the temperature of the edge partition is 38°C. The vertical axis represents the IMB value, and the horizontal axis represents the wafer radius corresponding to the IMB. Test IMB is the IMB under the temperature conditions of this embodiment, and Baseline IMB is the IMB at the base temperature. Figure 7It can be seen that from the center to the edge of the wafer, the IMB increases as the temperature decreases, indicating that the Gap CD gradually increases from the center to the edge of the wafer. The problem with IMB is that the Gap CD is larger than the Core CD. The direction of process tuning is to increase the Core CD or decrease the Gap CD. This can be achieved by increasing the sidewall protective gas or lowering the temperature in the oxide etching step to reduce the Gap CD and optimize IMB.
[0078] The above acquisition steps may specifically include: measuring the characteristic dimensions of multiple slots and determining the correspondence between the characteristic dimensions of each slot and the measurement position; dividing two adjacent slots into a group based on the correspondence; and subtracting the characteristic dimensions of two slots in each group and taking the absolute value to obtain the balance of multiple characteristic dimensions and their corresponding positions. Using this method for data measurement, statistics, and analysis is highly efficient.
[0079] Specifically, the characteristic dimensions of several empty slots obtained through measurement can include coordinates. During subsequent data processing, the coordinates can be used to determine which partition of the data partitioning chuck is the center partition, inner partition, outer partition, or edge partition, and the characteristic dimension balance of each partition can be calculated accordingly.
[0080] Specifically, the characteristic dimensions of the empty slot can be measured using a feature-size scanning electron microscope, resulting in high data measurement accuracy and enabling precise location of IMB problems at the reference temperature.
[0081] The aforementioned partition chuck is specifically an electrostatic adsorption chuck.
[0082] Figure 8 An embodiment of the present invention provides a method for evaluating the feature dimensions of a semiconductor device, the method comprising:
[0083] S202, Processing step: The wafer is placed in a chuck, and multiple empty slots are obtained by processing the wafer through a self-aligned patterning process; In the oxide etching step of the self-aligned patterning process, the temperature of the chuck is higher or lower than the reference temperature.
[0084] S204, Acquisition step, acquire the feature size balance of the wafer; wherein, the feature size balance is the absolute value of the feature size difference between two adjacent slots, and the slots include the core area and the gaps;
[0085] S206, Determine the relationship between the feature dimensions of the core area and the feature dimensions of the gap at the reference temperature, based on the chuck temperature and feature dimension balance.
[0086] The relationship between the characteristic dimensions of the core region and the characteristic dimensions of the gap at the reference temperature can be determined according to the following conditions:
[0087] A, when the chuck temperature is lower than the reference temperature.
[0088] If the IMB after temperature adjustment is lower than the IMB at the reference temperature, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots becomes smaller, it indicates that at the reference temperature, the core CD is smaller and the gap CD is larger. Therefore, the IMB is optimized after the gap CD becomes smaller.
[0089] If the IMB after temperature adjustment is higher than the IMB at the reference temperature, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots becomes smaller, it indicates that at the reference temperature, the core CD is larger and the gap CD is smaller. Therefore, after the gap CD becomes smaller, the IMB deteriorates.
[0090] A, when the chuck temperature is higher than the reference temperature.
[0091] If the IMB after temperature adjustment is lower than the IMB at the reference temperature, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots gradually decreases, it indicates that at the reference temperature, the core CD is larger and the gap CD is smaller. Therefore, the IMB is optimized after the gap CD increases.
[0092] If the IMB after temperature adjustment is higher than the IMB at the reference temperature, that is, the absolute value of the difference in characteristic dimensions between two adjacent empty slots becomes larger, it indicates that at the reference temperature, the core CD is smaller and the gap CD is larger. Therefore, after the gap CD becomes larger, the IMB deteriorates.
[0093] In summary, the method described in this embodiment can quickly determine the characteristic dimensional relationship between the core area and the gap of the wafer, thereby rapidly locating the IMB problem at the reference temperature, improving the efficiency of process debugging, and reducing the cost of process debugging.
[0094] An embodiment of the present invention provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are invoked and executed by a processor, the machine-executable instructions cause the processor to implement the feature size balance determination method in the above-described self-aligned patterning process.
[0095] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described equipment and apparatus can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0096] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0097] In the description of this invention, it should be noted that the terms "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0098] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for evaluating the feature dimensions of a semiconductor device, characterized in that, The method includes: In the processing step, the wafer is placed in a partitioned chuck, and the wafer is processed using a self-aligned patterning process to obtain multiple empty slots. In the oxide etching step of the self-aligned patterning process, the temperature difference between any two partitions of the partitioned chuck is greater than zero, the highest temperature of the partitioned chuck is higher than or equal to the reference temperature, and the lowest temperature of the partitioned chuck is lower than or equal to the reference temperature. The empty slots include core regions and gaps. After the self-aligned patterning process is completed, the feature size of the gaps is positively correlated with the temperature of the corresponding partition on the partitioned chuck. The feature size of each core region is substantially consistent with the feature size of the core region formed when the partitioned chuck is etched at the reference temperature in the oxide etching step. In the acquisition step, the feature size balance degree of each partition of the wafer is acquired; wherein, the feature size balance degree is the absolute value of the difference in feature size between two adjacent slots; In the determination step, based on the temperature of each partition of the partitioned chuck and the corresponding characteristic dimension balance, the size relationship between the characteristic dimension of the core area and the characteristic dimension of the gap is determined at the reference temperature. The feature size balance is sorted in order of increasing temperature of the corresponding partition. If the feature size balance gradually decreases, it is determined that the feature size of the core area is greater than the feature size of the gap at the reference temperature. If the feature size balance gradually increases, it is determined that the feature size of the core area is smaller than the feature size of the gap at the reference temperature.
2. The method for evaluating the feature dimensions of semiconductor devices according to claim 1, characterized in that, The partitions are radially distributed from the center of the partition chuck outwards, and the temperature of the partitions gradually decreases or increases from the inside outwards.
3. The method for evaluating the feature dimensions of semiconductor devices according to claim 2, characterized in that, The temperature of the innermost partition is consistent with the reference temperature.
4. The method for evaluating the feature dimensions of a semiconductor device according to claim 3, characterized in that, The determining step includes: Under the condition that the temperature of the partition chuck gradually decreases from the inside to the outside, if the feature size balance gradually decreases or first decreases and then increases from the center of the wafer to the edge, it is determined that at the reference temperature, the feature size of the core region is smaller than the feature size of the gap; if the feature size balance gradually increases from the center of the wafer to the edge, it is determined that at the reference temperature, the feature size of the core region is larger than the feature size of the gap. Under the condition that the temperature of the partition chuck gradually increases from the inside to the outside, if the feature size balance gradually decreases or first decreases and then increases from the center of the wafer to the edge, it is determined that at the reference temperature, the feature size of the core region is greater than the feature size of the gap; if the feature size balance gradually increases from the center of the wafer to the edge, it is determined that at the reference temperature, the feature size of the core region is greater than the feature size of the gap.
5. The method for evaluating the feature dimensions of a semiconductor device according to claim 1, characterized in that, The partitions include a central partition, an inner-middle partition, an outer-middle partition, and an edge partition, which are distributed radially from the center of the partition chuck outwards.
6. The method for evaluating the feature dimensions of a semiconductor device according to claim 1, characterized in that, The temperature difference between two adjacent partitions of the partition chuck is less than or equal to 5°C.
7. The method for evaluating the feature dimensions of a semiconductor device according to claim 6, characterized in that, The temperature difference between two adjacent partitions of the partition chuck is 4°C.
8. The method for evaluating the feature dimensions of a semiconductor device according to any one of claims 1-7, characterized in that, The acquisition step includes: Measure the feature dimensions of multiple empty slots and determine the correspondence between the feature dimensions of each empty slot and the measurement position; Based on the aforementioned correspondence, two adjacent empty slots are grouped together; The difference between the characteristic dimensions of the two empty slots in each group is calculated and the absolute value is taken to obtain the balance of multiple characteristic dimensions and their corresponding positions.
9. The method for evaluating the feature dimensions of a semiconductor device according to claim 8, characterized in that, The acquisition step includes: The characteristic dimensions of the empty slot were measured using a feature-dimension scanning electron microscope.
10. A method for evaluating the feature dimensions of a semiconductor device, characterized in that, The method includes: In the processing step, the wafer is placed in a chuck, and a self-aligned patterning process is used to process the wafer to obtain multiple slots. In the oxide etching step of the self-aligned patterning process, the temperature of the chuck is higher or lower than a reference temperature. The slots include a core region and gaps. After the self-aligned patterning process is completed, the feature size of the gaps is positively correlated with the temperature of the chuck, and the feature size of the core region is basically the same as the feature size of the core region formed when the chuck is etched at the reference temperature in the oxide etching step. In the acquisition step, the feature size balance of the wafer is acquired; wherein, the feature size balance is the absolute value of the difference in feature size between two adjacent slots; In the determination step, based on the temperature of the chuck and the balance of the feature dimensions, the size relationship between the feature dimensions of the core area and the feature dimensions of the gap is determined at the reference temperature. If the characteristic dimension balance after temperature adjustment is lower than the characteristic dimension balance at the reference temperature, it indicates that the characteristic dimension of the core area is smaller than the characteristic dimension of the gap at the reference temperature; if the characteristic dimension balance after temperature adjustment is higher than the characteristic dimension balance at the reference temperature, it indicates that the characteristic dimension of the core area is larger than the characteristic dimension of the gap at the reference temperature. If the characteristic dimension balance after temperature adjustment is lower than the characteristic dimension balance at the reference temperature when the chuck temperature is higher than the reference temperature, it indicates that the characteristic dimension of the core area is larger than the characteristic dimension of the gap at the reference temperature; if the characteristic dimension balance after temperature adjustment is higher than the characteristic dimension balance at the reference temperature, it indicates that the characteristic dimension of the core area is smaller than the characteristic dimension of the gap at the reference temperature.