Apparatus with multiple vertical cavity surface emitting lasers
By using alternating row contacts and multi-layer RDL connections, the design complexity and irregularity of multi-channel VCSEL arrays are solved, the manufacturing process is simplified, and the performance and reliability of the transmitter are improved.
Patent Information
- Application Number
- CN202411326955.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-26
- Filing Date
- 2024-09-23
- Publication Date
- 2025-12-16
AI Technical Summary
Existing technologies struggle to effectively design and manufacture multi-channel vertical cavity surface-emitting laser arrays with hybrid and irregular positioning, resulting in issues such as processing complexity, emitter power non-uniformity, and dielectric breakdown.
The design and manufacturing of multi-channel VCSEL arrays are simplified by using alternating row contact design and multi-layer redistribution layer (RDL) connection, which combines ohmic contacts and top RDL. The number of RDLs is reduced by connecting transmitters in an interleaved configuration.
This simplifies the design and manufacturing of multi-channel VCSEL arrays, improves the pulse velocity and power uniformity of the transmitter, and reduces the risk of dielectric breakdown.
Smart Images
Figure CN121149784A_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 659,567, filed June 13, 2024, entitled “METHODS FOR AND SYSTEM OF VERTICAL CAVITYSURFACE EMITTING LASERS ARRAYS,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field
[0003] This disclosure relates to systems and methods for addressing vertical cavity surface-emitting lasers (VCSELs). Background Technology
[0004] By comparing these methods with some aspects of the current methods and systems set forth in the remainder of this disclosure, with reference to the accompanying drawings, the limitations and disadvantages of conventional systems and methods for addressing vertical cavity surface-emitting lasers (VCSELs) will become apparent to those skilled in the art. Summary of the Invention
[0005] Systems and methods for addressing vertical cavity surface-emitting lasers (VCSELs) are proposed, substantially as shown in at least one of the accompanying drawings and / or described in combination with them, as set forth more fully in the claims. Attached Figure Description
[0006] Figure 1 Examples of Ohm RDLs in systems including independently addressable VCSELs according to various exemplary embodiments of this disclosure are shown.
[0007] Figure 2 Examples of insulating layers in a system including a stand-alone addressable VCSEL according to various exemplary embodiments of the present disclosure are shown.
[0008] Figure 3 Examples of a first address layer in a system including a stand-alone addressable VCSEL according to various exemplary embodiments of the present disclosure are shown.
[0009] Figure 4 Examples of top RDLs in systems including independently addressable VCSELs according to various exemplary embodiments of this disclosure are shown.
[0010] Figure 5 Examples of cross-sections of systems including independently addressable VCSELs according to various exemplary embodiments of the present disclosure are shown.
[0011] Figure 6 Another example of a system including independently addressable VCSELs according to various example embodiments of the disclosure is shown. DETAILED DESCRIPTION
[0012] Vertical Cavity Surface Emitting Laser (VCSEL) arrays can be used for three- dimensional sensing applications. The present disclosure describes VCSEL array designs with multiple independent channels (or sub-arrays). VCSEL emitters of different channels can be mixed and positioned in irregular (e.g., random or semi-random) locations.
[0013] Multi-channel regular arrays can be relatively simple in design and processing, and thus can be single-channel irregular arrays. However, irregular arrays with multiple independent and mixed channels tend to be more complex in design and / or processing.
[0014] The present disclosure presents systems and methods for designing multi-channel arrays with mixed and irregularly positioned emitters, while maintaining the relative simplicity enjoyed by multi-channel arrays with alternating row contacts in layout, processing, and design rules.
[0015] Multi-channel VCSEL arrays can have sub-arrays of emitters that are physically isolated from each other, or mixed in the form of alternating row contacts. These alternating row contact designs typically place a row of emitters within the center of the row contact. As a result, they tend to have regular emitter positions and the emitters are not fully mixed.
[0016] Addressable VCSEL arrays can include arrays of emitters arranged in one- dimensional (e.g., rows or columns), two-dimensional, or three-dimensional configurations. The emitters in the array can be arranged such that emitters belonging to different channels are spatially separated and / or interleaved within the array locations.
[0017] In interleaved configurations, emitters belonging to different arrays are connected via multiple layers of redistribution layers (RDLs), with one RDL assigned to one array channel. The RDLs can be routed and overlaid to connect to the individual ohmic contacts of the VCSELs, resulting in the desired interleaved pattern.
[0018] The present disclosure describes methods for multi-channel, interleaved VCSEL arrays, where ohmic RDLs and RDLs can be used in combination to connect assigned emitters together. This minimizes the number of RDLs required, thus simplifying the design and fabrication of the device.
[0019] Multi-channel VCSEL arrays with hybrid emitters and irregular emitter locations can use vertical stacked mesa contacts. While these solutions are able to achieve significant hybridization and irregularity in the emitter locations, the processing and layout requirements tend to be more complex to ensure effective isolation between different channels, and there are concerns about capacitance between parallel mesa contacts (which can potentially limit the pulse speed of these arrays), emitter power uniformity (as lower mesa contacts can have significantly different series resistance to different emitters), and dielectric breakdown (as lower mesa contacts introduce additional topology).
[0020] The present disclosure relates to the design of individual vertical cavity surface emitting lasers (VCSELs) and methods of positioning and electrically contacting them in arrays. Such VCSEL arrays can be used for three-dimensional sensing, for example.
[0021] Figure 1 An example of ohmic RDL in a system including individually addressable VCSELs according to various example embodiments of the present disclosure is shown.
[0022] Figure 1 The device of includes a plurality of VCSELs, showing emitters 101 and emitters 103 for each VCSEL. Each VCSEL of the plurality of VCSELs includes an emitter aperture that can have, for example, a diameter between 10 microns and 15 microns. Each VCSEL of the plurality of VCSELs is operable to emit light (e.g., infrared light) of a particular wavelength (e.g., no greater than 1000 nanometers).
[0023] Figure 1 The bottom / ohmic RDL in includes a first continuous metal surface 102 and one or more discrete metal surfaces 104. Each VCSEL of the plurality of VCSELs is connected to either the ohmic contact metal 102 or the ohmic contact metal 104 of the bottom RDL.
[0024] The first continuous metal surface 102 is capable of electrically coupling a first set of VCSELs (e.g., VCSELs with emitters 103) to a first bond pad (see Figures 3 to 5 Channel B is formed by the first set of VCSELs (including emitter B 103) as shown in FIG. 1 15. The second set of VCSELs (including emitter A 101) forms Channel A.
[0025] Each discrete metal surface 104 is capable of electrically coupling one VCSEL of a second set of VCSELs (e.g., VCSELs with emitters 101) to a second bond pad (see Figures 3 to 5of 111). As shown, the second set of VCSELs (including emitter A 101) forms channel A. Each VCSEL in the second set of VCSELs is connected to a different discrete metal surface 104 in the bottom RDL. Each different discrete metal surface 104 is coupled to a different VCSEL via hole 105. Each discrete metal surface 104 in the bottom RDL is physically separated 106 from the first continuous metal surface 102. The physical separation can be between 1.5 microns and 2 microns.
[0026] In different example embodiments, the first set of VCSELs and the second set of VCSELs each include one or more of a plurality of VCSELs. For purposes of illustration, Figures 1 to 5 The first set of VCSELs and the second set of VCSELs are shown as each being one VCSEL. Figure 6 The first set of VCSELs and the second set of VCSELs are shown as each being more than one VCSEL.
[0027] Figure 2 An example of an insulating layer 109 in a system including independently addressable VCSELs 101 and 103 according to various example embodiments of the present disclosure is shown. The insulating layer 109 (including, for example, SiO2and / or SiN) can electrically separate the bottom RDL (see Figure 1 of 102 and 104) from the top RDL (see Figure 4 of 113) in Figure 5 The set of VCSEL via holes 105 and the first bond pad via holes 107 extend through the insulating layer 109.
[0028] Figure 3 An example of a first address layer in a system including independently addressable VCSELs according to various example embodiments of the present disclosure is shown. The first bond pad 115 is physically connected to (and on top of) the insulating layer 109 and electrically coupled to the first set of VCSELs (including emitter B 103) through the via holes 107 and the first continuous metal surface 102.
[0029] Figure 4 An example of a top RDL 113 in a system including independently addressable VCSELs according to various example embodiments of the present disclosure is shown.
[0030] The second bond pad (bond pad A 111) is physically connected to the top RDL 113. The top RDL 113 is operable to electrically couple the second group of VCSELs 101 to the second bond pad 111 through the group of VCSEL vias 105. The second group of VCSELs 101 includes one or more of the plurality of VCSELs. The first group of VCSELs 103 includes different VCSELs than the second group of VCSELs 101. Each VCSEL in the second group of VCSELs 101 is electrically coupled to a corresponding VCSEL via 105 in the group of VCSEL vias.
[0031] Figure 5 An example of a cross-section of a system including independently addressable VCSELs is shown in accordance with various example embodiments of the present disclosure.
[0032] The bottom RDL 123 includes ohmic contact metal dedicated and designated to connect each emitter to a designated channel of the emitter array. The plurality of RDLs are then connected to the bond pads 111 or 115 of the device. For each emitter in the plurality of VCSELs 101 and 103, the optical path 117 and 119 passes through the aperture.
[0033] The emitters A 101 and B 103 are connected to the bottom RDL 123. The bottom RDL 123 is connected directly to the bond pads 115 bypassing the top RDL 113. As shown in Figure 1 The bottom RDL 123 includes a continuous metal surface 102 and a discrete metal surface 104 as shown in
[0034] This approach, where the bottom RDL is used for addressability, reduces the number of RDL layers used to implement the staggered address VCSEL design, thereby simplifying the process flow.
[0035] Figure 6 Another example of a system including independently addressable VCSELs is shown in accordance with various example embodiments of the present disclosure.
[0036] Figure 6 The plurality of VCSELs in the device 601 includes three channel groups. Channel A addresses the group of devices A 601 using bond pad A 607. Channel B addresses the group of devices B 603 using bond pad B 609. Channel C addresses the group of devices C 605 using bond pad C 611. All VCSELs within a particular channel (e.g., A, B, or C) are driven simultaneously.
[0037] The group of device B 603 and the group of device C 605 are each coupled to a different continuous metal surface in the bottom RDL. As shown, the plurality of VCSELs are positioned randomly. Also, the number of VCSELs within each particular channel / group (e.g., A, B, or C) can not need to be the same. For example, in some implementations, the number of VCSELs in one group can be more than ten times the number of VCSELs in another group.
[0038] As used in the present disclosure, the terms "circuit" and "circuitry" refer to physical electronic components (i.e. hardware) and any software and / or firmware (code) which can configure the hardware, execute with the hardware, and / or otherwise be associated with the hardware as it is fabricated. As used in the present disclosure, for example, a particular processor and memory can comprise a first "circuit" when executing a first one or more lines of code and can comprise a second "circuit" when executing a second one or more lines of code. As used in the present disclosure, "and / or" means any one or more of the listed terms. As an example, "x and / or y" means any element of the three-element set {(x), (y), (x, y)}. As another example, "x, y, and / or z" means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As used in the present disclosure, the term "exemplary" means serving as a non-limiting example, instance, or illustration. As used in the present disclosure, the terms "for example" and "e.g." list one or more non-limiting examples, instances, or illustrations. As used in the present disclosure, a circuit "operable" to perform a function means that hardware and code required to perform the function, if any, are present and enabled to perform the function, regardless of whether execution of the function is disabled or not enabled (e.g., by a user-configurable setting, factory trim, etc.). As used in the present disclosure, the term "based on" means "based, at least in part, on." For example, "x is based on y" means that "x" is based, at least in part, on "y" (and can also be based on z, for example).
[0039] While the current method and / or system has been described with reference to certain implementations, it is understood that modifications can be made without departing from the scope of the current method and / or system. Additionally, many modifications can be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is understood that the current method and / or system is not limited to the specific implementations disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims.
Claims
1. An apparatus having multiple vertical-cavity surface-emitting lasers, the apparatus comprising: Multiple vertical cavity surface-emitting lasers (VCSELs); The bottom redistribution layer RDL is operable to electrically couple the first set of VCSELs to the first bonding pad through the first bonding pad via the first bonding pad via. The top RDL is operable to electrically couple a second set of VCSELs to a second bonding pad via the VCSEL vias. as well as An insulating layer operable to electrically decouple the bottom RDL from the top RDL, wherein: The first group of VCSELs includes one or more VCSELs from a plurality of VCSELs. The second group of VCSELs includes one or more VCSELs from the plurality of VCSELs. The first group of VCSELs includes VCSELs that are different from the second group of VCSELs, and Each VCSEL in the second group is electrically coupled to the corresponding VCSEL via in the group of VCSEL vias.
2. The device according to claim 1, wherein: Each of the plurality of VCSELs includes an emitter aperture with a diameter of less than 15 micrometers.
3. The device according to claim 1, wherein: Each of the plurality of VCSELs is operable to emit light in the infrared spectrum.
4. The device according to claim 1, wherein: Each of the plurality of VCSELs is connected to an ohmic contact metal in the bottom RDL.
5. The device according to claim 1, wherein: Each VCSEL in the first group of VCSELs is connected to a first continuous metal surface in the bottom RDL.
6. The device according to claim 5, wherein: The first continuous metal surface is electrically coupled to the first bonding pad via.
7. The device according to claim 5, wherein: Each VCSEL in the second group is connected to a discrete metal surface in the bottom RDL.
8. The device according to claim 7, wherein: Each discrete metal surface connected to each VCSEL in the second group of VCSELs is electrically coupled to the corresponding VCSEL via.
9. The device according to claim 7, wherein: Each discrete metal surface in the bottom RDL is physically separated from the first continuous metal surface.
10. The device according to claim 9, wherein: The physical spacing is between 1.5 micrometers and 2 micrometers.
11. The device according to claim 1, wherein: The group of VCSEL vias and the first bonding pad via extend through the insulating layer.
12. The device according to claim 1, wherein: The first bonding pad is physically connected to the insulating layer.
13. The device according to claim 1, wherein: The second bonding pad is physically connected to the top RDL.
14. The device according to claim 1, wherein: The optical path of each of the plurality of VCSELs passes through the insulating layer and the top RDL.
15. The device according to claim 1, wherein: The bottom RDL is operable to electrically couple a third set of VCSELs to a third bonding pad via a second bonding pad via.
16. The device according to claim 15, wherein: Each VCSEL in the third group is connected to the second continuous metal surface of the bottom RDL.
17. The apparatus according to claim 16, wherein: The second continuous metal surface is electrically coupled to the second bonding pad via.
18. The device according to claim 1, wherein: The multiple VCSELs are placed randomly.
19. The device according to claim 1, wherein: The second group of VCSELs includes more than ten times the number of VCSELs in the first group of VCSELs.