A harmonic extraction method and device based on an improved quadrature phase shift keying loop, a terminal and a medium

Abstract

This invention discloses a harmonic extraction method, apparatus, terminal, and medium based on an improved quadrature phase-locked loop (QPL). The method includes: acquiring three-phase voltage signals and preprocessing them; calculating frequency fluctuations based on the fundamental frequency tracked by a quadrature signal generator; generating quadrature signals by processing the preprocessed signals using the quadrature signal generator based on a damping coefficient; performing notch filtering on the preprocessed signals and the quadrature signals to optimize the damping coefficients; performing Park transform on the preprocessed signals and the quadrature signals, and outputting fundamental parameters through a PI controller; configuring a center angular frequency for each harmonic component to be extracted based on the fundamental parameters, and calculating the harmonic amplitude and phase. This invention improves the fundamental phase-locked loop's anti-interference capability through an improved quadrature signal generator, reduces fundamental phase-locking errors, and avoids extraction deviations caused by frequency fluctuations.

Description

Technical Field

[0001] This invention relates to the field of power technology, and in particular to a harmonic extraction method, apparatus, terminal and medium based on an improved orthogonal phase-locked loop. Background Technology

[0002] With the widespread application of power electronic equipment in industrial and civilian fields, the problem of power grid harmonic pollution has become increasingly prominent. Harmonics not only cause additional losses in equipment such as transformers and motors, but may also lead to problems such as relay protection malfunctions and power metering deviations. Therefore, accurate harmonic detection technology has become a core support for power system power quality management. Current harmonic detection methods mainly rely on Fast Fourier Transform (FFT) and its improved algorithms. Although they perform well in steady-state harmonic analysis, their spectral leakage and picket fence effects significantly reduce measurement accuracy under frequency fluctuations or non-steady-state harmonic conditions. To overcome the limitations of FFT, harmonic extraction methods based on phase-locked loops (PLLs) have gradually become a research hotspot. In particular, orthogonal PLL structures are widely used for harmonic separation in synchronous reference coordinate systems because they can generate orthogonal signals and achieve frequency adaptive tracking. In recent years, scholars have proposed various improved QPLL structures, such as QPLLs based on dual second-order generalized integrators and adaptive filter QPLLs. By introducing feedforward compensation, frequency adaptive loops, or multi-stage filtering strategies, the dynamic response speed and anti-interference capability of harmonic extraction have been improved to a certain extent. However, existing QPLL methods still face many challenges in complex power grid environments, such as phase tracking lag during frequency abrupt changes, amplitude estimation errors caused by harmonic coupling, and insufficient stability under low signal-to-noise ratio conditions.

[0003] Although existing QPLL technology achieves preliminary separation of the fundamental and harmonic frequencies through orthogonal signal generation, its performance is still limited by insufficient frequency fluctuation suppression and design flaws related to fixed damping characteristics. Firstly, traditional QPLL frequency loops typically employ proportional-integral controllers (PI controllers), which struggle to balance tracking speed and stability when the grid frequency changes dynamically, leading to phase errors during harmonic extraction and consequently affecting amplitude calculation accuracy. Secondly, existing solutions generally use fixed damping coefficients, which cannot adaptively adjust according to grid conditions, potentially causing system resonance or slow response under disturbances. Furthermore, the engineering practicality of harmonic phase calculation is lacking. Existing technologies often directly calculate the absolute phase of harmonics without combining the fundamental phase to generate a relative phase difference. Compensation devices such as APF (Active Power Filter) require generating an anti-phase compensation current based on the relative phase difference between harmonics and the fundamental, resulting in a disconnect between detection results and engineering application requirements. Most importantly, traditional QPLL structures lack mechanisms to suppress harmonic frequency drift. Their notch filters are typically designed with fixed bandwidth, making it difficult to effectively suppress interference components other than specific harmonics when frequencies fluctuate, leading to a decrease in harmonic extraction purity. These problems severely limit the application effectiveness of existing technologies in high-quality demand scenarios. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this invention provides a harmonic extraction method based on an improved quadrature phase-locked loop (QPL), characterized by comprising: acquiring three-phase voltage signals and preprocessing them; calculating frequency fluctuations based on the fundamental frequency tracked by a quadrature signal generator; generating quadrature signals by processing the preprocessed signals based on a damping coefficient and through the quadrature signal generator; performing notch filtering on the preprocessed signals and the quadrature signals to optimize the damping coefficient; performing Park transform on the notch-filtered signals and the quadrature signals, and outputting fundamental parameters through a PI controller; configuring a center angular frequency for each harmonic component to be extracted based on the fundamental parameters, and calculating the harmonic amplitude and phase.

[0005] As a preferred embodiment of the harmonic extraction method based on the improved quadrature phase-locked loop described in this invention, the preprocessing includes: separating and removing the negative sequence component from the three-phase voltage signal using the symmetrical component method to obtain the positive sequence component; and performing Clark transform and wavelet transform processing on the positive sequence component.

[0006] As a preferred embodiment of the harmonic extraction method based on the improved orthogonal phase-locked loop described in this invention, the damping coefficient includes:

[0007] Calculate the frequency fluctuation Δf based on the fundamental frequency f1 tracked by the quadrature signal generator:

[0008] Δf=|f1-50|

[0009] Using the power grid voltage distortion (THD) and frequency fluctuation (Δf) as adjustment dimensions, combined with the load sensitivity (K) in the application scenario variables. load Accuracy requirement correction amount L stab Dynamically calculate the damping coefficient of the orthogonal signal generator:

[0010] k=[0.5+0.15×min(THD,5%)+0.1×min(Δf,1Hz)]×(1+(0.08×K load +0.05×L stab ))

[0011] In the formula, k is the damping coefficient.

[0012] As a preferred embodiment of the harmonic extraction method based on the improved orthogonal phase-locked loop described in this invention, the generation of orthogonal signals includes: the orthogonal signal generator comprising an input preprocessing unit, a second-order integral loop, and an amplitude calibration unit; and the preprocessed α-axis positive sequence signal u at time t... α0 (t) Input the quadrature signal generator, extract the fundamental frequency f1 tracked by the generator from it through the input preprocessing unit, and calculate the proportional feedback coefficient K and the integral time constant according to the damping coefficient k. The positive-sequence signal u along the α-axis is obtained through a second-order integrator circuit. α0 (t) Perform a second integration, and simultaneously compensate for the amplitude through the amplitude calibration unit to generate an orthogonal signal u. q (t); where the proportional feedback coefficient K = k × 2πf1, and the integral time constant is... =1 / (k×2πf1).

[0013] As a preferred embodiment of the harmonic extraction method based on the improved orthogonal phase-locked loop described in this invention, the optimized damping coefficient includes:

[0014] Step 1: From the positive sequence signal u on the α axis α0 (t) and the orthogonal signal u q The positive sequence components of the 2nd to 11th harmonics are separated from (t) to obtain the harmonic parameters;

[0015] Step 2: Calculate the interference intensity based on the harmonic parameters, sort them in descending order of interference intensity exponent, and select the first two as notch targets. If the interference intensity is <0.01, it will not be included in the notch range.

[0016] Step 3: Configure the notch frequency and notch damping coefficient of the notch target with ANF, and perform notch suppression on the harmonic target through a second-order Notch filter to generate the notched α-axis signal u. α0_notch (t) and the orthogonal signal u after notching q_notch(t);

[0017] Step 4: Detect the total amplitude of residual harmonics and set a dynamic threshold. When the total amplitude of residual harmonics is greater than the dynamic threshold, increase the damping coefficient k to enhance the anti-interference capability of the quadrature signal generator; otherwise, do not adjust the damping coefficient k.

[0018] As a preferred embodiment of the harmonic extraction method based on the improved orthogonal phase-locked loop described in this invention, the fundamental parameters include:

[0019] For the α-axis signal u after notch filtering α0_notch (t) and the orthogonal signal u after notching q_notch (t) Perform low-pass filtering to extract the α-axis fundamental signal u α1 (t) and the orthogonal fundamental signal u q1 (t);

[0020] For the α-axis fundamental signal u α1 (t) and the orthogonal fundamental signal u q1 (t) Perform Park transform to generate the fundamental amplitude reference signal u α2 (t) and phase deviation reference signal u q2 (t);

[0021] The fundamental amplitude reference signal u α2 (t) and phase deviation reference signal u q2 (t) Input to the PI controller to output fundamental parameters, including fundamental angular frequency ω0 and fundamental phase θ0.

[0022] As a preferred embodiment of the harmonic extraction method based on the improved orthogonal phase-locked loop described in this invention, the configuration of the center angular frequency includes: inputting the fundamental phase θ0 into the frequency-locked loop and calculating the phase change rate; correcting the fundamental angular frequency ω0 based on the phase change rate to obtain the final fundamental angular frequency ω; and calculating the center angular frequencies ω of each harmonic based on the final fundamental angular frequency ω. h Where h is the target harmonic order; the α-axis signal u after notch filtering is obtained from the filter. α0_notch Extracting the harmonic in-phase component u from (t) h (t), the center frequency of the filter is set to ω. h The filter bandwidth is ≤2Hz; for harmonic in-phase components u h (t) Perform a 90° phase shift to obtain the orthogonal component u z (t); based on the harmonic in-phase component u h (t) and orthogonal component u z (t) Calculate the harmonic amplitude and absolute phase Based on absolute phase Calculate the harmonic phase using the fundamental phase θ0.

[0023] This invention also provides a harmonic extraction device based on an improved quadrature phase-locked loop (QPL), used to implement the harmonic extraction method based on an improved QPL as described in any of the preceding claims. The harmonic extraction device based on the improved QPL includes: an acquisition module configured to acquire three-phase voltage signals and preprocess them; a frequency fluctuation calculation module configured to calculate frequency fluctuations based on the fundamental frequency tracked by a quadrature signal generator; a quadrature signal generation module configured to generate quadrature signals by processing the preprocessed signals based on a damping coefficient and through the quadrature signal generator; a coefficient optimization module configured to perform notch filtering on the preprocessed signals and the quadrature signals to optimize the damping coefficients; a fundamental parameter calculation module configured to perform Park transform on the preprocessed signals and the quadrature signals and output fundamental parameters through a PI controller; and a harmonic extraction module configured to configure a center angular frequency for each harmonic component to be extracted based on the fundamental parameters and calculate the harmonic amplitude and phase.

[0024] The present invention also provides a terminal device, comprising:

[0025] One or more processors;

[0026] A memory, coupled to the processor, for storing one or more programs;

[0027] When the one or more programs are executed by the one or more processors, the one or more processors implement the harmonic extraction method based on the improved quadrature phase-locked loop as described in any of the preceding claims.

[0028] The present invention also provides a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the harmonic extraction method based on the improved quadrature phase-locked loop as described in any of the preceding claims.

[0029] The beneficial effects of this invention are as follows: This invention improves the fundamental phase-locked loop anti-interference capability by using an improved orthogonal signal generator, reduces the fundamental phase-locking error, and dynamically corrects the harmonic center frequency by combining fundamental parameters, avoiding extraction deviation caused by frequency fluctuations. The harmonic amplitude error is ≤0.5%, which meets the requirements of high-precision power quality management. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0031] Figure 1 This is a schematic flowchart of a harmonic extraction method based on an improved orthogonal phase-locked loop according to the first embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the process for generating orthogonal signals according to the first embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the process for calculating harmonic amplitude and harmonic phase according to the first embodiment of the present invention. Detailed Implementation

[0034] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0036] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0037] This invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of this invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0038] Furthermore, in the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," or "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" in this invention should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; similarly, they can refer to mechanical connections, electrical connections, or direct connections, or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] Example 1

[0041] Reference Figures 1-3 This is the first embodiment of the present invention, which provides a harmonic extraction method based on an improved quadrature phase-locked loop, comprising:

[0042] S1: Acquire three-phase voltage signals and preprocess them.

[0043] The three-phase voltage signal u of the 10kV medium-voltage distribution network is acquired by a voltage sensor. a (t), u b (t), u c (t), the negative sequence component is separated and removed from the three-phase voltage signal by the symmetrical component method to obtain the positive sequence component u. a1 (t), u b1 (t), u c1 (t), to avoid the distortion of subsequent orthogonal components caused by negative order components.

[0044] For the positive-order component u a1 (t), u b1 (t), u c1 (t) Perform Clark transform to reduce signal dimensionality, then perform wavelet transform to process the non-harmonic interference signal to obtain the positive sequence signal u on the α axis. α0 (t) and the positive sequence signal u of the β axis β0 (t).

[0045] S2: Calculate the frequency fluctuation based on the fundamental frequency tracked by the quadrature signal generator.

[0046] The orthogonal signal generator includes an input preprocessing unit, a second-order integration loop, and an amplitude calibration unit; it generates the preprocessed α-axis positive sequence signal u at time t. α0 (t) Input the quadrature signal generator, extract the fundamental frequency f1 tracked by the generator from it through the input preprocessing unit, and calculate the frequency fluctuation Δf based on the fundamental frequency f1 tracked by the quadrature signal generator:

[0047] Δf=|f1-50|

[0048] S3: Based on the damping coefficient, the preprocessed signal is processed by an orthogonal signal generator to generate an orthogonal signal.

[0049] Reference Figure 2 Using the grid voltage distortion (THD) and frequency fluctuation (Δf) as adjustment dimensions, and combining the load sensitivity K from the application scenario variables... load Accuracy requirement correction amount L stab Dynamically calculate the damping coefficient k of the orthogonal signal generator:

[0050] k=[0.5+0.15×min(THD,5%)+0.1×min(Δf,1Hz)]×(1+(0.08×K load +0.05×L stab ))

[0051] In the application scenario of the present invention, it is first determined which category the final downstream device belongs to. For example, if it is used for APF compensation, it belongs to high precision requirements, and if it is used for ordinary monitoring, it belongs to ordinary precision requirements.

[0052] Example 1: If integrated into a 10kV distribution network APF, then it corresponds to high precision, L stab =1.5;

[0053] Example 2: If used for power quality monitoring in residential communities, then the corresponding accuracy is L. stab =1.0;

[0054] Example 3: If used for lighting control power supply in a factory workshop, then low precision is required, L stab =0.6.

[0055] Furthermore, the proportional feedback coefficient K and the integral time constant are calculated based on the damping coefficient k. The positive-sequence signal u along the α-axis is obtained through a second-order integrator circuit. α0 (t) Perform a second integration, and simultaneously compensate for the amplitude through the amplitude calibration unit to avoid signal amplitude attenuation during integration, generating an orthogonal signal u. q (t);

[0056] Wherein, the proportional feedback coefficient K = k × 2πf1, and the integral time constant is... =1 / (k×2πf1).

[0057] For the positive sequence signal u along the α axis α0 (t) is integrated for the first time, resulting in a phase shift of 45°;

[0058] The feedback signal is extracted from the signal after the first integration based on the proportional feedback coefficient K, and compared with the original α-axis positive sequence signal u. α0 (t) superposition, initially compensating for amplitude attenuation;

[0059] Furthermore, the superimposed signal is integrated twice, and the phase is shifted by 45°.

[0060] After two integrations, although the signal amplitude is corrected by feedback, there may still be a small deviation. Therefore, calibration is performed through an amplitude calibration unit. The calibration coefficient is W = k × 2πf1 (the same as the proportional feedback coefficient, requiring no additional calculation and simplifying hardware design). The calibration logic is as follows: multiply the output signal of the second integration by W to cancel the amplitude attenuation caused by integration, generating an orthogonal signal u. q (t).

[0061] Preferably, the integration time constant of the traditional SOGI integrator is... It is fixed; when the power grid frequency fluctuates, The inability to follow changes leads to inaccurate amplitude compensation, while the optimized quadrature signal generator of this invention achieves this through... =1 / (k×2πf1) design, It can dynamically change with the fundamental frequency f1 and damping coefficient k tracked by the generator.

[0062] S4: Notch filtering is applied to the preprocessed signal and the orthogonal signal to optimize the damping coefficient.

[0063] Step 1: From the positive sequence signal u on the α axis α0 (t) and the orthogonal signal u q The positive-sequence components of the 2nd to 11th harmonics are separated from (t) to obtain the harmonic parameters, i.e., the amplitude of the h-th harmonic. , This represents the amplitude of the first harmonic.

[0064] Step 2: Calculate the interference intensity based on harmonic parameters And sorted in descending order of interference intensity index (e.g.) HII 3> HII 5> HII 7>...), select the first 2 as notch targets. If the interference intensity is <0.01, it will not be included in the notch range to avoid wasting computing power.

[0065] ;

[0066] In the formula, h is the harmonic order.

[0067] Step 3: Configure the notch frequency of ANF for the notch target. and notch damping coefficient Harmonic targets are suppressed by a second-order Notch filter to generate the notched α-axis signal u. α0_notch (t) and the orthogonal signal u after notching q_notch (t);

[0068] ;

[0069] In the formula, is the fundamental frequency, h is the harmonic order, and n is the abbreviation for notch.

[0070] When the power grid frequency fluctuation rate When, the notch damping coefficient The value is 0.1 when the power grid frequency fluctuation rate is... When, the notch damping coefficient The damping coefficient of the notch wave is 0.2. The larger the value, the wider the notch bandwidth and the stronger its ability to adapt to frequency fluctuations, but the notch depth decreases slightly. It is suitable for scenarios with severe frequency fluctuations and can be dynamically adjusted. This allows ANF to maintain optimal notch filtering performance under different power grid operating conditions, avoiding fixed... This leads to insufficient suppression in stable scenarios or failure of notch filtering in abrupt scenarios.

[0071] Step 4: Detect the total amplitude of residual harmonics and set a dynamic threshold. When the total amplitude of the residual harmonics is greater than the dynamic threshold, the damping coefficient k is increased to enhance the anti-interference capability of the quadrature signal generator; otherwise, the damping coefficient k is not adjusted.

[0072] ;

[0073] S5: Perform Park transform on the notch-suppressed signal and the quadrature signal, and output the fundamental parameter through a PI regulator.

[0074] The notch-suppressed signal and the quadrature signal are subjected to Park transform using an improved quadrature phase-locked loop, and the fundamental parameter is output through a PI controller. The specific steps are as follows:

[0075] The α-axis signal u after notch filtering α0_notch (t) and the orthogonal signal u after notching q_notch (t) still contains a small amount of unnotched harmonics, therefore it is necessary to first filter the notched α-axis signal u. α0_notch (t) and the orthogonal signal u after notching q_notch (t) Perform low-pass filtering to extract the α-axis fundamental signal u α1 (t) and the orthogonal fundamental signal u q1 (t);

[0076] For the α-axis fundamental signal u α1 (t) and the orthogonal fundamental signal u q1 (t) Perform Park transform to convert the fundamental AC component in the α-β stationary coordinate system into the DC component in the dq synchronous rotating coordinate system, eliminating the influence of the fundamental phase change and generating the fundamental amplitude reference signal u. α2 (t) and phase deviation reference signal uq2 (t);

[0077] The fundamental amplitude reference signal u α2 (t) and phase deviation reference signal u q2 (t) Input to the PI controller to output the fundamental wave parameter to eliminate phase deviation. The fundamental wave parameter includes the fundamental wave angular frequency ω0 and the fundamental wave phase θ0.

[0078] S6: Configure the center angular frequency for each harmonic component to be extracted based on the fundamental wave parameter, and calculate the harmonic amplitude and phase.

[0079] Reference Figure 3 Calculate the harmonic amplitude and phase:

[0080] (1) Input the fundamental phase θ0 into the frequency-locked loop and calculate the phase change rate: dθ0 / dt;

[0081] (2) Based on the phase change rate, the fundamental angular frequency ω0 is corrected to obtain the final fundamental angular frequency ω = ω0 + Δω final Among them, the deviation between dθ0 / dt and ω0 is compared through a PI controller (proportional coefficient k). p =0.1, integral coefficient k i =10) Output frequency correction Δω final ;

[0082] (3) Calculate the center angular frequencies ω of each harmonic based on the final fundamental angular frequency ω. h , where h is the harmonic order;

[0083] ;

[0084] (4) The α-axis signal u after notch filtering is obtained through a filter. α0_notch Extracting the harmonic in-phase component u from (t) h (t), the center frequency of the filter is set to ω. h The filter bandwidth is ≤2Hz;

[0085] (5) For harmonic in-phase components u h (t) Perform a 90° phase shift to obtain the orthogonal component u z (t);

[0086] (6) Based on the harmonic in-phase component u h (t) and orthogonal component u z (t) Calculate the harmonic amplitude A h and absolute phase :

[0087] ;

[0088] ;

[0089] (7) Based on absolute phase Calculate the harmonic phase from the fundamental phase θ0 :

[0090] ;

[0091] Preferably, this invention utilizes the phase difference characteristics of in-phase and quadrature components to eliminate the influence of time variables and instantaneous fluctuations, ensuring that the amplitude calculation result is always equal to the actual stable amplitude with an error ≤0.5%. Simultaneously, it can directly convert the dynamic absolute phase into the static relative phase difference without additional secondary calculations, significantly simplifying the control logic and reducing response delay.

[0092] Example 2

[0093] This invention provides a harmonic extraction device based on an improved quadrature phase-locked loop (QPL), used to implement the steps of the harmonic extraction method based on an improved QPL as described in any of the above embodiments. The harmonic extraction device based on an improved QPL includes:

[0094] The acquisition module is configured to acquire 10kV three-phase voltage signals and preprocess them;

[0095] The frequency fluctuation calculation module is configured to perform frequency fluctuation calculation based on the fundamental frequency tracked by the quadrature signal generator.

[0096] The orthogonal signal generation module is configured to perform orthogonal signal generation based on the damping coefficient and by processing the preprocessed signal through the orthogonal signal generator.

[0097] The coefficient optimization module is configured to perform notch suppression on the preprocessed signal and the orthogonal signal to optimize the damping coefficient.

[0098] The fundamental parameter calculation module is configured to perform Park transform on the preprocessed signal and the quadrature signal, and output the fundamental parameter through a PI regulator.

[0099] The harmonic extraction module is configured to perform operations based on the fundamental parameters, configuring the center angular frequency for each harmonic component to be extracted, and calculating the harmonic amplitude and phase.

[0100] Example 3

[0101] This embodiment provides a terminal device, including:

[0102] One or more processors;

[0103] A memory, coupled to the processor, for storing one or more programs;

[0104] When the one or more programs are executed by the one or more processors, the one or more processors implement the harmonic extraction method based on the improved quadrature phase-locked loop as described above.

[0105] The processor controls the overall operation of the terminal device to complete all or part of the steps of the aforementioned harmonic extraction method based on the improved quadrature phase-locked loop. The memory stores various types of data to support the operation of the terminal device; this data may include, for example, instructions for any application or method operating on the terminal device, as well as application-related data. The memory can be implemented using any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0106] The terminal device can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to execute the harmonic extraction method based on the improved quadrature phase-locked loop as described in any of the above embodiments, and achieve the same technical effect as the above method.

[0107] Example 4

[0108] This embodiment provides a computer-readable storage medium whose program instructions, when executed by a processor, implement the steps of the harmonic extraction method based on the improved quadrature phase-locked loop as described in any of the above embodiments. For example, the computer-readable storage medium can be the memory including the program instructions, which can be executed by the processor of a terminal device to complete the harmonic extraction method based on the improved quadrature phase-locked loop as described in any of the above embodiments, and achieve the same technical effect as the above method.

[0109] It should be recognized that embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can be implemented using standard programming techniques—including a non-transitory computer-readable storage medium configured with a computer program, wherein such a storage medium causes the computer to operate in a specific and predefined manner—according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0110] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0111] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described herein, the invention also includes the computer itself. A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the invention, the converted data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on a display.

[0112] As used herein, the terms “component,” “module,” “system,” etc., are intended to refer to a computer-related entity, which may be hardware, firmware, a combination of hardware and software, software, or running software. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a running thread, a program, and / or a computer. As an example, an application running on a computing device and the computing device itself can both be components. One or more components may reside in a running process and / or thread, and components may be located in a single computer and / or distributed among two or more computers. Furthermore, these components are capable of execution from various computer-readable media having various data structures thereon. These components may communicate locally and / or remotely via signals, such as those containing one or more data packets (e.g., data from a component that interacts with a local system, another component in a distributed system, and / or signals that interact with other systems via a network such as the Internet).

[0113] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A harmonic extraction method based on an improved orthogonal phase-locked loop, characterized in that, include: Acquire three-phase voltage signals and preprocess them; The frequency fluctuation is calculated based on the fundamental frequency tracked by the quadrature signal generator. Based on the damping coefficient, an orthogonal signal generator is used to process the preprocessed signal to generate an orthogonal signal. Notch filtering is applied to the preprocessed signal and the orthogonal signal to optimize the damping coefficient; The notch-suppressed signal and the quadrature signal are subjected to Park transform, and the fundamental parameters are output through a PI controller. Based on the fundamental parameters, a center angular frequency is configured for each harmonic component to be extracted, and the harmonic amplitude and phase are calculated. The generation of orthogonal signals includes: The orthogonal signal generator includes an input preprocessing unit, a second-order integration loop, and an amplitude calibration unit; it processes the preprocessed α-axis positive sequence signal u at time t. α0 (t) Input the quadrature signal generator, extract the fundamental frequency f1 tracked by the generator from it through the input preprocessing unit, and calculate the proportional feedback coefficient K and the integral time constant according to the damping coefficient k. The positive-sequence signal u along the α-axis is obtained through a second-order integrator circuit. α0 (t) Perform a second integration, and simultaneously compensate for the amplitude through the amplitude calibration unit to generate an orthogonal signal u. q (t); Wherein, the proportional feedback coefficient K = k × 2πf1, and the integral time constant is... =1 / (k×2πf1); The optimized damping coefficient includes: Step 1: From the positive sequence signal u on the α axis α0 (t) and the orthogonal signal u q The positive sequence components of the 2nd to 11th harmonics are separated from (t) to obtain the harmonic parameters; Step 2: Calculate the interference intensity based on the harmonic parameters, sort them in descending order of interference intensity exponent, and select the first two as notch targets. If the interference intensity is <0.01, it will not be included in the notch range. Step 3: Configure the notch frequency and notch damping coefficient of the notch target with ANF, and perform notch suppression on the harmonic target through a second-order Notch filter to generate the notched α-axis signal u. α0_notch (t) and the orthogonal signal u after notching q_notch (t); Step 4: Detect the total amplitude of residual harmonics and set a dynamic threshold. When the total amplitude of residual harmonics is greater than the dynamic threshold, increase the damping coefficient k to enhance the anti-interference capability of the quadrature signal generator; otherwise, do not adjust the damping coefficient k.

2. The harmonic extraction method based on an improved orthogonal phase-locked loop as described in claim 1, characterized in that, The preprocessing includes: The negative sequence component is separated and removed from the three-phase voltage signal by the symmetrical component method to obtain the positive sequence component; The positive-order components are processed by Clark transform and wavelet transform.

3. The harmonic extraction method based on an improved quadrature phase-locked loop as described in claim 2, characterized in that, The damping coefficient includes: Calculate the frequency fluctuation Δf based on the fundamental frequency f1 tracked by the quadrature signal generator: Δf=|f1-50| Using the power grid voltage distortion (THD) and frequency fluctuation (Δf) as adjustment dimensions, combined with the load sensitivity (K) in the application scenario variables. load Accuracy requirement correction amount L stab Dynamically calculate the damping coefficient of the orthogonal signal generator: k=[0.5+0.15×min(THD,5%)+0.1×min(Δf,1Hz)]×(1+(0.08×K load +0.05×L stab )) In the formula, k is the damping coefficient.

4. The harmonic extraction method based on an improved quadrature phase-locked loop as described in claim 3, characterized in that, The fundamental wave parameters include: For the α-axis signal u after notch filtering α0_notch (t) and the orthogonal signal u after notching q_notch (t) Perform low-pass filtering to extract the α-axis fundamental signal u α1 (t) and the orthogonal fundamental signal u q1 (t); For the α-axis fundamental signal u α1 (t) and the orthogonal fundamental signal u q1 (t) Perform Park transform to generate the fundamental amplitude reference signal u α2 (t) and phase deviation reference signal u q2 (t); The fundamental amplitude reference signal u α2 (t) and phase deviation reference signal u q2 (t) Input to the PI controller to output fundamental parameters, including fundamental angular frequency ω0 and fundamental phase θ0.

5. The harmonic extraction method based on an improved orthogonal phase-locked loop as described in claim 4, characterized in that, The configured center angular frequency includes: Input the fundamental phase θ0 into the frequency-locked loop and calculate the phase change rate; The fundamental angular frequency ω0 is corrected based on the phase change rate to obtain the final fundamental angular frequency ω. The center angular frequencies of each harmonic are calculated based on the final fundamental angular frequency ω. h , where h is the target harmonic order; The α-axis signal u after notch filtering is obtained through a filter. α0_notch Extracting the harmonic in-phase component u from (t) h (t), the center frequency of the filter is set to ω. h The filter bandwidth is ≤2Hz; For harmonic in-phase components u h (t) Perform a 90° phase shift to obtain the orthogonal component u z (t); According to the harmonic in-phase component u h (t) and orthogonal component u z (t) Calculate the harmonic amplitude and absolute phase ; Based on absolute phase Calculate the harmonic phase using the fundamental phase θ0.

6. A harmonic extraction device based on an improved quadrature phase-locked loop (QPL), used to implement the harmonic extraction method based on an improved QPL as described in any one of claims 1 to 5, characterized in that, The harmonic extraction device based on the improved orthogonal phase-locked loop includes: The acquisition module is configured to acquire three-phase voltage signals and preprocess them; The frequency fluctuation calculation module is configured to perform frequency fluctuation calculation based on the fundamental frequency tracked by the quadrature signal generator. The orthogonal signal generation module is configured to perform orthogonal signal generation based on the damping coefficient and by processing the preprocessed signal through the orthogonal signal generator. The coefficient optimization module is configured to perform notch suppression on the preprocessed signal and the orthogonal signal to optimize the damping coefficient. The fundamental parameter calculation module is configured to perform Park transform on the preprocessed signal and the quadrature signal, and output the fundamental parameter through a PI regulator. The harmonic extraction module is configured to perform operations such as configuring a center angular frequency for each harmonic component to be extracted based on the fundamental parameters, and calculating the harmonic amplitude and phase.

7. A terminal device, characterized in that, include: One or more processors; A memory, coupled to the processor, for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the harmonic extraction method based on the improved quadrature phase-locked loop as described in any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program is executed by a processor to implement the harmonic extraction method based on an improved orthogonal phase-locked loop as described in any one of claims 1 to 5.

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