Medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization and reconstruction method and device

Abstract

This application provides a method and apparatus for medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization and reconfiguration. The method includes: determining the number of healthy submodules and the minimum insertion number, generating grid-connection and energy constraint parameters; reconfiguring the voltage equalization and reconfiguration parameter set when triggering conditions are met; using nearest-level modulation based on phase voltage reference and effective insertion number to generate control commands; executing second harmonic circulating current reference in the inner loop of the arm current, and adjusting the modulation bias and second harmonic circulating current reference in the outer energy loop based on arm energy deviation; performing charge and discharge control on each submodule's DC converter and subjecting it to safety limiting; when a submodule fails, it is bypassed and the voltage equalization and reconfiguration parameter set is refreshed; driving the modular multilevel converter to synthesize three-phase phase voltages, and outputting current at the grid connection point corresponding to the upper-level active and reactive power commands. This application can achieve adaptive voltage equalization and modulation, as well as second harmonic circulating current coordination, taking into account both state of charge and health, and grid connection under fault bypass and capacity degradation conditions.

Description

Technical Field

[0001] This application relates to the field of energy storage technology, and in particular to a method and device for reconfiguring grid-connected voltage equalization of medium-voltage direct-connected modular multilevel energy storage. Background Technology

[0002] With the increasing integration of medium-voltage energy storage into distribution networks, direct grid connection is gradually being used to reduce losses and land occupation. These systems often adopt a three-phase modular multilevel topology, with each arm connected in series with several power sub-modules containing sub-module capacitors and connected to the battery pack via an insulated bidirectional DC-DC converter. The system must simultaneously meet grid voltage synthesis and arm current constraints while also achieving energy distribution and balancing among the sub-modules.

[0003] Existing technologies generally achieve voltage equalization by sorting capacitor voltages or shifting levels, which limits the equalization speed and makes it difficult to take into account differences in battery state of charge, capacity, and health. When a submodule is bypassed or its capacity degrades, the minimum insertion number and modulation depth are not adaptively updated, which can easily lead to device voltage exceeding limits and increased circulating current. Voltage equalization strategies are often designed separately from modulation and circulating current control, lacking coordination with second harmonic circulating current. There is a lack of unified handling for constraints such as minimum dwell time, upper and lower arm insertion difference, power change rate, and temperature. Grid-connected and islanded grids, as well as charging / discharging and reactive power switching, also lack synchronous activation mechanisms. Summary of the Invention

[0004] In view of this, the present application provides a medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization reconstruction method and device to solve the problems of the prior art, such as ignoring the state of charge and health of voltage equalization, the inability of parameters to adapt under bypass faults and capacity degradation, and the lack of unified coordination between voltage equalization, modulation, second harmonic circulating current and safety constraints.

[0005] A first aspect of this application provides a medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization reconstruction method, applied to a three-phase modular multilevel device, comprising: collecting grid connection point voltage and current, phase voltage, arm current, submodule capacitor voltage, and battery state of charge; determining the number of healthy submodules and the minimum insertion number; and generating grid connection and energy constraint parameters. When triggering conditions are met, a comprehensive weighting of the submodules is formed based on state of charge deviation, capacitor voltage deviation, health status, and capacity to reconstruct a voltage equalization reconstruction parameter set. The voltage equalization reconstruction parameter set includes the effective insertion number, modulation bias, second harmonic circulating current reference, and power reference of each submodule's DC-DC converter. Based on the phase voltage reference and the effective insertion number, the nearest-level modulation is adopted, and the submodule insertion combination is determined according to the comprehensive weight and minimum dwell time to form control commands. The second harmonic circulating current reference is executed in the inner loop of the arm current, and the modulation bias and the second harmonic circulating current reference are adjusted according to the arm energy deviation in the outer loop of energy. Each submodule DC converter is charged and discharged according to the power reference and is subject to safety limiting. When a submodule fails, it is connected to the bypass and the voltage equalization reconstruction parameter set is refreshed. The control commands, modulation bias, second harmonic circulating current reference and power reference are issued to drive the modular multilevel converter to synthesize the three-phase phase voltage, and output the current corresponding to the upper active and reactive power commands at the grid connection point.

[0006] A second aspect of this application provides a medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization and reconstruction device, applied to a three-phase modular multilevel device, comprising: a data acquisition module, used to acquire grid connection point voltage and current, phase voltage, arm current, submodule capacitor voltage and battery state of charge, determine the number of healthy submodules and the minimum insertion number, and generate grid connection and energy constraint parameters; a reconstruction module, used to, when the triggering conditions are met, reconstruct a voltage equalization and reconstruction parameter set based on the state of charge deviation, capacitor voltage deviation, health status and capacity to form a comprehensive weight of the submodules, the voltage equalization and reconstruction parameter set including the effective insertion number, modulation bias, second harmonic circulating current reference and power reference of each submodule DC converter; and a determination module, used to determine... The control command is formed by using the nearest-level modulation based on the phase voltage reference and the effective insertion number, and determining the submodule insertion combination according to the comprehensive weight and minimum dwell time. The adjustment module is used to execute the second harmonic circulating current reference in the inner loop of the arm current, and adjust the modulation bias and the second harmonic circulating current reference in the outer loop of energy based on the arm energy deviation. The refresh module is used to control the charging and discharging of each submodule DC converter according to the power reference and subject it to safety limiting. When a submodule fails, it is connected to the bypass and refreshes the voltage equalization reconstruction parameter set. The output module is used to issue control commands, modulation bias, second harmonic circulating current reference and power reference, drive the modular multilevel converter to synthesize the three-phase phase voltage, and output the current corresponding to the upper active and reactive power commands at the grid connection point.

[0007] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0008] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0009] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0010] By collecting grid connection point voltage and current, phase voltage, arm current, submodule capacitor voltage, and battery state of charge, the number of healthy submodules and the minimum insertion number are determined, generating grid connection and energy constraint parameters. When the triggering conditions are met, a comprehensive weighting of the submodules is formed based on the state of charge deviation, capacitor voltage deviation, health status, and capacity, reconstructing the voltage equalization reconstruction parameter set. The voltage equalization reconstruction parameter set includes the effective insertion number, modulation bias, second harmonic circulating current reference, and power reference of each submodule DC converter. Based on the phase voltage reference and the effective insertion number, nearest-level modulation is adopted, and the parameters are calculated according to the comprehensive weighting. The submodule insertion combination is determined by the weight and minimum residence time to form control commands. A second harmonic circulating current reference is executed in the inner loop of the arm current, and the modulation bias and second harmonic circulating current reference are adjusted by the arm energy deviation in the outer loop of the energy. Each submodule DC-DC converter is charged and discharged according to the power reference and subject to safety limits. When a submodule fails, it is bypassed and the voltage equalization and reconstruction parameter set is refreshed. Control commands, modulation bias, second harmonic circulating current reference, and power reference are issued to drive the modular multilevel converter to synthesize three-phase phase voltages, and output current at the grid connection point corresponding to the active and reactive power commands from the upper level. This application can achieve adaptive voltage equalization and modulation and second harmonic circulating current coordination, taking into account both state of charge and health, and grid connection under fault bypass and capacity degradation conditions. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating the medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization and reconstruction method provided in this application embodiment;

[0013] Figure 2 This is a schematic diagram of the structure of the medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization and reconstruction device provided in the embodiments of this application;

[0014] Figure 3 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0015] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0016] In distribution networks, medium-voltage direct-connected energy storage grid-connected devices mostly adopt three-phase modular multilevel topologies. Basic voltage equalization is typically achieved by sorting or shifting the voltage levels of submodule capacitors, with modulation and circulating current control often being separate designs. When facing submodule bypass, capacity degradation, uneven temperature rise, and switching between grid-connected and islanded grids, as well as charging / discharging and reactive power support modes, the minimum insertion number and modulation depth are difficult to update adaptively. Second harmonic circulating current and energy distribution lack coordination, and constraints such as minimum dwell time, upper and lower arm insertion difference, power change rate, and device withstand voltage lack unified processing and synchronized implementation mechanisms.

[0017] The existing technical problem is: in medium-voltage direct connection scenarios, how to uniformly handle energy distribution and battery consistency among submodules within grid connection constraints, achieve adaptive parameter reconfiguration under fault bypass and capacity differences, and enable voltage equalization, modulation and second harmonic circulation to work together within safe limits.

[0018] In view of the problems existing in the prior art, this application proposes a trigger-based voltage equalization reconstruction method: The method collects grid connection point voltage and current, phase voltage, arm current, submodule capacitor voltage, and battery state of charge; determines healthy submodules and calculates the minimum insertion number; and generates grid connection and energy constraint parameters. When the triggering condition is met, a comprehensive weight is constructed based on the state of charge deviation, capacitor voltage deviation, health status, and capacity to reconstruct the voltage equalization reconstruction parameter set. This parameter set includes the effective insertion number, modulation bias, second harmonic circulating current reference, and power reference. The insertion combination is determined by using the nearest-level modulation combined with the comprehensive weight and minimum dwell time. The inner loop of the arm current executes the second harmonic circulating current reference, while the outer loop of the energy uses the arm energy deviation to link the modulation bias and circulating current reference. Each submodule DC converter is charged and discharged according to the power reference and is subject to safety limiting constraints. The voltage equalization reconstruction parameter set is refreshed when a fault bypass occurs. Control commands are issued under the synchronization window to synthesize the three-phase phase voltages to meet the upper-level active and reactive power commands.

[0019] Through the above-mentioned technical solution of this application, this application can achieve integrated coordination of adaptive voltage equalization and modulation, and second harmonic circulating current for medium-voltage direct connection, while taking into account battery consistency and device withstand voltage constraints; maintain parameter adaptation and stable grid connection under bypass and capacity degradation conditions; and reduce switching jitter and circulating current level by limiting minimum dwell time and upper and lower arm insertion difference.

[0020] The technical solution of this application will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0021] Figure 1 This is a flowchart illustrating the medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization and reconfiguration method provided in this application embodiment. For example... Figure 1 As shown, the medium-voltage direct-connected modular multi-level energy storage grid-connected voltage equalization and reconstruction method may specifically include:

[0022] S101 collects grid connection point voltage and current, phase voltage, arm current, submodule capacitor voltage and battery state of charge, determines the number of healthy submodules and the minimum number of insertions, and generates grid connection and energy constraint parameters;

[0023] S102, when the triggering condition is met, the equalization reconstruction parameter set is reconstructed based on the comprehensive weight of the sub-module formed by the state of charge deviation, capacitor voltage deviation, health and capacity. The equalization reconstruction parameter set includes the effective number of insertions, modulation bias, second harmonic circulating current reference and power reference of each sub-module DC converter.

[0024] S103 uses the nearest level modulation based on the phase voltage reference and the effective number of insertions, and determines the submodule insertion combination according to the comprehensive weight and minimum dwell time to form control commands;

[0025] S104 performs a second harmonic circulating current reference in the inner loop of the arm current and adjusts the modulation bias and the second harmonic circulating current reference in the outer loop of energy with arm energy deviation.

[0026] S105, each sub-module DC converter is charged and discharged according to the power reference and is subject to safety limit. When a sub-module fails, it is connected to the bypass and the voltage equalization reconstruction parameter set is refreshed.

[0027] S106 issues control commands, modulation bias, second harmonic circulating current reference and power reference, drives the modular multilevel converter to synthesize three-phase phase voltage, and outputs current at the grid connection point corresponding to the active and reactive power commands from the upper level.

[0028] In some embodiments, determining the number of healthy submodules and the minimum number of insertions, and generating grid connection and energy constraint parameters, includes:

[0029] Construct a health determination vector and perform a probability consistency test to obtain the number of healthy sub-modules;

[0030] Based on the grid connection point voltage reference peak, the allowable operating voltage of the health submodule, the arm reactance voltage drop estimation, and the modulation bias and second harmonic circulating current reference limiting, an integer constraint is established for the arm voltage synthesis, and the minimum number of insertions is obtained.

[0031] Based on the number of healthy submodules and the minimum number of insertions, combined with the grid connection point voltage reference and device withstand voltage parameters, grid connection and energy constraint parameters are generated.

[0032] Specifically, firstly, a health assessment vector is constructed. Within a sliding time window, this vector consists of the following components: submodule capacitor voltage offset, temperature rise rate, DC-DC converter current limiting trigger count, bypass self-test result, and online identification deviation of the submodule capacitor equivalent value. The controller normalizes these components and establishes a statistical baseline for the submodule group. Subsequently, a probabilistic consistency check is performed, outputting the health assessment result for each submodule and counting the number of healthy submodules accordingly.

[0033] Secondly, an integer constraint model for arm voltage synthesis is established to determine the minimum number of insertions. The controller reads the reference peak voltage at the grid connection point, the allowable operating voltage of the healthy submodule, the estimated arm reactance voltage drop, and the reference limit for modulation bias and second harmonic circulating current, etc., to construct the inequality that "the required arm voltage is not less than the sum of the target phase voltage peak and the arm reactance voltage drop". The device withstand voltage and safety margin constraints are then superimposed to obtain the solution problem of the number of submodules to be inserted in each arm being an integer. The smallest integer solution that satisfies all constraints is taken as the minimum number of insertions.

[0034] Finally, grid connection and energy constraint parameters are generated. Based on the number of healthy submodules and the minimum insertion number, and combined with the grid connection point voltage reference and device withstand voltage parameters, the controller provides upper and lower limits for modulation depth, upper and lower arm insertion difference limits, second harmonic circulating current reference limit, target voltage range for submodule capacitors, limits for DC converter charging and discharging power and rate of change, minimum dwell time limit, and synchronization window parameters, which serve as unified constraints for subsequent modulation, sequencing, and circulating current control.

[0035] In some examples, the health determination vector is used to unify electrical stress, thermal stress, energy constraints, and self-test results into a single criterion framework. The probabilistic consistency test compares the normalized components of a single submodule with the group baseline and outputs a pass probability. The controller generates a health flag based on a threshold. The "integer constraint" for the minimum insertion number refers to the rule that the insertion number must be an integer when voltage synthesis is performed using submodules as discrete-level units. Grid connection and energy constraint parameters are a set of limits shared by subsequent control stages, ensuring that modulation depth, circulating current reference, insertion difference, and power change rate are coordinated within the same parameter domain.

[0036] For example, taking a device with 24 sub-modules per phase and per arm as an example, during a certain operating period, statistics within the sliding time window show that: one sub-module failed its bypass self-test; the capacitor voltage deviation of two of the remaining sub-modules was consistently higher than the group average threshold; and the temperature rise rate of another sub-module exceeded the preset threshold but was still within the allowable range. After a probability consistency test, the number of healthy sub-modules was determined to be 22. The reference peak phase voltage at the grid connection point is 8.0 kV, the estimated arm reactance voltage drop is 0.5 kV, the allowable operating voltage of the healthy sub-modules is 1.2 kV, and the device withstand voltage and safety margin are converted into voltage redundancy coefficients. Based on this, the controller establishes an arm voltage synthesis inequality and calculates the minimum insertion number as 8. The insertion difference limit between upper and lower arms in the same phase is given by the constraint model as not exceeding 2.

[0037] At this moment, the controller generates grid connection and energy constraint parameters: the upper and lower limits of modulation depth correspond to the current minimum number of insertions and the number of healthy submodules; the reference limit for second harmonic circulating current is constrained by the arm inductance and device current ratings; the target voltage range for submodule capacitors is set according to the allowable operating voltage and redundancy coefficient; the limits for DC-DC converter charging and discharging power and rate of change are given in conjunction with the battery state of charge and temperature; and the minimum dwell time limit is set to no less than 3 carrier cycles and is constrained by the synchronization window. These parameters are sent to the phase-level and arm-level controllers within the control cycle, providing a unified reference basis for subsequent comprehensive weight calculation, insertion combination selection, and circulating current control.

[0038] In some embodiments, when the triggering condition is met, a voltage equalization reconstruction parameter set is reconstructed based on the comprehensive weights of the state of charge deviation, capacitor voltage deviation, health status, and capacity forming submodule, including:

[0039] The state of charge deviation, capacitor voltage deviation, health status and capacity are dimensionally normalized and piecewise monotonically mapped, and the comprehensive weight is obtained by combining them according to the preset importance coefficients.

[0040] Based on the comprehensive weight and grid connection and energy constraint parameters, the effective number of insertions and modulation offset are determined using a solution rule with integer constraints.

[0041] Power references are allocated to the DC converters of each submodule based on the comprehensive weight, and rate of change limits and state-of-charge boundary limits are applied.

[0042] The amplitude and phase of the second harmonic circulating current reference are calculated based on the arm energy target and modulation bias in the grid connection and energy constraint parameters, and are limited to the circulating current reference amplitude limit in the grid connection and energy constraint parameters.

[0043] The effective number of insertions, modulation bias, second harmonic circulating current reference, and power reference constitute the voltage equalization reconstruction parameter set.

[0044] Specifically, firstly, the state-of-charge deviation, capacitor voltage deviation, health status, and capacity are normalized. Dimensional normalization is achieved by normalizing each quantity to its baseline and threshold within a sliding time window, mapping the four indicators to the 0-1 range. Then, a piecewise monotonic mapping is performed: a gradually changing slope is used when the indicator is in the normal range, the slope increases as it approaches the threshold range, and saturation is applied to the exceeding range to ensure that the mapped value does not decrease monotonically as the deviation increases. The four mapped values ​​are then combined according to a preset importance coefficient to obtain the comprehensive weight of each submodule.

[0045] For example, in some examples, the importance coefficients are set to 0.35 for state of charge, 0.25 for capacitor voltage, 0.20 for health, and 0.20 for capacity. At a certain moment, the four components of two sub-modules numbered a and b in the same arm after normalization mapping are (0.70, 0.20, 0.10, 0.10) and (0.30, 0.50, 0.10, 0.10), respectively, and their comprehensive weights are 0.42 and 0.32, respectively. Therefore, a has a higher priority than b.

[0046] Secondly, based on the comprehensive weight and grid connection and energy constraint parameters, the effective number of insertions and modulation bias are determined. The controller first reads the minimum number of insertions, the upper and lower limits of modulation depth, the upper and lower arm insertion difference limit, and the device withstand voltage boundary from the grid connection and energy constraint parameters, and establishes a level reachability criterion with "phase voltage reference reachability" as the objective. Under the premise of satisfying the minimum number of insertions and the device withstand voltage boundary, a solution rule with integer constraints is adopted: sub-modules are selected in descending order of comprehensive weight to form a candidate insertion set. When the synthesized level of the candidate set first satisfies the level reachability and the upper and lower arm insertion difference does not exceed the limit, the number of insertions corresponding to the set is recorded as the effective number of insertions; at the same time, a modulation bias matching the number of insertions is selected within the upper and lower limits of modulation depth, so that the level synthesis and the arm energy target have the same bias direction.

[0047] For example, in some cases, the effective insertion number of a certain phase upper arm is calculated to be 9, corresponding to an upper limit of modulation bias of 0.82 and a lower limit of 0.68, and the modulation bias of this cycle is calculated to be 0.74.

[0048] Next, power references are allocated to the DC-DC converters of each submodule according to the comprehensive weight. The controller uses the arm energy target and the current active and reactive power commands as the total power constraints, and distributes the total power among the submodules according to the comprehensive weight ratio, and superimposes the temperature and state of charge boundary limits of each module for amplitude limiting; in order to avoid stress abrupt changes, a rate of change limit is applied to the power reference. In the example, the rate of change limit is set to not exceed 5% of the rated power per control cycle. When the calculated power exceeds any limit, it is truncated according to the nearest limit.

[0049] Subsequently, the amplitude and phase of the second harmonic circulating current reference are calculated based on the arm energy target and modulation bias in the grid connection and energy constraint parameters. Using the energy difference between the upper and lower arms as input, the controller converts the required energy migration into the second harmonic circulating current reference amplitude according to a preset amplitude-phase decoupling law, and determines the reference phase direction based on the phase synchronization relationship with the grid fundamental wave. The resulting reference is truncated within the circulating current reference limit; in this example, the limit is given based on the arm inductance and the rated current of the devices, restricting the reference amplitude to within 15% of the rated current.

[0050] Finally, the effective number of insertions, modulation bias, second harmonic circulating current reference, and power reference are used to form a voltage equalization reconstruction parameter set, which is then sent to the phase-level and arm-level controllers for execution: the arm-level controller generates the current cycle insertion combination and gate sequence based on the effective number of insertions and the comprehensive weight; the inner current loop is executed according to the second harmonic circulating current reference; and the DC side performs charging and discharging closed loop according to the power reference.

[0051] Through the above implementation methods, this part of the embodiments realizes the unified reconstruction of the number of insertions, modulation bias, circulating current reference and power reference under triggering conditions, ensuring that the insertion selection, voltage synthesis, energy target and safety limiting are coordinated in the same parameter domain, improving the timeliness and consistency of energy distribution among sub-modules, and realizing replicable engineering implementation under device constraints and grid-connection constraints.

[0052] In some embodiments, the nearest-level modulation is used based on the phase voltage reference and the effective number of insertions, and the submodule insertion combination is determined according to the comprehensive weight and minimum dwell time to form control commands, including:

[0053] The target level and corresponding target insertion number for this cycle are determined based on the phase voltage reference and the effective insertion number.

[0054] Healthy sub-modules that do not meet the minimum residence time requirement are filtered out, and the candidate set is formed by sorting them in descending order of comprehensive weight;

[0055] Select the insertion combination that matches the target number of insertions from the candidate set according to the comprehensive weight, and constrain the insertion difference between the upper and lower arms of the same phase to be within a predetermined range;

[0056] The obtained insertion combinations are used to generate gate drive sequences and insertion state tables, and then issued as control commands in the synchronization window.

[0057] Specifically, firstly, the target voltage level and target insertion number for the current cycle are determined based on the phase voltage reference and the effective insertion number. The controller normalizes the current phase voltage reference to the arm voltage reference to obtain the target voltage level index, and combines it with the effective insertion number to determine the target insertion number for the upper and lower arms in the same phase during this sampling cycle.

[0058] For example, in some examples, the target level of a certain phase at the sampling time corresponds to 9 upper arm insertions and 7 lower arm insertions, and it is required that the upper and lower arm insertion difference in the same phase does not exceed the upper and lower arm insertion difference limit in the grid connection and energy constraint parameters.

[0059] Then, healthy sub-modules that do not meet the minimum residence time requirement are filtered out, forming a candidate set. Based on the insertion state of the previous cycle, the controller determines the insertion residence count of each healthy sub-module, and removes sub-modules whose residence time has not reached the limit; the remaining sub-modules are sorted from high to low according to their comprehensive weight to generate a candidate set.

[0060] For example, in some cases, two submodules in the upper arm health submodule were temporarily removed because their residency time was not full, and the candidate set retained the top fifteen submodules by weight.

[0061] Subsequently, insertion combinations matching the target insertion number are selected from the candidate set according to a comprehensive weight. The controller sequentially selects sub-modules from the first candidate module to add to the temporary insertion combination, and immediately checks three constraints after each addition: first, whether the level reachability meets the target level; second, whether the insertion difference between the upper and lower arms of the in-phase module is within the limits set by grid connection and energy constraints; and third, whether the device withstand voltage and grid modulation depth are still within the limits. If any constraint is violated, the sub-module is skipped and the selection continues downwards until the target insertion number is reached.

[0062] For example, in some examples, the final determined insertion combination for the upper arm is number 1, 3, 5, 7, 10, 12, 14, 17, 20; and for the lower arm it is number 2, 4, 6, 9, 11, 15, 18. The insertion difference between the two is 2, which meets the limit requirement.

[0063] Next, a gate drive sequence and insertion state table are generated. The controller maps the insertion combination of the current cycle to the insertion state, gate conduction timing, and dead time configuration of each submodule, and aligns it with the current modulation bias to form a gate drive sequence oriented towards the upper and lower arms. To avoid high-frequency jitter, the controller sets a minimum dwell count for submodules entering the insertion state for the first time, and checks submodules about to exit and delays their exit until the nearest synchronization point after reaching the minimum dwell time.

[0064] Finally, control commands are issued within the synchronization activation window. The controller selects the synchronization activation window after the carrier zero crossing as the command switching time, and simultaneously issues the gate drive sequence and insertion state table for this phase and the other two phases to ensure that all three phases are consistent and effective. If the grid connection and energy constraint parameters are detected to have been refreshed by the upper layer before issuance, a fast consistency check is performed on the insertion combination, and issuance is only performed if the level reachability and limits are still met.

[0065] Through the above implementation methods, this part of the embodiment realizes the landing of the nearest level modulation under the constraints of a predetermined number of effective insertions and comprehensive weights. The generated insertion combination takes into account both the minimum dwell time and the upper and lower arm insertion difference limit. The gate drive switches consistently within the synchronous effective window, thereby reducing frequent switching and improving the determinism of insertion selection while satisfying the requirements of level reachability and device withstand voltage.

[0066] In some embodiments, a second harmonic circulating current reference is performed in the inner loop of the arm current, and the modulation bias and the second harmonic circulating current reference are adjusted in the outer loop of the energy using arm energy deviation, including:

[0067] Calculate the arm energy deviation based on the submodule capacitor voltage and arm current;

[0068] The arm energy deviation is input into the coupling regulator to generate the modulation bias increment and the second harmonic circulating current reference increment, which are respectively limited to the upper and lower limits of modulation depth and the circulating current reference limit in the grid connection and energy constraint parameters.

[0069] The current loop is closed in the inner loop of the arm current according to the second harmonic circulating current reference.

[0070] When any limit is triggered, the second harmonic circulating current reference increment is first reduced according to the preset priority, then the modulation bias increment is reduced, while keeping the effective number of insertions unchanged.

[0071] Specifically, this embodiment will describe the process of "implementing a second harmonic circulating current reference in the inner loop of the arm current, and adjusting the modulation bias and the second harmonic circulating current reference in the outer loop of energy based on the arm energy deviation". The system is a three-phase modular multilevel device, and the controller has obtained the grid connection and energy constraint parameters, the effective insertion number, and the current initial value of the modulation bias.

[0072] First, the arm energy deviation is calculated. In each control cycle, the phase-level controller collects the submodule capacitor voltage and arm current of the upper and lower arms in the same phase. After suppressing switching ripple using a low-pass filter, the arm energy estimate is obtained by summing the equivalent capacitance of the submodule and the square of the voltage. This arm energy estimate is compared with the arm energy target in the grid connection and energy constraint parameters to obtain the upper arm energy deviation and the lower arm energy deviation. The difference between the two is then calculated as the energy imbalance. In the example, the upper arm energy deviation of a certain phase is positive, and the lower arm energy deviation is negative, indicating that energy needs to be transferred from the upper arm to the lower arm.

[0073] Next, the arm energy deviation is input into the coupling regulator to generate the modulation bias increment and the second harmonic circulating current reference increment. The coupling regulator includes an energy difference channel and an energy sum channel: the energy difference channel performs proportional integration on the energy difference between the upper and lower arms, outputting the amplitude and polarity of the second harmonic circulating current reference increment; the energy sum channel performs proportional integration on the average energy deviation between the in-phase upper and lower arms, outputting the modulation bias increment, used to fine-tune the average voltage of the in-phase arms. A cross-compensation term is set between the two channels to suppress the coupling of the modulation bias to the circulating current and the reverse influence of the circulating current on the modulation bias. The output of the coupling regulator, after being limited by amplitude and rate of change, is superimposed on the modulation bias and second harmonic circulating current reference of the previous cycle, respectively limited within the upper and lower limits of modulation depth and the limit of circulating current reference in the grid connection and energy constraint parameters. In the example, the coupling regulator gives a negative modulation bias increment and a positive second harmonic circulating current reference increment, indicating that energy return is completed by reducing the modulation bias and injecting in-phase second harmonic circulating current.

[0074] Next, a current loop is executed within the inner loop of the arm current, using the second harmonic circulating current as a reference. The arm-level controller tracks the reference arm current using a fast current loop, which is composed of the grid-connected current decomposition term and the superposition of the second harmonic circulating current reference. To improve tracking accuracy, the inner loop of the arm current employs feedforward decoupling compensation for the phase voltage and the grid-connected point voltage, and corrects the drive timing within the gate dead zone compensation range. In the example, the amplitude of the second harmonic circulating current reference is limited to within 15% of the arm's rated current, and the inner loop tracking error is constrained within the rate of change limit.

[0075] Subsequently, priority contraction is performed when any limit is reached. The controller monitors in real time whether the modulation bias and second harmonic circulating current reference have reached the limits and rate of change limits of the grid connection and energy constraint parameters: if the second harmonic circulating current reference reaches the limit first, the second harmonic circulating current reference increment is contracted to within the limit according to the preset priority, while the modulation bias increment remains unchanged; if there is still a tendency to exceed the limit or the modulation bias reaches the upper or lower limit, the modulation bias increment is contracted further; the effective insertion number remains unchanged throughout the contraction process to avoid damage to the level reachability and device withstand voltage boundary. In the example, when the second harmonic circulating current reference reaches the limit, it is preferentially contracted to the limit, and the modulation bias continues to converge in small steps until the arm energy deviation is within the allowable band.

[0076] Finally, the execution parameters are updated within the synchronization window. During the synchronization window when the carrier crosses zero, the phase-level controller sends the updated modulation bias and second harmonic circulating current reference to each arm-level controller. The inner loop of the arm current immediately operates according to the new reference, while the outer loop of energy continues to calculate the increment based on the new arm energy deviation in the next cycle.

[0077] Through the above implementation methods, this part of the embodiment realizes the coupled adjustment of modulation bias and second harmonic circulating current driven by arm energy deviation, and completes energy migration within the limits and rate of change of grid connection and energy constraint parameters. The priority contraction strategy ensures that when the limit is reached, the circulating current reference is constrained first, and then the modulation bias is constrained, without changing the effective number of insertions, thereby stably achieving dynamic balance and reference tracking of inter-arm energy without destroying the level reachability and device withstand voltage boundary.

[0078] In some embodiments, each submodule DC converter is charged and discharged according to a power reference and is subject to safety limiting. When a submodule fails, a bypass is activated and the voltage equalization reconfiguration parameter set is refreshed, including:

[0079] Calculate the DC-side current command based on the power reference and execute the current closed loop;

[0080] Based on the safety limit constraint current command and power change rate, the safety limit includes temperature limit, state of charge boundary and upper limit of charging and discharging power;

[0081] When a submodule fails or is triggered by protection, the power reference of the submodule is set to zero, the DC-DC converter of the submodule is disconnected and the bypass switch is closed.

[0082] Update the number of health submodules and the minimum number of insertions, and trigger a refresh of the equalization reconstruction parameter set, outputting the new effective number of insertions, modulation bias, second harmonic circulating current reference, and power reference.

[0083] Specifically, this embodiment will describe the process of "each sub-module DC-DC converter being charged and discharged according to the power reference and subject to safety limits, and bypassing and refreshing the voltage equalization reconstruction parameter set in the event of a fault." The device is a three-phase modular multilevel structure, with several sub-modules connected in series in each arm. Each sub-module contains a sub-module capacitor and is connected to the battery pack via an insulated bidirectional DC-DC converter. After the controller issues the power reference, grid connection, and energy constraint parameters at the phase level, the control strategy of this embodiment is executed at the sub-module level.

[0084] First, the DC-side current command is calculated based on the power reference and the current closed-loop is executed. The submodule controller reads the power reference for the current cycle and the current battery pack terminal voltage, and obtains the DC-side current command by dividing the signed power by the terminal voltage. The polarity of the command is determined by charging or discharging. The inner current loop uses current sampling as feedback, employs proportional-integral and feedforward compensation to achieve closed-loop tracking, and updates the adjustment amount within the synchronization window when the carrier crosses zero to align with the gate sequence of the higher-level controller.

[0085] For example, when the power reference of a certain submodule is 6 kW and the terminal voltage is 300 volts, the calculated current command is 20 amps, and the inner loop tracks to the allowable error band within one control cycle.

[0086] Secondly, the current command and power change rate are constrained according to safety limits. Safety limits include temperature limits, state of charge boundaries, and upper limits for charging and discharging power: when the temperature is close to the temperature limit, the current command is linearly drated to the zero gradient point; when the state of charge is below the lower boundary or above the upper boundary, discharging or charging is prohibited respectively; when the instantaneous power exceeds the upper limit for charging and discharging power, it is cut off to the upper limit according to the nearest principle and the rate of change is limited.

[0087] For example, the temperature limit is 55°C, the state of charge boundary is 15% to 90%, the maximum charging and discharging power of a single submodule is 8 kW, and the rate of change limit is no more than 5% of the rated power per control cycle. When the temperature rises from 54°C to 55°C, the controller will reduce the current command to 40% of the original value according to the derating curve in the current period, and continue to reduce it according to the rate of change limit in the next synchronization window.

[0088] Next, fault and protection triggering is performed, and the bypass switch is closed. The submodule monitors trigger quantities such as overvoltage, overcurrent, temperature exceeding limits, insulation abnormalities, and drive faults. Once any trigger quantity meets the fault condition, the submodule's power reference is immediately set to zero, a disconnect command is sent to the DC-DC converter, and gate de-energization is executed. Subsequently, the bypass switch is closed to form a safe conduction path. A minimum dead time is set between disconnection and closure to avoid parallel circulating current. In the example, if a submodule detects that the capacitor voltage exceeds the limit, the controller will establish a zero-power reference and disconnect the DC-DC converter in the same control cycle. After a delay that meets the minimum dead time, the bypass switch is closed, completing the exit of the submodule.

[0089] Subsequently, the number of healthy submodules and the minimum insertion count are updated, and the voltage equalization reconstruction parameter set is refreshed. After receiving the submodule exit event, the phase-level controller recounts the number of healthy submodules and estimates the minimum insertion count based on the grid connection point voltage reference, device withstand voltage parameters, and arm reactance voltage drop. Based on this, the voltage equalization reconstruction process is triggered, generating a new voltage equalization reconstruction parameter set. The parameter set includes at least the new effective insertion count, modulation bias, second harmonic circulating current reference, and power reference, and is uniformly distributed in the next synchronization window.

[0090] For example, the number of healthy sub-modules in the upper arm of a certain phase changes from 24 to 23. After solving the integer constraint, the minimum number of insertions is still 9, but the insertion difference limit between the upper and lower arms is tightened to no more than 1. The modulation bias obtained by reconstruction is reduced by 0.02 compared with the previous cycle, the second harmonic circulating current reference amplitude is limited to within 15% of the rated current of the arm, and the sub-module power reference is redistributed under the new boundary.

[0091] Finally, a consistency check and recovery strategy are implemented. If the grid connection and energy constraint parameters are refreshed again before the parameter set is issued, a consistency check is performed on the effective number of insertions and insertion combinations, which only takes effect when the level reachability and device withstand voltage boundaries are met. When the faulty submodule recovers and passes the health determination, the controller re-includes it in the healthy submodule set under the conditions of meeting the minimum dwell time and synchronization window, and gradually restores it according to the comprehensive weight and power reference.

[0092] Through the above implementation methods, this part of the embodiment realizes power closed-loop and fault fast bypass with safety limiting as constraint, and completes adaptive refresh of effective insertion number, modulation bias and second harmonic circulating current reference in conjunction with the equalization reconstruction parameter set. In this way, the continuity of power command execution and level reachability is maintained under fault and temperature and state of charge limited conditions, and the impact of abnormal disturbances on grid-connected operation is reduced.

[0093] In some embodiments, driving a modular multilevel converter to synthesize three-phase phase voltages and outputting current corresponding to the active and reactive power commands from the upper-level controller at the grid connection point includes:

[0094] Based on the active and reactive power commands from the upper level and the grid connection point voltage, the active current reference and reactive current reference are calculated to form the three-phase grid connection current reference.

[0095] The amplitude and rate of change limits are applied to the grid-connected current reference according to the grid connection and energy constraint parameters, and consistency is verified with the modulation bias and second harmonic circulating current reference.

[0096] Within the synchronization window, control commands, modulation bias, second harmonic circulating current reference and power reference are issued, and gate drive is executed according to the inserted state table to synthesize three-phase voltages.

[0097] The grid-connected current closed loop is executed with the grid-connected current reference as the target. When the limits in the grid-connected and energy constraint parameters are triggered, the reactive current reference and modulation bias are contracted according to the preset priority to keep the effective insertion number unchanged.

[0098] Specifically, this embodiment will describe the process of "driving a modular multilevel converter to synthesize three-phase phase voltages and outputting currents corresponding to the active and reactive power commands from the upper-level controller at the grid connection point". The device is a three-phase modular multilevel structure, and the controller has obtained grid connection and energy constraint parameters, modulation bias, second harmonic circulating current reference, effective insertion count, and insertion state table.

[0099] First, the three-phase grid-connected current reference is calculated based on the active and reactive power commands from the upper-level controller and the grid-connected point voltage. The phase-level controller performs a synchronous rotating coordinate transformation on the three-phase voltage at the grid-connected point to obtain the direct-axis and quadrature-axis voltage components; the active power command is converted into a direct-axis current reference, and the reactive power command is converted into a quadrature-axis current reference, and the three-phase current reference waveform is generated through inverse transformation. In the example, at a certain moment, the upper-level controller sends 200 kW of active power and 80 kV of reactive power, and the effective value of the grid-connected point voltage is 10 kV. The calculated peak value of the three-phase current reference is approximately 120 amps.

[0100] Secondly, limits are imposed on the grid-connected current reference according to the grid connection and energy constraint parameters, and consistency verification is performed. The phase-level controller imposes upper limits on the amplitude and rate of change of the three-phase current reference. The upper limit on amplitude is given by the rated current of the device and the arm inductance, and the upper limit on rate of change is given by thermal and electromagnetic constraints. Then, a consistency verification is performed: the reachability of the level is checked by the effective insertion number and modulation bias, and the circulation current and insertion difference are checked by the second harmonic circulating current reference and the upper and lower arm insertion difference limits to see if they exceed the limits. If inconsistencies are found, the current reference is scaled proportionally until all constraints are met. In the example, the upper limit on amplitude is 150 amps and the upper limit on rate of change is 20 amps per cycle. After verification, only a small scaling is performed on the peak period.

[0101] Then, within the synchronization window, control quantities are issued and three-phase voltages are synthesized. During the synchronization window at the zero-crossing of the carrier wave, the controller simultaneously issues control commands, modulation bias, second harmonic circulating current reference, and power reference to each phase and arm. The arm-level controller, based on the insertion state table and the nearest-level modulation strategy, selects the submodule for insertion and generates gate timing to synthesize the target phase voltage waveform. To avoid command jitter, the submodule entering the insertion state for the first time must meet a minimum dwell time before exiting; the exit operation is also performed in the next synchronization window.

[0102] Next, the grid-connected current closed loop is executed with the grid-connected current reference as the target. The phase-level current regulator takes the three-phase current reference and real-time current as inputs, outputs phase voltage commands, and superimposes a modulation bias. To improve tracking accuracy, a feedforward decoupling term for the grid-connected point voltage is added, and the sampled quantity is low-pass filtered to suppress switching ripple. The arm-level regulator superimposes a second harmonic circulating current reference in the inner current loop to ensure that the circulating current control and the grid-connected current control do not interfere with each other. In the example, the current closed loop suppresses the error to within three percent of the reference peak value.

[0103] Finally, a priority contraction strategy is executed when the limits in the grid connection and energy constraint parameters are reached. The controller continuously monitors three types of constraints: modulation depth, circulating current amplitude, and current amplitude. When any limit is reached, the reactive current reference is first contracted to reduce its impact on modulation depth and device current. If the tendency to exceed the limit still exists, the modulation bias is then contracted, and the effective insertion number is kept constant throughout the process to avoid disrupting level accessibility. In the example, due to a short-term dip in the grid connection voltage causing the modulation depth to approach the upper limit, the system automatically lowers the reactive current reference by ten percentage points, the modulation bias is slightly backed down by one step, and the level synthesis remains stable.

[0104] Through the above implementation methods, this part of the embodiment realizes the consistent generation of constraints from active and reactive power commands to three-phase current references, issues and drives the gate within a unified synchronization window, and realizes phase voltage synthesis and grid-connected current closed-loop coordination; when the limit is reached, reactive power and modulation bias are preferentially contracted without changing the effective insertion number, thereby maintaining stable consistency of level reachability and current tracking within the constraints of devices and grid connection.

[0105] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0106] Figure 2 This is a schematic diagram of the structure of the medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization and reconfiguration device provided in the embodiments of this application. Figure 2 As shown, this medium-voltage direct-connected modular multilevel energy storage grid-connected voltage equalization and reconstruction device is applied to a three-phase modular multilevel device and includes:

[0107] The data acquisition module 201 is used to acquire grid connection point voltage and current, phase voltage, arm current, submodule capacitor voltage and battery state of charge, determine the number of healthy submodules and the minimum number of insertions, and generate grid connection and energy constraint parameters.

[0108] The reconfiguration module 202 is used to reconstruct the voltage equalization reconfiguration parameter set based on the state of charge deviation, capacitor voltage deviation, health and capacity to form a comprehensive weight of the sub-module when the triggering conditions are met. The voltage equalization reconfiguration parameter set includes the effective number of insertions, modulation bias, second harmonic circulating current reference and power reference of each sub-module DC converter.

[0109] The determination module 203 is used to determine the submodule insertion combination based on the phase voltage reference and the effective number of insertions, using the nearest level modulation, and according to the comprehensive weight and minimum dwell time, to form control commands;

[0110] The adjustment module 204 is used to perform a second harmonic circulating current reference in the inner loop of the arm current and to adjust the modulation bias and the second harmonic circulating current reference in the outer loop of energy by arm energy deviation.

[0111] The refresh module 205 is used to control the charging and discharging of each sub-module DC converter according to the power reference and subject it to safety limits. When a sub-module fails, it is connected to the bypass and refreshes the voltage equalization and reconstruction parameter set.

[0112] Output module 206 is used to issue control commands, modulate bias, second harmonic circulating current reference and power reference, drive the modular multilevel converter to synthesize three-phase phase voltage, and output current corresponding to the active and reactive power commands at the grid connection point.

[0113] In some embodiments, Figure 2 The acquisition module 201 constructs a health determination vector and performs a probability consistency test to obtain the number of healthy sub-modules. Based on the grid connection point voltage reference peak, the allowable operating voltage of the healthy sub-module, the arm reactance voltage drop estimation, and the modulation bias and second harmonic circulating current reference limiting, an integer constraint for arm voltage synthesis is established to obtain the minimum insertion number. According to the number of healthy sub-modules and the minimum insertion number, combined with the grid connection point voltage reference and device withstand voltage parameters, grid connection and energy constraint parameters are generated.

[0114] In some embodiments, Figure 2 The reconstructing module 202 performs dimensionless and piecewise monotonic mapping on the state-of-charge deviation, capacitor voltage deviation, health, and capacity, and obtains a comprehensive weight by combining preset importance coefficients. Based on the comprehensive weight and grid connection and energy constraint parameters, it uses a solution rule with integer constraints to determine the effective insertion number and modulation bias. Based on the comprehensive weight, it allocates power references to the DC converters of each submodule and applies rate of change limits and state-of-charge boundary limits. Based on the arm energy target and modulation bias in the grid connection and energy constraint parameters, it calculates the amplitude and phase of the second harmonic circulating current reference and limits it to the circulating current reference amplitude in the grid connection and energy constraint parameters. The effective insertion number, modulation bias, second harmonic circulating current reference, and power reference constitute a voltage equalization reconstructing parameter set.

[0115] In some embodiments, Figure 2 The determination module 203 determines the target level and the corresponding target insertion number for the current cycle based on the phase voltage reference and the effective insertion number; it filters out healthy sub-modules that do not meet the minimum dwell time and arranges them in descending order of comprehensive weight to form a candidate set; it selects the insertion combination that matches the target insertion number from the candidate set according to the comprehensive weight and constrains the insertion difference between the upper and lower arms of the same phase to be within a predetermined range; it generates the gate drive sequence and insertion state table from the obtained insertion combination and issues it as a control command in the synchronization effective window.

[0116] In some embodiments, Figure 2The adjustment module 204 calculates the arm energy deviation based on the submodule capacitor voltage and arm current; inputs the arm energy deviation into the coupling regulator to generate the modulation bias increment and the second harmonic circulating current reference increment, and limits them to the upper and lower limits of modulation depth and the reference amplitude of circulating current in the grid connection and energy constraint parameters, respectively; executes current closed loop in the inner loop of arm current according to the second harmonic circulating current reference; when any limit is touched, the second harmonic circulating current reference increment is first shrunk according to the preset priority, then the modulation bias increment is shrunk, and the effective insertion number remains unchanged.

[0117] In some embodiments, Figure 2 The refresh module 205 calculates the DC-side current command based on the power reference and executes the current closed loop; it constrains the current command and power change rate according to the safety limit, which includes temperature limit, state of charge boundary and upper limit of charging and discharging power; when a submodule fails or protection is triggered, it sets the submodule's power reference to zero, disconnects the submodule's DC converter and connects the bypass switch; it updates the number of healthy submodules and the minimum number of insertions, and triggers the refresh of the voltage equalization reconstruction parameter set, outputting the new effective number of insertions, modulation bias, second harmonic circulating current reference and power reference.

[0118] In some embodiments, Figure 2 The output module 206 calculates the active current reference and reactive current reference based on the active and reactive power commands from the upper level and the grid connection point voltage to form a three-phase grid-connected current reference; it applies amplitude and rate of change limits to the grid-connected current reference according to the grid connection and energy constraint parameters, and performs consistency verification with the modulation bias and second harmonic circulating current reference; within the synchronization window, it issues control commands, modulation bias, second harmonic circulating current reference, and power reference, and performs gate drive according to the insertion state table to synthesize the three-phase phase voltage; it executes grid-connected current closed loop with the grid-connected current reference as the target, and when the limits in the grid connection and energy constraint parameters are touched, it shrinks the reactive current reference and modulation bias according to the preset priority to keep the effective insertion number unchanged.

[0119] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0120] Figure 3 This is a schematic diagram of the structure of the electronic device 3 provided in an embodiment of this application. Figure 3 As shown, the electronic device 3 of this embodiment includes a processor 301, a memory 302, and a computer program 303 stored in the memory 302 and executable on the processor 301. When the processor 301 executes the computer program 303, it implements the steps in the various method embodiments described above. Alternatively, when the processor 301 executes the computer program 303, it implements the functions of each module / unit in the various device embodiments described above.

[0121] For example, computer program 303 may be divided into one or more modules / units, which are stored in memory 302 and executed by processor 301 to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 303 in electronic device 3.

[0122] Electronic device 3 can be a desktop computer, laptop, handheld computer, cloud server, or other electronic device. Electronic device 3 may include, but is not limited to, processor 301 and memory 302. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 3 and does not constitute a limitation on electronic device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device may also include input / output devices, network access devices, buses, etc.

[0123] Processor 301 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0124] The memory 302 can be an internal storage unit of the electronic device 3, such as a hard disk or RAM. The memory 302 can also be an external storage device of the electronic device 3, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 302 can include both internal and external storage units of the electronic device 3. The memory 302 is used to store computer programs and other programs and data required by the electronic device. The memory 302 can also be used to temporarily store data that has been output or will be output.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0126] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0127] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0128] In the embodiments provided in this application, it should be understood that the disclosed apparatus / computer devices and methods can be implemented in other ways. For example, the apparatus / computer device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. Multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of apparatus or units may be electrical, mechanical, or other forms.

[0129] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0130] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0131] If integrated modules / units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program may include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0132] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although the technical solutions of this application are described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A medium-voltage direct-hanging modular multilevel energy storage grid-connected voltage equalization reconstruction method applied to a three-phase modular multilevel device, characterized in that, The method comprises the following steps: Collecting grid-connected point voltage and current, phase voltage, arm current, submodule capacitor voltage and battery state of charge, determining the number of healthy submodules and the minimum number of insertions, and generating grid-connected and energy constraint parameters; When the trigger condition is met, the comprehensive weight of the submodule is formed based on the state of charge deviation, the capacitor voltage deviation, the health degree and the capacity, and the voltage balancing reconstruction parameter set is reconstructed, which comprises the effective number of insertions, the modulation bias, the second harmonic circulating current reference and the power reference of each submodule DC / DC converter; According to the phase voltage reference and the effective number of insertions, nearest level modulation is adopted, and the submodule insertion combination is determined according to the comprehensive weight and the minimum residence time to form the control instruction; The second harmonic circulating current reference is executed in the arm current inner loop, and the modulation bias and the second harmonic circulating current reference are adjusted according to the arm energy deviation in the energy outer loop; Each submodule DC / DC converter is controlled by charging and discharging according to the power reference and is subjected to safety limiting, and when a submodule fails, the bypass is combined and the voltage balancing reconstruction parameter set is refreshed; The control instruction, the modulation bias, the second harmonic circulating current reference and the power reference are issued to drive the modular multilevel converter to synthesize three-phase phase voltage, and the current corresponding to the upper active and reactive power instruction is output at the grid-connected point; The method comprises the following steps: A health judgment vector is constructed, and a probability consistency test is performed to obtain the number of healthy submodules; Based on the grid-connected point voltage reference peak value, the allowable working voltage of the healthy submodule, the arm reactance voltage drop estimation, the modulation bias and the second harmonic circulating current reference limiting, the integer constraint of the arm voltage synthesis is established to obtain the minimum number of insertions; According to the number of healthy submodules and the minimum number of insertions, the grid-connected point voltage reference and the device voltage withstand parameter are combined to generate the grid-connected and energy constraint parameters.

2. The method of claim 1, wherein, The method comprises the following steps: The state of charge deviation, the capacitor voltage deviation, the health degree and the capacity are dimensionally normalized and segmented and monotonically mapped, and the comprehensive weight is obtained by combining the preset importance coefficient group; According to the comprehensive weight and the grid-connected and energy constraint parameters, the effective number of insertions and the modulation bias are determined by using a solving rule with integer constraint; According to the comprehensive weight, the power reference of the DC / DC converter of each submodule is allocated, and the change rate limit and the state of charge boundary limit are applied; The amplitude and phase of the second harmonic circulating current reference are calculated according to the arm energy target in the grid-connected and energy constraint parameters and the modulation bias, and are limited in the circulating current reference limiting in the grid-connected and energy constraint parameters; The effective number of insertions, the modulation bias, the second harmonic circulating current reference and the power reference constitute the voltage balancing reconstruction parameter set.

3. The method of claim 1, wherein, The method comprises the following steps: The target level and the corresponding target insertion number of the current period are determined according to the phase voltage reference and the effective number of insertions; Screening out healthy sub-modules that do not meet the minimum dwell time, and arranging in descending order of the comprehensive weight to form a candidate set; Selecting an insertion combination matching the target insertion number from the candidate set according to the comprehensive weight, and restricting the insertion difference of the same-phase upper and lower arms to be within a predetermined range; Generating a gate drive sequence and an insertion state table according to the obtained insertion combination, and issuing as the control instruction within a synchronization effective window.

4. The method of claim 1, wherein, The performing of the second harmonic circulating current reference in the arm current inner loop, and the adjusting of the modulation bias and the second harmonic circulating current reference by the arm energy deviation in the energy outer loop, comprises: Calculating an arm energy deviation according to the sub-module capacitor voltage and the arm current; Inputting the arm energy deviation into a coupling regulator to generate a modulation bias increment and a second harmonic circulating current reference increment, and limiting the modulation depth upper and lower limits and the circulating current reference amplitude limits in the grid-connected and energy constraint parameters, respectively; Performing current closed-loop control in the arm current inner loop according to the second harmonic circulating current reference; When any limit is touched, first contract the second harmonic circulating current reference increment, then contract the modulation bias increment according to a preset priority, and keep the effective insertion number unchanged.

5. The method of claim 1, wherein, The direct-current converter of each sub-module is controlled to charge and discharge according to the power reference and is subject to safety amplitude limiting, and when a sub-module fails, the bypass is integrated and the set of equalization reconstruction parameters is refreshed, comprising: Converting a direct-current side current instruction according to the power reference and performing current closed-loop control; Restricting the current instruction and the power change rate according to safety amplitude limiting, wherein the safety amplitude limiting comprises temperature limit, state of charge boundary and upper limit of charge and discharge power; When a sub-module fails or protection is triggered, setting the power reference of the sub-module to zero, disconnecting the direct-current converter of the sub-module and integrating the bypass switch; Updating the number of healthy sub-modules and the minimum insertion number, triggering the refresh of the set of equalization reconstruction parameters, and outputting a new effective insertion number, modulation bias, second harmonic circulating current reference and power reference.

6. The method of claim 3, wherein, The drive modular multilevel converter synthesizes three-phase phase voltages and outputs currents corresponding to upper active and reactive power instructions at a grid-connected point, comprising: Calculating active and reactive current references according to upper active and reactive power instructions and grid-connected point voltages to form three-phase grid-connected current references; Applying amplitude limits and change rate limits to the grid-connected current references according to the grid-connected and energy constraint parameters, and performing consistency checking with the modulation bias and the second harmonic circulating current reference; Issuing the control instruction, the modulation bias, the second harmonic circulating current reference and the power reference within the synchronization effective window, and performing gate drive according to the insertion state table to synthesize three-phase phase voltages; Targeting the grid-connected current references to perform grid-connected current closed-loop control, and when limits in the grid-connected and energy constraint parameters are touched, contracting the reactive current reference and the modulation bias according to a preset priority to keep the effective insertion number unchanged.

7. A medium voltage direct hanging modular multilevel energy storage grid connected voltage sharing reconfiguration device based on the method of any one of claims 1 to 6, applied to a three-phase modular multilevel device, characterized in that, Comprising: A collection module for collecting grid-connected point voltage and current, phase voltage, arm current, sub-module capacitor voltage and battery state of charge, determining the number of healthy sub-modules and the minimum insertion number, and generating grid-connected and energy constraint parameters; The reconstruction module is configured to, when the trigger condition is met, reconstruct a set of voltage-sharing reconstruction parameters based on a comprehensive weight of the state-of-charge deviation, the capacitance voltage deviation, the health degree, and the capacity formation sub-module, wherein the set of voltage-sharing reconstruction parameters comprises an effective insertion number, a modulation bias, a second harmonic circulating reference, and a power reference of each sub-module DC / DC converter. The determination module is configured to determine a sub-module insertion combination according to the phase voltage reference and the effective insertion number by using the nearest level modulation and according to the comprehensive weight and the minimum dwell time, to form a control instruction. The adjustment module is configured to execute the second harmonic circulating reference in an arm current inner loop and to adjust the modulation bias and the second harmonic circulating reference according to an arm energy deviation in an energy outer loop. The refresh module is configured to perform charge and discharge control of each sub-module DC / DC converter according to the power reference and to be subjected to safety limiting, to integrate a bypass and refresh the set of voltage-sharing reconstruction parameters when a sub-module fails. The output module is configured to output the control instruction, the modulation bias, the second harmonic circulating reference, and the power reference, to drive a modular multilevel converter to synthesize a three-phase phase voltage, and to output a current corresponding to an upper active and reactive power instruction at a point of common coupling. The acquisition module is configured to construct a health judgment vector and perform probability consistency verification to obtain a number of healthy sub-modules, to establish an integer constraint of arm voltage synthesis based on a peak value of a point of common coupling voltage reference, an allowable working voltage of a healthy sub-module, an arm reactance voltage drop estimation, and a modulation bias and a second harmonic circulating reference limiting, to obtain a minimum insertion number, and to generate a grid and energy constraint parameter according to the number of healthy sub-modules and the minimum insertion number, in combination with the point of common coupling voltage reference and a device withstand voltage parameter.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method of any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 8. The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.

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