Trench metal gate mosfet structure and preparation method thereof, chip

Abstract

The application belongs to the technical field of power devices, and provides a trench metal gate MOSFET structure, a preparation method thereof and a chip. A trench etching mask is used to define a trench region, a gate trench is etched to reach the N-type drift region under the coverage of the trench etching mask, a double-pattern photolithography process is used to complete pattern transfer by twice photolithography and etching processes using a first sacrificial dielectric layer and a second sacrificial dielectric layer, the first sacrificial dielectric layer is used to form a P-type shielding region at the bottom of the trench, and the second sacrificial dielectric layer is used to form a concave isolation protective layer along the inner wall of the gate trench, so that the etching precision is improved, the nanometer photolithography process can be realized without an extreme ultraviolet photolithography machine, and the process cost is reduced.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a trench metal gate MOSFET structure, its fabrication method, and a chip. Background Technology

[0002] Silicon carbide-based devices, due to their excellent material properties, including wide bandgap, high critical electric field, and good thermal conductivity, offer very high gate density in SiC trench-gate metal-oxide-semiconductor field-effect transistors (SiC TG-MOSFETs). This is achieved without the limitation of parasitic JFET channels found in planar SiC MOSFETs, thus reducing the contribution of channel resistance to the total on-resistance. Compared to traditional planar MOSFETs, TG-MOSFETs can significantly reduce specific on-resistance by accommodating more channels within a given chip area and completely eliminating the JFET effect.

[0003] However, the current fabrication process of SiC trench MOSFETs requires multiple layers of photoresist for photolithography and etching, which is not only costly but also time-consuming. Summary of the Invention

[0004] To address the aforementioned technical issues, this application provides a trench-type metal gate MOSFET structure, its fabrication method, and a chip. A P-type shielding region and an isolation protection layer are formed at the bottom of the gate trench using a dual-pattern photolithography process to reduce the electric field of the central oxide layer at the bottom of the trench-type gate, thereby reducing gate leakage current and improving device reliability.

[0005] The first aspect of this application provides a method for fabricating a trench metal gate MOSFET structure, the method comprising:

[0006] A silicon carbide substrate is provided, and a buffer layer, an N-type drift region, a current spreading material layer, and a P-type doped layer are sequentially formed on the front side of the silicon carbide substrate.

[0007] N-type dopant ions are implanted into a predetermined region of the P-type doped layer to form an N-type doped layer, and a gate trench is formed by etching along a portion of the N-type doped layer, extending into the N-type drift region. The gate trench divides the current spreading material layer into a first current spreading layer and a second current spreading layer, divides the P-type doped layer into a first P-type well region and a second P-type well region, and divides the N-type doped layer into a first N-type doped region and a second N-type doped region.

[0008] After depositing a first sacrificial dielectric material in the gate trench to form a first sacrificial dielectric layer, and forming a first photomask on the first sacrificial dielectric layer, selective etching is performed on the first sacrificial dielectric layer to form a first trench on the first sacrificial dielectric layer.

[0009] After removing the first photomask, the first sacrificial dielectric layer is etched to obtain a second trench extending into the N-type drift region in the direction of the first trench, so as to form a first corner blocking layer and a second corner blocking layer on both sides of the bottom of the second trench, respectively.

[0010] After forming a protective layer along the inner surface of the second trench, a second photomask is formed on the protective layer, and the protective layer is etched under the cover of the second photomask to expose the first region;

[0011] After removing the second photolithography mask, P-type doped ions are implanted, and after removing the protective layer, the first corner blocking layer and the second corner blocking layer, annealing is performed to form a P-type shielding region;

[0012] A second sacrificial dielectric material is deposited to form a second sacrificial dielectric layer, and a third photomask is formed on the second sacrificial dielectric layer to selectively etch the second sacrificial dielectric layer to form a third trench;

[0013] After removing the third photolithography mask, the second sacrificial dielectric layer is etched to obtain a fourth trench and an isolation protective layer; the isolation protective layer is disposed along the inner wall of the fourth trench;

[0014] A concave gate oxide layer is formed on the inner surface of the fourth trench on the isolation protective layer, a gate layer is formed in the groove of the gate oxide layer, and a field oxide layer is formed on the gate layer; wherein the gate oxide layer and the field oxide layer form a closed structure that encloses the gate layer.

[0015] In some embodiments, the preparation method further includes:

[0016] The field oxide layer is etched, and a source electrode material is deposited to form a source layer that contacts the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, both sides of the gate oxide layer, and the field oxide layer.

[0017] Drain electrode material is deposited on the back side of the silicon carbide substrate to form a drain layer.

[0018] In some embodiments, implanting P-type dopant ions into the first region and annealing after removing the first sacrificial dielectric layer to form a P-type shielding region at the bottom of the gate trench includes:

[0019] P-type dopant ions are injected to inject P-type dopant ions into the N-type drift region through the first region;

[0020] After removing the protective layer, the first corner blocking layer and the second corner blocking layer, the material is annealed at 1650-1800°C to form the P-type shielding area at the bottom of the first region.

[0021] In some embodiments, forming a field oxide layer on the gate layer includes:

[0022] A field oxide material is deposited to form the field oxide layer, and photoresist is coated on the field oxide layer. The field oxide layer is etched until the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, and the regions on both sides of the gate oxide layer are exposed; wherein the width of the field oxide layer is greater than the width of the gate layer.

[0023] In some embodiments, the step of removing the first photomask and etching the first sacrificial dielectric layer to obtain a second trench extending into the N-type drift region in the direction of the first trench, and forming a first corner blocking layer and a second corner blocking layer on both sides of the bottom of the second trench, includes:

[0024] After removing the first photolithographic mask, the first sacrificial dielectric layer is etched in its entirety using an etchant, resulting in a second trench extending into the N-type drift region in the direction of the first trench, and exposing a first region that needs to be implanted with P-type doped ions; wherein, the position of the first region is defined by the initial gate structure of the device, and a first corner blocking layer and a second corner blocking layer are formed on both sides of the first region, respectively.

[0025] In some embodiments, the step of removing the third photolithographic mask and then etching the second sacrificial dielectric layer to obtain a fourth trench and an isolation protective layer includes:

[0026] After removing the third photolithography mask, the second sacrificial dielectric layer is etched in its entirety with an etchant to obtain a fourth trench and a concave isolation protective layer; wherein the fourth trench is opposite to the P-type shielding area.

[0027] In some embodiments, the step of removing the third photolithographic mask and then etching the second sacrificial dielectric layer to obtain the fourth trench and the isolation protective layer further includes:

[0028] The etching selectivity ratio of silicon oxide and silicon nitride in the second sacrificial dielectric material is adjusted to regulate the shape of the fourth trench.

[0029] In some embodiments, the interface between the gate layer and the field oxide layer is arc-shaped or stepped.

[0030] A second aspect of this application also provides a trench metal gate MOSFET structure, wherein the trench metal gate MOSFET structure is prepared by any of the preparation methods described above.

[0031] A third aspect of this application also provides a chip, including a trench metal gate MOSFET structure fabricated by the fabrication method described in any of the preceding claims.

[0032] The beneficial effects of this application's embodiments are as follows: the trench region is defined by a trench etching mask, and a gate trench extending into the N-type drift region is formed under the coverage of the trench etching mask. The pattern transfer is completed in two photolithography processes using a first sacrificial dielectric layer and a second sacrificial dielectric layer. A P-type shielding region is formed at the bottom of the trench using the first sacrificial dielectric layer, and a concave isolation protection layer is formed along the inner wall of the gate trench using the second sacrificial dielectric layer. This improves etching accuracy, enables nanolithography without extreme ultraviolet lithography, and reduces process costs. Attached Figure Description

[0033] Figure 1 This is a schematic flowchart of a method for fabricating a trench metal gate MOSFET structure provided in an embodiment of this application;

[0034] Figure 2 This is a schematic diagram of a portion of the fabrication process of the trench metal gate MOSFET structure provided in the embodiments of this application;

[0035] Figure 3 This is a schematic diagram of a portion of the fabrication process of the trench metal gate MOSFET structure provided in the embodiments of this application;

[0036] Figure 4 This is a schematic diagram of a portion of the fabrication process of the trench metal gate MOSFET structure provided in the embodiments of this application;

[0037] Figure 5 This is a schematic diagram of a portion of the fabrication process of the trench metal gate MOSFET structure provided in the embodiments of this application;

[0038] Figure 6 This is a schematic diagram of a portion of the fabrication process of the trench metal gate MOSFET structure provided in the embodiments of this application;

[0039] Figure 7 This is a schematic diagram of a portion of the fabrication process of the trench metal gate MOSFET structure provided in the embodiments of this application;

[0040] Figure 8This is a schematic flowchart of a method for fabricating a trench metal gate MOSFET structure provided in an embodiment of this application;

[0041] Figure 9 This is a schematic diagram of a portion of the fabrication process of the trench metal gate MOSFET structure provided in the embodiments of this application;

[0042] Figure 10 This is a schematic diagram of one structure of a silicon carbide power device prepared by the method for preparing a trench metal gate MOSFET structure provided in this application embodiment;

[0043] Figure 11 This is a schematic diagram of one structure of a silicon carbide power device prepared by the method for preparing a trench metal gate MOSFET structure provided in this application embodiment;

[0044] Figure 12 This is a schematic diagram of one of the structures of silicon carbide power devices prepared by the trench metal gate MOSFET structure preparation method provided in this application embodiment. Detailed Implementation

[0045] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0046] TG-MOSFETs can significantly reduce specific on-resistance by accommodating more channels on a given chip area and completely eliminating the JFET effect. However, for conventional SiC trench MOSFETs in reverse blocking mode, the high electric field in the gate oxide layer at the bottom of the trench is a major problem, which limits the breakdown voltage (VBR) to gate oxide collapse at voltages far below the inherent breakdown capability of the drift region semiconductor junction.

[0047] To address the aforementioned technical problems, this application provides a method for fabricating dual patterns for silicon carbide power devices. (See attached document.) Figure 1 As shown, the fabrication method of the trench metal gate MOSFET structure in this embodiment includes steps S100 to S900.

[0048] In step S100, a silicon carbide substrate 210 is provided, and a buffer layer 220, an N-type drift region 230, a current spreading material layer 240, and a P-type doped layer 250 are sequentially formed on the front side of the silicon carbide substrate 210.

[0049] In this embodiment, N-type and P-type impurities can be sequentially implanted onto the front side of the silicon carbide substrate 210 via epitaxial growth or ion implantation to form a buffer layer 220, an N-type drift region 230, a current spreading material layer 240, and a P-type doped layer 250, as shown below. Figure 2 The schematic structure (a) is shown in the figure.

[0050] In some embodiments, the buffer layer 220 is N-type doped, and the doping concentration of the buffer layer 220 is less than the doping concentration of the N-type drift region 230.

[0051] In step S200, N-type dopant ions are implanted in a preset region of the P-type doped layer 250 to form an N-type doped layer 260, and a gate trench 311 extending into the N-type drift region 230 is formed under the cover of the trench etching mask 301.

[0052] In this embodiment, combined with Figure 2 As shown in the schematic structure (a), the preset region of the P-type doped layer 250 can be its central region. By injecting N-type dopant ions into the central region of the P-type doped layer 250, the injection depth of the N-type dopant ions is less than the thickness of the P-type doped layer 250, so that the thickness of the formed N-type doped layer 260 is less than the thickness of the P-type doped layer 250.

[0053] Combination Figure 2 As shown in the schematic structure (b), a trench etching mask 301 is used to define the trench region. The trench etching mask 301 covers the P-type doped layer 250 and the N-type doped layer 260, exposing the trench region to be etched. Combined with... Figure 2 As shown in schematic structure (b), a gate trench 311 extending into the N-type drift region 230 is formed under the cover of the trench etching mask 301. The depth of the gate trench 311 is greater than the sum of the thicknesses of the P-type doped layer 250 and the current spreading material layer 240. After etching, the trench etching mask 301 is removed. Figure 2 The schematic structure shown in (b) is as follows. The formed gate trench 311 divides the current spreading material layer 240 into a first current spreading layer 241 and a second current spreading layer 242, divides the P-type doped layer 250 into a first P-type well region 251 and a second P-type well region 252, and divides the N-type doped layer 260 into a first N-type doped region 261 and a second N-type doped region 262.

[0054] In some embodiments, an N-type doped layer 260 is formed by implanting N-type dopant ions into the central region of the P-type doped layer 250, and the first P-type well region 251 and the second P-type well region 252 are L-shaped structures; the first N-type doped region 261 is formed on the horizontal portion of the first P-type well region 251, and the second N-type doped region 262 is formed on the horizontal portion of the second P-type well region 252.

[0055] In some embodiments, the gate trench 311 extends into the N-type drift region 230, and the lower surface of the gate trench 311 forms the bottom of the recess in the N-type drift region 230. The distance between the bottom of the recess in the N-type drift region 230 and the lower surface of the current spreading material layer 240 is greater than the thickness of the current spreading material layer 240. The N-type drift region 230 has a concave structure. The first current spreading layer 241 and the first P-type well region 251 are formed on the first side of the N-type drift region 230, and the second current spreading layer 242 and the second P-type well region 252 are formed on the second side of the N-type drift region 230.

[0056] In step S300, a first sacrificial dielectric material is deposited in the gate trench 311 to form a first sacrificial dielectric layer 401, and a first photomask 302 is formed on the first sacrificial dielectric layer 401. Then, the first sacrificial dielectric layer 401 is selectively etched to form a first trench 312 on the first sacrificial dielectric layer 401.

[0057] In this embodiment, combined with Figure 3 As shown, a first sacrificial dielectric layer 401 can be formed by depositing a first sacrificial dielectric material on the bottom and inner wall of the gate trench 311, as well as on the P-type doped layer 250 and the N-type doped layer 260. Figure 3 The schematic structure (b) is shown in the figure. After passing through the first photolithography mask 302, the first sacrificial dielectric layer 401 is selectively etched to form a first trench 312 on the first sacrificial dielectric layer 401, and the bottom of the new first trench 312 extends into the interior of the first sacrificial dielectric layer 401.

[0058] In some embodiments, the bottom of the first trench 312 is lower than the lower surfaces of the first N-type doped region 261 and the second N-type doped region 262.

[0059] In step S400, after removing the first photomask 302, the first sacrificial dielectric layer 401 is etched to obtain a second trench 313 extending into the N-type drift region 230 in the direction of the first trench 312, and a first corner blocking layer 411 and a second corner blocking layer 412 are formed on both sides of the bottom of the second trench 313, respectively.

[0060] In this embodiment, the structure after removing the first photolithographic mask 302 is as follows: Figure 3The schematic structure (c) is shown in the diagram. After removing the first photomask 302, the first sacrificial dielectric layer 401 is etched. Due to the presence of the first trench 312, the contact N-type drift region 230 is etched first along the depth direction of the first trench 312 to obtain the second trench 313, exposing the first region that needs to be implanted with P-type doped ions. The first region is located at the bottom region of the second trench 313. At this time, all the first sacrificial dielectric material on the first N-type doped region 261 and the second N-type doped region 262 is etched away to obtain the second trench 313. A first corner barrier layer 411 and a second corner barrier layer 412 are formed on both sides of the bottom of the second trench 313, as shown in the diagram. Figure 3 The schematic structure (d) is shown in the figure.

[0061] In step S500, after forming a protective layer 413 along the inner surface of the second trench 313, a second photomask 303 is formed on the protective layer 413, and the protective layer 413 is etched under the cover of the second photomask 303 to expose the first region.

[0062] In this embodiment, a protective layer 413 is formed along the inner surface of the second groove 313 to achieve the following: Figure 4 The schematic structure (a) shows that a second photomask 303 is formed on the protective layer 413 to obtain the structure shown. Figure 4 The schematic structure (b) is etched under the protection of the second photolithographic mask 303 to obtain the ion implantation trench 314, as shown. Figure 4 The schematic structure (c) is shown in the figure.

[0063] In step S600, after removing the second photolithography mask 303, P-type doped ions are implanted, and after removing the protective layer 413, the first corner blocking layer 411 and the second corner blocking layer 412, annealing is performed to form a P-type shielding region 310.

[0064] In this embodiment, the first corner barrier layer 411 and the second corner barrier layer 412 can serve as new etching protection layers to form new ion implantation patterns or etching patterns, combined with Figure 4 and Figure 5 As shown, after removing the second photolithographic mask 303, as Figure 4 The schematic structure (d) shows the implantation of P-type doped ions into the first region at the bottom of the ion implantation trench 314, as shown in the diagram. Figure 5 The schematic structure (a) is shown in the figure. The result is obtained after removing the protective layer 413, the first corner blocking layer 411, and the second corner blocking layer 412. Figure 5 The schematic structure (b) shows a new trench 315 obtained after removing the protective layer 413, the first corner blocking layer 411, and the second corner blocking layer 412. After removing the protective layer 413, the first corner blocking layer 411, and the second corner blocking layer 412, annealing is performed, forming a P-type shielding area 310. Figure 5 In the schematic structure (b), the P-type shielding area 310 is formed at the bottom of the groove of the N-type drift area 230, and the width of the P-type shielding area 310 is less than or equal to the width of the groove 315.

[0065] In some embodiments, the doping concentration of the P-type shielding region 310 exhibits a gradient distribution.

[0066] In step S700, a second sacrificial dielectric material is deposited to form a second sacrificial dielectric layer 402, and a third photomask 304 is formed on the second sacrificial dielectric layer 402 to selectively etch the second sacrificial dielectric layer 402 to form a third trench 316.

[0067] In this embodiment, combined with Figure 5 As shown, a second sacrificial dielectric material is deposited on the bottom and inner wall of the third trench 316, as well as on the P-type doped layer 250 and the N-type doped layer 260 to form a second sacrificial dielectric layer 402, thus obtaining... Figure 5 The schematic structure (c) is shown in the diagram. A third photomask 304 is formed on the second sacrificial dielectric layer 402 to obtain... Figure 5 The schematic structure (d) is shown in the diagram. The third trench 316 is formed by selective etching of the second sacrificial dielectric layer 402 under the coverage of the third photolithographic mask 304. Figure 6 The schematic structure in (a) is shown. The third photomask 304 is removed to obtain... Figure 6 The schematic structure (b) is shown in the figure.

[0068] In step S800, combined Figure 6 As shown, after removing the third photolithography mask 304, the second sacrificial dielectric layer 402 is etched to obtain a fourth trench 317 and an isolation protective layer 320. The fourth trench 317 makes the isolation protective layer 320 have a concave structure. The isolation protective layer 320 is disposed along the bottom of the fourth trench 317 and the inner walls on both sides of its bottom.

[0069] In this embodiment, after selective etching of the second sacrificial dielectric layer 402, a third trench 316 is formed within the second sacrificial dielectric layer 402. Then, the second sacrificial dielectric layer 402 is fully etched to obtain a fourth trench 317. The fourth trench 317 is located at the opening of the isolation protective layer 320, such as... Figure 6 The schematic structure (c) is shown in the figure.

[0070] In this embodiment, the design pattern is split into two sets of photomasks according to odd / even lines or spatial positions using a dual-pattern photolithography process. This ensures that the spacing between each set of photomasks is greater than the photolithographic resolution limit. During the photolithography stage, a marker layer is added to ensure that the patterns from the two exposures are accurately superimposed, with an error control of <3nm. In the deposition stage, the core is first deposited, then etched to form the initial lines. Then, a sacrificial dielectric material (such as silicon oxide or silicon nitride) can be deposited using ALD or CVD to form the sidewall material. The sidewalls are etched to form double the lines, and then the core is removed to obtain the final pattern.

[0071] In some embodiments, during the deposition of sidewall material, spacers can be selectively etched to retain them. Using the spacers as a mask, the underlying material can be selectively etched to form new gate trenches. By utilizing material properties (such as etching selectivity and surface energy differences) or the physical properties of the deposition / etching process, the pattern can be automatically aligned without multiple photolithography alignments, thereby improving etching accuracy, increasing yield, and reducing the complexity of the photolithography process.

[0072] In some embodiments, the first side of the isolation layer 320 contacts the bottom of the first step of the first current spreading layer 241 and the gate oxide layer 410; the second side of the isolation layer 320 contacts the bottom of the second step of the second current spreading layer 242 and the gate oxide layer 410.

[0073] In this embodiment, the first side of the P-type shielding region 310 and the second side of the isolation protection layer 320 on both sides of the gate oxide at the bottom of the trench can further reduce the electric field concentration effect in the corner region at the bottom of the gate, avoid high electric field collapse, reduce the gate leakage current phenomenon of the device, and improve the reliability of the device.

[0074] In step S900, after forming a concave gate oxide layer 410 on the isolation protection layer 320 and along the inner surface of the fourth trench 317, a gate layer 500 is formed in the groove of the gate oxide layer 410, and a field oxide layer 420 is formed on the gate layer 500.

[0075] In this embodiment, combined with Figure 6 and Figure 7 As shown, a gate oxide layer 410 is deposited at the bottom and inner wall of the fourth trench 317. Figure 6 The schematic structure (d) shows that the gate layer material 403 is filled into the groove of the gate oxide layer 410. Figure 7 In the schematic structure (a), the gate layer material is etched to form the gate layer 500, as shown. Figure 7 The schematic structure (b) is shown in the diagram. Combined with... Figure 7As shown in the schematic structure (c), a field oxide material is deposited on the gate layer to form a field oxide layer 420, and a gate oxide layer 410 is formed on the P-type shielding region 310. The gate oxide layer 410 has a concave structure, and the gate oxide layer 410 and the field oxide layer 420 form a closed structure that encloses the gate layer 500.

[0076] In some embodiments, a first N-type doped region 261 is formed between a first side portion of the gate oxide layer 410 and a first P-type well region 251, and a second N-type doped region 262 is formed between a second side portion of the gate oxide layer 410 and a second P-type well region 252. The spacing between the two sides of the gate oxide layer 410 gradually increases from the bottom towards the opening, and the height of the gate oxide layer 410 is greater than the sum of the heights of the first current spreading layer 241 and the first P-type well region 251. The first side portion and the second side portion of the isolation protection layer 320 are located on both sides of the gate oxide layer 410, and the bottom of the first side portion and the second side portion of the isolation protection layer 320 are flush with the bottom of the gate oxide layer 410. The source layer 120 is in contact with the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, the two sides of the gate oxide layer 410, and the field oxide layer 420.

[0077] In some embodiments, see Figure 8 As shown, the preparation method in this embodiment further includes steps S910 to S920.

[0078] In step S910, after etching the field oxide layer 420, source electrode material is deposited to form a source layer 120 that contacts the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, both sides of the gate oxide layer 410, and the field oxide layer 420.

[0079] Combination Figure 9 As shown in the schematic structure (a), photoresist 305 is formed on the field oxide layer 420 to define the source electrode region. Then, under the coverage of the photoresist 305, the field oxide layer 420 is etched to expose parts of the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, and the second N-type doped region 262, as shown in the schematic structure (a). Figure 9 The schematic structure (b) is shown in the diagram. After removing the photoresist 305, source electrode material is deposited to form the source layer 120, as shown in the diagram. Figure 9 The schematic structure (c) is shown in the figure.

[0080] In step S920, drain electrode material is deposited to form a drain layer 110 on the back side of the silicon carbide substrate 210.

[0081] In this embodiment, the trench metal gate MOSFET structure obtained by forming the source layer 120 and the drain layer 110 is as follows: Figure 10 As shown, the trench metal gate MOSFET structure includes: a drain layer 110, a silicon carbide substrate 210, a buffer layer 220, an N-type drift region 230, a first current spreading layer 241, a second current spreading layer 242, a first P-type well region 251, a second P-type well region 252, a gate oxide layer 410, an isolation protection layer 320, a gate layer 500, a P-type shielding region 310, a first N-type doped region 261, a second N-type doped region 262, a field oxide layer 420, and a source layer 120. A drain layer 110, a silicon carbide substrate 210, a buffer layer 220, and an N-type drift region 230 are stacked. The N-type drift region 230 has a concave structure. A first current spreading layer 241 and a first P-type well region 251 are formed on the first side of the N-type drift region 230, and a second current spreading layer 242 and a second P-type well region 252 are formed on the second side of the N-type drift region 230. A P-type shielding region 310 is formed at the bottom of the groove of the N-type drift region 230. An isolation protection layer 320 is formed on the P-type shielding region 310 and has a concave structure. A gate oxide layer 410 is located on the isolation protection layer 320 and has a concave structure. Its two sides are respectively disposed along the first current spreading layer 241 and the second current spreading layer 242. The gate oxide layer 410 and the field oxide layer 420 form a closed structure that encloses the gate layer 500. The first N-type doped region 261 is formed between the first side of the gate oxide layer 410 and the first P-type well region 251, and the second N-type doped region 262 is formed between the second side of the gate oxide layer 410 and the second P-type well region 252. The spacing between the two sides of the gate oxide layer 410 gradually increases from the bottom to the opening. The height of the gate oxide layer 410 is greater than the sum of the heights of the first current extension layer 241 and the first P-type well region 251. The first side and the second side of the isolation protection layer 320 are located on both sides of the gate oxide layer 410, and the bottom of the first side and the second side of the isolation protection layer 320 are flush with the bottom of the gate oxide layer 410. The source layer 120 is in contact with the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, the two sides of the gate oxide layer 410, and the field oxide layer 420.

[0082] In some embodiments, such as Figure 11 As shown, the gate oxide layer 410 is formed on the isolation protective layer 320, and the gate oxide layer 410 has a concave structure with an arc-shaped bottom. The first side and the second side of the isolation protective layer 320 are respectively attached to the bottom sides of the gate oxide layer 410, and the first side and the second side of the isolation protective layer 320 are arc-shaped.

[0083] In some embodiments, such as Figure 11 As shown, the gate oxide layer 410 has a concave structure. The first side and the second side of the gate oxide layer 410 extend outward at their opening positions, respectively. The left extension portion does not exceed the left boundary of the first N-type doped region 261, and the right extension portion does not exceed the right boundary of the second N-type doped region 262.

[0084] In some embodiments, the thickness of the gate oxide layer 410 gradually increases from the drain layer 110 toward the source layer 120, thereby improving the electric field distribution in the first current spread layer 241, the first P-type well region 251, the first N-type doped region 261, the second current spread layer 242, the second P-type well region 252, and the second N-type doped region 262. This helps to reduce the electric field accumulation in the N-type drift region 230 and also facilitates the gradual reduction of the trench gate width, minimizing the width of the central oxide layer at the bottom, which helps to reduce the gate drain charge Qgd of the device.

[0085] In some embodiments, the width between the two sidewalls of the gate oxide layer 410 gradually increases from the drain layer 110 toward the source layer 120. This results in an electric field distribution within the first current spread layer 241, the first P-type well region 251, the first N-type doped region 261, the second current spread layer 242, the second P-type well region 252, and the second N-type doped region 262. This helps to reduce the electric field accumulation within the N-type drift region 230 and also facilitates the gradual reduction of the trench gate width, minimizing the width of the central oxide layer at the bottom, which helps to reduce the gate drain charge Qgd of the device.

[0086] In some embodiments, the thickness of the isolation protection layer 320 gradually decreases from both sides to the middle in the longitudinal direction, which is the direction from the drain layer 110 to the source layer 120. This helps to reduce the electric field accumulation in the N-type drift region 230 and also facilitates the gradual reduction of the width of the trench gate, so that the width of the central oxide layer at the bottom is minimized, which helps to reduce the gate drain charge Qgd of the device.

[0087] In some embodiments, the dielectric constant of the isolation protective layer 320 is greater than that of the silicon oxide material, and the isolation protective layer 320 can be a silicon nitride layer.

[0088] In some embodiments, the gate oxide layer 410 has a symmetrical structure.

[0089] In some embodiments, such as Figure 12 As shown, the inner wall of the groove in the gate oxide layer 410 has a stepped structure.

[0090] In this embodiment, the inner diameter of the groove in the gate oxide layer 410 gradually decreases from the source layer 120 to the drain layer 110, and the inner wall of the groove in the gate oxide layer 410 has a stepped structure.

[0091] In some embodiments, the two sides of the gate oxide layer 410 have a stepped structure.

[0092] In this embodiment, the inner wall of the groove of the gate oxide layer 410 has a stepped structure, and the outer surfaces of both sides of the gate oxide layer 410 also have a stepped structure.

[0093] In TG-MOS devices, during reverse operation and high-voltage drain operation, an electric field concentration effect exists at the gate oxide corners at the bottom of the trench gate, causing gate oxide collapse and leakage current, which may prevent the device from passing reliability tests. In this application, a P-type shielding region 310 is formed at the bottom of the trench in the N-type drift region 230, and a concave isolation protection layer 320 is formed on the P-type shielding region 310. The isolation protection layer 320 wraps around the bottom of the gate oxide layer 410, and the gate oxide layer 410 and the field oxide layer 420 form a closed structure enclosing the gate layer 500. This reduces the electric field in the central oxide layer at the bottom of the trench gate. Furthermore, the P-type shielding region 310 and the sides of the isolation protection layer 320 further reduce the electric field concentration effect at the bottom corners of the gate, preventing high-field collapse, reducing gate leakage current, and improving device reliability.

[0094] In some embodiments, step S600 involves implanting P-type dopant ions into the first region and then annealing after removing the first sacrificial dielectric layer 401 to form a P-type shielding region at the bottom of the gate trench. This includes: implanting P-type dopant ions to implant P-type dopant ions into the N-type drift region 230 through the first region; and annealing after removing the protective layer 413, the first corner barrier layer 411, and the second corner barrier layer 412 at an environment of 1650-1800°C to form a P-type shielding region 310 at the bottom of the first region.

[0095] In this embodiment, using the first sacrificial dielectric layer 401 as a mask, P-type dopant ions can be injected into the N-type drift region 230 through the first region at the bottom of the trench 314 to form a P-type shielding region 310. With the first sacrificial dielectric layer 401 as a mask, the injection process of P-type dopant ions can be carried out in multiple stages, so that the doping concentration of the P-type shielding region 310 gradually changes in a trapezoidal shape.

[0096] In some embodiments, the p-type doped ion may include aluminum ions.

[0097] In some embodiments, step S600, forming a field oxide layer 420 on the gate layer 500 includes: depositing a field oxide material to form the field oxide layer 420, coating the field oxide layer 420 with photoresist, and etching the field oxide layer 420 until the regions of the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, and the regions on both sides of the gate oxide layer 410 are exposed.

[0098] In this embodiment, photoresist is used to define the coverage area of ​​the field oxide layer 420, and silicon oxide material is etched under the photoresist coverage up to the first P-type well region 251 and the second P-type well region 252 to form the field oxide layer 420 on the gate oxide layer 410 and the gate layer 500. By etching the field oxide layer 420, the width of the field oxide layer 420 is set to be greater than the width of the gate layer 500, so that the subsequent electrode deposition material can contact the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, and both sides of the gate oxide layer 410.

[0099] In some embodiments, the gate layer 500 may be an N-type polycrystalline silicon material or a TiN material.

[0100] In some embodiments, in step S400, after removing the first photomask 302, the first sacrificial dielectric layer 401 is etched to obtain a second trench extending into the N-type drift region in the direction of the first trench, and a first corner blocking layer 411 and a second corner blocking layer 412 are formed on both sides of the bottom of the second trench, respectively. This includes: after removing the first photomask 302, the first sacrificial dielectric layer 401 is fully etched with an etchant to obtain a second trench extending into the N-type drift region in the direction of the first trench, and exposing a first region that needs to be implanted with P-type doped ions.

[0101] In this embodiment, after removing the first photolithography mask 302, the first sacrificial dielectric layer 401 is fully etched using an etchant, resulting in a second trench 313 extending into the N-type drift region 230 in the direction of the first trench 312. Due to the presence of the first trench 312, the N-type drift region 230 is first etched along the depth direction of the first trench 312, thereby exposing the first region in the second trench 313 that needs to be implanted with P-type doped ions. The first region is located in the bottom region of the second trench 313.

[0102] In some embodiments, the location of the first region is defined by the initial gate structure of the device. A first corner barrier layer 411 and a second corner barrier layer 412 are formed on both sides of the first region, respectively. The first corner barrier layer 411 and the second corner barrier layer 412 are used to define the ion implantation region. P-type doped ions are injected into the N-type drift region 230 through the first region to form a P-type shielding region 310.

[0103] In some embodiments, the location of the first region is defined by the initial gate structure of the device. Depositing silicon nitride as an etch stop layer can ensure high-precision pattern transfer, control critical dimensions, and reduce process defects. Specifically, in the photolithography pattern transfer process, the etch stop layer utilizes the difference in etching rate with adjacent materials (such as silicon oxide or polysilicon) to precisely stop etching during pattern transfer, avoiding over-etching of the underlying structure. Furthermore, the etch stop layer can also prevent the loss of stop layer height inside and outside the sidewalls, ensuring the uniformity of subsequent pattern transfer.

[0104] In some embodiments, the etching selectivity ratio between the etch stop layer and the adjacent material is greater than or equal to 10:1.

[0105] In some embodiments, by adjusting the nitrogen content in the silicon nitride material, the etch stop layer can include a multi-layer structure. Adjusting the etching rate of the etch stop layer can also facilitate the adjustment of the shape and size of the first region.

[0106] In some embodiments, step S800, which involves removing the third photolithography mask and then etching the second sacrificial dielectric layer to obtain a fourth trench and an isolation protection layer, includes: removing the third photolithography mask and then using an etchant to fully etch the second sacrificial dielectric layer to obtain a fourth trench and a concave isolation protection layer; wherein the fourth trench is opposite to the P-type shielding area.

[0107] In this embodiment, after removing the third photolithography mask, the second sacrificial dielectric layer is fully etched with an etchant to obtain the fourth trench 317. Due to the presence of the third trench 316, the thickness of the isolation protective layer 320 relative to the third trench 316 is smaller. The isolation protective layer 320 is formed on both sides of the third trench 316. Furthermore, the fourth trench 317 is opposite to the P-type shielding region 310. The area where the bottom of the fourth trench 317 contacts the N-type drift region 230 is defined as the first region. The position of the P-type shielding region 310 is defined by the initial gate structure of the device, and the position of the first region is defined by the initial gate structure of the device. A first corner blocking layer 411 and a second corner blocking layer 412 are formed on both sides of the first region, respectively. In the second photolithography pattern transfer process, the mandrel is first determined, an initial linear pattern is established, and silicon nitride material is deposited as an etch stop layer. The mandrel provides a geometric reference for subsequent sidewall deposition, and the sidewall thickness of the etch stop layer is determined, which can ensure high-precision pattern transfer, control critical dimensions, and reduce process defects. Then, an interlayer dielectric layer is deposited, and an etchant is used to etch the bottom of the gate trench to retain the silicon nitride material on both sides of the P-type shielding region 310 as the first side and the second side of the isolation protection layer 320.

[0108] In the photolithography pattern transfer process, the etch stop layer utilizes the difference in etching rate with adjacent materials (such as silicon oxide and polysilicon) to precisely stop etching during the pattern transfer process, avoiding over-etching of the underlying structure. Furthermore, the etch stop layer can also prevent the loss of height of the stop layer inside and outside the sidewalls, ensuring the uniformity of subsequent pattern transfer.

[0109] In some embodiments, step S500, after removing the third photomask, etching the second sacrificial dielectric layer to obtain the fourth trench and the isolation protective layer, further includes: adjusting the etching selectivity ratio of silicon oxide material and silicon nitride material in the second sacrificial dielectric material to adjust the shape of the fourth trench.

[0110] In this embodiment, selective removal is achieved by utilizing the difference in etching rates of different materials (such as silicon oxynitride and silicon). By utilizing material properties (such as etching selectivity and surface energy differences) or the physical properties of the deposition / etching process, the pattern can be automatically aligned without the need for multiple photolithographic alignments.

[0111] In some embodiments, the interface between the gate layer 500 and the field oxide layer 420 is arc-shaped or stepped.

[0112] In some embodiments, the top of the first side step of the gate oxide layer 410 is formed on the upper surface of the first N-type doped region 261; the top of the second side step of the gate oxide layer 410 is formed on the upper surface of the second N-type doped region 262.

[0113] In some embodiments, the interface between the gate layer 500 and the field oxide layer 420 is arc-shaped, with the apex of the arc close to the P-type shielding region 310.

[0114] In some embodiments, the contact interface between the P-type shielding region 310 and the gate oxide layer 410 is located between the first side of the isolation protection layer 320 and the second side of the isolation protection layer 320.

[0115] In this embodiment, compared to the dual-trench MOSFET structure, this application uses dual-pattern photolithography to apply bottom corner barrier oxide layers at the bottom corners of both sides of the trench in the SiC trench gate MOSFET. This reduces the electric field concentration effect at the corners, avoids high-field collapse, reduces gate leakage current, and improves device operational reliability. This process and structure can significantly reduce the high electric field of the central oxide layer at the bottom of the trench gate, and also reduce the cell size and the impedance of the JFET region within the device, improving the specific on-resistance R of the device. on，sp , compared to the on-resistance R on，sp For the on-resistance R on The product of the chip area and the on-resistance R is used to characterize the intrinsic properties of the semiconductor device. on Used to characterize the absolute conduction loss of a device.

[0116] The trench-gate MOSFET structure (DT_MOS) fabricated by the method provided in this embodiment significantly reduces the electric field concentration effect at the corners compared to the example silicon carbide power device (without isolation protection layer 320), avoiding high electric field collapse and reducing gate leakage current, thus improving device operational reliability. Furthermore, the breakdown voltage BV of the silicon carbide power device (DT_MOS) is significantly improved compared to the example silicon carbide power device, the on-resistance Ron (56.73Ω) of the silicon carbide power device (DT_MOS) is significantly reduced compared to the example silicon carbide power device, and the gate charge Qg of the silicon carbide power device (DT_MOS) is significantly reduced compared to the example silicon carbide power device.

[0117] Static FOM (Field-of-Metrology) measures the "area-resistance" benchmark of device conduction efficiency, determining the upper limit of chip cost and thermal design. Dynamic FOM is typically used to evaluate device performance during switching, especially charge-related characteristics. It can quantify the topology-sensitive index of switching-conduction loss balance, driving high-frequency and energy efficiency optimization. To reduce switching losses and improve high-frequency application performance, it is necessary to improve device performance by reducing gate charge or on-resistance; the smaller the value, the better. Comparison of simulation parameters for several devices shows that the static FOM of the silicon carbide power device (DT_MOS) is significantly improved compared to the example silicon carbide power device, and the dynamic FOM of the silicon carbide power device (DT_MOS) is significantly reduced compared to the example silicon carbide power device. The silicon carbide power device (DT_MOS) fabricated by the trench metal gate MOSFET structure fabrication method provided in this application can significantly achieve optimizations in both dynamic and static FOM compared to the example silicon carbide power device.

[0118] This application also provides a chip, including a trench metal gate MOSFET structure fabricated by the fabrication method of any of the above embodiments.

[0119] In this embodiment, the chip includes a chip substrate, on which one or more trench metal gate MOSFET structures prepared by the preparation method of any of the above embodiments are disposed.

[0120] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the trench metal gate MOSFET structure.

[0121] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0122] In this embodiment, one or more trench-type metal gate MOSFET structures prepared by the preparation method in any of the above embodiments are provided on the chip. In the chip process, the trench region is defined by a trench etching mask. Under the coverage of the trench etching mask, a gate trench extending into the N-type drift region is etched. A dual-patterning photolithography process is used to complete the pattern transfer by using a first sacrificial dielectric layer and a second sacrificial dielectric layer in two photolithography and etching processes. A P-type shielding region is formed at the bottom of the trench using the first sacrificial dielectric layer, and a concave isolation protection layer is formed along the inner wall of the gate trench using the second sacrificial dielectric layer. This improves the etching accuracy and enables nano-lithography without an extreme ultraviolet lithography machine, thus reducing the process cost.

[0123] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0124] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0125] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0126] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0127] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for fabricating a trench-type metal-gate MOSFET structure, characterized in that, The preparation method includes: A silicon carbide substrate is provided, and a buffer layer, an N-type drift region, a current spreading material layer, and a P-type doped layer are sequentially formed on the front side of the silicon carbide substrate. N-type dopant ions are implanted into a predetermined region of the P-type doped layer to form an N-type doped layer, and a gate trench is formed by etching along a portion of the N-type doped layer, extending into the N-type drift region. The gate trench divides the current spreading material layer into a first current spreading layer and a second current spreading layer, divides the P-type doped layer into a first P-type well region and a second P-type well region, and divides the N-type doped layer into a first N-type doped region and a second N-type doped region. After depositing a first sacrificial dielectric material in the gate trench to form a first sacrificial dielectric layer, and forming a first photomask on the first sacrificial dielectric layer, selective etching is performed on the first sacrificial dielectric layer to form a first trench on the first sacrificial dielectric layer. After removing the first photomask, the first sacrificial dielectric layer is etched to obtain a second trench extending into the N-type drift region in the direction of the first trench, so as to form a first corner blocking layer and a second corner blocking layer on both sides of the bottom of the second trench, respectively. After forming a protective layer along the inner surface of the second trench, a second photomask is formed on the protective layer, and the protective layer is etched under the cover of the second photomask to expose the first region; After removing the second photolithography mask, P-type doped ions are implanted, and after removing the protective layer, the first corner blocking layer and the second corner blocking layer, annealing is performed to form a P-type shielding region; A second sacrificial dielectric material is deposited to form a second sacrificial dielectric layer, and a third photomask is formed on the second sacrificial dielectric layer to selectively etch the second sacrificial dielectric layer to form a third trench; After removing the third photolithography mask, the second sacrificial dielectric layer is etched to obtain a fourth trench and an isolation protective layer; the isolation protective layer is disposed along the inner wall of the fourth trench; A concave gate oxide layer is formed on the inner surface of the fourth trench on the isolation protective layer, a gate layer is formed in the groove of the gate oxide layer, and a field oxide layer is formed on the gate layer; wherein the gate oxide layer and the field oxide layer form a closed structure that encloses the gate layer.

2. The preparation method according to claim 1, characterized in that, The preparation method further includes: The field oxide layer is etched, and source electrode material is deposited to form a source layer that contacts the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, both sides of the gate oxide layer, and the field oxide layer. Drain electrode material is deposited on the back side of the silicon carbide substrate to form a drain layer.

3. The preparation method according to claim 1 or 2, characterized in that, The process of implanting P-type doped ions after removing the second photolithographic mask, and then annealing after removing the protective layer, the first corner barrier layer, and the second corner barrier layer, includes: P-type dopant ions are injected to inject P-type dopant ions into the N-type drift region through the first region; After removing the protective layer, the first corner blocking layer and the second corner blocking layer, the material is annealed at 1650-1800°C to form the P-type shielding area at the bottom of the first region.

4. The preparation method according to claim 2, characterized in that, The formation of a field oxide layer on the gate layer includes: A field oxide material is deposited to form the field oxide layer, and photoresist is coated on the field oxide layer. The field oxide layer is etched until the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, and the regions on both sides of the gate oxide layer are exposed; wherein the width of the field oxide layer is greater than the width of the gate layer.

5. The preparation method according to claim 1 or 2, characterized in that, The step of removing the first photomask and etching the first sacrificial dielectric layer to obtain a second trench extending into the N-type drift region in the direction of the first trench, and forming a first corner blocking layer and a second corner blocking layer on both sides of the bottom of the second trench, includes: After removing the first photolithographic mask, the first sacrificial dielectric layer is etched in its entirety using an etchant, resulting in a second trench extending into the N-type drift region in the direction of the first trench, and exposing a first region that needs to be implanted with P-type doped ions; wherein, the position of the first region is defined by the initial gate structure of the device, and a first corner blocking layer and a second corner blocking layer are formed on both sides of the first region, respectively.

6. The preparation method according to claim 1 or 2, characterized in that, The process of removing the third photolithographic mask and then etching the second sacrificial dielectric layer to obtain the fourth trench and the isolation protective layer includes: After removing the third photolithography mask, the second sacrificial dielectric layer is etched in its entirety with an etchant to obtain a fourth trench and a concave isolation protective layer; wherein the fourth trench is opposite to the P-type shielding area.

7. The preparation method according to claim 6, characterized in that, The process of removing the third photolithographic mask and etching the second sacrificial dielectric layer to obtain the fourth trench and the isolation protective layer further includes: The etching selectivity ratio of silicon oxide and silicon nitride in the second sacrificial dielectric material is adjusted to regulate the shape of the fourth trench.

8. The preparation method according to claim 7, characterized in that, The interface between the gate layer and the field oxide layer is arc-shaped or stepped.

9. A trench-type metal-gate MOSFET structure, characterized in that, The trench-type metal gate MOSFET structure is prepared by the preparation method according to any one of claims 1-8.

10. A chip, characterized in that, Including the trench metal gate MOSFET structure prepared by the preparation method according to any one of claims 1-8.

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