Ring gate transistor and manufacturing method thereof
By setting specific spacing and etching buffer layers in the gate-around transistor, the problem of interface state defects in the top nanostructure was solved, thereby improving the transistor's yield and performance.
Patent Information
- Application Number
- CN202511108078.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-12-16
AI Technical Summary
Existing gate-around transistor manufacturing methods result in numerous interface state defects in the top-layer nanostructure, leading to low yield and affecting its performance.
In a gate-around transistor, the distance between the top of the top nanowire/sheet and the bottom of the gate sidewall is set to be greater than the distance between two adjacent nanowire/sheet layers. An etching buffer layer is introduced during the manufacturing process to prevent the top nanowire/sheet from excessively contacting the etchant, thus forming a gate stack structure.
This improved the yield of gate-around transistors, reduced interface state defects in the top-layer nanostructure, and enhanced transistor performance.
Smart Images
Figure CN121152267A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a gate-ring transistor and its manufacturing method. Background Technology
[0002] With the development of semiconductor technology, higher-performance semiconductor devices such as gate-around transistors (GMT-A) have emerged. Compared with planar transistors and fin field-effect transistors, GMT-A has higher gate control capability, which is beneficial for suppressing short-channel effects.
[0003] However, the yield of gate-around transistors manufactured using existing methods is low, which is not conducive to further improving the performance of gate-around transistors. Summary of the Invention
[0004] The purpose of this invention is to provide a gate-around transistor and its manufacturing method, which enables the top nanostructure in the gate-around transistor to have a thickness that meets the working requirements, reduces interface state defects in the top nanostructure, and improves the yield of the gate-around transistor.
[0005] To achieve the above objectives, in a first aspect, the present invention provides a gate-around transistor, comprising: a semiconductor substrate, and an active structure, a gate stack structure, and a gate sidewall disposed on the semiconductor substrate. The active structure includes multiple nanowires / sheets spaced apart along the thickness direction of the semiconductor substrate, and source / drain regions disposed on both sides of the multiple nanowires / sheets. The gate stack structure surrounds the outer periphery of each nanowire / sheet. The gate sidewall is disposed on at least two sides of the gate stack structure along its length direction. Wherein, along the thickness direction of the semiconductor substrate, a first distance between the top of the top nanowire / sheet and the bottom of the gate sidewall is greater than a second distance between two adjacent nanowires / sheets.
[0006] With the above technical solution, in the ring-gate transistor provided by the present invention, there is a first gap between the top of the bottom nanowire / sheet and the bottom of the gate sidewall along the thickness direction of the semiconductor substrate. This indicates that in the actual manufacturing process, before forming the gate stack structure, there are other film layers on top of the top channel layer used to manufacture the nanowire / sheet. Furthermore, this first gap is greater than the second gap between two adjacent nanowire / sheet layers along the thickness direction of the semiconductor substrate. That is, the total thickness of the other film layers is greater than the thickness of the single sacrificial layer located between two adjacent channel layers during the manufacturing of the ring-gate transistor. At this time, the other film layers have a certain etching buffering effect, so that the top of the top nanowire / sheet can be effectively shielded when the nanowire / sheet is released, preventing excessive contact between the top of the top nanowire / sheet and the etchant. This ensures that the top nanostructure in the ring-gate transistor has a thickness that meets the operating requirements, reduces interface state defects in the top nanostructure, and improves the yield of the ring-gate transistor.
[0007] In one example, the gate-around transistor further includes a first material portion and a second material portion located between the gate stack structure and the source / drain regions, respectively. An interface exists between the first and second material portions. Each nanowire / sheet layer is disposed between two adjacent first material portions. The second material portion is disposed between the gate sidewall and the first material portion located on the top layer. The material of the first material portion differs from the materials of the second material portion and the nanowire / sheet.
[0008] In one example, the second material section and the nanowire / sheet are made of the same or similar materials.
[0009] In one example, the second material section is integrally continuous with the gate stack structure.
[0010] In one example, the height of the second material portion along the thickness direction of the semiconductor substrate is greater than or equal to 1 nm and less than or equal to 3 nm.
[0011] In one example, the materials and / or thicknesses of the first material sections in different layers are the same.
[0012] In one example, the material of the first material section is a semiconductor material or an insulating material.
[0013] In one example, the material of the nanowires / sheets includes Si. 1-x Ge x The materials in the first material section include Si. 1-y Ge y The materials in the second material section include Si. 1-y Ge y 0≤x≤0.15, 0≤y≤0.2, 0.3≤z≤1.
[0014] In one example, the top height of the source / drain region is less than the top height of the first material section located on the top layer, but greater than the top height of the nanowire / sheet located on the top layer.
[0015] In a second aspect, the present invention provides a method for manufacturing a gate-around transistor, the method comprising: first, forming a fin structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes alternating layers of sacrificial layers and channel layers, and an etching buffer layer located on the alternating layers of sacrificial layers and channel layers. The bottom and top layers of the alternating layers of sacrificial layers and channel layers are both sacrificial layers. Next, forming a sacrificial gate and gate sidewalls spanning the fin structure. The gate sidewalls are located at least on both sides of the sacrificial gate along its length. Next, processing the portion of the fin structure exposed outside the sacrificial gate and gate sidewalls to form source / drain regions. Next, removing the sacrificial gate; and removing at least the sacrificial layer and etching buffer layer located below the sacrificial gate, so that the remaining channel layer forms a nanowire / sheet. Next, forming a gate stack structure surrounding the periphery of the nanowire / sheet.
[0016] In one example, the portion of the fin structure exposed outside the sacrificial gate and gate sidewalls is processed, including: removing the portion of the fin structure exposed outside the sacrificial gate and gate sidewalls. Next, source / drain regions are epitaxially formed on both sides of the remaining fin structure. Then, an anisotropic etching process is used to remove the portions of the source / drain regions located on both sides of the etch buffer layer.
[0017] In one example, after removing the portion of the fin structure exposed outside the sacrificial gate and gate sidewalls, and before epitaxially forming source / drain regions on both sides of the remaining fin structure, the method for manufacturing a gate-around-the-loop transistor further includes: removing the edge portions of the sacrificial layer along the length direction of the sacrificial gate. Next, a first material portion is formed on both sides of the remaining sacrificial layer.
[0018] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description
[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0020] Figure 1 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 1 ;
[0021] Figure 2 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 2 ;
[0022] Figure 3 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 3 ;
[0023] Figure 4 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 4 ;
[0024] Figure 5 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 5 ;
[0025] Figure 6 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 6 ;
[0026] Figure 7 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 7 ;
[0027] Figure 8 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 8 ;
[0028] Figure 9 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 9 ;
[0029] Figure 10 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 ;
[0030] Figure 11 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 one;
[0031] Figure 12 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 two;
[0032] Figure 13 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 three;
[0033] Figure 14 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 Four;
[0034] Figure 15 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 five;
[0035] Figure 16 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 six;
[0036] Figure 17 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 seven;
[0037] Figure 18 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 eight;
[0038] Figure 19 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 Nine;
[0039] Figure 20 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 2 ten;
[0040] Figure 21 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 2 eleven;
[0041] Figure 22 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 2 twelve.
[0042] Reference numerals: 11 is semiconductor substrate, 12 is gate stack structure, 13 is gate sidewall, 14 is nanowire / sheet, 15 is source / drain region, 16 is first material section, 17 is second material section, 18 is shallow trench isolation structure, 19 is insulating dielectric layer, 20 is fin structure, 21 is sacrificial layer, 22 is channel layer, 23 is etching buffer layer, and 24 is sacrificial gate. Detailed Implementation
[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.
[0044] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0045] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.
[0047] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0048] With the development of semiconductor technology, gate-around transistors (GMT-A) have emerged. Because the gate stacking structure of a GMT-A is formed not only on the top and sidewalls of the channel region, but also at the bottom of the channel region, it has stronger gate control capability compared with planar transistors and fin field-effect transistors, which is beneficial for suppressing short-channel effects.
[0049] However, the yield of the aforementioned gate-around transistors (GMT-A) manufactured using existing methods is low. Specifically, in the actual manufacturing process, after forming a fin structure comprising alternating layers of sacrificial and channel layers, a sacrificial gate and gate sidewalls need to be formed across the fin structure. Under the masking effect of the sacrificial gate and gate sidewalls, source / drain regions and insulating dielectric layers are formed. Next, the sacrificial gate and the remaining sacrificial layer need to be removed to release the channel layer. During selective removal of the sacrificial layer, the exposure time of the non-top channel layers gradually decreases from the edge to the center along the width direction. Since the top channel layer is not shielded, it remains in constant contact with the etchant, resulting in deteriorated interface characteristics, increased interface states, and a smaller thickness. This leads to a low yield of the GMT-A and hinders the improvement of the operating performance of GMT-A.
[0050] To address the aforementioned technical problems, embodiments of the present invention provide a gate-around transistor and a method for manufacturing the same. In the gate-around transistor provided by this embodiment, along the thickness direction of the semiconductor substrate, the first distance between the top of the top nanowire / sheet and the bottom of the gate sidewall is greater than the second distance between two adjacent nanowire / sheet layers. This prevents excessive contact between the top of the top nanowire / sheet and the etchant, ensuring that the top nanostructure in the gate-around transistor has a thickness that meets operational requirements and reducing interface state defects in the top nanostructure.
[0051] In a first aspect, embodiments of the present invention provide a gate-around transistor. For example... Figures 19 to 22 As shown, the gate-around transistor includes a semiconductor substrate 11, and an active structure, a gate stack structure 12, and a gate sidewall 13 disposed on the semiconductor substrate 11. The active structure includes multiple nanowires / sheets 14 spaced apart along the thickness direction of the semiconductor substrate 11, and source / drain regions 15 disposed on both sides of the multiple nanowires / sheets 14. The gate stack structure 12 surrounds the outer periphery of each nanowire / sheet 14. The gate sidewall 13 is disposed at least on both sides of the gate stack structure 12 along its length direction. A first distance between the top of the top nanowire / sheet 14 and the bottom of the gate sidewall 13 along the thickness direction of the semiconductor substrate 11 is greater than a second distance between two adjacent nanowires / sheets 14.
[0052] When the above technical solution is adopted, such as Figures 19 to 22 As shown, in the ring-gate transistor provided in this embodiment of the invention, there is a first gap between the top of the bottom nanowire / sheet 14 and the bottom of the gate sidewall 13 along the thickness direction of the semiconductor substrate 11. This indicates that in the actual manufacturing process, before forming the gate stack structure 12, there are other film layers on top of the top channel layer 22 used to manufacture the nanowire / sheet 14. Furthermore, this first gap is greater than the second gap between two adjacent nanowire / sheet layers 14 along the thickness direction of the semiconductor substrate 11. That is, the total thickness of the other film layers is greater than the thickness of the single-layer sacrificial layer 21 located between two adjacent channel layers 22 during the manufacturing process of the ring-gate transistor. At this time, the other film layers have a certain etching buffer effect, so that the top of the top nanowire / sheet 14 can be effectively shielded when the nanowire / sheet 14 is released, preventing excessive contact between the top of the top nanowire / sheet 14 and the etchant. This ensures that the top nanostructure in the ring-gate transistor has a thickness that meets the operating requirements, reduces interface state defects in the top nanostructure, and improves the yield of the ring-gate transistor.
[0053] In practical applications, the embodiments of the present invention do not specifically limit the structure and material of the semiconductor substrate, as long as it can be applied to the gate-ring transistor provided in the embodiments of the present invention. For example, the semiconductor substrate can be any semiconductor material such as silicon, silicon germanium, or germanium.
[0054] For active structures, such as Figures 19 to 22As shown, the active structure includes multiple nanowires / sheets 14 spaced apart along the thickness direction of the semiconductor substrate 11, and source / drain regions 15 disposed on both sides of the multiple nanowires / sheets 14. This embodiment of the invention does not specifically limit the number of nanowires / sheets 14 layers included in the active structure; it can be set according to actual needs. Gaps exist between the bottom nanowires / sheets 14 and the semiconductor substrate 11, as well as between adjacent nanowires / sheets 14. The gate stack structure 12 surrounds the outer periphery of the nanowires / sheets 14 through these gaps. Therefore, the height of these gaps can be determined based on the thickness of the gate stack structure 12. Furthermore, along the thickness direction of the semiconductor substrate 11, the height of the gap between the bottom nanowires / sheets 14 and the semiconductor substrate 11, and the size of the second spacing between adjacent nanowires / sheets 14, can be approximately equal, so that each gap has a large height, ensuring proper filling of the gate stack structure 12 and improving the yield of the gate-around transistor.
[0055] The materials for the nanowires / sheets and the source / drain regions can include any semiconductor material such as silicon, silicon germanium, or germanium.
[0056] For a gate stack structure, the gate stack structure may include a gate dielectric layer surrounding the periphery of each nanowire / sheet layer, and a gate electrode located on the gate dielectric layer. The gate dielectric layer can be made of insulating materials such as HfO2, ZrO2, TiO2, or Al2O3. The gate electrode can be made of conductive materials such as TiN, TaN, or TiSiN.
[0057] For the gate sidewalls, they can be disposed only on both sides of the gate stack structure along its length. Alternatively, they can surround the outer perimeter of the sidewalls of the gate stack structure. For example... Figures 19 to 22 As shown, the size of the first spacing between the top nanowire / sheet 14 and the gate sidewall 13 along the thickness direction of the semiconductor substrate 11, and the difference between the first spacing and the second spacing between two adjacent nanowire / sheet layers 14 along the thickness direction of the semiconductor substrate 11, can be determined based on the difference in etching rates of the etchant on the sacrificial layer 21 and the channel layer 22 used to manufacture the nanowire / sheet 14 when releasing the nanowire / sheet 14 in the actual application scenario, as well as the size of the sacrificial layer 21. As long as the thickness and interface state characteristics of the top nanowire / sheet 14 meet the working requirements, it is acceptable.
[0058] In addition, in practical applications, along the thickness direction of the semiconductor substrate, the space between the top nanowire / sheet and the gate sidewall can be filled only with a gate stack structure.
[0059] Or, in some cases, such as Figures 19 to 22As shown, the gate-ring transistor further includes a first material portion 16 and a second material portion 17 located between the gate stack structure 12 and the source / drain regions 15, respectively. An interface exists between the first material portion 16 and the second material portion 17. Each nanowire / sheet 14 is disposed between two adjacent first material portions 16. The second material portion 17 is disposed between the gate sidewall 13 and the first material portion 16 located on the top layer. The material of the first material portion 16 is different from the materials of the second material portion 17 and the nanowire / sheet 14. In this case, an interface exists between the first material portion 16 and the second material portion 17, which are formed separately in different operating steps.
[0060] Specifically, the material of the second material section can be a semiconductor material. The type of semiconductor material can be determined based on the material of the sacrificial layer in the manufacturing process, as long as it is different from the sacrificial layer material. Optionally, the material of the second material section and the nanowire / sheet can be the same as or similar. This configuration, such as... Figures 1 to 18 As shown, in the actual manufacturing process, after removing the sacrificial gate 24, the film layer exposed on the top layer is a second material portion 17 that is the same as or similar to the material of the nanowire / sheet 14. Since there is a certain etching selectivity between the nanowire / sheet 14 and the sacrificial layer 21, there is also a certain etching selectivity between the second material portion 17 and the sacrificial layer 21. This can act as an etching buffer when the sacrificial layer 21 is released, reducing excessive contact between the nanowire / sheet 14 on the top layer and the etchant. It can also make the contact state between the nanowire / sheet 14 on the top layer and the etchant during the release process roughly the same as the contact state between the nanowire / sheet 14 on the other layers of nanowire / sheet 14 and the etchant during the release process (i.e., both the top and bottom of the nanowire / sheet 14 are shielded). Compared to only epitaxially adding a sacrificial layer 21 on the nanowire / sheet 14 on the top layer, the presence of the second material portion 17 can further reduce the excessive etching of the top nanowire / sheet 14 by the etchant, and further improve the yield of the gate-around transistor.
[0061] The material of the second material section is similar to that of the nanowires / sheets, and can be determined based on the material of the nanowires / sheets; no specific limitation is made here. For example, when the material of the nanowires / sheets includes Si... 1-x Ge x At that time, the material of the second material section includes Si. 1-z Ge z 0≤x≤0.15, 0≤z≤0.2.
[0062] Or, such as Figure 21 and Figure 22 As shown, the second material section 17 can also be integrally continuous with the gate stack structure 12. This arrangement, as... Figure 17 , Figure 18 , Figure 21 and Figure 22As shown, under the premise that the etching buffer layer acts as an etching buffer for the second material part 17, which is a semiconductor material as mentioned above, after releasing the nanowire / sheet 14, the portion of the etching buffer layer 23 located between the gate sidewall 13 and the top nanowire / sheet 14 is completely removed. At this time, the second material part 17 can be formed between the top nanowire / sheet 14 and the gate sidewall 13 while forming the gate stack structure 12. This can improve the control capability of the gate stack structure 12 over the top nanowire / sheet 14 and improve the driving performance of the gate ring transistor.
[0063] As for the thickness of the second material section, it can be determined based on the type of etchant used in the actual manufacturing process and the material of the second material section, etc., and no specific limit is made here.
[0064] For example, along the thickness direction of the semiconductor substrate, the height of the second material portion can be greater than or equal to 1 nm and less than or equal to 3 nm. For instance, the height of the second material portion can be 1 nm, 1.2 nm, 1.5 nm, 2 nm, 2.2 nm, 2.5 nm, 2.8 nm, or 3 nm, etc.
[0065] For the first material section, the material of the first material section can be a semiconductor material, and the type of semiconductor material is different from the type of material of the nanowire / sheet and the second material section.
[0066] For example, materials for nanowires / sheets include Si. 1-x Ge x The materials in the first material section include Si. 1-y Ge y The materials in the second material section include Si. 1-z Ge z 0≤x≤0.15, 0≤z≤0.2, 0.3≤y≤1.
[0067] Alternatively, the material of the first material section can also be an insulating material. This configuration further isolates the gate stack structure from the source / drain regions through the first material section, reducing parasitic capacitance and improving transistor performance.
[0068] In addition, the materials of the first material sections in different layers can be the same, and the thickness of the first material sections in different layers can also be the same, so as to simplify the manufacturing process of the gate ring transistor.
[0069] In addition, such as Figures 19 to 22As shown, the top height of the source / drain region 15 can be less than the top height of the first material portion 16 located on the top layer, but greater than the top height of the nanowire / wafer 14 located on the top layer. It is understood that if the source / drain region 15 is formed using an epitaxial method, the presence of the second material portion 17 of the semiconductor material will cause epitaxial impurities to exist above the source / drain region 15 formed during the epitaxial process. Therefore, when the top height of the source / drain region 15 is less than the top height of the first material portion 16 located on the top layer, the epitaxial impurities can be removed by processes such as etching, thereby improving the yield of the gate-around transistor.
[0070] In some cases, such as Figure 6 ,as well as Figures 19 to 22 As shown, the gate-around transistor provided in this embodiment of the invention may further include a shallow trench isolation structure 18 and / or an insulating dielectric layer 19. The shallow trench isolation structure 18 is formed on the semiconductor substrate 11 to define the active region of the semiconductor substrate 11, reducing leakage risk and further improving the yield and performance of the gate-around transistor. The insulating dielectric layer 19 is disposed on the source / drain regions 15 and the semiconductor substrate 11, and the top of the insulating dielectric layer 19 is flush with the top of the gate stack structure 12 to protect the source / drain regions 15 from the etching and cleaning operations during the removal of the sacrificial gate 24 and the sacrificial layer 21, thereby improving the yield of the gate-around transistor.
[0071] As for the materials of the shallow trench isolation structure and the insulating dielectric layer, they can include any insulating material such as silicon oxide, silicon oxynitride, or silicon oxynitride, without specific limitations here.
[0072] Secondly, embodiments of the present invention provide a method for manufacturing a gate-ring transistor. The following will describe a method based on... Figures 1 to 22 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the manufacturing method of this gate-ring transistor includes the following steps:
[0073] First, such as Figures 1 to 3 As shown, a fin structure 20 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 20 includes alternating layers of sacrificial layers 21 and channel layers 22, and an etching buffer layer 23 located on the alternating layers of sacrificial layers 21 and channel layers 22. The film layers located at the bottom and top layers of the alternating layers of sacrificial layers 21 and channel layers 22 are both sacrificial layers 21.
[0074] In actual manufacturing, the channel layer in the fin structure is used to fabricate the nanowires / sheets in the gate-around transistor. Therefore, the material and number of channel layers in the fin structure can be determined based on the number and material of the nanowires / sheets. The material of the sacrificial layer differs from that of the channel layer; the specific type of sacrificial layer material can be found in the semiconductor material types described in the first material section above. As for the etching buffer layer, the type of semiconductor material and the thickness of the second material section described in the second material section above can be referenced, and will not be elaborated further here.
[0075] For example, such as Figure 1 As shown, epitaxial growth and other processes can be used to form a sacrificial layer 21, a channel layer 22, and an etching buffer layer 23 for fabricating the fin structure along the thickness direction of the semiconductor substrate 11. Then, as... Figure 2 As shown, the sacrificial layer 21, channel layer 22, and etching buffer layer 23, as well as a portion of the semiconductor substrate 11, are patterned using photolithography and etching processes to form a Fin structure. Next, as... Figure 3 As shown, shallow trench isolation structures 18 for defining active regions can be formed between adjacent fin structures using processes such as deposition and etching. The top height of the shallow trench isolation structure 18 is less than or equal to the bottom height of the underlying sacrificial layer 21. The portion of the fin structure exposed outside the shallow trench isolation structure 18 includes fin-like structures 20.
[0076] It should be noted that when the manufactured gate ring transistor does not include the shallow trench isolation structure mentioned above, only the sacrificial layer, the channel layer, and the etch buffer layer can be patterned; and the fin structure can be directly obtained after patterning.
[0077] Next, as Figure 4 and Figure 5 As shown, processes such as deposition and etching can be used to form the sacrificial gate 24 and gate sidewall 13 spanning the fin structure 20. The gate sidewall 13 is located at least on both sides of the sacrificial gate 24 along its length.
[0078] The material of the sacrificial gate may include easily removable materials such as polysilicon, as long as they can be applied to the manufacturing method provided in the embodiments of the present invention.
[0079] Next, as Figures 6 to 12 As shown, the portion of the fin structure 20 exposed outside the sacrificial gate 24 and the gate sidewall 13 is processed to form the source / drain region 15.
[0080] In actual manufacturing, under the masking effect of the sacrificial gate and gate sidewalls, processes such as ion implantation can be used to directly dope the portion of the fin structure exposed outside the sacrificial gate and gate sidewalls to form the source / drain regions. Alternatively, as... Figures 6 to 8As shown, dry etching or wet etching processes can be used to first remove the portion of the fin structure exposed outside the sacrificial gate 24 and gate sidewall 13. Next, as... Figure 11 As shown, source / drain regions 15 are epitaxially formed on both sides of the remaining fin-like structure. At this time, because the etching buffer layer 23 of the semiconductor material is also exposed, semiconductor material is also epitaxially formed on both sides of it. Based on this, as... Figure 12 As shown, anisotropic etching can be used to remove the portions of the source / drain regions 15 located on both sides of the etching buffer layer 23, thereby improving the yield of the gate ring transistor.
[0081] Among them, such as Figure 8 and Figure 9 As shown, after removing the portion of the fin structure exposed outside the sacrificial gate 24 and gate sidewall 13, and before forming the source / drain regions 15 epitaxially on both sides of the remaining fin structure, dry etching or wet etching processes can be used to remove the edge portions of the sacrificial layer 21 along the length direction of the sacrificial gate 24. Next, as... Figure 10 As shown, deposition and etching processes can be used to form first material portions 16 on both sides of the remaining sacrificial layer 21. The material of the first material portion 16 is an insulating material, which acts as an inner sidewall, reducing the parasitic capacitance between the subsequently formed gate stack structure 12 and the source / drain region 15, and improving the operating performance of the gate-around transistor.
[0082] Next, as Figure 13 As shown, an insulating dielectric layer 19 can be formed over the existing structure using processes such as deposition and planarization. The top of this insulating dielectric layer 19 is flush with the top of the sacrificial gate 24. The material of the insulating dielectric layer can be referred to the previous text and will not be repeated here.
[0083] Next, as Figure 14 As shown, the sacrificial gate can be removed using processes such as dry etching or wet etching. At this point, the remaining sacrificial layer 21, channel layer 22, and etching buffer layer 23 are exposed. Above the top channel layer 22, there exists not only the sacrificial layer 21 but also the etching buffer layer 23.
[0084] Next, as Figures 15 to 18 As shown, dry etching or wet etching processes can be used to remove at least the sacrificial layer and etching buffer layer located below the sacrificial gate, allowing the remaining channel layer 22 to form nanowires / sheets 14. It is evident that during the release of the nanowires / sheets 14, the etching buffer layer has an etching-retarding effect on the top-layer nanowires / sheets 14. This not only ensures that the thickness of the top-layer nanowires / sheets 14 meets operational requirements and reduces interface state defects, but also completely removes at least the exposed portion of the etching buffer layer while removing the sacrificial layer, eliminating the need for additional etching operations and simplifying the manufacturing process of the gate-around transistor.
[0085] like Figures 15 to 18 As shown, the etch buffer layer and sacrificial layer located below the gate sidewall may or may not be removed. If the first material portion has already formed an insulating material, the sacrificial layer located below the gate sidewall has been removed.
[0086] Next, as Figures 19 to 22 As shown, a gate stack structure 12 surrounding the nanowire / sheet 14 can be formed using processes such as atomic layer deposition.
[0087] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.
[0088] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0089] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.
Claims
1. A ring gate transistor, characterized by, The ring gate transistor comprises: a semiconductor substrate, and an active structure, a gate stack structure and a gate sidewall disposed on the semiconductor substrate; the active structure comprises a plurality of layers of nanowires / sheets arranged at intervals along the thickness direction of the semiconductor substrate, and source-drain regions arranged on both sides of the plurality of layers of nanowires / sheets; the gate stack structure surrounds the outer periphery of each layer of nanowires / sheets; the gate sidewall is arranged at least on both sides of the gate stack structure along the length direction; wherein, along the thickness direction of the semiconductor substrate, the first spacing between the top of the nanowire / sheet on the top layer and the bottom of the gate sidewall is greater than the second spacing between the adjacent two layers of nanowires / sheets.
2. The ring gate transistor of claim 1, wherein The ring gate transistor further comprises a first material part and a second material part between the gate stack structure and the source-drain region respectively; the first material part and the second material part have a boundary surface therebetween; each layer of nanowires / sheets is arranged between the adjacent two layers of the first material part; the second material part is arranged between the gate sidewall and the first material part on the top layer; the material of the first material part is different from the material of the second material part and the nanowires / sheets.
3. The ring gate transistor of claim 2, wherein, The material of the second material part and the nanowires / sheets is the same or similar; or, the second material part is integrally continuous with the gate stack structure.
4. The ring gate transistor of claim 2, wherein Along the thickness direction of the semiconductor substrate, the height of the second material part is greater than or equal to 1 nm and less than or equal to 3 nm.
5. The ring gate transistor of claim 2, wherein The material and / or thickness of the first material part of different layers are the same.
6. The ring gate transistor of claim 2, wherein The material of the first material part is a semiconductor material or an insulating material.
7. The ring gate transistor of claim 2, wherein The material of the nanowire / sheet includes Si 1-x Ge x The material of the first material portion includes Si 1-y Ge y The material of the second material portion includes Si 1-z Ge z ; 0≤x≤0.15, 0≤z≤0.2, 0.3≤y≤1.
8. The ring gate transistor of claim 2, wherein, The top height of the source-drain region is less than the top height of the first material part on the top layer and greater than the top height of the nanowire / sheet on the top layer.
9. A method of manufacturing a gate-all-around transistor, characterized by, The method comprises: forming a fin structure on a semiconductor substrate; along the thickness direction of the semiconductor substrate, the fin structure comprises alternately stacked sacrificial layers and channel layers, and an etching buffer layer on the alternately stacked sacrificial layers and channel layers; the film layers on the bottom layer and the top layer in the alternately stacked sacrificial layers and channel layers are both the sacrificial layers; forming a sacrificial gate and a gate sidewall across the fin structure; the gate sidewall is arranged at least on both sides of the sacrificial gate along the length direction; processing the part of the fin structure exposed outside the sacrificial gate and gate sidewall to form a source-drain region; removing the sacrificial gate; and removing at least the sacrificial layers and etching buffer layers under the sacrificial gate, so that the remaining channel layers form nanowires / sheets; forming a gate stack structure surrounding the outer periphery of the nanowires / sheets.
10. The method of manufacturing a gate-all-around transistor according to claim 9, wherein The processing of the part of the fin structure exposed outside the sacrificial gate and gate sidewall comprises: removing the part of the fin structure exposed outside the sacrificial gate and gate sidewall; epitaxially forming a source-drain region on both sides of the remaining fin structure; using an anisotropic etching process, removing the part of the source-drain region on both sides of the etching buffer layer.
11. The method of manufacturing a gate-all-around transistor according to claim 10, wherein After removing the part of the fin structure exposed outside the sacrificial gate and gate sidewall, before epitaxially forming a source-drain region on both sides of the remaining fin structure, the method for manufacturing the ring gate transistor further comprises: removing two side edge portions of the sacrificial layer along a length direction of the sacrificial gate; forming a first material portion on both sides of the remaining sacrificial layer.