Semiconductor device

Abstract

The invention discloses a semiconductor device, relates to the technical field of power semiconductors, and can improve the conduction performance of the device while ensuring the voltage withstanding performance. The semiconductor device includes: a semiconductor substrate in which a plurality of trenches are formed; a control grid and a shield grid are arranged in the groove, the control grid comprises a first sub-grid and a second sub-grid which are connected with each other, the first sub-grid is located in the lower region of the groove, and the shield grid and the second sub-grid are both located in the upper region of the groove; the upper region is close to the notch of the groove, and the lower region is close to the groove bottom of the groove; projections of the second sub-grid and the shielding grid on a first plane and / or a second plane are partially overlapped, the first plane is perpendicular to the length direction of the groove, and the second plane is perpendicular to the width direction of the groove; dielectric layers are arranged between the inner wall of the groove and the control grid, between the inner wall of the groove and the shield grid, between the control grid and the shield grid, and on the top surface of the second sub-grid and the top surface of the shield grid.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor device. BACKGROUND

[0002] At present, semiconductor devices, especially power semiconductor devices, have been widely used in various electric energy conversion and circuit control systems. These application scenarios often require semiconductor devices not only to have excellent current handling capability, but also to be able to withstand high voltage, that is, to have good voltage withstanding capability. In order to meet this demand, the industry generally adopts split gate structure, also known as separate gate structure.

[0003] In the split gate structure, the gate is divided into two parts, control gate and shield gate. By applying appropriate voltage to the control gate, the opening and closing of the channel is controlled, thereby realizing accurate control of the current. The shield gate is usually grounded and plays the role of field plate, and its main function is to optimize the electric field distribution and effectively improve the voltage withstanding capability of the device. The introduction of split gate structure not only significantly improves the stability of the device in high voltage environment, but also effectively reduces the switching loss of the device and improves the overall energy efficiency.

[0004] Although the split gate structure brings many advantages, the grounding characteristics of the shield gate limit its role in current control, so that the device has to sacrifice part of the current handling capability while pursuing high voltage withstanding capability, limiting the performance of slot gate type power semiconductor devices in some application scenarios that require high current conduction capability.

[0005] Therefore, how to improve the current conduction capability while maintaining high voltage withstanding capability has become an important research direction in the design and research and development process of semiconductor devices. SUMMARY

[0006] To solve the above problems, the application provides a semiconductor device, which comprises a semiconductor substrate, a plurality of trenches are arranged in the semiconductor substrate, the arrangement direction of the plurality of trenches is parallel to the width direction of the trenches, the trenches extend along the length direction, the width direction of the trenches is perpendicular to the length direction and both are perpendicular to the thickness direction of the semiconductor substrate; a control gate and a shielding gate are arranged in the trenches, the control gate comprises a first sub-gate and a second sub-gate which are connected to each other, the first sub-gate is located in the lower region of the trench, and the shielding gate and the second sub-gate are both located in the upper region of the trench; the upper region is close to the slot opening of the trench, and the lower region is close to the slot bottom of the trench; the projection of the second sub-gate and the shielding gate on the first plane partially overlaps, or the projection of the second sub-gate and the shielding gate on the second plane partially overlaps, or the projection of the second sub-gate and the shielding gate on the first plane and the second plane both partially overlaps, wherein the first plane is perpendicular to the length direction of the trench, and the second plane is perpendicular to the width direction of the trench; the inner wall of the trench and the control gate, the inner wall of the trench and the shielding gate, the control gate and the shielding gate, and the top surface of the second sub-gate and the top surface of the shielding gate are all provided with a dielectric layer; a drain region is arranged between the two adjacent trenches, the drain region extends from the top surface of the semiconductor substrate into the semiconductor substrate, and the doping type of the drain region is opposite to the doping type of the semiconductor substrate.

[0007] The semiconductor device provided by the application can improve the current conduction performance of the semiconductor device by arranging the control gate as the first sub-gate and the second sub-gate which are connected to each other and are located in the lower region and the upper region of the trench respectively, so that the second sub-gate occupies part of the space originally occupied by the shielding gate, the area of the channel region formed by the control gate is increased, the on-resistance of the device is reduced, and the current conduction performance of the semiconductor device is improved, and the remaining shielding gate still has sufficient area to deplete the charges of the drain region through the dielectric layer, so that the voltage resistance performance of the semiconductor device is not affected, thereby better balancing the voltage resistance and conduction performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A schematic partial structural view of a semiconductor device provided by the prior art;

[0009] Figure 2 A schematic equivalent circuit diagram of a typical bidirectional conduction device;

[0010] Figure 3 A schematic partial structural view of a semiconductor device provided by the first embodiment of the application;

[0011] Figure 4 And Figure 5 Respectively Figure 3 The sectional views of the semiconductor device provided by the application along A1-A2 and B1-B2;

[0012] Figure 6A cross-sectional view of a semiconductor device provided for Embodiment Two of the present application along the direction of the trench width;

[0013] Figure 7 A cross-sectional view of a semiconductor device provided for Embodiment Three of the present application along the direction of the trench width;

[0014] Figure 8 A schematic structural diagram of a semiconductor device provided for Embodiment Four of the present application;

[0015] Figure 9 A schematic structural diagram of a semiconductor device provided for Embodiment Five of the present application;

[0016] Figure 10 and Figure 11 are respectively Figure 9 cross-sectional views of the semiconductor device provided along A1-A2 and along B1-B2;

[0017] Figure 12 is a schematic cross-sectional view of the semiconductor device provided along C1-C2; Figure 9

[0018] Figure 13 is another schematic cross-sectional view of the semiconductor device provided along C1-C2; Figure 9

[0019] Figure 14 A schematic structural diagram of a semiconductor device provided for Embodiment Six of the present application;

[0020] Figures 15 to 17 are respectively Figure 14 cross-sectional views along A1-A2, along B1-B2 and along C1-C2;

[0021] Figure 18 A schematic structural diagram of a semiconductor device provided for Embodiment Seven of the present application;

[0022] Figure 19 is a schematic cross-sectional view along A1-A2; Figure 18

[0023] Figure 20 is a schematic cross-sectional view along B1-B2; Figure 18

[0024] Figure 21 is a schematic cross-sectional view along C1-C2; Figure 18

[0025] Figure 22 is another schematic cross-sectional view along A1-A2; Figure 18

[0026] ​​​​​​Figure 23 is Figure 18 another schematic cross-sectional view along C1-C2;

[0027] Figure 24 is a schematic structural diagram of a semiconductor device provided for Embodiment Eight of the present application;

[0028] Figure 25 is Figure 24 a schematic cross-sectional view along A1-A2;

[0029] Figure 26 is Figure 24 a cross-sectional view along B1-B2;

[0030] Figure 27 is Figure 24 a schematic cross-sectional view along C1-C2;

[0031] Figure 28 is Figure 24 another schematic cross-sectional view along A1-A2;

[0032] Figure 29 is Figure 24 another schematic cross-sectional view along C1-C2;

[0033] Figure 30 is a schematic structural diagram of a semiconductor device provided for Embodiment Nine of the present application;

[0034] Figure 31 is Figure 30 a schematic cross-sectional view along A1-A2;

[0035] Figure 32 is Figure 30 a schematic cross-sectional view along B1-B2;

[0036] Figure 33 is Figure 30 a schematic cross-sectional view along C1-C2;

[0037] Figure 34 is Figure 30 another schematic cross-sectional view along A1-A2;

[0038] Figure 35 is Figure 30 another schematic cross-sectional view along C1-C2;

[0039] Figure 36 is a schematic structural diagram of a semiconductor device provided for Embodiment Ten of the present application;

[0040] Figure 37 is Figure 36 a schematic cross-sectional view along A1-A2;

[0041] Figure 38 is Figure 36 a schematic cross-sectional view along B1-B2;

[0042] Figure 39 is Figure 36 a schematic cross-sectional view along C1-C2;

[0043] Figure 40 is Figure 36 another schematic cross-sectional view along B1-B2;

[0044] Figure 41 is Figure 36 another schematic cross-sectional view along C1-C2. DETAILED DESCRIPTION

[0045] Figure 1 is a schematic partial structure diagram of a semiconductor device provided by the prior art. As shown in Figure 1 , the semiconductor device includes a semiconductor substrate 100, in which a plurality of trenches 110 are provided, and a split gate structure is provided in the trenches 110. The split gate structure includes a control gate 1 and a shield gate 2, which are insulated and spaced apart along the thickness direction (i.e., the Z direction in Figure 1 ) of the semiconductor substrate 100. The control gate 1 is relatively closer to the bottom of the trench 110, and the shield gate 2 is relatively closer to the top of the trench 110, i.e., the control gate 1 is located in the lower region of the trench, and the shield gate 2 is located in the upper region of the trench; and both the control gate 1 and the shield gate 2 extend along the length direction (i.e., the X direction in Figure 1 ) of the trench 110. A drain region is provided in the semiconductor substrate 100 between adjacent trenches 110, the drain region is provided with a lead-out electrode as a drain electrode, the drain region can be N-type doped, and the semiconductor substrate can be P-type material.

[0046] The above semiconductor device can be used as a bidirectional conduction device. In combination with the schematic equivalent circuit diagram in Figure 2 , the control gate 1 can be used as the gate G of a transistor, and the drain regions on both sides of the trench 110 are used to connect the first drain D1 and the second drain D2, respectively. A channel can be formed at the bottom of the control gate 1 of the P-type semiconductor substrate, and the conduction and cutoff of the device can be controlled by controlling the conduction and cutoff of the channel. The shield gate 2 can be used as a source gate S with a field plate function (which can be grounded), and through the field plate depletion effect of the shield gate 2, the withstand voltage capability of the PN junction formed by the auxiliary drain region and the P-type semiconductor substrate is assisted. When the device is turned on, the channel corresponding to the control gate is in a conduction state, and then the current flows from the first drain D1 to the second drain D2 (as shown in Figure 1As shown in the figure, when the device is in on-state, the current flows from the first drain D1 to the second drain D2 (as indicated by the arrowed line), or the current flows from the second drain D2 to the first drain D1, realizing bidirectional current conduction. When the device is in off-state, the voltage resistance of the device is borne by the P-type semiconductor substrate and the drain region, and by selecting appropriate P-type semiconductor substrate material resistivity and drain region doping concentration design, the voltage resistance requirement of a typical bidirectional conduction device can be met, usually 30-50V. At the same time, in order to realize the characteristics of low on-resistance, the gate structure of the device adopts a split gate structure design, so that when a higher doping concentration is used in the drain region (usually ~1E17), the expected voltage resistance capability can still be maintained.

[0047] However, for power field effect transistors, it is often difficult to have both voltage resistance and low on-resistance. For example, in order to reduce the on-resistance of the device, the drain region needs to use as high a doping concentration as possible, which is conducive to current flow; but if the doping concentration is too high, an effective depletion region cannot be formed, affecting the voltage resistance capability of the device. The inventors have found that, Figure 1 The semiconductor device shown in the figure, although the voltage resistance and low on-resistance are improved compared with traditional bidirectional conduction devices, the current conduction capability is still not as expected, and the reason is presumably that the shielding gate in the device only serves as a field plate gate and cannot provide an auxiliary current channel, which to some extent weakens the current conduction capability of the device.

[0048] In view of the above problems, the semiconductor device provided by the present application sets the control gate as two parts connected to each other, one part occupies part of the space where the original shielding gate is arranged, so that the channel area corresponding to the control gate becomes larger, thereby reducing the on-resistance of the device and improving the current conduction performance of the semiconductor device, and the remaining shielding gate still has sufficient area to deplete the charge of the drain region through the dielectric layer, so that the voltage resistance performance of the semiconductor device is basically not affected, thereby better balancing the voltage resistance and conduction performance of the device.

[0049] In order to better understand the technical solutions of the present application, the technical solutions of the present application will be described in detail below by means of the accompanying drawings and specific embodiments. It should be understood that the following embodiments and specific features in the embodiments are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the following embodiments and the embodiments can be combined with each other.

[0050] In the description of the present application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a sequence or priority between the entities or operations.

[0051] Reference Figures 3 to 5The embodiment one of the application provides a semiconductor device, which comprises a semiconductor substrate 100, which can be a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a well region formed in the semiconductor substrate, or a well region formed in the epitaxial layer. The semiconductor substrate 100 has a bottom surface 101 and a top surface 102 arranged oppositely, wherein the top surface 102 can also be referred to as a front surface, and the bottom surface 101 can also be referred to as a back surface. The semiconductor substrate 100 is provided with a plurality of trenches 110; the trench 110 comprises a trench bottom 111, a trench opening 112 and an inner wall, the trench opening 112 is towards the top surface 102 of the semiconductor substrate 100, and the trench bottom 111 is arranged in the semiconductor substrate 100 and is relatively closer to the bottom surface 101 of the semiconductor substrate 100; the inner wall comprises a side wall 113 and a bottom wall. The arrangement direction of the plurality of trenches 110 is parallel to the width direction (Y direction) of the trench 110, the trench 110 extends along the length direction (X direction) thereof, the width direction (Y direction) of the trench is perpendicular to the length direction (X direction), and both are perpendicular to the thickness direction (Z direction) of the semiconductor substrate 100.

[0052] Reference Figure 3 The trench 110 comprises an upper region 115 and a lower region 114, wherein the upper region 115 is close to the trench opening 112 of the trench 110, and the lower region 114 is close to the trench bottom 111 of the trench 110. The lower region 114 and the upper region 115 are only artificially defined different spatial regions of the trench 110 for the convenience of describing the specific structure. The trench 110 is provided with a control gate 120 and a shielding gate 130, the control gate 120 comprises a first sub-gate 121 and a second sub-gate 122 connected to each other, and the first sub-gate 121 and the second sub-gate 122 can be an integral structure. The first sub-gate 121 is located in the lower region 114 of the trench 110, and the second sub-gate 122 and the shielding gate 130 are both located in the upper region 115 of the trench 110. The second sub-gate 122 and the shielding gate 130 have a part of overlap in the orthographic projection on a first plane, wherein the first plane is perpendicular to the length direction (X direction) of the trench 110, or in other words, the first plane is parallel to the Z direction and the Y direction.

[0053] As shown in Figure 3 and Figure 4 , in the same trench 110, the number of the second sub-gate 122 and the shielding gate 130 is both multiple, and the plurality of second sub-gates 122 and the plurality of shielding gates 130 are arranged alternately in the length direction of the trench.

[0054] Reference Figure 3The inner wall of the trench 110 and the control gate 120, the inner wall of the trench 110 and the shielding gate 130, the control gate 120 and the shielding gate 130, and the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 are all provided with a dielectric layer. For example, the inner wall of the trench 110 and the control gate 120, and the inner wall of the trench 110 and the shielding gate 130 can be provided with a first dielectric layer 116, the control gate 120 and the shielding gate 130 can be provided with a second dielectric layer 117, and the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 can be provided with a third dielectric layer 118. For example, the first dielectric layer 116, the second dielectric layer 117, and the third dielectric layer 118 can be the same material, or can be different materials. In addition, even if it is the first dielectric layer 116, it can also be composed of multiple materials, and the embodiment is not limited specifically. For example, the dielectric layer can include silicon nitride or silicon oxide, can be a stack of silicon nitride and silicon oxide, or can be other insulating materials.

[0055] Reference Figure 3 The drain region 140 is provided between two adjacent trenches 110, and the drain region 140 extends from the top surface 102 of the semiconductor substrate 100 into the semiconductor substrate 100. The doping type of the drain region 140 is opposite to the doping type of the semiconductor substrate 100. The drain region 140 can be connected to an electrode signal. The drain regions 140 on both sides of the trench 110 can be connected to an electrode signal. One side of the drain region can be connected to a signal input terminal, and the other side of the drain region can be connected to a signal output terminal. Of course, the electrode conduction direction can also be exchanged to realize bidirectional conduction and bidirectional output.

[0056] Reference Figure 3 When the control gate signal is applied to the control gate 120, the semiconductor substrate 100 near the control gate 120 will generate a reverse type of charge, thereby forming a channel. In other words, the channel is formed near the control gate 120. The control gate 120 is spaced apart from the channel by the first dielectric layer 116. The shielding gate 130 can be connected to ground or connected to the semiconductor substrate of the semiconductor substrate. When the control gate signal reaches the threshold voltage, the channel is turned on, and the semiconductor device is turned on. When the control gate signal does not reach the threshold voltage, the channel is in an off state, and at this time, the semiconductor device is cut off, i.e., the semiconductor device is in an off state.

[0057] For example, reference Figure 3 and in combination Figure 2In the case that the semiconductor device is in the on state, one of the drain regions 140 on both sides of the trench 110 is connected to the input signal, and the other drain region 140 outputs the signal as the output terminal. By selecting different input signals of the drain regions, the bidirectional conduction performance of the semiconductor device can be realized. Since the shield gate 130 is connected to the ground or zero potential, in the case that the semiconductor device is in the off state, the shield gate 130 is in a depletion state between the two trenches 110 by the field plate effect formed between the shield gate 130 and the semiconductor substrate, so that the resistance is increased, thereby improving the withstand voltage performance of the semiconductor device.

[0058] The semiconductor device provided by the embodiment one of the application has the following advantages. The control gate is set as the first sub-gate and the second sub-gate which are connected to each other, and the projection of the second sub-gate and the shield gate on the first surface at least partially overlaps. In other words, the second sub-gate occupies part of the space where the shield gate is arranged, or the second sub-gate replaces part of the shield gate, and the rest of the shield gate is reserved. Since the upper region and the lower region of the trench are both provided with the control gate, the overall space occupied by the control gate is larger, and the area of the channel region formed by the control gate is larger, thereby further reducing the on-resistance of the device and improving the current conduction performance of the semiconductor device. The orthographic projection of the second sub-gate and the shield gate on the first surface overlaps, so that a larger area of the control gate can be arranged in the limited space of the trench to improve the on-resistance, and a certain area of the shield gate is reserved. Even if the area of the shield gate is smaller, the reserved shield gate still has sufficient area to deplete the charge of the drain region through the dielectric layer in the off state of the semiconductor device, and the depletion effect of the shield gate is not affected, so the withstand voltage performance of the semiconductor device is not affected. Therefore, the withstand voltage and the on-resistance of the device are better balanced, and the performance of the semiconductor device is optimized. In addition, in the process, the shape of the control gate can be controlled by modifying the mask plate pattern corresponding to the control gate, thereby obtaining ideal device parameters, and therefore the process difficulty is not significantly increased.

[0059] Reference Figure 3, along the thickness direction (Z direction) of the semiconductor substrate 100, the distance that the drain region 140 extends into the semiconductor substrate from the top surface 102 of the semiconductor substrate 100 (i.e. the depth of the drain region) is denoted as h0, and the distance between the bottom surface of the shield gate 130 and the top surface 102 of the semiconductor substrate is denoted as h1. In some examples, the distance that the drain region 140 extends into the semiconductor substrate from the top surface 102 of the semiconductor substrate 100 exceeds the bottom surface of the shield gate 130, i.e. h0>h1, in other words, compared with the bottom surface of the shield gate 130, the bottom surface of the drain region 140 is relatively closer to the bottom surface 101 of the semiconductor substrate 100, so as to ensure the field plate depletion effect of the shield gate 130. On this basis, the drain region 140 extends into the semiconductor substrate from the top surface 102 of the semiconductor substrate 100 but preferably does not exceed the bottom of the trench 110. In further examples, the distance between the bottom surface of the first sub-gate 121 and the top surface 102 of the semiconductor substrate is denoted as h2, and h1<h0<h2, so as to ensure the connection between the drain region 140 and the channel, and in the case of channel conduction, the drain regions on both sides of the channel are connected to achieve semiconductor device conduction. In still further examples, the depth h0 of the drain region does not exceed the top surface of the first sub-gate 121, i.e. the depth of the drain region 140 can be between the bottom surface of the second sub-gate 122 and the top surface of the first sub-gate 121, for example, in the embodiment shown in Figure 3 , the bottom surface of the drain region 140 is approximately flush with the top surface of the first sub-gate 121, so as to ensure that the channel has sufficient length and avoid the risk of short channels.

[0060] In some examples, along the width direction of the trench 110, the thickness of the dielectric layer on both sides of the shield gate 130 is greater than the thickness of the dielectric layer on both sides of the first sub-gate 121, so as to improve the withstand voltage capability of the semiconductor device. Referring to Figure 3 , in the present example, along the width direction (Y direction) of the trench 110, the width of the upper region 115 of the trench 110 is approximately equal to or greater than the width of the lower region 114, i.e. the cross section of the trench is rectangular or has a shape with a large top and a small bottom, and the adjustment of the thickness of the dielectric layer can be achieved by controlling the width of the shield gate 130 and the first sub-gate 121, for example, the size of the shield gate 130 along the Y direction is denoted as W1, and the width of the first sub-gate 121 is denoted as W2, W1W2 can be controlled, so that the thickness of the dielectric layer between the inner wall of the trench 110 and the shield gate 130 is greater than the thickness of the dielectric layer between the inner wall of the trench 110 and the first sub-gate 121. Of course, in practice, the thickness of the dielectric layer and the specific width of the split gate structure can be determined according to the actual product requirements and the shape of the trench.

[0061] Referring to Figure 4The thickness of the shielding gate 130 along the thickness direction (Z direction) of the semiconductor substrate 100 is denoted as H1, the thickness of the second sub-gate 122 is denoted as H2, the thickness of the first sub-gate 121 is denoted as H3, the distance between the bottom surface of the shielding gate 130 and the top surface of the first sub-gate 121 is the first distance H4, and H4>0. For example, H2≥H3, and further, H1≥H3.

[0062] The thickness of the second sub-gate 122 along the Z direction is denoted as H5, and the thickness H3 of the first sub-gate 121 can be greater than 30% and less than 50% of the thickness of the entire control gate 120, that is, 30%≤K0<50%, where K0=H3 / (H3+H5); further, the value of K0 can also be 30% to 45%, that is, 30%≤K0≤45%, for example, K0 can be 30%, 35%, 37%, 45%, or 40%, etc.

[0063] For example, referring to Figure 3 and Figure 4 , the top surface of the second sub-gate 122 can be flush with the top surface of the shielding gate 130, and H2=H1+H4.

[0064] In some examples, referring to Figure 4 , along the length direction (X direction) of the trench 110, the interval distance between two adjacent second sub-gates 122 is denoted as L1, and the length of the shielding gate 130 along the X direction is less than L1, which can be considered as the shielding gate 130 being embedded in the interval region between the two adjacent second sub-gates 122, and the shielding gate and the adjacent second sub-gate 122 are isolated by a dielectric layer.

[0065] Referring to Figure 4 , along the length direction of the trench 110, the length of the second sub-gate 122 is denoted as L2, and there is a relationship between L1 and L2 as follows: L1=(L1+L2)×Ka. The value of Ka can be K1, and a reasonable value of K1 can achieve a balance between the on-state performance and the withstand voltage performance of the semiconductor device. Specifically, if L1 is too large, the optimization degree of the low on-state resistance is limited, and if L1 is too small, the field plate depletion effect of the shielding gate 130 will be greatly weakened, affecting the withstand voltage of the device. In the specific implementation process, the value of K1 can be controlled within the range of 40% to 60%, for example, the value of K1 can be 40%, 45%, 48%, 50%, 55%, 58%, or 60%, etc., such as 50%±5%.

[0066] In some examples, the first sub-gate 121 and the second sub-gate 122 can be an integral structure, and the second sub-gate 122 can be considered as a part of the top surface of the first sub-gate 121 extending into the upper region 115 of the trench 110 from the opening of the trench 110. Referring to Figure 3 and Figure 5In the width direction (Y direction) of the trench 110, the width of the first sub-gate 121 can be the same as the width of the second sub-gate 122; of course, it is not limited thereto. In some examples, the width of the second sub-gate 122 can be greater than the width of the shield gate 130.

[0067] In some examples, referring to Figure 5 , the side surface of the first sub-gate 121 is flush with the side surface of the second sub-gate 122, where the side surface refers to the side surface extending in the depth direction of the trench 110, then Figure 5 the cross section of the control gate 120 shown is rectangular. In other examples, the width of the shield gate 130 can also be the same as the width of the second sub-gate 122, and then the side surface of the shield gate can be flush with the side surface of the second sub-gate.

[0068] Embodiment two provides a semiconductor device, which is a further improvement based on embodiment one. Referring to Figure 6 , in embodiment two, the drain region 140 is provided with a lead region 141 as a contact region, the doping type of the lead region 141 is consistent with the doping type of the drain region 140, and the doping concentration of the lead region 141 is greater than the doping concentration of the drain region 140. The top surface of the semiconductor substrate 100 can be provided with an electrode layer 150, which can specifically include a first electrode 151 and a second electrode 152 as pads, and a metal wiring. The lead regions 141 on both sides of the trench 110 are respectively connected to the first electrode 151 and the second electrode 152. In the case where the first electrode 151 is an input terminal, the second electrode 152 can be an output terminal; conversely, in the case where the second electrode 152 is an input terminal, the first electrode 151 can be an output terminal. In addition, there are other electrodes not shown in the figure to lead out the shield gate and the control gate respectively. Exemplarily, the electrode layer can adopt a single metal layer or a multi-layer stacked metal layer. The material of the electrode layer can be titanium and titanium nitride, aluminum copper, aluminum silicon copper, or aluminum silicon.

[0069] Since the lead region 141 needs to be a heavily doped region as a contact region, if the top surface of the shield gate 130 is flush with the top opening of the trench 110, an uneven electric field distribution can be induced near the contact region, which affects the device voltage resistance or reliability. Therefore, the top surface of the shield gate 130 is preferably lower than the top surface of the semiconductor substrate 100, i.e., part or all of the third dielectric layer 118 is located in the trench 110, in which case, the top surface of the shield gate 130 is preferably controlled to be not higher than the bottom surface of the contact region.

[0070] Embodiment three of the present application provides a semiconductor device, which is a further improvement based on embodiments one and two. Referring to Figure 7In the semiconductor device provided in Embodiment Three, the top surface of the semiconductor substrate 100 is provided with a fourth dielectric layer 160, which can have a flat top surface. The fourth dielectric layer 160 can be an undoped silicon glass (USG) or a boron-phosphorus-doped silicon glass (BPSG), etc. The fourth dielectric layer 160 is provided with a plurality of through holes 161 penetrating the fourth dielectric layer 160. The first electrode 151 and the second electrode 152 are both electrically connected to the corresponding lead regions 141 through the through holes 161.

[0071] It should be noted that in the above embodiments, the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 are both lower than the slot opening 112 of the trench 110, and the space between the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 and the slot opening 112 can be filled with a third dielectric layer 118. Alternatively, a dielectric layer can be further provided on the third dielectric layer 118 and the semiconductor substrate 100, and the configuration, position and overall thickness of the dielectric layer can be reasonably set according to the device voltage withstand requirement, electrode lead-out condition, etc. Figures 3 to 7 Unlike the foregoing embodiments, the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 are both flush with the slot opening 112 of the trench 110 in the semiconductor device provided in Embodiment Four of the present application. The dielectric layer on the top surface of the second sub-gate 122 and the shielding gate 130 is located outside the trench 110 and covers the top surface of the second sub-gate 122 and the shielding gate 130 and the top surface 102 of the semiconductor substrate.

[0072] Figure 8 Unlike the foregoing embodiments, the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 are both flush with the slot opening 112 of the trench 110 in the semiconductor device provided in Embodiment Four of the present application. The dielectric layer on the top surface of the second sub-gate 122 and the shielding gate 130 is located outside the trench 110 and covers the top surface of the second sub-gate 122 and the shielding gate 130 and the top surface 102 of the semiconductor substrate.

[0073] Unlike the foregoing embodiments, the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 are both flush with the slot opening 112 of the trench 110 in the semiconductor device provided in Embodiment Four of the present application. The dielectric layer on the top surface of the second sub-gate 122 and the shielding gate 130 is located outside the trench 110 and covers the top surface of the second sub-gate 122 and the shielding gate 130 and the top surface 102 of the semiconductor substrate. Figures 9 to 12 Unlike the foregoing embodiments, the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 are both flush with the slot opening 112 of the trench 110 in the semiconductor device provided in Embodiment Four of the present application. The dielectric layer on the top surface of the second sub-gate 122 and the shielding gate 130 is located outside the trench 110 and covers the top surface of the second sub-gate 122 and the shielding gate 130 and the top surface 102 of the semiconductor substrate.

[0074] Figure 9 Unlike the foregoing embodiments, the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 are both flush with the slot opening 112 of the trench 110 in the semiconductor device provided in Embodiment Four of the present application. The dielectric layer on the top surface of the second sub-gate 122 and the shielding gate 130 is located outside the trench 110 and covers the top surface of the second sub-gate 122 and the shielding gate 130 and the top surface 102 of the semiconductor substrate. Figure 12 ​​In the semiconductor device provided in Embodiment Five, along the depth direction (Z direction) of the trench 110, the first sub-gate 121 has oppositely arranged top and bottom surfaces, wherein the top surface faces the trench mouth (i.e. faces the top surface 102 of the semiconductor substrate 100). The normal projection of the second sub-gate 122 on the plane where the top surface of the first sub-gate 121 is located at least partially falls into the top surface of the first sub-gate 121, and the normal projection of the shielding gate 130 on the plane where the top surface of the first sub-gate 121 is located at least partially falls into the top surface of the first sub-gate 121. In the cross-sectional structure in the width direction of the trench 110, as shown in Figure 11 , the cross section of the control gate 120 formed by the integral first sub-gate 121 and second sub-gate 122 is in the shape of “L”, i.e. the width of the first sub-gate 121 is greater than the width of the second sub-gate 122; the width of the first sub-gate 121 can also be greater than the width of the shielding gate 130, which can be regarded as the shielding gate 130 being embedded in the gap position of the “L”-shaped control gate 120.

[0075] In Embodiment Five, the second sub-gate 122 is in the shape of a long strip and is arranged along the length direction of the trench 110, so the area of the second sub-gate 122 is greater than the area of the second sub-gate 122 arranged in the middle in Embodiment One, the area of the control gate 120 is thus increased, the area of the control gate for forming the channel is increased, the area of the channel is increased, the on-current of the channel is increased, and the on-resistance of the device is thus reduced, and the on-performance is stronger.

[0076] Compared with the need to separately lead out the plurality of spaced shielding gates in Embodiments One to Four, in the present embodiment, since the control gate and the shielding gate are both in the shape of a long strip, the electrical leading out of the two gates, especially the shielding gate, is more convenient, and the process difficulty is lower. Exemplarily, one end or both ends in the length direction of the trench can be used as the leading end of the control gate 120 and the shielding gate 130, for connecting the leading electrode and the line structure, etc.; in the length direction of the trench, when one end is used as the leading end, the opposite end can be a non-leading end; or both ends can be leading ends.

[0077] In some examples, at least one side surface of the second sub-gate 122 is flush with at least one side surface of the first sub-gate 121, where the side surface is a side surface extending in the depth direction of the trench. Exemplarily, referring to Figure 9 and Figure 11 , the side surface of the second sub-gate 122 facing away from the shielding gate 130 is flush with the side surface of the first sub-gate 121 connected thereto. The end surface of the second sub-gate 122 at the non-leading end can be flush with the end surface of the first sub-gate 121 at the non-leading end. In some examples, one side surface of the shielding gate 130 is flush with one side surface of the first sub-gate 121. Referring to Figure 9 and Figure 11The side of the shielding gate 130 facing away from the second sub-gate 122 is flush with the side of the first sub-gate 121 facing away from the connected second sub-gate 122 in the Y direction. The end surface of the shielding gate 130 at the non-lead-out end is flush with the end surface of the second sub-gate 122 at the non-lead-out end.

[0078] In Embodiment Five, with reference to Figure 9 and Figure 11 The top surface of the second sub-gate 122 is flush with the top surface of the shielding gate 130. The top surfaces of the second sub-gate 122 and the shielding gate 130 are both lower than the slot opening 112 of the trench 110. The third dielectric layer 118 covered by the top surfaces of the second sub-gate 122 and the shielding gate 130 is at least partially located in the trench 110, and is arranged in the region close to the slot opening 112. However, it is not limited thereto, and in other embodiments, the top surface of the second sub-gate 122 and the top surface of the shielding gate 130 can also be flush with the slot opening of the trench 110, and the third dielectric layer is arranged outside the trench 110, i.e., the third dielectric layer covers the top surface of the semiconductor substrate.

[0079] As described above, in the plurality of trenches 110 arranged in the Y direction, the second sub-gate 122 and the shielding gate 130 are alternately arranged in the width direction (Y direction) of the trench 110. The shielding gate 130 is grounded or connected to a low potential (lower than the potential connected to the drain region). In the case of device cutoff, the low potential shielding gate 130 can deplete the charge of the drain region 140 through the interval first dielectric layer 116, and each drain region 140 needs to be adjacent to at least one shielding gate 130 in the trench 110 to ensure that the semiconductor device has sufficient withstand voltage performance, so in the Y direction, the second sub-gate 122 and the shielding gate 130 in the plurality of trenches 110 are sequentially and alternately arranged. In the Y direction, both sides of each drain region 140 are adjacent to the second sub-gate 122 and the shielding gate 130, respectively. That is, one side of the drain region 140 is adjacent to the shielding gate 130, and the other side is adjacent to the second sub-gate 122, and then one side of each drain region 140 is adjacent to the shielding gate 130, which can ensure that the corresponding dielectric layer of the shielding gate 130 depletes the charge of the corresponding drain region 140, and ensures the withstand voltage performance of each drain region 140.

[0080] In Embodiment Five, with reference to Figures 10 to 12The second sub-gate 122 and the shielding gate 130 are both arranged in the groove 110 and extend along the length direction (X direction) of the groove 110. Specifically, the first sub-gate 121, the second sub-gate 122 and the shielding gate 130 can all be strip electrodes arranged along the length direction of the groove 110. For example, in this embodiment, the first sub-gate 121, the second sub-gate 122 and the shielding gate 130 are all strip electrodes, and the cross section of the three along the top surface of the semiconductor substrate is rectangular. Of course, this is not limited thereto, and in other embodiments, the second sub-gate 122 and the shielding gate 130 both have a plurality of protrusions facing each other, the plurality of protrusions are arranged at intervals along the length direction of the groove, and the protrusions of the two are staggered, similar to a mosaic fit.

[0081] In some examples, reference is made to Figure 11 The size of the shielding gate 130 in the Z direction is the thickness of the shielding gate, denoted as H1, the thickness of the first sub-gate 121 is denoted as H3, and the thickness of the second sub-gate 122 is denoted as H5. For example, H1≥H3, but this is not limited thereto. In comparison, the thickness H1 of the shielding gate 130 is large and the thickness H3 of the first sub-gate 121 is small, which means that the depth of the drain region is large, which is equivalent to compressing the length of the channel, thereby reducing the on-resistance and improving the withstand voltage. Conversely, if the thickness of the shielding gate 130 is small and the thickness H3 of the first sub-gate 121 is large, the on-resistance of the device is low and the on-current is large. In practice, the thickness of the shielding gate 130 and the first sub-gate 121 and the size relationship between the two can be set according to different withstand voltage requirements, such as in other embodiments, H1

[0082] For example, the thickness H3 of the first sub-gate 121 can be more than 30% and less than 50% of the thickness of the entire control gate 120, that is, the value of H3:(H3+H5) is denoted as K2, 30%≤K2<50%; further, 30%≤K2≤45%, for example, K2 can be 30%, 35%, 40% or 45%, etc.

[0083] As Figure 9 , Figure 11 and Figure 12As shown, along the Y direction, the width of the shielding gate 130 is denoted as W1, the width of the first sub-gate 121 is denoted as W2, and the width of the second sub-gate 122 is denoted as W3. In this embodiment, the width W2 of the first sub-gate 121 is greater than the width W1 of the shielding gate 130 (W2 > W1), but it is not limited thereto. In other embodiments, the width W1 of the shielding gate 130 may also be greater than or equal to the width W2 of the first sub-gate 121 (W2 ≤ W1). In this embodiment, the width W1 of the shielding gate 130 is equal to or approximately equal to the width W3 of the second sub-gate 122 (W1 ≈ W3); in other embodiments, the width W1 of the shielding gate 130 may also be greater than or less than the width W3 of the second sub-gate 122. In this embodiment, the sum of the width W3 of the second sub-gate 122 and the width W1 of the shielding gate 130 is less than the width of the first sub-gate 121, i.e., W1 + W3 < W2; in other embodiments, the sum of the width of the second sub-gate 122 and the width of the shielding gate 130 may also be greater than or equal to the width of the first sub-gate 121.

[0084] In some examples, such as Figure 13 As shown, along the length direction (X direction) of the trench 110, the trench 110 includes a middle section region 119 and end regions on both sides of the middle section region 119. In some examples, refer to Figure 13 Along the length direction (X direction) of the trench 110, the two ends of the second sub-gate 122 are a lead-out end 122-1 and a free end 122-2, respectively. The lead-out end 122-1 of the second sub-gate 122 is used to connect electrodes, and the free end 122-2 of the second sub-gate 122 is not connected to electrodes. The two ends of the shielding gate 130 are a lead-out end 131 and a free end 132, respectively. The lead-out end 131 of the shielding gate 130 is used to connect electrodes, and the free end 132 of the shielding gate 130 is not connected to electrodes. Along the length direction (X direction) of the trench 110, the length of the second sub-gate 122 is greater than the length of the shielding gate 130, and the width of the second sub-gate 122 located in the middle section region 119 is smaller than the width of its free end 122-2 to facilitate the connection of the lead-out electrodes. The length of the first sub-gate 121 can be the same as the length of the second sub-gate 122. The second sub-grid 122 and the shielding grid 130 overlap in their orthographic projections on the first plane, and the second sub-grid 122 and the shielding grid 130 overlap in their orthographic projections on the second plane. The first plane is perpendicular to the length direction of the trench, i.e., the first plane is parallel to the Y and Z directions, and the second plane is perpendicular to the width direction (Y direction) of the trench, i.e., the second plane is parallel to the Z and X directions.

[0085] refer to Figures 14 to 17In the semiconductor device provided in Embodiment Six based on Embodiment Five, the second sub-gate 122 further includes a first structure part 122-3 and a plurality of second structure parts 122-4 in the same trench 110. Exemplarily, the first structure part 122-3 and the second structure part 122-4 can be an integrated structure. Specifically, the second sub-gate 122 can be regarded as the part of the first structure part 122-3 extending or protruding towards the shielding gate 130 along the width direction (Y direction) of the trench 110, and the part of the extension or protrusion is the second structure part 122-4. The first structure part 122-3 and the shielding gate 130 are arranged along the width direction (Y direction) of the trench 110, and the plurality of second structure parts 122-4 and the shielding gate 130 are arranged along the length direction (X direction) of the trench 110.

[0086] With reference to Figures 14 to 17 , the second sub-gate 122 and the shielding gate 130 have overlapping projections on a second plane, wherein the second plane is perpendicular to the width direction (Y direction) of the trench, i.e., the second plane is parallel to the Z direction and the X direction; more specifically, the first structure part 122-3 and the shielding gate 130 have overlapping or partially overlapping projections on the second plane, and the second sub-gate 122 and the shielding gate 130 have overlapping projections on a first plane and the second plane, wherein the first plane is perpendicular to the length direction (X direction) of the trench 110, i.e., the first plane is parallel to the Z direction and the Y direction; more specifically, the second structure part 122-4 and the shielding gate 130 have overlapping projections on the first plane.

[0087] Exemplarily, with reference to Figure 15 and Figure 17 , one first structure part 122-3, a plurality of second structure parts 122-4 and a plurality of shielding gates 130 are provided in the same trench 110. In the same trench 110, the second structure part 122-4 and the shielding gate 130 are arranged alternately along the length direction (X direction) of the trench 110 and the first structure part 122-3.

[0088] Exemplarily, with reference to Figure 16 and Figure 17In a plurality of trenches 110, along the width direction (Y direction) of the trenches 110, the first structural portion 122-3 and the shielding gate 130 are arranged alternately. The dielectric between the shielding gate 130 and the drain region 140 can be the first dielectric layer 116 on the inner wall of the trench 110. When the semiconductor device is off, the low-potential shielding gate 130 can deplete the charge of the drain region 140 through the first dielectric layer 116. Each drain region 140 needs to be adjacent to at least one shielding gate 130 in the trench 110 to ensure that the semiconductor device has sufficient withstand voltage performance. Therefore, in the Y direction, the second structural portion 122-4 and the shielding gate 130 in the plurality of trenches 110 are arranged alternately in sequence. In other words, in the Y direction, each drain region 140 is adjacent to the second sub-gate 122 and the shielding gate 130 on both sides, respectively. That is, one side of the drain region 140 is adjacent to the shielding grid 130, and the other side is adjacent to the second sub-grid 122. Thus, one side of each drain region 140 is adjacent to the shielding grid 130, and multiple shielding grids 130 are provided in each trench 110. This can ensure that the dielectric layer of the shielding grid 130 near the drain region 140 can deplete the charge of the corresponding drain region 140, thereby ensuring the withstand voltage performance of each drain region 140.

[0089] and Figure 1 Compared to the prior art, in the semiconductor devices provided in Embodiments 5 and 6, the second sub-gate occupies the original position of the shielding gate. However, in Embodiment 5, the shielding gate is a continuous elongated strip, while in Embodiment 6, the size of the shielding gate is further reduced due to the "extrusion" of the second structural portion 122-4. Therefore, under the same conditions, the shielding gate 130 in Embodiment 5 has a larger volume, and under reverse cutoff conditions, the shielding gate depletes the drain region more fully, resulting in less leakage current. Furthermore, compared to Embodiment 6, which requires each shielding gate to be led out separately, the shielding gate lead-out method in Embodiment 5 is more flexible and easier to manufacture.

[0090] For example, refer to Figure 16 and Figure 17In the depth direction (Z direction) of the trench 110, the first sub-gate 121 has oppositely arranged top and bottom surfaces, wherein the top surface faces the slot of the trench, the second sub-gate 122 has a normal projection on the plane where the top surface of the first sub-gate 121 is located, and the normal projection at least partially falls on the top surface of the first sub-gate 121, and the shielding gate 130 has a normal projection on the plane where the top surface of the first sub-gate 121 is located, and the normal projection at least partially falls on the top surface of the first sub-gate 121. In some examples, at least one side surface of the second sub-gate 122 is flush with at least one side surface of the first sub-gate 121, and the side surface is a side surface extending in the depth direction of the trench. For example, in the present embodiment, in the same trench, the side surface of the second sub-gate 122 facing away from the shielding gate 130 is flush with the corresponding side surface of the first sub-gate 121, that is, the side surface of the first structure part 122-3 facing away from the shielding gate 130 is flush with the corresponding side surface of the first sub-gate 121, and in the Y direction, the width of the first structure part 122-3 is smaller than the width of the first sub-gate 121, so the cross section of the first sub-gate 121 and the first structure part 122-3 is in the shape of “L”, and the shielding gate 130 can be regarded as being embedded in the gap of the “L” shaped structure. The present embodiment does not particularly limit the side surface of the second structure part 122-4 facing the shielding gate 130 to be flush with the corresponding side surface of the first sub-gate 121, that is, the two can be flush or not flush.

[0091] For example, one side surface of the shielding gate 130 is flush with one side surface of the first sub-gate 121, for example, in the embodiment shown in the figure, the side surface of the shielding gate 130 facing away from the first structure part 122-3 is flush with the corresponding side surface of the first sub-gate 121. Of course, the two can also not be flush, and in other embodiments, the normal projection of the shielding gate 130 on the plane where the top surface of the first sub-gate 121 is located partially overlaps with the top surface of the first sub-gate 121, that is, the side surface of the shielding gate 130 facing away from the first structure part 122-3 can exceed the corresponding side surface of the first sub-gate 121. Figure 16

[0092] For example, in the embodiment shown in the figure, the side surface of the shielding gate 130 facing away from the first structure part 122-3 is flush with the corresponding side surface of the first sub-gate 121. Of course, the two can also not be flush, and in other embodiments, the normal projection of the shielding gate 130 on the plane where the top surface of the first sub-gate 121 is located partially overlaps with the top surface of the first sub-gate 121, that is, the side surface of the shielding gate 130 facing away from the first structure part 122-3 can exceed the corresponding side surface of the first sub-gate 121. Figure 15 For example, in the embodiment shown in the figure, the side surface of the shielding gate 130 facing away from the first structure part 122-3 is flush with the corresponding side surface of the first sub-gate 121. Of course, the two can also not be flush, and in other embodiments, the normal projection of the shielding gate 130 on the plane where the top surface of the first sub-gate 121 is located partially overlaps with the top surface of the first sub-gate 121, that is, the side surface of the shielding gate 130 facing away from the first structure part 122-3 can exceed the corresponding side surface of the first sub-gate 121.

[0093] For example, in the embodiment shown in the figure, the side surface of the shielding gate 130 facing away from the first structure part 122-3 is flush with the corresponding side surface of the first sub-gate 121. Of course, the two can also not be flush, and in other embodiments, the normal projection of the shielding gate 130 on the plane where the top surface of the first sub-gate 121 is located partially overlaps with the top surface of the first sub-gate 121, that is, the side surface of the shielding gate 130 facing away from the first structure part 122-3 can exceed the corresponding side surface of the first sub-gate 121. Figure 15 ​, the thickness of the shielding gate 130 is H1, and the thickness of the first sub-gate 121 is H3. In this embodiment, H1 is greater than H3, but the present application is not limited thereto. In other embodiments, H1 can be less than H3. The distance between the top surface of the first sub-gate 121 and the top surface of the shielding gate 130 is H2, and the distance between the top surface of the first sub-gate 121 and the bottom surface of the shielding gate 130 is H4, which is the thickness of the dielectric layer between the shielding gate 130 and the first sub-gate 121. When the top surface of the shielding gate 130 is flush with the top surface of the second sub-gate 122, H4 = H2 - H1, and H4 > 0.

[0094] Reference is made to Figure 16 and Figure 17 , along the Y direction, the width of the shielding gate 130 is W1, the width of the first sub-gate 121 is W2, and the width of the first structure 122-3 is W3. W2 > W1 + W3. The width of the second structure 122-4 can be greater than the width W1 of the shielding gate 130.

[0095] The top surfaces of the second sub-gate 122 and the shielding gate 130 do not exceed the opening of the trench 110. In this embodiment, the top surface of the second sub-gate 122 is flush or approximately flush with the top surface of the shielding gate 130, and the top surfaces of the second sub-gate 122 and the shielding gate 130 are both lower than the opening of the trench 110. At least part of the third dielectric layer 118 on the top surfaces of the second sub-gate 122 and the shielding gate 130 is located in the trench 110. In other embodiments, the top surfaces of the second sub-gate and the shielding gate are both flush with the opening of the trench, and the third dielectric layer is located outside the trench. Figures 14 to 16 Reference is made to

[0096] , this embodiment provides a semiconductor device, which also has a shielding gate 130 and a control gate 120 in the trench 110. The shielding gate 130 and the second sub-gate 122 are both located in the upper region 115 of the trench 110, and the first sub-gate 121 is located in the lower region 114 of the trench 110. Different from the foregoing embodiments, in this embodiment, the shielding gate 130 has a groove 133, the opening of the groove 133 faces the lower region 114 of the trench 110, and part of the second sub-gate 122 is embedded in the groove 133. The length direction of the groove 133 is the same as the length direction (X direction) of the trench 110. Figures 18 to 21 Exemplarily, reference is made to

[0097] Figures 18 to 21 ​The groove 133 penetrates the shielding gate 130 in the width direction (Y direction). Both ends of the groove 133 in the Y direction have openings, that is, the groove 133 has a bottom wall at the groove bottom and side walls on both sides (in the X direction) of the bottom wall, wherein the side walls extend in the Y direction and the Z direction. The second sub-gate 122 does not overlap with the shielding gate 130 in the orthographic projection on the second plane, and partially overlaps with the shielding gate 130 in the orthographic projection on the first plane, wherein the second plane is perpendicular to the width direction (Y direction) of the trench 110, and the first plane is perpendicular to the length direction (X direction) of the trench 110.

[0098] The semiconductor device provided by the seventh embodiment can accommodate part of the second sub-gate 122 in the space of the groove 133 by arranging the groove 133 on the shielding gate 130, and the second sub-gate 122 occupies part of the space of the upper region of the trench 110, which is different from the first embodiment. Figure 1 Compared with the prior art shown in FIG. 1 and the first embodiment, the size of the shielding gate 130 and the control gate 120 and the positions of the two in the trench 110 can be more flexibly controlled, which is beneficial to optimizing the on-state performance and the withstand voltage performance of the semiconductor device.

[0099] Reference is made to FIG. 1 and FIG. 2. Figure 19 The maximum thickness of the shielding gate 130 in the Z direction is denoted as H1, and the thickness of the first sub-gate 121 is denoted as H3. The present application does not particularly limit the relationship between H1 and H3. In the present embodiment, H1≥H3, and in other embodiments, H1 can also be less than H3. Relatively speaking, the thickness H1 of the shielding gate 130 is large, and the thickness H3 of the first sub-gate 121 is small, which means that the depth of the drain region is large, which is equivalent to compressing the length of the channel, thereby reducing the on-state resistance and improving the withstand voltage. Conversely, if the thickness H1 of the shielding gate 130 is small and the thickness H3 of the first sub-gate 121 is large, the on-state resistance of the device is low, and the on-state current is large. In practice, the values and proportions of the two can be reasonably determined according to the actual product performance requirements. The distance between the top surface of the first sub-gate 121 and the top surface of the shielding gate 130 is denoted as H2. The thickness of the second sub-gate 122 is denoted as H5, and H5

[0100] For example, reference is made to FIG. 1 and FIG. 2. Figure 19 For example, the thickness H3 of the first sub-gate 121 can be more than 30% and less than 50% of the total thickness of the control gate 120, that is, H3:(H3+H5)=K5, 30%≤K5<50%, for example, K5 is any value (including the end value) in 30% to 45%.

[0101] For example, reference is made to FIG. 1 and FIG. 2. Figure 19The thickness of the shielding gate 130 corresponding to the bottom of the groove 133 is denoted as H7, and the maximum thickness of the control gate 120 is the sum of the thicknesses of the first sub-gate 121 and the second sub-gate 122, that is, H3+H5, and the ratio of H7:(H3+H5) is denoted as K6, 0.5≤K6<1, which can be 0.5, 0.6, 0.7, 0.8, 0.9, or 0.95, etc. This value is conducive to adapting to various working voltages and on-resistance scenarios. If K6 is greater than or equal to 0.5, it is conducive to improving the voltage resistance and reducing the gate-source capacitance of the device; if K6 is less than 1, it is conducive to reducing the on-resistance of the device. Therefore, K6 is within the above value range, which can better adjust the voltage resistance and on-resistance of the device.

[0102] In some examples, in the same trench, the number of grooves is one, and the number of second sub-gates is one or more. For example, in the structure shown in FIG. 1C, in the same trench 110, the number of grooves 133 is one, and the number of second sub-gates 122 is also one, and the second sub-gate 122 is partially embedded in the groove 133. Figure 19 In other examples, in the same trench, the number of grooves is multiple, and the number of second sub-gates is multiple, and at least one second sub-gate is partially embedded in each groove. Referring to FIG. 1D, in the same trench 110, multiple grooves 133 and multiple second sub-gates 122 are provided, and the multiple grooves 133 and the multiple second sub-gates 122 are arranged along the length direction (X direction) of the trench 110. Each groove 133 is embedded with one second sub-gate 122. Figure 22 Figure 23 In the same trench 110, multiple grooves 133 and multiple second sub-gates 122 are provided, and the multiple grooves 133 and the multiple second sub-gates 122 are arranged along the length direction (X direction) of the trench 110. Each groove 133 is embedded with one second sub-gate 122.

[0103] It should be noted that, Figure 19 Figure 22 Figure 23 The number of grooves 133 and the number of second sub-gates 122 shown in FIGS. 1C and 1D are only illustrative and are not a specific limitation of the present application.

[0104] Referring to FIG. 1D, in the same trench 110, multiple grooves 133 and multiple second sub-gates 122 are provided, and the multiple grooves 133 and the multiple second sub-gates 122 are arranged along the length direction (X direction) of the trench 110. Each groove 133 is embedded with one second sub-gate 122. Figure 22 ​​​In the length direction (X direction) of the trench 110, the length of the second sub-gate 122 is L2, the length of the groove 133 is L3, and the interval width between two adjacent grooves 133 is L4. If L2 is too large, the field plate depletion effect of the shielding gate 130 will be greatly weakened, which will affect the device voltage resistance. If L2 is too small, the optimization degree of low on-resistance is limited. Therefore, reasonable control of the value of L2 can better balance low on-resistance and high voltage resistance. Exemplarily, the length L2 of the second sub-gate 122, the length L3 of the groove 133, and the interval width L4 between two adjacent grooves 133 satisfy the following relationship: L2 = (L3 + L4) × Kb, where the value of Kb can be K7, and the value range of K7 is 30% to 60%, i.e. 30% ≤ K7 ≤ 60%, such as 30%, 35%, 40%, 47%, 50%, 55% or 60%, etc. In one example, 40% ≤ K7 ≤ 60%, and in another example, 30% ≤ K7 ≤ 50%.

[0105] In some examples, at least one side surface of the second sub-gate 122 is flush with at least one side surface of the first sub-gate 121. The side surface is a side surface extending in the depth direction of the trench. At least one side surface of the shielding gate is flush with at least one side surface of the first sub-gate. At least one side surface of the shielding gate is flush with at least one side surface of the second sub-gate. Exemplarily, referring to Figure 18 、 Figure 20 、 Figure 21 and Figure 23 , two side surfaces of the second sub-gate 122 in the Y direction are flush with the corresponding side surfaces of the first sub-gate 121, and two side surfaces of the shielding gate 130 in the Y direction are flush with the corresponding side surfaces of the first sub-gate. Referring to Figure 20 In the Y direction, the width of the shielding gate 130 is represented as W1, and the width of the control gate 120 is represented as W2. Exemplarily, W1 = W2. In this embodiment, the two surfaces of the shielding gate 130 and the control gate 120 facing the drain region 140 are coplanar. In some other examples, the width of the shielding gate can also be smaller than the width of the control gate. The width of the shielding gate and the control gate can be reasonably determined according to the thickness requirement of the dielectric layer between the shielding gate, the control gate and the inner wall of the trench, etc., to ensure that the device has high voltage resistance performance. In other examples, the side surface of the second sub-gate in the Y direction can not be flush with the side surface of the first sub-gate, and the side surface of the shielding gate can also not be flush with the side surface of the first sub-gate.

[0106] The top surfaces of the second sub-gate 122 and the shielding gate 130 do not exceed the slot of the trench. Referring to Figures 18 to 20In the embodiment, the top surface of the shield gate 130 is lower than the slot 112 of the trench 110, and the space between the top surface of the shield gate 130 and the slot 112 can be filled with the third dielectric layer 118; or in other words, part or all of the third dielectric layer 118 is located in the trench 110. Since the second sub-gate 122 is partially embedded in the groove 133, the second dielectric layer 117 is filled between the second sub-gate 122 and the shield gate 130. The top surface of the second sub-gate 122 is lower than the top surface of the shield gate 130. In other embodiments, the top surface of the shield gate 130 can be flush with the slot of the trench; and the dielectric layer on the top surface of the shield gate is located outside the trench.

[0107] Compared with the semiconductor devices provided in Embodiments 1 to 4 and Embodiment 6, in the semiconductor device provided in Embodiment 7, the shield gate 130 is in an integral structure rather than being arranged in multiple shield gates in a spaced manner, which is more conducive to electrode lead-out, i.e., the number of conductive vias can be set according to actual needs, and the size of the conductive vias can also be more flexibly adjusted, and the process tolerance is greater.

[0108] Reference Figures 24 to 27 Embodiment 8 of the present application provides a semiconductor device, which is similar to Embodiment 7, and the shield gate 130 is provided with a groove 133, the slot of the groove 133 faces the lower region 114 of the trench 110, and part of the second sub-gate 122 is embedded in the groove 133. The inner wall of the groove 133 includes a bottom wall located at the bottom of the groove and a side wall connected to the bottom wall, and the length direction of the groove 133 is the same as the length direction (X direction) of the trench 110. Different from Embodiment 7, in Embodiment 8, the groove 133 penetrates the shield gate 130 in the X direction, the bottom of the groove 133 is close to the top surface of the shield gate 130, and the side wall of the groove 133 extends along the X direction and the Z direction. The groove 133 has openings at both ends in the length direction (X direction), the second sub-gate 122 and the shield gate 130 do not overlap in the orthogonal projection on the first surface, and the second sub-gate 122 and the shield gate 130 partially overlap in the orthogonal projection on the second surface.

[0109] Reference Figure 24 The groove 133 has openings at at least one end in the length direction, i.e., the groove 133 has one side wall or no side wall in the X direction, so as to facilitate the lead-out of the end of the second sub-gate 122. The groove 133 has side walls on both sides in the Y direction.

[0110] Reference Figure 25 and 26, the maximum thickness of the shielding gate 130 in the thickness direction (Z direction) of the semiconductor substrate is denoted as H1, and the thickness of the first sub-gate 121 in the Z direction is denoted as H3. In this embodiment, H1≥H3, and of course it is not limited thereto, and the size between H1 and H3 can be set according to different voltage requirements and the like. Relatively speaking, the maximum thickness H1 of the shielding gate 130 is large, the thickness H3 of the first sub-gate 121 is small, the depth of the drain region is large, which is equivalent to compressing the length of the channel, thereby reducing the on-resistance and improving the withstand voltage. Conversely, if the maximum thickness H1 of the shielding gate 130 is small and the thickness H3 of the first sub-gate 121 is large, the on-resistance of the device is low and the on-current is large. The distance between the top surface of the first sub-gate 121 and the top surface of the shielding gate 130 is denoted as H2, the thickness of the second sub-gate 122 is denoted as H5, and H5

[0111] Reference Figure 25 and Figure 26 , the thickness H3 of the first sub-gate 121 can be more than 30% of the thickness of the entire control gate 120 and less than 50%, that is, the value K9 of H3:(H3+H5) can be in the range of 30% to 50%, and further, the value of K9 can be 30% to 45%, 30%≤K9≤45%, and K9 can be 30%, 35%, 40%, or 45%, and the like.

[0112] Reference Figure 25 and Figure 26 , the thickness of the bottom of the groove 133 is denoted as H7, and the maximum thickness of the control gate 120 is the sum of the thicknesses of the first sub-gate 121 and the second sub-gate 122, that is, H3+H5. The ratio of H7 to (H3+H5) is denoted as K10, 0.5≤K10<1, and for example, K10 can be 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or 0.99, and the like. If K9 is greater than 0.5, it is beneficial to improve the withstand voltage of the device and reduce the gate-source capacitance; and if K9 is less than 1, it is beneficial to reduce the on-resistance of the device, and therefore, the value range of K10 is 0.5 to 1 (not including 1), which can better adjust the withstand voltage and on performance of the device, and is beneficial to adapt to multiple working voltage and on-resistance scenarios.

[0113] Reference Figure 26In the Y direction, the maximum width of the shielding gate 130 is denoted as W1, and the width of the first sub-gate 121 is denoted as W2. W1 can be equal to or approximately equal to W2, or can not be equal to W2. The width of the second sub-gate 122 is denoted as W3, and the thickness of the shielding gate corresponding to the single-side wall of the groove 133 in the Y direction is denoted as W4. W3 and W4 can be set according to specific process capabilities, and are subject to the ability to ensure the withstand voltage capability of the shielding gate 130 and the control capability of the channel.

[0114] In one example, referring to Figures 24 to 27 In the same trench 110, the number of grooves 133 is one, and the number of second sub-gates 122 is also one, both of which extend along the length direction of the trench 110, and the second sub-gate 122 is partially embedded in the groove 133. However, it is not limited thereto. For example, in another example of the present application, referring to Figure 28 and Figure 29 In the same trench 110, one groove 133 and a plurality of second sub-gates 122 are provided, the plurality of second sub-gates 122 are embedded in the same groove 133, and the plurality of second sub-gates 122 are arranged and spaced apart along the X direction. Although three second sub-gates 122 are shown in the figure, the number of second sub-gates can be more or less.

[0115] Referring to Figure 28 In the length direction (X direction) of the trench 110, the spacing distance between the adjacent two second sub-gates 122 is denoted as L1, and the width of the second sub-gate 122 is denoted as L2. L1 and L2 have the following relationship: L2=(L1+L2)×Ka. If L1 is too large, the optimization degree of the low on-resistance is limited; if L1 is too small, the field plate depletion effect of the shielding gate 130 will be greatly weakened, which will affect the withstand voltage of the device. Therefore, it is necessary to set a reasonable Ka parameter to balance the on-resistance and high withstand voltage performance. Preferably, the value of Ka can be K11, and the value range of K11 is 40% to 60%, that is, 40≤K11≤60%. For example, the value of K10 can be 40%, 45%, 47%, 50%, 55% or 60%, etc.

[0116] In this embodiment, referring to Figure 24 and Figure 26 The side surface of the shielding gate 130 in the Y direction is flush with the side surface of the first sub-gate in the Y direction; referring to Figure 24 and Figure 27 At least one end surface of the shielding gate 130 in the X direction is flush with the end surface of the first sub-gate in the X direction. In other embodiments, the side surface of the shielding gate in the Y direction can also not be flush with the side surface of the first sub-gate. The orthogonal projection of the shielding gate on the top surface of the first sub-gate can partially fall into the top surface of the first sub-gate.

[0117] Referring to Figures 30 to 33Compared with the semiconductor device provided in the embodiment seven and the embodiment eight, the semiconductor device provided in the embodiment nine also has the shielding gate 130 and the control gate 120 in the trench 110, and the recess 133 is also arranged in the shielding gate 130, the opening of the recess 133 faces the lower region 114 of the trench 110, and part of the second sub-gate 122 is embedded in the recess 133. The length direction of the recess 133 is the same as the length direction (X direction) of the trench 110. However, different from the embodiment seven and the embodiment eight, the recess 133 has side walls in the X direction and the Y direction, and all the side walls of the recess 133 surround the end of the second sub-gate 122 away from the first sub-gate 121, that is, the recess 133 does not penetrate the shielding gate 130 in the X direction and the Y direction.

[0118] Specifically, the recess 133 has a groove bottom and a groove opening, and four side walls connected between the groove bottom and the groove opening, wherein the groove bottom is close to the top surface of the shielding gate 130, and the recess 133 has only one opening facing the first sub-gate 121; there are two side walls in the length direction (X direction) and the width direction (Y direction) of the trench 110. The projection of the second sub-gate 122 on the first plane overlaps the control gate 120, and the projection of the second sub-gate 122 on the second plane overlaps the control gate 120, wherein the first plane is perpendicular to the length direction (X direction) of the trench 110, and the second plane is perpendicular to the width direction (Y direction) of the trench 110. Compared with the embodiment eight, the recess in the embodiment nine does not penetrate the shielding gate 130 in the X direction and the Y direction, so that, under the condition that other conditions are the same, the reserved area of the shielding gate in the embodiment nine is larger, but the length of the recess is shorter, and the length of the second sub-gate 122 is relatively shorter, so that the withstand voltage of the embodiment nine is better, and the current conduction of the embodiment eight is better.

[0119] Reference Figure 31 and 32 The maximum thickness of the shielding gate 130 in the Z direction is represented as H1, and the thickness of the first sub-gate 121 is represented as H3. In this embodiment, H1≥H3, but it is not limited thereto, and the size relationship therebetween can be set according to different withstand voltage requirements, which is not limited in the present application. The distance between the top surface of the first sub-gate 121 and the top surface of the shielding gate 130 is represented as H2, and the thickness of the second sub-gate 122 is represented as H5, and H5

[0120] Reference is made to Figure 31 and Figure 32 , the thickness of the shield gate 130 corresponding to the bottom of the recess 133 is denoted as H7, and the maximum thickness of the control gate 120 is the sum of the thicknesses of the first sub-gate 121 and the second sub-gate 122, i.e., denoted as H3+H5. The ratio K13 of H7:(H3+H5) ranges from 0.5 to 1, i.e., 0.5≤K13<1. Exemplarily, it can be 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, or 0.99, etc. It is beneficial to adapt to various working voltages and scenarios of on-resistance. If the ratio of H7:(H3+H5) is greater than or equal to 0.5, it is beneficial to improve the voltage resistance of the device and reduce the gate-source capacitance; if the ratio of H7:(H3+H5) is less than 1, it is beneficial to reduce the on-resistance of the device, therefore, the value range of K13 is from 0.5 to 1, which can better adjust the voltage resistance and on performance of the device.

[0121] Exemplarily, reference is made to Figure 31 , the length of the recess 133 in the X direction is denoted as L3, obviously, the length L3 of the recess is less than the length of the shield gate 130.

[0122] Exemplarily, reference is made to Figure 32 , in the Y direction, the maximum width of the shield gate 130 is denoted as W1, and the width of the first sub-gate 121 is denoted as W2, W1 can be equal to or approximately equal to W2. In fact, in order to ensure the voltage resistance and control ability of the shield gate 130 to the channel, the thickness of the dielectric layer on both sides thereof is relatively large, therefore W2 is preferably greater than W1. In the Y direction, the thickness of the dielectric layer on both sides of the shield gate 130 is greater than the thickness of the dielectric layer on both sides of the first sub-gate 121, so as to improve the depletion performance of the shield gate 130 and further improve the voltage resistance of the semiconductor device. Reference is made to Figure 3 , in the width direction (Y direction) of the trench 110, the width of the upper region 115 of the trench 110 is approximately equal to or greater than the width of the lower region 114. In the Y direction, the width of the second sub-gate 122 is denoted as W3, and the thickness of the shield gate corresponding to the single-side wall of the recess 133 in the Y direction is denoted as W4. Exemplarily, W3 and W4 can be set according to the specific process capability.

[0123] In one example of the present embodiment, reference is made to Figures 30 to 33 , in the same trench 110, the number of recesses 133 is one, and the number of second sub-gates 122 is also one, and the second sub-gate 122 is partially embedded in the recess 133. In another example of the present embodiment, reference is made to Figure 34 and Figure 35The same trench 110 is provided with a plurality of recesses 133 and a plurality of second sub-gates 122. The recesses 133 and the second sub-gates 122 are arranged one by one, i.e., each recess 133 is embedded with a second sub-gate 122. In the same trench 110, the plurality of recesses 133 are arranged along the X direction, and the plurality of second sub-gates 122 are arranged along the X direction. The adjacent second sub-gates 122 are separated by a shielding gate 130, and the adjacent recesses 133 are separated by a shielding gate 130. Of course, in other examples, each recess 133 can be embedded with a plurality of second sub-gates 122 arranged at intervals.

[0124] For the plurality of recesses 133, refer to Figure 34 In the length direction (X direction) of the trench 110, the length of the recess 133 is denoted as L3, the interval width of the adjacent two recesses 133 is denoted as L4, and the length of the second sub-gate 122 is denoted as L2. If L2 is too large, the field plate depletion effect of the shielding gate 130 will be greatly weakened, affecting the device voltage resistance; if L2 is too small, the optimization degree of the low on-resistance is limited. Therefore, by reasonably controlling the ratio relationship of L2 and (L3+L4), the low on-resistance and high voltage resistance can be better balanced. In the specific implementation process, the length L2 of the second sub-gate 122 and the length L3 of the recess 133 and the interval width L4 of the adjacent two recesses 133 have the following relationship: L2=(L3+L4)×Kb, and the value of Kb can be K14, where 30%≤K14≤60%. For example, the value of K14 can be 35%, 40%, 45%, 47%, 50%, 55%, 58%, or 60%, etc. In one example, 30%≤K14≤50%; in another example, 40%≤K14≤60%.

[0125] For example, refer to Figure 32 The two side surfaces of the shielding gate 130 in the Y direction are flush with the side surfaces of the first sub-gate in the Y direction. For example, refer to Figure 32 , Figure 33 and Figure 35 At least one end surface of the shielding gate 130 in the X direction is flush with the end surface of the first sub-gate in the X direction. In other examples, the side surfaces of the shielding gate in the Y direction can also not be flush with the side surfaces of the first sub-gate. The orthogonal projection of the shielding gate on the top surface of the first sub-gate can partially fall on the top surface of the first sub-gate.

[0126] For example, refer to Figures 36 to 39In the semiconductor device provided by the tenth embodiment of the present application, the trench 110 is provided with a control gate 120 and a shielding gate 130. The control gate 120 includes a first sub-gate 121 and a second sub-gate 122, which are the same as those in the ninth embodiment. The shielding gate 130 is provided with a recess 133. The bottom of the recess 133 is close to the top surface of the shielding gate 130, and the opening of the recess 133 faces the lower region 114 of the trench 110. Part of the second sub-gate 122 is embedded in the recess 133. The length direction of the recess 133 is the same as the length direction (X direction) of the trench 110. Different from the ninth embodiment, the recess 133 has an opening at at least one end in the length direction in the tenth embodiment, i.e., the recess 133 has one side wall or no side wall in the X direction. The recess 133 has an opening at at least one end in the length direction, which can facilitate the electrode lead-out at the end of the control gate 120.

[0127] Taking the case that the recess 133 penetrates the shielding gate 130 in the X direction, i.e., the recess 133 has openings at both ends in the X direction, the recess 133 has a bottom wall at the bottom and two side walls connected to the bottom wall, and the two side walls extend along the X direction and the Z direction. The two side walls of the recess 133 overlap the orthographic projection of the second sub-gate 122 on a second plane, and the second plane is perpendicular to the width direction (Y direction) of the trench. The orthographic projection of the second sub-gate 122 on the second plane overlaps the shielding gate 130.

[0128] In the present embodiment, one recess 133 and one second sub-gate 122 are provided in the same trench 110. The second sub-gate 122 is a long strip structure extending along the X direction. The shielding gate 130 is provided with a recess 133, so that the shielding gate 130 has sufficient facing area with the drain region 140, thereby ensuring the withstand voltage performance of the device. On this basis, the second sub-gate 122 is arranged in a long strip shape and embedded in the recess 133, so that the second sub-gate 122 has a large enough area. Then, the area of the control gate for forming the channel is increased, the area of the channel is increased, and the on-current of the channel is increased, thereby being able to greatly reduce the on-resistance of the device and improve the on-performance of the device.

[0129] Reference Figure 37 and 38, the maximum thickness of the shielding gate 130 along the thickness direction (Z direction) of the semiconductor substrate is denoted as H1, the thickness of the first sub-gate 121 along the Z direction is denoted as H3, and for example, H1≥H3, but it is not limited thereto, and H1 can also be less than H3, and the size therebetween can be set according to different voltage withstand requirements. The distance between the top surface of the first sub-gate 121 and the top surface of the shielding gate 130 is denoted as H2. The thickness of the second sub-gate 122 along the Z direction is denoted as H5, and H5

[0130] Reference is made to Figure 37 and Figure 38 , the thickness of the shielding gate 130 corresponding to the bottom of the groove 133 is denoted as H7, and the maximum thickness of the control gate 120 is the sum of the thicknesses of the first sub-gate 121 and the second sub-gate 122, denoted as H3+H5. The ratio K16 of H7:(H3+H5) ranges from 0.5 to 1 (not including 1), i.e., 0.5≤K16

[0131] Reference is made to Figure 38 , in the Y direction, the maximum width of the shielding gate 130 is denoted as W1, and the width of the first sub-gate 121 is denoted as W2, i.e., W1=W2. In the Y direction, the width of the second sub-gate 122 is denoted as W3, the thickness of the shielding gate corresponding to the single-side wall of the groove 133 in the Y direction is denoted as W4, and W3 and W4 can be set according to the specific process capability.

[0132] In the specific implementation process, the width of the shielding gate and the control gate can be reasonably determined according to the thickness of the dielectric layer on both sides of the shielding gate and the control gate along the Y direction and other factors. For example, in another example, reference is made to Figure 40W1>W2, i.e. the maximum width of the shield gate 130 is greater than the width of the first sub-gate 121.

[0133] Referring to Figure 39 In the X direction, the length of the second sub-gate 122 can be the same as the length of the shield gate 130. Both ends of the second sub-gate 122 in the X direction are flush with both ends of the shield gate 130 in the X direction; the side of the shield gate 130 in the Y direction is flush with the side of the first sub-gate in the Y direction. For example, referring to Figure 40 The side of the shield gate 130 in the Y direction is not flush with the side of the first sub-gate in the Y direction. In another example, referring to Figure 41 In the X direction, at least one end of the second sub-gate 122 can protrude beyond the corresponding end of the shield gate 130, such as Figure 41 In the X direction, at least one end of the second sub-gate 122 can protrude beyond the corresponding end of the shield gate 130, such as

[0134] In some embodiments, the present application provides a method for manufacturing a semiconductor device, comprising the following steps:

[0135] Step one, etching a plurality of trenches in a semiconductor substrate.

[0136] The semiconductor substrate can be a single crystal silicon substrate, a silicon carbide substrate, or an epitaxial layer formed on a semiconductor substrate, or a well region formed in a semiconductor substrate or an epitaxial layer.

[0137] Step two, forming a first dielectric layer on the inner wall of the trench.

[0138] The dielectric layer can be prepared by chemical vapor deposition or thermal oxidation process, and the dielectric layer covers the inner wall of the trench. The dielectric layer outside the trench can be removed by etching, and only the dielectric layer on the inner wall of the trench is reserved.

[0139] Step three, forming a control gate in the trench.

[0140] The control gate includes a first sub-gate and a second sub-gate connected to each other, the first sub-gate is located in the lower region of the trench, and the second sub-gate is located in the upper region of the trench; in the upper region and the lower region, the upper region is close to the slot of the trench, and the lower region is close to the slot bottom of the trench.

[0141] The control gate can be doped polysilicon, or other materials that can be used as a gate. For example, the control gate can be obtained by filling the trench with doped polysilicon and then etching. Specifically, after filling the trench with doped polysilicon, the first patterning process is used to remove the doped polysilicon outside the trench, so that the top surface of the remaining doped polysilicon in the trench does not exceed the slot of the trench. Then, the second patterning process is used to etch the doped polysilicon in the trench to partially remove the doped polysilicon in the upper region. In this way, the doped polysilicon in the lower region of the trench is the first sub-gate, and the remaining doped polysilicon in the upper region of the trench is the second sub-gate.

[0142] Step four, forming a second dielectric layer in the trench.

[0143] The second dielectric layer can also be prepared by a chemical vapor deposition process and patterned according to the required pattern, especially the structure of the shielding gate. According to the relative position relationship between the first sub-gate and the second sub-gate, the coverage area of the second dielectric layer is also different. For example, in one embodiment, the second dielectric layer covers at least part of the top surface of the first sub-gate and the side surface of the second sub-gate; according to different embodiments, the second dielectric layer covers part of the top surface of the first sub-gate. The material of the second dielectric layer can be the same as or different from the material of the first dielectric layer.

[0144] Step five, forming a shielding gate in the trench.

[0145] The shielding gate is located in the upper region of the trench, and the projection of the second sub-gate on the sidewall of the trench and the projection of the shielding gate on the sidewall of the trench at least partially overlap in the length direction and / or the width direction of the trench.

[0146] The material of the shielding gate can be doped polysilicon, or other materials that can be used as a gate. For example, in the specific implementation process, the trench can be filled with doped polysilicon first, and then the doped polysilicon can be etched. According to the specific shape of the shielding gate, the shielding gate can be etched accordingly.

[0147] Step six, forming a third dielectric layer covering the top surface of the shielding gate and the top surface of the second sub-gate in the trench.

[0148] According to different device structures, at least part of the third dielectric layer is arranged in the trench when the top surfaces of the shielding gate and the second sub-gate are lower than the slot of the trench. When the top surfaces of the shielding gate and the second sub-gate are flush with the slot of the trench, the third dielectric layer is arranged outside the trench.

[0149] For example, the third dielectric layer can be the same as or different from the materials of the first dielectric layer and the second dielectric layer.

[0150] Step seven, forming a drain region between the adjacent trenches.

[0151] Specifically, the drain region can be formed in the semiconductor substrate by ion implantation. The doping type of the drain region is opposite to the doping type of the semiconductor substrate. For example, if the semiconductor substrate is P-type doped, the doping type of the drain region can be N-type.

[0152] Step eight, forming a lead region in the drain region.

[0153] For example, referring to Figure 6 , the lead region 141 is located in the area of the drain region 140 close to the top surface 112 of the semiconductor substrate. The doping type of the lead region 141 is consistent with the doping type of the drain region 140, and the doping concentration of the lead region 141 is greater than the doping concentration of the drain region 140.

[0154] Step nine, forming a through hole (via hole) in the dielectric layer on the top surface of the semiconductor substrate, the through hole penetrating the dielectric layer.

[0155] The through hole penetrates the dielectric layer covering the lead region. For example, the through hole can penetrate the third dielectric layer, or the stack of the third dielectric layer and the fourth dielectric layer. For the case of the fourth dielectric layer, the process of forming the fourth dielectric layer is also included in step nine. In addition, the order of step eight and step nine can be adjusted, that is, the through hole is formed first, and then ion implantation is performed with the dielectric layer as a mask, thereby forming the lead region.

[0156] Step ten, forming an electrode layer on the dielectric layer, the electrode layer passing through the through hole and electrically connected with the lead region, the shielding gate and the control gate.

[0157] For example, referring to Figure 6 and Figure 7 , the top surface of the semiconductor substrate 100 can be provided with an electrode layer 150. The electrode layer can include a first electrode to a fourth electrode, wherein the first electrode 151 and the second electrode 152 are respectively used to connect the lead regions 141 on both sides of the trench 110. In the case that the first electrode 151 is used as an input terminal, the second electrode 152 can be used as an output terminal; in the case that the second electrode 152 is used as an input terminal, the first electrode 151 can be used as an output terminal. The third electrode is used to electrically connect with the shielding gate, and the fourth electrode is used to electrically connect with the control gate. Of course, according to the shape and number of the shielding gate and the actual product demand, the position and number of the third electrode are also different; the same is true for the fourth electrode.

[0158] For example, the electrode layer can be a single metal layer or a multi-layer stacked metal layer. The material of the electrode layer can be titanium and titanium nitride, aluminum copper, aluminum silicon copper or aluminum silicon.

[0159] The above examples are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they understand the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application. Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and changes of the present application belong to the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and changes.

Claims

1. A semiconductor device, characterized by, The semiconductor substrate includes a plurality of trenches, the arrangement direction of the plurality of trenches is parallel to the width direction of the trenches, the trenches extend along the length direction of the trenches, the width direction of the trenches is perpendicular to the length direction of the trenches, and both the width direction and the length direction are perpendicular to the thickness direction of the semiconductor substrate; The trenches are provided with a control gate and a shielding gate, the control gate includes a first sub-gate and a second sub-gate connected to each other, the first sub-gate is located in a lower region of the trench, and the shielding gate and the second sub-gate are both located in an upper region of the trench; The upper region is close to the notch of the trench, and the lower region is close to the bottom of the trench; The second sub-gate and the shielding gate overlap in the projection on a first plane and / or a second plane, the first plane is perpendicular to the length direction of the trench, and the second plane is perpendicular to the width direction of the trench; The inner wall of the trench, the control gate, the shielding gate, the top surface of the second sub-gate, and the top surface of the shielding gate are all provided with a dielectric layer; Between two adjacent trenches, a drain region is provided, the drain region extends from the top surface of the semiconductor substrate into the semiconductor substrate, and the doping type of the drain region is opposite to the doping type of the semiconductor substrate.

2. The semiconductor device of claim 1, wherein In the same trench, the second sub-gate and the shielding gate are arranged in the width direction of the trench; in the plurality of trenches, the second sub-gate and the shielding gate are alternately arranged along the width direction of the trench; In the depth direction of the trench, the first sub-gate has oppositely arranged top and bottom surfaces, the top surface of the first sub-gate faces the notch of the trench, the orthographic projection of the second sub-gate on the plane where the top surface of the first sub-gate is located at least partially falls into the top surface of the first sub-gate, and the orthographic projection of the shielding gate on the plane where the top surface of the first sub-gate is located at least partially falls into the top surface of the first sub-gate.

3. The semiconductor device of claim 2, wherein, In the same trench, one second sub-gate and one shielding gate are provided, the length of the second sub-gate and the length of the shielding gate both extend along the length direction of the trench.

4. The semiconductor device according to claim 2 or 3, characterized by In the same trench, the second sub-gate includes a first structure part and a plurality of second structure parts connected to each other, the first structure part and the shielding gate are arranged in the width direction of the trench, and the plurality of second structure parts and the shielding gate are arranged in the length direction of the trench.

5. The semiconductor device of claim 4, wherein, In the same trench, a plurality of shielding gates are provided, the length of the first structure part extends along the length direction of the trench, the plurality of second structure parts and the plurality of shielding gates are alternately arranged in the length direction of the trench. In the plurality of trenches, the first structure part and the shielding gate are alternately arranged in the width direction of the trench.

6. The semiconductor device of claim 1, wherein In the same trench, the number of the second sub-gate and the number of the shielding gate are both plural, the plurality of second sub-gates and the plurality of shielding gates are alternately arranged in the length direction of the trench.

7. The semiconductor device according to claim 5 or 6, wherein In the same trench, along the length direction of the trench, the interval distance L1 between two adjacent second sub-gates and the length L2 of the second sub-gate satisfy the following relationship: L1 = (L1 + L2) x Ka, where Ka is in the range of 40% to 60%.

8. The semiconductor device of any one of claims 1 to 7, wherein at least one side surface of the second sub-gate is flush with at least one side surface of the first sub-gate; and / or, at least one side surface of the shielding gate is flush with at least one side surface of the first sub-gate; and / or, a top surface of the second sub-gate is flush with a top surface of the shielding gate; and / or, neither the top surface of the second sub-gate nor the top surface of the shielding gate exceeds a lip of the trench; wherein the side surface is a side surface extending in a depth direction of the trench.

9. The semiconductor device of claim 1, wherein, the shielding gate is provided with a recess, a lip of the recess faces a lower region of the trench, and part of the second sub-gate is embedded in the recess.

10. The semiconductor device of claim 9, wherein, in the same trench, the number of the recesses is one, and the number of the second sub-gates is one; alternatively, in the same trench, the number of the recesses is one, and the number of the second sub-gates is multiple, and the multiple second sub-gates are arranged at intervals along a length direction of the trench; alternatively, in the same trench, the number of the recesses is multiple, and the number of the second sub-gates is multiple, and part of at least one second sub-gate is embedded in one recess.

11. The semiconductor device of claim 9, wherein, the recess has an opening at at least one end thereof along the length direction of the trench; or the recess has an opening at at least one end thereof along a width direction of the trench.

12. The semiconductor device of claim 9, wherein, a ratio of a thickness of the second sub-gate embedded in the recess to a thickness of the second sub-gate along a thickness direction of the semiconductor substrate is in the range of 30% to 90%.

13. The semiconductor device according to any one of claims 9, 10, and 12, wherein in the same trench, the number of the recesses and the number of the second sub-gates are both multiple, and part of one second sub-gate is embedded in one recess; wherein: a ratio of a thickness of the shielding gate at a bottom of the recess to a maximum thickness of the control gate is in the range of 0.5 to 1; and / or, in the length direction of the trench, a length L3 of the recess, a spacing width L4 between two adjacent recesses, and a length L2 of the second sub-gate satisfy the following relationship: L2 = (L3 + L4) x Kb, where 30% ≤ Kb ≤ 60%.

14. The semiconductor device of any one of claims 9 to 13, wherein at least one side surface of the second sub-gate is flush with at least one side surface of the first sub-gate; and / or, at least one side surface of the shielding gate is flush with at least one side surface of the first sub-gate; and / or, in a case where the length direction of the recess is the same as the width direction of the trench, at least one side surface of the shielding gate is flush with at least one side surface of the second sub-gate; wherein the side surface is a side surface extending in a depth direction of the trench.

15. The semiconductor device of any one of claims 1 to 14, wherein The drain region extends from a top surface of the semiconductor substrate into the semiconductor substrate by a distance greater than a distance between a bottom surface of the shield gate and the top surface of the semiconductor substrate and less than a distance between a bottom surface of the first sub-gate and the top surface of the semiconductor substrate in a thickness direction of the semiconductor substrate.

16. The semiconductor device according to claim 15, wherein a lead region as a contact region is provided in the drain region, a doping type of the lead region is identical to a doping type of the drain region, and a doping concentration of the lead region is greater than a doping concentration of the drain region; the lead region extends from a top surface of the drain region into the drain region to not more than a top surface of the shield gate.

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