Gate structure device, chip and related equipment
By setting a low-resistivity metal layer on the sidewall of the gate structure, the problem of high resistivity of high dielectric constant metal gates is solved, thereby improving the transistor turn-on speed and performance.
Patent Information
- Application Number
- CN202410744464.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-12-16
AI Technical Summary
In the prior art, the work function of metal gates with high dielectric constants has a high resistivity, resulting in a large resistance of the metal gate, which in turn slows down the turn-on speed of the transistor and fails to meet the performance requirements of the device.
A first metal layer is disposed on the sidewalls at both ends of the extension direction of the gate. The metal layer is formed of a material with a resistivity lower than that of a metal with a work function and covers part or all of the sidewall area. A second metal layer is combined to further reduce the overall gate resistance.
By reducing the overall gate resistance, the device's turn-on speed and power consumption performance are improved, while maintaining the threshold voltage control capability, thus enhancing the overall performance of the device.
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Figure CN121152283A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a gate structure device, a chip and related equipment. BACKGROUND
[0002] In a Metal-Oxide-Semiconductor (MOS) field effect transistor, the threshold voltage corresponding to the gate and the opening speed thereof are one of the most important parameters for measuring the performance of a transistor.
[0003] With the development of technology, the size of the transistor is continuously reduced. In order to meet the demand, a High K metal gate process is widely used in current advanced semiconductor processes. In the process, the gate dielectric formed by the high dielectric constant material can adjust the effective work function of the work function metal (WF metal) in the metal gate, so as to achieve the purpose of adjusting the threshold voltage. However, the resistivity of the current work function metal is generally high, which will cause the resistance of the metal gate to be large, and thus the opening speed of the transistor will be slow, which cannot meet the demand of the device.
[0004] Therefore, how to reduce the resistance corresponding to the metal gate and improve the opening speed of the gate structure device is a technical problem to be solved. SUMMARY
[0005] The embodiments of the present application provide a gate structure device, a chip and related equipment, which can reduce the resistance corresponding to the metal gate and improve the opening speed of the gate structure device.
[0006] In a first aspect, the embodiments of the present application provide a gate structure device, comprising: a substrate, and a gate and a semiconductor structure arranged on the substrate, and the gate covers the surface of the semiconductor structure away from the substrate and the sidewall of the semiconductor structure at both ends in a first direction, the first direction being the extension direction of the gate; the gate comprises a work function metal layer; a part or all of the area of the sidewall of at least one end of the gate in the first direction is covered with a first metal layer, and the first metal layer contacts the work function metal layer; wherein the resistivity of the material forming the first metal layer is lower than the resistivity of the material forming the work function metal layer.
[0007] Compared to existing technologies where the gate is often made of a work function metal with high resistivity, resulting in high gate resistance and slower transistor turn-on speed, which fails to meet device requirements, this application provides a gate structure device. This device has a first metal layer disposed on the sidewall at at least one end of the gate's extension direction (i.e., the first direction). This first metal layer is connected to the work function metal and covers part or all of the sidewall area. The first metal layer is formed of a metal material with a resistivity lower than that of the work function metal, i.e., a low-resistivity metal layer is formed on the sidewalls at both ends of the gate. This structure ensures the device's gate control capability while reducing the overall gate resistance, thereby improving the device's turn-on speed and ultimately enhancing the overall device's energy efficiency.
[0008] In one possible implementation, the semiconductor structure extends along a second direction, the first direction and the second direction being perpendicular to each other and parallel to the substrate; the semiconductor structure is a fin structure or at least one nanosheet stacked on the substrate.
[0009] In the embodiments of this application, the gate structure device can be applied in transistors formed by fin structures or transistors formed by nanosheets, thereby reducing resistance and improving the turn-on speed of the gate structure device.
[0010] In one possible implementation, the thickness of the first metal layer in the first direction is greater than or equal to 1 nanometer and less than or equal to 10 nanometers.
[0011] In this embodiment, the thickness of the first metal layer is between 1 and 10 nanometers. A thinner first metal layer can reduce the overall resistance of the metal gate without affecting the threshold voltage regulation of the work function metal, thereby improving the corresponding turn-on speed of the device.
[0012] In one possible implementation, the width of the first metal layer in the second direction is less than or equal to the width of the gate in the second direction.
[0013] In this embodiment, the first metal layer may cover only part or all of the regions at both ends of the gate, and the width of the first metal layer in the first direction may be less than or equal to the width of the gate in the first direction. For example, the first metal layer may cover only the region where the work function metal is located, or it may cover the region including the region where the high dielectric constant gate dielectric layer is located. The larger the area of the first metal layer, the lower the overall resistance of the gate.
[0014] In one possible implementation, the material forming the first metal layer includes at least one of the following: tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo).
[0015] In this embodiment, the material of the first metal layer includes at least one of the following: tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). These metal materials have lower resistivity compared to work function metals, allowing the addition of the first metal layer to at least one sidewall of the gate to reduce the overall resistance of the gate, thereby increasing the device's turn-on speed, while maintaining the gate's threshold voltage, thus significantly improving device performance.
[0016] In one possible implementation, a second metal layer is coated on the surface of the gate on the side away from the substrate, and the second metal layer is connected to the work function metal layer; the resistivity of the material forming the second metal layer is lower than the resistivity of the material forming the work function metal layer.
[0017] In this embodiment, in order to further reduce the overall resistance of the gate, a second metal layer can be provided on the upper surface of the gate. The second metal layer is also formed of a material with a resistivity lower than that of the work function metal layer. The turn-on speed of the device with both the first metal layer and the second metal layer will be further improved, resulting in good device performance.
[0018] In one possible implementation, the material forming the first metal layer may be the same as or different from the material forming the second metal layer.
[0019] In the embodiments of this application, the materials used to form the first metal layer and the second metal layer can be different or the same. Using the same material for both the first and second metal layers facilitates fabrication and reduces processing complexity. Furthermore, different materials can be selected for the first and second metal layers to meet different requirements, resulting in better device performance.
[0020] In one possible implementation, the material forming the work function metal layer includes at least one of the following: titanium (Ti), tantalum (Ta), or tungsten (W).
[0021] In the embodiments of this application, the work function metal layer can be made of at least one of titanium (Ti), tantalum (Ta), or tungsten (W), or any one or more of the above compounds. Different work function metal materials can be adapted to various application scenarios, and their higher work function allows for better control of the gate threshold voltage, avoiding gate leakage and ensuring good device performance.
[0022] In a second aspect, embodiments of this application provide a method for fabricating a gate structure device. The method includes: forming at least one semiconductor structure extending along a second direction and at least one gate extending along a first direction on a substrate surface; wherein each gate covers a surface of the at least one semiconductor structure away from the substrate and sidewalls at both ends of the semiconductor structure in the first direction, the first direction and the second direction being perpendicular to each other and parallel to the substrate; etching along the second direction on the surface of each gate located between adjacent semiconductor structures to form at least one first opening, and forming a barrier layer at each first opening; wherein the projection of each first opening on the substrate is located between adjacent semiconductor structures; etching along the second direction on the surface of each gate and at least one end adjacent to each barrier layer to form at least one second opening, and forming a first metal layer at each second opening; wherein the second opening exposes an active function metal layer along one sidewall of the first direction, and exposes the barrier layer on the other sidewall.
[0023] In one possible implementation, the resistivity of the material forming the first metal layer is lower than the resistivity of the material forming the work function metal layer.
[0024] In one possible implementation, the height of the barrier layer in the direction perpendicular to the substrate is greater than the height of the corresponding gate in the direction perpendicular to the substrate, and the width of the barrier layer in the second direction is greater than the width of the corresponding gate in the second direction; the width of the first metal layer in the second direction is less than or equal to the width of the gate in the second direction.
[0025] In one possible implementation, etching along the second direction on the surface of each of the gates and at least one end adjacent to each of the barrier layers to form at least one second opening, and fabricating a first metal layer at each second opening, comprises: etching along the second direction on the surface of each of the gates and at least one end adjacent to each of the barrier layers to form at least one second opening; etching on the surface of each of the gates above the semiconductor structure to form at least one third opening; fabricating a first metal layer at each second opening; and fabricating a second metal layer at each third opening; wherein the bottom of the third opening exposes an active function metal layer.
[0026] In one possible implementation, the resistivity of the material forming the second metal layer is lower than the resistivity of the material forming the work function metal layer; the material forming the first metal layer may be the same as or different from the material forming the second metal layer.
[0027] In one possible implementation, the semiconductor structure is a fin structure or at least one nanosheet stacked on the substrate.
[0028] Thirdly, embodiments of this application provide a semiconductor device, including a substrate and the gate structure device provided in the first aspect disposed on the substrate.
[0029] Fourthly, embodiments of this application provide a chip, including a circuit and the gate structure device provided in the first aspect applied to the circuit.
[0030] Fifthly, embodiments of this application provide an electronic device, including a circuit board and a gate structure device as described in the first aspect or a chip as described in the second aspect, applied to the circuit board.
[0031] It should be understood that the method for fabricating the gate structure device provided in the second aspect of this application, the semiconductor device provided in the third aspect, the chip provided in the fourth aspect, and the electronic device provided in the fifth aspect are consistent with the technical solutions of the first aspect of this application. Their specific contents and beneficial effects can be referred to the gate structure device provided in the first aspect above, and will not be repeated here. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.
[0033] Figure 1 These are schematic diagrams of gate structures in several prior art technologies provided in the embodiments of this application.
[0034] Figure 2 This is a schematic diagram of a gate structure device provided in an embodiment of this application.
[0035] Figure 3 and Figure 4 These are schematic diagrams of several gate structure devices provided in the embodiments of this application.
[0036] Figure 5 This is a schematic diagram of another gate structure device provided in the embodiments of this application.
[0037] Figure 6 This is a schematic diagram of another gate structure device provided in the embodiments of this application.
[0038] Figure 7 A flowchart illustrating the steps of a method for fabricating a gate structure device according to an embodiment of this application.
[0039] Figures 8-12 This is a set of schematic diagrams illustrating the fabrication of gate structure devices provided in the embodiments of this application. Detailed Implementation
[0040] The embodiments of this application will now be described with reference to the accompanying drawings.
[0041] The terms "first," "second," and "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0042] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0043] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0044] For ease of description, embodiments of this application may use spatial relation terms such as "below," "below," "lower than," "below," "above," "upper," etc., to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings. For example, if the device in the drawings is flipped, the orientation of an element described as "below," "below," or "below" other elements or features will change to "above" said other elements or features. Thus, the exemplary terms "below" and "below" can encompass both up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between.
[0045] First, to facilitate understanding of the embodiments of this application, the following detailed analysis addresses the technical problems to be solved and the applicable application scenarios of the embodiments of this application.
[0046] In metal-oxide-semiconductor (MOS) field-effect transistors, the threshold voltage of the gate and its turn-on speed are among the most important parameters for evaluating transistor performance. With technological advancements, transistor dimensions continue to shrink. To meet these demands, high-k metal gate (HKMG) technology is widely used in advanced semiconductor processes. In this process, the gate dielectric formed by the high-k metal can adjust the effective work function of the work function metal (WF metal) in the gate, thereby regulating the threshold voltage.
[0047] Due to structural differences, several different gate structures are provided in the prior art, for example, please refer to the appendix. Figure 1 , Figure 1 These are schematic diagrams of gate structures in several prior art technologies provided in the embodiments of this application. For example... Figure 1As shown, the gates in gate structures-1 and-2 are metal gates formed by a work function metal layer. A high-dielectric-constant dielectric layer, i.e., an HK layer, is also disposed between the metal gate and the semiconductor structure or substrate. This technique, which uses HK dielectric material to replace silicon oxynitride (SiON) and a metal gate to replace the polysilicon gate, is called HKMG process technology. This HKMG process technology can solve the problems of polysilicon depletion and gate leakage. However, the resistivity of the work function metal used to form the metal gate in the HKMG process technology is generally high; therefore, the resistance of the formed metal gate is relatively high. The higher the gate resistance of this type of gate structure device, the slower the gate structure reaches the threshold voltage, i.e., the slower the device turns on, failing to meet the device's performance requirements.
[0048] To address this issue, this application provides a gate structure device with low resistance. The device has a first metal layer disposed on the sidewall at at least one end of the gate's extension direction (i.e., the first direction). This first metal layer is connected to the work function metal and covers part or all of the sidewall area. Since the first metal layer is formed of a material with a resistivity lower than the work function metal, forming a low-resistance metal layer on the sidewalls at both ends of the gate reduces the overall resistance of the gate, thereby increasing the turn-on speed of the gate structure device and improving the overall energy efficiency of the device. These gate structure devices can be applied to various field-effect transistors, semiconductor devices, chips, or electronic devices. The specific structure of this gate structure device can be referred to the relevant descriptions in the following embodiments, which will not be repeated here.
[0049] Secondly, based on the technical problems mentioned above, and in order to facilitate understanding of the embodiments of this application, several gate structure devices on which the embodiments of this application are based will be described below.
[0050] This application provides a gate structure device, which includes: a substrate, and a gate and a semiconductor structure disposed on the substrate, wherein the gate covers the surface of the semiconductor structure away from the substrate and the sidewalls at both ends of the semiconductor structure in a first direction, wherein the first direction is the extension direction of the gate; the gate includes a work function metal layer; a first metal layer covers a portion or all of the sidewalls at at least one end of the gate in the first direction, and the first metal layer contacts the work function metal layer; wherein the resistivity of the material forming the first metal layer is lower than the resistivity of the material forming the work function metal layer.
[0051] Please refer to the attached document. Figure 2 , Figure 2 This is a schematic diagram of a gate structure device provided in an embodiment of this application.
[0052] like Figure 2 As shown in the front view of the gate structure device, the gate structure device includes: a substrate 10, and a gate 20 and a semiconductor structure 30 disposed on the substrate 10, wherein the gate 20 covers the surface of the semiconductor structure 30 away from the substrate 10 and the sidewalls of the semiconductor structure 30 at both ends in a first direction. That is, as Figure 2 As shown in the top view of the gate structure device, the gate 20 extends along a first direction, the semiconductor structure 30 extends along a second direction, and the gate 20 vertically covers a portion of the upper surface and the sidewalls at both ends of the semiconductor structure 30.
[0053] It should be noted that in the embodiments of this application and the following related embodiments, the extension direction of the gate 20 is taken as the first direction, that is, as... Figure 2 The X-axis direction shown is the front-to-back direction parallel to the surface of substrate 10. The direction parallel to the surface of substrate 10 and perpendicular to the first direction is the second direction, i.e., as shown... Figure 2 The Y-axis direction shown is the left-right direction parallel to the surface of substrate 10. The direction perpendicular to the surface of substrate 10 is the third direction, i.e., as shown... Figure 2 The Z-axis direction is shown. The first, second, and third directions are all perpendicular to each other.
[0054] Among them, such as Figure 2 As shown in the cross-sectional view of the gate structure device, the gate 20 may include a work function metal layer 201. A high dielectric constant layer, i.e., an HK layer, may also be included around the work function metal layer 201 (e.g., in the contact area with the semiconductor structure 30). The work function metal layer 201 and the HK layer can form an HKMG structure, which can prevent leakage current in the gate structure. A first metal layer 202 covers a portion or all of the sidewall of at least one end of the gate 20 in the first direction. The first metal layer 202 is formed of a metal material with a resistivity lower than that of the work function metal, and the first metal layer 202 contacts the work function metal layer 201. That is, the device has a first metal layer with a resistivity lower than that of the work function metal layer on the sidewall of at least one end in the extension direction (i.e., the first direction). The first metal layer 202 is connected to the work function metal layer 201, and the first metal layer 202 covers a portion or all of the sidewall area. This type of gate structure device, which forms a low-resistivity metal layer on the sidewall of at least one end of the gate, can ensure the gate control capability of the device and reduce the overall resistance of the gate, thereby improving the turn-on speed of the device and thus improving the overall energy consumption performance of the device.
[0055] In some embodiments, the material forming the work function metal layer includes at least one of the following: titanium (Ti), tantalum (Ta), or tungsten (W). It is understood that the material of the work function metal layer can be at least one of titanium (Ti), tantalum (Ta), or tungsten (W), or it can be any one or more of the above compounds. A higher work function allows for better control of the gate's threshold voltage, ensuring good device performance.
[0056] In some embodiments, the material forming the first metal layer includes at least one of the following: tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). It is understood that the resistivity of the material forming the first metal layer needs to be lower than the resistivity of the material forming the work function metal layer. Therefore, after the material of the work function metal layer 201 is determined, different materials can be selected to form the first metal layer 202 according to different requirements. For example, the material forming the first metal layer 202 includes at least one of the following: tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo), and may also be any one or more of the above compounds. These metal materials not only have low resistivity but also correspond to good work functions, so that adding the first metal layer can reduce the overall resistance of the gate, improve the corresponding turn-on speed of the device, and not affect the threshold voltage corresponding to the gate, greatly improving the performance of the device.
[0057] Furthermore, it should be noted that when a first metal layer is provided on both sidewalls of the gate, the materials of the first metal layers on the two sidewalls can be the same or different, and this application embodiment does not specifically limit this. For example, the material of the first metal layer on one sidewall of the gate can be tungsten (W), and the material of the first metal layer on the other sidewall of the gate can be cobalt (Co). For instance, the material of the first metal layer on both sidewalls of the gate can be tungsten (W).
[0058] The above Figure 2 In the gate structure device shown, the first metal layer 202 can cover the entire area of both end sidewalls. In other embodiments, the first metal layer 202 can also cover a portion of at least one end sidewall of the gate 20. This application does not impose specific limitations on this aspect.
[0059] Taking the area where the first metal layer 202 covers one sidewall of the gate 20 as an example, please refer to the appendix. Figure 3 -Appendix Figure 4 , Figure 3 and Figure 4 These are schematic diagrams of several gate structure devices provided in the embodiments of this application.
[0060] like Figure 3As shown, a portion of one sidewall of the gate 20 in the first direction (i.e., the X-axis direction) is covered by a first metal layer 202, wherein the first metal layer 202 covers the work function metal layer 201, and the HK layer is not covered. The width K1 of the first metal layer 202 in the second direction is the same as the width K2 of the work function metal layer 201 in the second direction, that is, the width K1 of the first metal layer 202 in the second direction is smaller than the width K3 of the gate 20 in the second direction. The height G1 of the first metal layer 202 in the third direction (i.e., the direction perpendicular to the surface of the substrate 10) is smaller than the height G2 of the gate 20 in the third direction.
[0061] like Figure 4 As shown, the first metal layer 202 covers a portion of the work function metal layer 201 and the HK layer on one sidewall of the gate 20. The width K1 of the first metal layer 202 in the second direction is greater than the width K2 of the work function metal layer 201 in the second direction, and the width K1 of the first metal layer 202 in the second direction is equal to the width K3 of the gate 20 in the second direction. The height G1 of the first metal layer 202 in the third direction (i.e., the direction perpendicular to the surface of the substrate 10) is less than the height G2 of the gate 20 in the third direction.
[0062] Therefore, it can be understood that the width K1 of the first metal layer 202 in the second direction can be less than or equal to the width K2 of the gate 20 in the second direction, and the height G1 of the first metal layer 202 in the third direction can be less than or equal to the height G2 of the gate 20 in the third direction, so that the first metal layer 202 can cover part or all of the area of at least one sidewall of the gate 20. The larger the area covered by the first metal layer 202, the lower the overall resistance of the gate 20 and the faster the turn-on speed of the device.
[0063] It should be noted that in some other embodiments, when a first metal layer is provided on both ends of the gate, the size of the area covered by the first metal layer on both ends of the gate may be the same or different. This application does not make specific limitations on this.
[0064] For example, the first metal layer on one sidewall of the gate can cover the entire area of the sidewall, while the first metal layer on the other sidewall of the gate can cover a portion of the sidewall. For instance, the first metal layer on one sidewall of the gate can cover the area described above. Figure 3 The first metal layer on the other sidewall of the gate can cover a portion of the sidewall as described above. Figure 4 The area shown is a portion of the sidewall.
[0065] In some embodiments, in the first direction described above, the thickness of the first metal layer is greater than or equal to 1 nanometer and less than or equal to 10 nanometers. As described above. Figure 4 As shown, the thickness H1 of the first metal layer is between 1 and 10 nanometers. The thinner first metal layer can reduce the overall resistance of the metal gate without affecting the threshold voltage regulation of the work function metal, thereby improving the corresponding turn-on speed of the device.
[0066] In some embodiments, a second metal layer is further covered on the surface of the gate on the side away from the substrate, and the second metal layer is connected to the work function metal layer; the resistivity of the material forming the second metal layer is lower than the resistivity of the material forming the work function metal layer.
[0067] Please refer to the attached document. Figure 5 , Figure 5 This is a schematic diagram of another gate structure device provided in an embodiment of this application. For example... Figure 5 As shown, a second metal layer 203 is also covered on the upper surface of the gate 20 (i.e., the surface away from the substrate), and the second metal layer 203 is also connected to the work function metal layer; wherein, the resistivity of the material forming the second metal layer 203 is lower than the resistivity of the material forming the work function metal layer 201. Therefore, the turn-on speed of the gate structure device with both the first metal layer 202 and the second metal layer 203 is further improved, resulting in good device performance.
[0068] It is understood that, in the aforementioned third direction, the thickness of the second metal layer is greater than or equal to 1 nanometer and less than or equal to 10 nanometers. As described above... Figure 5 As shown, the thickness of the second metal layer 203 can also be between 1 and 10 nanometers. This application does not impose a specific limitation on this aspect.
[0069] It should be noted that the length of the second metal layer in the first direction may be less than or equal to the length of the gate in the first direction; and the width of the second metal layer in the second direction may be less than or equal to the width of the gate in the second direction.
[0070] In other embodiments, the material forming the first metal layer may be the same as or different from the material forming the second metal layer. The material forming the second metal layer may also include at least one of the following: tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). For example, the material forming the first metal layer and the material forming the second metal layer may be the same; for example, the first and second metal layers can be formed together using tungsten. It is understood that using the same material for the first and second metal layers facilitates fabrication and reduces process complexity. The material forming the first metal layer and the material forming the second metal layer may also be different; that is, the first and second metal layers may be fabricated using different materials according to different needs, to adapt to different fabrication processes and application scenarios, thereby improving transistor performance. This application does not impose specific limitations on this aspect.
[0071] In some embodiments, the semiconductor structure extends along a second direction, and the first direction and the second direction are perpendicular to each other and parallel to the substrate; the semiconductor structure is a fin structure or at least one nanosheet stacked on the substrate.
[0072] As mentioned above Figures 2-5 The gate structure device shown can be a fin structure, which can be adapted to a transistor formed by a fin structure. Alternatively, the semiconductor structure can be at least one nanosheet stacked parallel to each other on the substrate, which can be adapted to a transistor formed by a nanosheet.
[0073] Please refer to the attached document. Figure 6 , Figure 6 This is a schematic diagram of another gate structure device provided in an embodiment of this application. For example... Figure 6 As shown, the semiconductor structure can be composed of three parallel nanosheets 301 extending along the second direction. Due to their high aspect ratio, the nanosheets make it easier to turn the gate structure device on or off. In other words, they can work with the first metal layer to reduce the gate resistance and further improve the gate turn-on speed.
[0074] In other embodiments, as described above Figure 2 As shown, a virtual gate 50 is also provided between the gate 20 and the substrate 10, which is not shown in the top view. The virtual gate 50 can extend along the second direction to fill the gaps between adjacent semiconductors, and can thus be used to support the gate 20.
[0075] In other embodiments, the gap between any two adjacent gate structures is further filled with an insulating medium for insulating the supporting gate.
[0076] Secondly, the embodiments of this application provide a method for fabricating gate structure devices, which can be used to fabricate multiple gate structure devices.
[0077] Please refer to Figures 7-12 , Figure 7 This is a flowchart illustrating the steps of a method for fabricating a gate structure device according to an embodiment of this application. Figures 8-12 This is a set of schematic diagrams illustrating the fabrication of gate structure devices provided in the embodiments of this application.
[0078] like Figure 7 As shown, the preparation method includes:
[0079] Step S1: At least one semiconductor structure extending along a second direction and at least one gate extending along a first direction are formed on the substrate surface.
[0080] Specifically, such as Figure 8 As shown, at least one semiconductor structure 30 extending in a second direction and parallel to each other, and at least one gate 20 extending in a first direction and parallel to each other, can be formed on the surface of the substrate 10. The first direction and the second direction are perpendicular to each other and parallel to the substrate. The strip gate 20 covers the surface of the semiconductor structure away from the substrate and the sidewalls at both ends of the semiconductor structure in the first direction. The gate is perpendicular to the semiconductor structure and covers the surface of the semiconductor structure away from the substrate and the sidewalls at both ends of the semiconductor structure in the first direction. Furthermore, when there are multiple semiconductor structures or gates, the multiple semiconductor structures are parallel to each other, and the multiple gates are also parallel to each other.
[0081] Optionally, a dummy gate 50 is also filled between the multiple parallel semiconductor structures 30. In addition, the semiconductor structure 30 may be a fin structure or at least one nanosheet stacked parallel to each other on the substrate; the strip gate 20 may be an HKMG composed of a work function metal layer and a high dielectric constant dielectric layer.
[0082] In addition, such as Figure 9 As shown, the spaces between the multiple parallel gates 20 are filled with an insulating dielectric. That is, compared to the above... Figure 8 In the gate structure device shown in this embodiment, the gaps between multiple parallel gates 20 on the surface of the virtual gate 50 away from the substrate 10 are further filled with an insulating dielectric layer 60. This insulating dielectric layer 60 can be used to support and insulate the multiple parallel gates 20. It should be noted that the material of the insulating dielectric layer 60 is not specifically limited in this embodiment.
[0083] Optionally, the substrate material includes one of bulk silicon, SOI, germanium, germanium silicon, gallium nitride, and indium gallium arsenide. Different substrate materials can be fabricated using different methods to form semiconductor structures, and this application does not impose specific limitations on this.
[0084] Optionally, the semiconductor structure can be a fin structure or at least one nanosheet stacked on the substrate.
[0085] In step S2, along the second direction, etching is performed on the surface of each gate located between adjacent semiconductor structures to form at least one first opening, and a barrier layer is formed at each first opening.
[0086] Specifically, a metal gate cut process is used to separate adjacent gate structures. For example... Figure 10 As shown, along the second direction, etching is performed on the upper surface of the gate 20 and the insulating dielectric layer 60 located between multiple semiconductor structures until the bottom of the virtual gate 50 is exposed to form a first opening. A barrier layer 40 is then formed within the region of the first opening using an insulating material. This barrier layer 40 can be used to completely block the strip-shaped gate 20, thereby separating and forming multiple independent gates 20 to create multiple gate structure devices. The height of the first opening in the direction perpendicular to the substrate is greater than the height of the gate in the direction perpendicular to the substrate, and the width of the first opening in the second direction is greater than the width of the gate in the second direction.
[0087] Optionally, the height of the barrier layer in the direction perpendicular to the substrate is greater than the height of the corresponding gate in the direction perpendicular to the substrate, and the width of the barrier layer in the second direction is greater than the width of the corresponding gate in the second direction; the width of the first metal layer in the second direction is less than or equal to the width of the gate in the second direction.
[0088] That is, the height of the barrier layer 40 formed at the first opening in the direction perpendicular to the substrate is greater than the height of the gate 20 in the direction perpendicular to the substrate, and the width of the barrier layer 40 in the second direction is greater than the width of the gate 20 in the second direction.
[0089] In order to facilitate preparation and reduce the difficulty of the process, such as Figure 10 As shown, the barrier layers 40 corresponding to each gate 20 can be connected together. In other embodiments, as described above... Figure 2 As shown, the barrier layer 40 corresponding to each gate 20 can also exist separately to separate the corresponding strip gate 20. This application embodiment does not make specific limitations on this.
[0090] Step S3: Along the second direction, etching is performed on the surface of at least one end of each gate adjacent to the barrier layer to form a second opening, and a first metal layer is formed at the second opening.
[0091] Specifically, such as Figure 11 As shown, along the second direction, etching is performed on at least one end of the gate after blocking, i.e., at least one end adjacent to the gate and the blocking layer, to form a second opening until the sidewall of the second opening near the gate 20 exposes the work function metal layer, and the sidewall away from the gate 20 exposes the blocking layer 40. That is, the second opening exposes the work function metal layer on one sidewall along the first direction, and the blocking layer is exposed on the other sidewall. A first metal layer 202 is formed at each second opening, thereby forming a gate structure device.
[0092] Optionally, the resistivity of the material forming the first metal layer is lower than the resistivity of the material forming the work function metal layer.
[0093] Optionally, the width of the first metal layer in the second direction is less than or equal to the width of the gate in the second direction. The specific dimensions and material descriptions can be found in the above embodiments, and will not be repeated in the embodiments of this application.
[0094] It is also understandable that the overlapping portion of each gate 20 and each semiconductor structure 30 can form a gate structure device, as described above. Figure 11 As shown, two gates 20 and two semiconductor structures 30 can be used to fabricate four gate structure devices. This application does not impose a specific limit on the number of gate structure devices fabricated simultaneously.
[0095] In other embodiments, a second metal layer may be formed on the gate away from the upper surface. Along the second direction, at least one second opening is formed on the surface of each gate adjacent to at least one end of each barrier layer, and a third opening is formed on the surface of each gate above the semiconductor structure. A first metal layer is formed at each second opening, and a second metal layer is formed at each third opening; wherein the bottom of the third opening exposes an active function metal layer.
[0096] like Figure 12 As shown, etching can also be performed on the upper surface of the gate after blocking and at both ends of the gate to form a second opening and a third opening. The second opening exposes a work function metal layer on the sidewall near the gate 20, and the bottom of the third opening exposes a work function metal layer. The projection of the third opening on the substrate overlaps with the corresponding semiconductor structure.
[0097] Optionally, the resistivity of the material forming the second metal layer is lower than the resistivity of the material forming the work function metal layer, and the material forming the first metal layer may be the same as or different from the material forming the second metal layer. When the first metal layer and the second metal layer are formed of the same material, a low-resistivity first metal layer 202 can be formed at the second opening and a low-resistivity second metal layer 203 can be formed at the third opening simultaneously.
[0098] Compared to existing technologies where the gate is often made of a work function metal with high resistivity, resulting in high gate resistance and slower transistor turn-on speed, which fails to meet device requirements, the gate structure device fabricated by the method provided in this application can reduce the overall gate resistance, thereby increasing the device's turn-on speed and improving overall device power consumption. Specifically, the device has a first metal layer on the sidewall at at least one end of the gate's extension direction (i.e., the first direction). This first metal layer is connected to the work function metal and covers part or all of the sidewall area. This first metal layer is formed of a metal material with a resistivity lower than that of the work function metal; that is, a low-resistivity metal layer is formed on the sidewalls at both ends of the gate. This structure ensures the device's gate control capability while reducing the overall gate resistance and improving the device's turn-on speed.
[0099] Furthermore, embodiments of this application also provide a semiconductor device, which includes a base plate and the aforementioned components disposed on the base plate. Figures 2-12 The illustrated embodiment mentions a gate structure device.
[0100] This application also provides a chip, wherein the chip includes circuitry and the aforementioned components applied to the circuitry. Figures 2-12 The gate structure device mentioned in the illustrated embodiment or the semiconductor device described in the above embodiment, wherein the chip can be a single chip or a combination of multiple chips.
[0101] This application also provides an electronic device, which may include a circuit board and, as described above, components applied to the circuit board. Figures 2-12 The illustrated embodiment mentions a gate structure device.
[0102] It should be understood that the semiconductor devices, chips, and electronic devices provided in this application may be consistent with the gate structure device technical solutions provided in this application, and their specific contents and beneficial effects can be referred to the above. Figures 2-12 The gate structure devices mentioned in the illustrated embodiments will not be described in detail here.
[0103] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0104] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.
[0105] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.
[0106] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0107] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0108] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A gate structure device, characterized in that, It includes: a substrate, and a gate and a semiconductor structure disposed on the substrate, wherein the gate covers the surface of the semiconductor structure away from the substrate and the sidewalls at both ends of the semiconductor structure in a first direction, the first direction being the extension direction of the gate; The gate includes a work function metal layer; a portion or all of the sidewall of the gate at at least one end in the first direction is covered by a first metal layer, and the first metal layer contacts the work function metal layer; The resistivity of the material forming the first metal layer is lower than the resistivity of the material forming the work function metal layer.
2. The device according to claim 1, characterized in that, The semiconductor structure extends along a second direction, and the semiconductor structure is a fin structure or at least one nanosheet stacked on the substrate, wherein the first direction and the second direction are perpendicular to each other and parallel to the substrate.
3. The device according to claim 1 or 2, characterized in that, The width of the first metal layer in the second direction is less than or equal to the width of the gate in the second direction.
4. The device according to any one of claims 1-3, characterized in that, In the first direction, the thickness of the first metal layer is greater than or equal to 1 nanometer and less than or equal to 10 nanometers.
5. The device according to any one of claims 1-4, characterized in that, The material forming the first metal layer includes at least one of the following: tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo).
6. The device according to any one of claims 1-5, characterized in that, A second metal layer is covered on the surface of the gate on the side away from the substrate, and the second metal layer is connected to the work function metal layer; The resistivity of the material forming the second metal layer is lower than the resistivity of the material forming the work function metal layer.
7. The device according to claim 6, characterized in that, The material forming the first metal layer may be the same as or different from the material forming the second metal layer.
8. The device according to any one of claims 1-7, characterized in that, The material forming the work function metal layer includes at least one of the following materials: titanium (Ti), tantalum (Ta), or tungsten (W).
9. A method for fabricating a gate structure device, characterized in that, The method includes: At least one semiconductor structure extending along a second direction and at least one gate extending along a first direction are formed on the surface of a substrate; wherein each of the gates covers the surface of the at least one semiconductor structure away from the substrate and the sidewalls at both ends of the semiconductor structure in the first direction, the first direction and the second direction being perpendicular to each other and parallel to the substrate; Along the second direction, the surface of each gate located between adjacent semiconductor structures is etched to form at least one first opening, and a barrier layer is formed at each first opening; wherein the projection of each first opening on the substrate is located between adjacent semiconductor structures. Along the second direction, etching is performed on the surface of each gate and at least one end adjacent to each barrier layer to form at least one second opening, and a first metal layer is formed at each second opening; wherein the second opening exposes an active function metal layer on one sidewall along the first direction, and the barrier layer is exposed on the other sidewall.
10. The method according to claim 9, characterized in that, The resistivity of the material forming the first metal layer is lower than the resistivity of the material forming the work function metal layer.
11. The method according to claim 9 or 10, characterized in that, The height of the barrier layer in the direction perpendicular to the substrate is greater than the height of the corresponding gate in the direction perpendicular to the substrate, and the width of the barrier layer in the second direction is greater than the width of the corresponding gate in the second direction; The width of the first metal layer in the second direction is less than or equal to the width of the gate in the second direction.
12. The method according to any one of claims 9-11, characterized in that, The etching along the second direction on the surface of at least one end of each gate adjacent to each barrier layer to form at least one second opening, and the fabrication of a first metal layer at each second opening, includes: Along the second direction, etching is performed on the surface of each gate and at least one end adjacent to each barrier layer to form at least one second opening, and etching is performed on the surface of each gate above the semiconductor structure to form at least one third opening; A first metal layer is formed at each of the second openings, and a second metal layer is formed at each of the third openings; wherein the bottom of the third opening exposes an active function metal layer.
13. The method according to claim 12, characterized in that, The resistivity of the material forming the second metal layer is lower than the resistivity of the material forming the work function metal layer; the material forming the first metal layer may be the same as or different from the material forming the second metal layer.
14. The method according to any one of claims 9-13, characterized in that, The semiconductor structure is a fin structure or at least one nanosheet stacked on the substrate.
15. A semiconductor device, characterized in that, It includes a base plate and a gate structure device as described in any one of claims 1-8 disposed on the base plate.
16. A chip, characterized in that, Includes a circuit and a gate structure device as described in any one of claims 1-8 applied to the circuit.
17. An electronic device, characterized in that, The electronic device includes: a circuit board and a gate structure device as described in any one of claims 1-8.