A method for manufacturing a BCD semiconductor device and a BCD semiconductor device

Abstract

The application discloses a preparation method of a BCD semiconductor device and the BCD semiconductor device. The method comprises the following steps: providing a conductive semiconductor substrate; performing an ion implantation process, implanting conductive ions in a region of the semiconductor substrate, and performing thermal annealing to form a buffer layer; forming an epitaxial layer on the semiconductor substrate with the buffer layer; and forming a first trench isolation structure and a second trench isolation structure on the semiconductor substrate with the epitaxial layer, wherein the second trench isolation structure is used for isolating different devices of the BCD semiconductor substrate; and wherein the trench depth of the second trench isolation structure is at least to the buffer layer, and the buffer layer at the bottom of the second trench isolation structure is used for improving the voltage resistance performance between the BCD devices. In this way, the ion implantation process and the thermal annealing process are advanced, defects existing in the preparation process of the BCD device are reduced, and the electrical stability of the BCD device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for fabricating a BCD semiconductor device and the BCD semiconductor device itself. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) is a special semiconductor manufacturing process that integrates bipolar transistors, complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) onto the same chip to achieve a combination of high-performance analog circuits, digital control, and high-voltage, high-current drive capabilities.

[0003] In existing technologies, a deep trench isolation structure is first formed on a semiconductor substrate, and then BCD devices are integrated to achieve lateral isolation between any two Bipolar, CMOS, or DMOS transistors through the deep trench isolation structure. Then, an interlayer dielectric layer is formed on the semiconductor substrate and covers the BCD devices, thereby achieving vertical physical isolation between the active devices and the subsequently formed metal interconnect layers.

[0004] The fabrication of deep trench isolation structures involves ion implantation and thermal annealing processes. Therefore, if thermal annealing is performed, the resistance value of the polysilicon resistor in the BCD device region will deviate from its set value. However, if thermal annealing is not performed, lattice defects caused by ion implantation can easily become leakage current generation centers or premature breakdown paths, thus reducing the breakdown voltage of the deep trench isolation structure and consequently lowering the breakdown voltage of the BCD device. For these reasons, the number of defects present during the fabrication of BCD semiconductor devices increases.

[0005] Therefore, how to reduce defects in the semiconductor device fabrication process is a technical problem that needs to be solved. Summary of the Invention

[0006] This application provides a method for fabricating a BCD semiconductor device, which can reduce defects present in the fabrication process of semiconductor devices. This application also provides a BCD semiconductor device.

[0007] The specific plan is as follows:

[0008] In a first aspect, embodiments of this application provide a method for fabricating a BCD semiconductor device, comprising: providing a conductive semiconductor substrate; performing an ion implantation process to implant conductive ions into a defined depth region in the semiconductor substrate, and performing thermal annealing to form a buffer layer; forming an epitaxial layer on the semiconductor substrate with the buffer layer; forming a first trench isolation structure and a second trench isolation structure on the semiconductor substrate with the epitaxial layer, wherein the second trench isolation structure is used to isolate different BCD devices on the semiconductor substrate; wherein the trench depth of the second trench isolation structure extends at least to the buffer layer, and the buffer layer at the bottom of the second trench isolation structure is used to improve the breakdown voltage performance between BCD devices.

[0009] Secondly, embodiments of this application provide a BCD semiconductor device, comprising: a conductive semiconductor substrate, a buffer layer formed in a predetermined depth region of the semiconductor substrate by implanting conductive ions and performing thermal annealing, an epitaxial layer on the semiconductor substrate, a first trench isolation structure and a second trench isolation structure formed on the semiconductor substrate, wherein the second trench isolation structure is used to isolate different BCD devices on the semiconductor substrate, the trench depth of the second trench isolation structure extends at least to the buffer layer, and the buffer layer at the bottom of the second trench isolation structure is used to improve the breakdown voltage performance between BCD devices.

[0010] Compared with the prior art, this application has the following advantages:

[0011] The method for fabricating a BCD semiconductor device provided in this application includes: providing a conductive semiconductor substrate; performing an ion implantation process to implant conductive ions into a designated region in the semiconductor substrate, and performing thermal annealing to form a buffer layer; forming an epitaxial layer on the semiconductor substrate with the buffer layer; forming a first trench isolation structure and a second trench isolation structure on the semiconductor substrate with the epitaxial layer, wherein the second trench isolation structure is used to isolate different BCD devices on the semiconductor substrate; wherein the trench depth of the second trench isolation structure extends at least to the buffer layer, and the buffer layer at the bottom of the second trench isolation structure is used to improve the breakdown voltage performance between BCD devices.

[0012] In the above process, after forming the conductive semiconductor substrate, ion implantation and thermal annealing are first performed to form a buffer layer in a designated region of the semiconductor substrate. Then, the epitaxial layer, the first trench isolation structure, and the second trench isolation structure are formed on the semiconductor substrate. This approach advances the ion implantation and thermal annealing processes. On the one hand, it avoids the release of inactive impurities from the polysilicon filled in the second trench isolation structure due to thermal annealing after its formation, which could affect the polysilicon resistance of the BCD device region integrated in the epitaxial layer in subsequent steps. On the other hand, thermal annealing can repair lattice damage caused by ion implantation, reduce lattice defects, and improve the breakdown voltage of the second trench isolation structure. Therefore, this method can improve the breakdown voltage performance of the BCD device. This reduces defects present in the BCD device fabrication process and improves the electrical stability of the BCD device. Attached Figure Description

[0013] Figure 1 This is a flowchart of the fabrication method of the BCD semiconductor device provided in the embodiments of this application.

[0014] Figure 2 This is a schematic diagram illustrating an example of forming a substrate oxide layer on a semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application.

[0015] Figure 3 This is a schematic diagram illustrating an example of the method for fabricating a BCD semiconductor device provided in this application, in which an ion implantation process and a thermal annealing process are performed in a semiconductor substrate to form a buffer layer.

[0016] Figure 4 This is a schematic diagram illustrating an example of forming a first epitaxial layer on a semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application.

[0017] Figure 5 This is a schematic diagram illustrating an example of forming an N-type buried layer and a second epitaxial layer on a semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application.

[0018] Figure 6 This is a schematic diagram illustrating an example of forming a first passivation oxide layer and a first hard mask layer on the epitaxial layer of a semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application.

[0019] Figure 7 This is a schematic diagram illustrating an example of forming a shallow trench on the epitaxial layer of a semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0020] Figure 8This is a schematic diagram illustrating an example of depositing a first material on a semiconductor substrate with a shallow trench in the fabrication method of the BCD semiconductor device provided in this application.

[0021] Figure 9 This is a schematic diagram illustrating an example of removing a first material from a semiconductor substrate in the fabrication method of a BCD semiconductor device provided in this application.

[0022] Figure 10 This is a schematic diagram illustrating an example of removing the first hard mask layer on the semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application.

[0023] Figure 11 This is a schematic diagram illustrating an example of forming polysilicon in the first passivation oxide layer and the top region of a portion of the shallow trench in the fabrication method of the BCD semiconductor device provided in this application.

[0024] Figure 12 This is a schematic diagram of an example of forming an interlayer dielectric layer on the first passivation oxide layer in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0025] Figure 13 This is a schematic diagram illustrating an example of a method for fabricating a BCD semiconductor device provided in this application, in which etching begins in the interlayer dielectric layer to form a deep trench on the semiconductor substrate.

[0026] Figure 14 This is a schematic diagram of a first example of filling a second material onto an interlayer dielectric layer forming a deep trench in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0027] Figure 15 This is a schematic diagram illustrating an example of removing the second material on the interlayer dielectric layer in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0028] Figure 16 This is a schematic diagram of a second example of filling a second material on the interlayer dielectric layer forming a deep trench in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0029] Figure 17 Is Figure 16 A schematic diagram of an example of filling the gaps formed by filling the second material with oxide of the second material.

[0030] Figure 18 This is a schematic diagram illustrating an example of forming a second passivation oxide layer and a second hard mask layer on the epitaxial layer of a semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application.

[0031] Figure 19This is a schematic diagram illustrating an example of forming a deep trench on a semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0032] Figure 20 This is a schematic diagram of a first example of depositing a second material on the surface of a semiconductor substrate forming a deep trench in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0033] Figure 21 This is a schematic diagram illustrating an example of removing a second material from the surface of a semiconductor substrate in the fabrication method of a BCD semiconductor device provided in this application.

[0034] Figure 22 This is a schematic diagram of a second example of depositing a second material on the surface of a semiconductor substrate forming a deep trench in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0035] Figure 23 Is Figure 22 A schematic diagram of an example of filling the gaps formed by filling the second material with oxide of the second material.

[0036] Figure 24 This is a schematic diagram illustrating an example of removing the second material oxide layer and the second material from the surface of the semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application.

[0037] Figure 25 This is a schematic diagram illustrating an example of the method for fabricating a BCD semiconductor device provided in this application, in which the second hard mask layer and the second passivation oxide layer on the surface of the semiconductor substrate are removed, and the third passivation oxide layer and the third hard mask layer are reformed on the epitaxial layer of the semiconductor substrate forming the second trench isolation structure.

[0038] Figure 26 This is a schematic diagram illustrating an example of forming a shallow trench on a semiconductor substrate with a second trench isolation structure in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0039] Figure 27 This is a schematic diagram illustrating an example of filling a shallow trench with a first material in the fabrication method of the BCD semiconductor device provided in this application.

[0040] Figure 28 This is a schematic diagram illustrating an example of removing the first material from the surface of a semiconductor substrate in the fabrication method of the BCD semiconductor device provided in this application embodiment.

[0041] Figure 29 This is a schematic diagram illustrating an example of removing a third hard mask layer on a semiconductor substrate in the fabrication method of a BCD semiconductor device provided in this application.

[0042] Figure 30 This is a schematic diagram illustrating an example of the deposition of polycrystalline silicon on the surface of a partial shallow trench and the surface of a third passivation oxide layer in the fabrication method of the BCD semiconductor device provided in this application.

[0043] Figure 31 This is a schematic diagram illustrating an example of forming an interlayer dielectric layer on the surface of a third passivation oxide layer formed with polycrystalline silicon in the fabrication method of the BCD semiconductor device provided in this application. Detailed Implementation

[0044] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific implementations disclosed below. It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in an order other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses. It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Containing A, B and / or C" means containing any one, two, or three of A, B, and C. It should be understood that in the embodiments of this application, "B corresponding to A," "B corresponding to A," "A and B correspond," or "B and A correspond" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0045] BCD (Bipolar-CMOS-DMOS) is a special semiconductor manufacturing process that integrates bipolar transistors, complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) onto the same chip to achieve a combination of high-performance analog circuits, digital control, and high-voltage, high-current drive capabilities.

[0046] In existing technologies, a deep trench isolation structure is first formed on a semiconductor substrate, and then BCD devices are integrated to achieve lateral isolation between any two Bipolar, CMOS, or DMOS transistors through the deep trench isolation structure. Then, an interlayer dielectric layer is formed on the semiconductor substrate and covers the BCD devices, thereby achieving vertical physical isolation between the active devices and the subsequently formed metal interconnect layers.

[0047] The fabrication of deep trench isolation structures involves ion implantation and thermal annealing processes. During thermal annealing, the polysilicon doping in the BCD device region is activated, resulting in a stable polysilicon resistance value in that region. However, the polysilicon filling the deep trench isolation structure is not sufficiently doped or fully activated. Therefore, during thermal annealing, the polysilicon filling the deep trench begins to release unactivated impurities (e.g., phosphorus or boron). These impurities diffuse laterally through the silicon substrate or interface into the polysilicon of adjacent BCD device regions, causing a change in the doping concentration of the polysilicon in the BCD device regions. Consequently, the polysilicon resistance value of the BCD device regions changes, deviating from its set value.

[0048] However, if the thermal annealing process is not performed, the lattice defects caused by ion implantation can easily become the center of leakage current generation or the path of premature breakdown. Therefore, the breakdown voltage of the deep trench isolation structure is reduced, that is, edge breakdown or leakage path conduction may occur at lower voltages. This causes the following defects: (1) Avalanche breakdown or tunneling current occurs prematurely on the sidewalls or bottom of the deep trench, resulting in leakage between different device regions in the BCD device. For example, parasitic leakage occurs between the high-voltage DMOS region and the low-voltage CMOS region. (2) When the high-voltage DMOS operates close to the rated voltage, the edge of the deep trench breaks down first. (3) Deep trenches are often used to isolate N-type doped regions or P-type doped regions to prevent parasitic bipolar transistors (e.g., PNP structures) from conducting. The reduction in the breakdown voltage of the deep trench leads to a decrease in the isolation capability of the deep trench. The potential difference between the substrate or doped regions leads to local electric field breakdown, which may trigger a latch-up effect. Once the latch-up effect occurs, it may cause a large current to burn out the device. For the reasons mentioned above, the number of defects in the fabrication process of BCD semiconductor devices has increased.

[0049] Therefore, how to reduce defects in the semiconductor device fabrication process is a technical problem that needs to be solved.

[0050] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0051] The following, combined with Figures 1-31 This application describes a method for fabricating a BCD semiconductor device according to embodiments. Figure 1 This is a flowchart of a method for fabricating a BCD semiconductor device provided in an embodiment of this application, including the following steps S101 to S104.

[0052] Step S101: Provide a conductive semiconductor substrate.

[0053] This step is used to provide a conductive semiconductor substrate. In semiconductor manufacturing, the semiconductor substrate is the base used to form semiconductor devices. Semiconductor substrate materials include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The material of the semiconductor substrate can be selected according to actual needs in the fabrication process.

[0054] In this embodiment, an ion implantation process and a thermal annealing process are performed on a conductive semiconductor substrate to form a buffer layer in the semiconductor substrate, as specifically described in step S102.

[0055] Prior to performing the ion implantation process, the method further includes forming a protective layer on the semiconductor substrate, wherein the protective layer is a substrate oxide layer. Figure 2 A schematic diagram is shown of a semiconductor substrate 01 and a substrate oxide layer 02 formed on the surface of the semiconductor substrate 01. The substrate oxide layer is used to protect the surface of the semiconductor substrate and prevent lattice damage to the semiconductor substrate surface during the ion implantation process.

[0056] In this embodiment, the semiconductor substrate 01 includes a P-type substrate, typically a single-crystal silicon wafer doped with P-type impurities. A P-type substrate is a semiconductor wafer (hereinafter referred to as a wafer) where holes are the primary charge carriers, serving as a substrate for manufacturing integrated circuits, power devices, or sensors. The P-type substrate provides mechanical support for the devices manufactured on it and acts as a working platform for the semiconductor devices. The P-type substrate exhibits P-type conductivity (hole concentration > electron concentration) by doping with acceptor impurities (such as boron, gallium, etc.).

[0057] Oxidation is performed on semiconductor substrate 01 to obtain substrate oxide layer 02. The substrate oxide layer is a thin pad oxide layer (SiO2) grown on the semiconductor substrate before the formation of the epitaxial layer. SiO2 has physical properties between silicon and silicon nitride, acting as a "flexible buffer layer" to effectively absorb and relax stress transferred from silicon nitride to the silicon substrate. Stress relaxation can be explained as follows: the pad oxide layer SiO2 is an amorphous material with a microstructure exhibiting some viscoelasticity, meaning it displays slight, ductile fluidity at high temperatures. When stress is transferred from the rigid silicon nitride layer, the pad oxide layer does not rigidly resist it like the silicon substrate. It can "absorb" and "digest" this stress through minute deformations in its internal structure and slight adjustments in atomic bond angles.

[0058] Without a pad oxide layer on the semiconductor substrate, enormous stress will be directly transmitted to the silicon substrate lattice, generating numerous lattice defects (such as dislocations). These defects will extend upwards, penetrating the subsequently grown epitaxial layers. The epitaxial layer forms the basis of the device's active region, and its crystal quality is crucial. The pad oxide layer indirectly ensures high-quality and defect-free growth of the epitaxial layer by protecting the substrate from stress damage.

[0059] Furthermore, growing a high-quality pad oxide layer on a semiconductor substrate at high temperature can consume the outermost layer of silicon, thereby "encapsulating" and isolating surface contaminants and defects in the underlying layers, forming an atomically clean and perfectly passivated silicon surface. Epitaxial growth is the process of replicating the substrate's crystal structure at the atomic level. A clean, intact, and undamaged substrate surface is a crucial prerequisite for single-crystal growth of the epitaxial layer with high interface quality. Subsequent processing steps etch away the pad oxide layer, exposing this perfect silicon surface and preparing it for epitaxial growth.

[0060] Step S102: Perform an ion implantation process to implant conductive ions into a semiconductor substrate at a defined depth region, and perform thermal annealing to form a buffer layer.

[0061] This step is used to form a buffer layer 03 at a specified depth within the semiconductor substrate, such as... Figure 3As shown, this step involves performing an ion implantation process on the semiconductor substrate before forming the epitaxial layer, deep trench isolation structure, and BCD device. Conductive ions are implanted at a predetermined depth in the semiconductor substrate, followed by thermal annealing to form a buffer layer. Then, the bottom of the trenches in the deep trench isolation structure formed in subsequent steps is positioned at the predetermined depth of the buffer layer. This approach advances the ion implantation and thermal annealing processes immediately after the semiconductor substrate is formed. This avoids the release of inactive impurities from the polysilicon filling the second trench isolation structure due to thermal annealing after its formation, which could affect the polysilicon resistance of the subsequently formed BCD device region and cause it to deviate from its predetermined value. Furthermore, thermal annealing repairs lattice damage caused by ion implantation, reduces lattice defects, increases the breakdown voltage of the second trench isolation structure, prevents BCD device breakdown at lower voltages, and improves the breakdown voltage performance of the BCD device.

[0062] In this embodiment, breakdown voltage refers to the strong electric field generated when the reverse bias voltage applied across the second trench isolation structure in a semiconductor device is continuously increased. When the strength of this electric field exceeds the critical value of the semiconductor substrate material itself, "avalanche breakdown" or other forms of breakdown (e.g., Zener breakdown) will occur.

[0063] Ion implantation is the process of forcibly implanting high-energy, charged impurity ions (such as boron, phosphorus, or arsenic) into the surface of a semiconductor material (such as a silicon wafer). This is a physical process. Ion implantation serves two purposes: firstly, it alters conductivity by implanting different types of impurities (acceptors or donors) to form P-type or N-type regions in silicon, thereby creating the source, drain, gate, and well structures of transistors. Secondly, it allows for precise control: the concentration (controlled by ion current intensity and time) and depth (controlled by ion energy) of the doping process can be controlled with extreme precision.

[0064] In this embodiment, the implantation angle and implantation energy for performing the ion implantation process can be determined by the voltage corresponding to the device integrated on the semiconductor substrate. The device includes a BCD device integrated on the epitaxial layer, a resistor, and a first trench isolation structure and a second trench isolation structure located on the semiconductor substrate.

[0065] Based on the implantation energy of the above-described ion implantation process, a conductive ion beam required for performing the ion implantation process is prepared; the conductive ion beam is emitted onto the surface of the semiconductor substrate according to the implantation angle of the above-described ion implantation process, and the position that the conductive ion beam can reach in the semiconductor substrate when the ion energy of the conductive ion beam is exhausted is obtained as the set depth region; based on the specific annealing method, annealing temperature, and annealing time of the thermal annealing process selected in the embodiments of this application, the conductive ion beam located in the set depth region in the semiconductor substrate is subjected to thermal annealing process to form the buffer layer.

[0066] One method for preparing a conductive ion beam is as follows:

[0067] (1) The required doping gas (e.g., phosphine PH3 for forming N-type regions, borane B2H6 for forming P-type regions) or solid source is introduced into the ion source vacuum chamber. The source material is ionized by arc discharge or radio frequency energy to generate plasma containing ions of the required doping element. (2) Positively charged ions are separated from the plasma by the ionization effect of the applied strong electric field at the ion source outlet to form a preliminary ion beam. The preliminary ion beam is accelerated by an electrostatic field to obtain an accelerated ion beam. The accelerated ion beam has high energy, which determines the depth of ion implantation into the silicon wafer. (3) The accelerated ion beam is separated by controlling the magnetic field strength to obtain an ion beam with a single element. (4) The ion beam with a single element is focused and shaped by a series of electrostatic lenses to form a collimated ion beam, called a conductive ion beam. The final conductive ion beam contains a single element, and the ion energy of the ion beam is higher than the preset energy threshold. The prepared conductive ion beam includes an ion beam formed by a single dopant element ion, and may also include an ion beam formed by a combination of multiple dopant element ions. Therefore, the conductive ions implanted in the semiconductor substrate include at least one of the following: arsenic, phosphorus, boron, and argon.

[0068] In addition to considering the ion energy of the conductive ion beam, the injection angle and injection dose of the conductive ion beam also need to be considered.

[0069] The injection angle is the angle between the conductive ion beam and the normal to the semiconductor substrate surface. By selecting a predetermined injection angle, the conductive ion beam is emitted to the target area on the surface of the semiconductor substrate. Typically, a non-zero angle is used (for example, the angle between the ion beam and the normal to the semiconductor substrate surface can be 0). This ensures that after the conductive ions collide with the silicon atoms in the semiconductor substrate, they become randomly injected, resulting in a controllable and steep doping distribution.

[0070] The implantation dose is the total number of ions implanted per unit area. It determines the impurity distribution density in the doped region and affects the material's conductivity, resistivity, and transistor threshold voltage. During ion implantation of a semiconductor substrate using an ion implanter, the total ion dose implanted into the buffer layer within the semiconductor substrate can be determined by controlling the conductive ion beam current and implantation time. The conductive ion beam current refers to the number of ions in the conductive ion beam emitted during this ion implantation process.

[0071] Based on the implantation dose, the density of conductive ions implanted into the final buffer layer is obtained. This density is determined by the breakdown voltage of the second trench isolation structure, typically 2e. 15 cm -2 This means that 200 trillion ions are implanted per square centimeter. The density of conductive ions implanted in the buffer layer, also known as the doping concentration of the implanted ions, is one of the key factors determining the breakdown voltage of the second trench isolation structure. When a reverse bias is applied in a deep trench isolation structure, a "depletion region" without free carriers is formed. The higher the doping concentration, the narrower the depletion region, the higher the internal electric field strength, and the lower the breakdown voltage. The lower the doping concentration, the wider the depletion region, the lower the internal electric field strength, and the higher the breakdown voltage.

[0072] Next, an ion implantation process is performed, firing a conductive ion beam onto the surface of the semiconductor substrate. The ions in this conductive ion beam have high energy, and they bombard the semiconductor substrate surface exposed below the ion implanter window. The ions penetrate the substrate oxide layer (e.g., silicon dioxide) at extremely high speeds and collide with the silicon lattice. The collisions between these high-energy ions and silicon atoms disrupt the lattice structure, causing damage. The location within the semiconductor substrate where the ions eventually reach due to energy depletion is defined as the predetermined depth region, where a buffer layer is formed.

[0073] In this embodiment, ion implantation and thermal annealing processes are performed to form a buffer layer. The purpose is to combine with the subsequently formed deep trench to prevent unnecessary current leakage and signal crosstalk between adjacent devices integrated on the semiconductor substrate. Therefore, deep trenches and a buffer layer are used to establish electrical isolation.

[0074] During the formation of deep trenches, defects in the silicon crystal structure due to etching may exist at the bottom and sidewalls of the trench, potentially forming unwanted conductive channels. Therefore, a high dose of conductive ion implantation is required at the bottom of the deep trench to form a P+ barrier layer in the silicon. The P+ barrier layer forms a PN junction with the silicon substrate (typically P-type) at the bottom of the deep trench or an adjacent N-type well. The PN junction exhibits unidirectional conductivity; when a certain operating bias voltage is applied, the PN junction is reverse biased, exhibiting high resistance. This effectively blocks the lateral flow of current between adjacent devices, achieving electrical isolation between them.

[0075] Therefore, implanting conductive ions into a defined depth region in the semiconductor substrate to form a buffer layer can include at least two methods:

[0076] The first method involves implanting conductive ions across the entire surface of the semiconductor substrate. The second method involves defining a target region for the conductive ion implantation on the surface of the semiconductor substrate using a photolithography process, and then implanting the conductive ions into the target region, wherein the target region is the region corresponding to the second trench isolation structure.

[0077] The buffer layer obtained by the first method is as follows: Figure 3 As shown in 301, since the conductive ion beam emission method is to inject the entire surface of the substrate oxide layer of the semiconductor substrate, the buffer layer formed in the set depth region of the semiconductor substrate is the entire surface of the semiconductor substrate cross section at that depth position.

[0078] The buffer layer obtained in the second method is as follows: Figure 3 As shown in 302, the conductive ion beam is emitted by injecting conductive ions into the region corresponding to the second trench isolation structure (deep trench isolation structure) on the surface of the substrate oxide layer of the semiconductor substrate.

[0079] The subsequent description of the solutions provided in the embodiments of this application is as follows: Figure 3 The first method of obtaining buffer layer 03-1, as shown in 301, will be used as an example for further introduction.

[0080] The conductive ions described above can provide electrons or holes in semiconductor substrates and achieve solubility in silicon substrates under predetermined conditions. High-energy ion bombardment severely disrupts the orderly arrangement of silicon atoms in the crystal lattice, creating numerous vacancies and interstitial atoms, and even causing the implanted region to become amorphous. The implanted impurity ions are also mostly located in inactive interstitial positions. Therefore, although the implanted silicon wafer exhibits impurity distribution, the crystal lattice is damaged, rendering it unable to function properly.

[0081] To repair the damaged crystal lattice, thermal annealing is required, which involves treating the ion-implanted semiconductor material at a high temperature for a period of time. This is a thermodynamic process.

[0082] The annealing process that can be selected in the embodiments of this application includes at least one of the following:

[0083] Traditional furnace tube annealing: The entire semiconductor substrate is placed in a high-temperature furnace tube and heated for a long time (e.g., 30 minutes to several hours) in an inert gas (e.g., nitrogen N2) or weak reducing gas (e.g., hydrogen H2) atmosphere, with an annealing temperature range of 800°C to 1000°C.

[0084] Rapid thermal annealing: Using a high-intensity light source (e.g., halogen tungsten lamp, arc lamp, etc.) to instantly heat a single wafer to the target temperature in a very short time (e.g., a few seconds to tens of seconds), and then rapidly cool it down. The annealing temperature range is 1000℃~1100℃.

[0085] Peak annealing: Similar to rapid thermal annealing, but with a faster heating rate and no holding time at the highest temperature. The temperature curve resembles a sharp "peak". Temperature range: 1050℃~1200℃.

[0086] Millisecond annealing (e.g., laser annealing or flash annealing): Laser annealing uses a high-energy excimer laser (e.g., argon fluoride (ArF) laser with a wavelength of 193 nm) to scan and irradiate the wafer surface at millisecond or even nanosecond levels. Only a very shallow surface layer is heated, while the substrate remains essentially cooled.

[0087] Flash annealing: This involves using a xenon flash lamp to irradiate the entire wafer surface with intense, millisecond-level light in a single application. Millisecond-level annealing can achieve wafer surface temperatures exceeding 1300°C, enabling ultra-solid-phase epitaxy.

[0088] According to the specific ion implantation process performed on the semiconductor substrate, the corresponding annealing method, annealing temperature and annealing time are selected to perform a thermal annealing process. This process has the following effects: (1) Repairing lattice damage, enabling silicon atoms to obtain sufficient energy to rearrange and restore a perfect single crystal structure. (2) Electro-activating impurities: causing the implanted interstitial impurity atoms to move to lattice positions (substitution type), thereby becoming electro-active dopants that can provide electrons or holes. The peak annealing process used in this embodiment eliminates the heat preservation stage, and immediately cools down after heating. The temperature curve is like a peak, with an extremely low thermal budget, which can effectively activate impurities while almost suppressing the diffusion of all impurity atoms.

[0089] Therefore, the ion implantation process here achieves the precision of impurity atom doping in the semiconductor substrate, while the thermal annealing process ensures the effectiveness of doping and the integrity of the crystal lattice.

[0090] This application embodiment advances the ion implantation and thermal annealing processes before the deep trench isolation structure is fabricated, performing them immediately after the semiconductor substrate is formed. This avoids performing the ion implantation and thermal annealing processes after the formation of the BCD device, polysilicon resistor, and deep trench isolation structure. Therefore, this method can prevent the resistance value of the polysilicon resistor in the BCD device region from deviating from its set value due to the thermal annealing process. Furthermore, the thermal annealing process can repair damaged crystal lattices, reduce lattice defects, improve the breakdown voltage of the second trench isolation structure, prevent the BCD device from breaking down at lower voltages, and improve the breakdown voltage performance of the BCD device.

[0091] Step S103: An epitaxial layer is formed on a semiconductor substrate on which a buffer layer has been formed.

[0092] This step is used to form an epitaxial layer on the semiconductor substrate after the buffer layer is formed in step S102.

[0093] The formation of an epitaxial layer on the semiconductor substrate with the buffer layer can be referred to... Figure 4 and Figure 5 A first epitaxial layer 04 of the semiconductor substrate is formed on the substrate oxide layer 02; an N-type buried layer 05 is formed at a designated position on the first epitaxial layer 04; and a second epitaxial layer 06 is formed on the first epitaxial layer and the N-type buried layer.

[0094] The first and second epitaxial layers formed on the semiconductor substrate can be P-type epitaxial layers, which are single-crystal thin films with P-type conductivity formed on the surface of a semiconductor substrate (such as silicon, gallium arsenide, etc.) through epitaxial growth technology. Their main purpose is to provide specific electrical properties (such as hole conduction, reduced resistance, increased breakdown voltage, etc.) or structural optimization (such as reduced defect density) for semiconductor devices by precisely controlling doping and crystal structure.

[0095] Epitaxial growth techniques can include chemical vapor deposition (CVD) and molecular beam epitaxy (MBE). CVD involves introducing a silicon-containing gas (e.g., silane (SiH4), dichlorosilane (SiH2Cl2), or silicon tetrachloride (SiCl4)) and a p-type dopant source (e.g., borane (B2H6)) into a high-temperature reaction chamber. Through a chemical reaction, silicon atoms are deposited on the substrate surface, gradually forming a single-crystal layer. MBE, on the other hand, operates in an ultra-high vacuum environment. By evaporating silicon and doping elements (e.g., boron), a beam of atoms or molecules is directly sprayed onto the substrate surface, causing a reaction and growth into a single-crystal layer.

[0096] In this embodiment, a first epitaxial layer, which is a lightly doped P-type (P-) or intrinsic silicon layer, is first formed on the substrate oxide layer of the semiconductor substrate. Its thickness and doping concentration need to be precisely controlled because they will affect the breakdown voltage and isolation characteristics of subsequent devices. Its main function is to act as a "pad layer," providing a high-quality growth substrate for the N-type buried layer (NBL).

[0097] An N-type buried layer (NBL) is a highly concentrated N-type doped region buried beneath a P-type epitaxial layer, typically fabricated during the initial stages of substrate preparation or before epitaxial growth. Specifically, the NBL region is defined on the surface of a P-type silicon substrate using photolithography, and then formed through high-dose ion implantation and high-temperature annealing. High-dose ion implantation refers to the implantation of N-type impurities (such as arsenic (As) or antimony (Sb)), typically with a dose of 10-1. 15 -10 16 cm -2 Energy ranges from 50 to 200 keV. High-temperature annealing refers to the diffusion of implanted ions at temperatures of 1000-1200℃, forming a deep junction (1-5μm deep) and activating impurities. One function of the N-type buried layer is to reduce collector / drain resistance: in bipolar transistors (BJTs) or power MOSFETs, NBLs act as low-resistance paths, improving current transport efficiency. Isolation and latch-up prevention: in CMOS processes, NBLs can block the conduction of parasitic PNP transistors, preventing latch-up. Reducing substrate interference: shielding noise or substrate leakage current.

[0098] In this embodiment, an N-type buried layer is formed on the first epitaxial layer. This serves two purposes: firstly, it provides a low-resistance collector path for the vertical NPN transistor. The NPN transistor is a core component of the bipolar junction transistor (BCD) device, primarily used for high-precision analog signal processing, high-speed switching, or drive circuits. In a vertical NPN transistor, the collector current needs to flow downwards from the top collector contact. Without NPN, the current must flow through the entire high-resistance epitaxial layer to reach the bottom collector contact, resulting in significant parasitic resistance and severely reducing transistor speed and efficiency. The NBL, as a heavily doped (N+) buried low-resistance path, allows the collector current to flow horizontally and almost losslessly to the collector contact hole, greatly reducing parasitic resistance and improving the transistor's high-frequency performance. Secondly, it forms an isolation wall: the NBL, together with the upper deep N-well and the lower P-type substrate, constitute an isolation structure. The NBL and DNW surround the P-type epitaxial layer from both top and bottom, forming a localized P-type "bucket." This P-type barrel is isolated from the P-type substrate by a reverse-biased NBL / P-type substrate junction. In this way, devices located in this P-type barrel (such as another NPN transistor or resistor) are well electrically isolated from the substrate, effectively preventing latch-up effects and mutual interference between devices.

[0099] A second epitaxial layer is formed on the N-type buried layer, which serves as the active layer on which the device is actually fabricated. All high-performance devices, such as vertical NPN transistors, CMOS devices, resistors, and capacitors, are fabricated on this second epitaxial layer. The NBL is buried beneath the second epitaxial layer, but it connects to the collector contact region on the upper surface through a deep N-well (DNW) or sink region formed in subsequent processes, thus providing a low-resistance path. The thickness and doping concentration of the second epitaxial layer directly determine the device performance, such as breakdown voltage, threshold voltage, and gain.

[0100] Step S104: A first trench isolation structure and a second trench isolation structure are formed on a semiconductor substrate on which an epitaxial layer is formed. The second trench isolation structure is used to isolate different devices of BCD on the semiconductor substrate. The trench depth of the second trench isolation structure extends at least to the buffer layer. The buffer layer at the bottom of the second trench isolation structure is used to improve the breakdown voltage performance between BCD devices.

[0101] This step involves performing ion implantation and thermal annealing processes on a predetermined depth region in the semiconductor substrate in step S102 to form a buffer layer. After forming an epitaxial layer on the semiconductor substrate in step S103, a first trench isolation structure and a second trench isolation structure are formed on the semiconductor substrate. The trench depth of the second trench isolation structure is at least set at the predetermined depth position of the buffer layer. The buffer layer at the bottom of the second trench isolation structure is used to improve the withstand voltage performance between BCD devices.

[0102] The step of forming a first trench isolation structure and a second trench isolation structure on the semiconductor substrate on which the epitaxial layer is formed includes: forming the first trench isolation structure on the epitaxial layer of the semiconductor substrate; forming an interlayer dielectric layer on the first trench isolation structure; and forming the second trench isolation structure on the semiconductor substrate on which the interlayer dielectric layer is formed, wherein the bottom of the trench of the second trench isolation structure is located at a predetermined depth of the cache layer inside the semiconductor substrate.

[0103] The following first describes the process of forming a first trench isolation structure on an epitaxial layer of a semiconductor substrate: a first passivation oxide layer and a first hard mask layer are formed on the epitaxial layer of the semiconductor substrate; a region where a shallow trench needs to be formed is defined on the first hard mask layer using a photolithography process; an etching process is performed on the region where the shallow trench needs to be formed on the first hard mask layer to form a shallow trench on the epitaxial layer of the semiconductor substrate; a first material is deposited on the semiconductor substrate where the shallow trench is formed to obtain the first trench isolation structure. The following is combined with... Figures 6 to 10 To elaborate further.

[0104] like Figure 6 As shown, a first passivation oxide layer 07 and a first hard mask layer 08 are formed sequentially from bottom to top on the second epitaxial layer 06 to help precisely control the depth and shape of the shallow trench, while protecting the semiconductor substrate from erosion or wear in subsequent process steps.

[0105] The first passivation oxide layer is a thin layer of silicon dioxide (SiO2) formed on a semiconductor substrate (e.g., a silicon substrate). Its function is to prevent contamination or oxidation of the silicon surface, reduce interface state density, isolate the metal layer, prevent short circuits, and alleviate mechanical stress within the device. The first passivation oxide layer can be generated by thermal oxidation or chemical vapor deposition. Thermal oxidation is a process of growing silicon dioxide by exposing the substrate to oxygen or water vapor in a high-temperature environment. Thermal oxidation includes dry oxygen oxidation and wet oxygen oxidation. Dry oxygen oxidation uses pure oxygen as an oxidant to generate a high-quality, dense oxide layer, while wet oxygen oxidation uses water vapor to react with silicon to generate the oxide layer. The growth rate of wet oxygen oxidation is faster than that of dry oxygen oxidation, but the oxide layer density of wet oxygen oxidation is lower than that of dry oxygen oxidation. Chemical vapor deposition (CVD) is a material preparation technique that deposits solid thin films on a substrate surface through a gas-phase chemical reaction. The principle is to utilize a gaseous precursor to undergo a chemical reaction under specific conditions to generate a solid product that is deposited on the substrate, while the byproducts are gaseous substances that are discharged from the system.

[0106] The first hard mask layer is a thin film material with high hardness and high etch selectivity used for pattern transfer in semiconductor manufacturing, located between the photoresist and the material to be etched. The first hard mask layer protects the first passivation oxide layer and the semiconductor substrate from over-etching during subsequent etching steps. The first hard mask layer includes, but is not limited to, silicon nitride (Si3N4) hard mask layers, silicon dioxide (SiO2) hard mask layers, metal hard mask layers, and amorphous carbon hard mask layers. In this embodiment, the first hard mask layer is a silicon nitride (Si3N4) hard mask layer.

[0107] Photolithography is a process that uses optical exposure to transfer a design pattern from a photomask onto a photoresist layer on the wafer surface. It creates a precise temporary pattern on the wafer surface, providing a template for subsequent etching or ion implantation.

[0108] Etching is a process that removes substrate material not protected by photoresist using physical or chemical methods, permanently transferring the photolithographic pattern onto a wafer. Its purpose is to precisely replicate the pattern to form device structures (such as gates and interconnect trenches). Etching includes wet etching and dry etching. Wet etching uses chemical solutions (such as hydrofluoric acid for silicon dioxide and phosphoric acid for silicon nitride) to selectively dissolve the material. Dry etching utilizes active ions or free radicals in plasma for etching, including physical etching (ion bombardment, such as Ar...). + Sputtering or chemical etching (gas reaction, such as carbon tetrafluoride plasma etching of silicon).

[0109] like Figure 7 As shown, a first photoresist layer 09 is coated on the first hard mask layer 08, and the area where shallow trenches need to be formed is defined on the first hard mask layer 08 by exposure and development. According to the depth and shape required for etching the shallow trenches, a shallow trench 10 is formed through the first hard mask layer 08, the first passivation oxide layer 07, and to a first predetermined position on the second epitaxial layer 06 of the semiconductor substrate by an etching process.

[0110] Then, remove Figure 7 The first photoresist layer 09 is applied until the surface of the first hard mask layer 08 is exposed. A first material is then deposited on the semiconductor substrate forming the shallow trench, and the deposited first material at least fills the shallow trench. The shallow trench filled with the first material is a first trench isolation structure.

[0111] The first material deposited within the shallow trench is an insulating filler material, primarily used to isolate different device regions, reduce crosstalk, and improve the overall performance of the integrated circuit. The insulating filler material includes, but is not limited to: silicon dioxide (SiO2), silicon nitride (Si3N4), borosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, and high-molecular-weight organic polymers.

[0112] In semiconductor manufacturing, trench filling is the process of filling trenches, vias, or other high aspect ratio structures formed by etching with material (e.g., dielectric, metal, or polysilicon) using deposition techniques. The main objectives are to achieve void-free filling, high uniformity, and process compatibility. Void-free filling avoids electrical failures or reduced mechanical strength caused by incomplete trench filling. High uniformity includes consistent material thickness throughout the trench. Process compatibility ensures seamless integration of the trench filling process with subsequent semiconductor device fabrication processes (e.g., etching or chemical mechanical polishing).

[0113] The process used to deposit the first material in the shallow trench is related to the material type of the first material, the aspect ratio of the trench, and the requirements of subsequent processes. It may include, but is not limited to: (1) High-density plasma chemical vapor deposition: shallow trenches are deposited by enhancing high-energy plasma to achieve good step coverage and gap filling ability. This makes the first material deposited in the shallow trench achieve the effect of high filling density and few voids. (2) Sub-atmospheric pressure chemical vapor deposition: oxides are deposited under low pressure, which has better filling uniformity for the shallow trench. (3) Atomic layer deposition: atomic-level thin films are deposited layer by layer. This method is suitable for nanoscale shallow trenches and can achieve good shape preservation and no voids. The deposition process used in the embodiments of this application is to deposit the first material on the semiconductor substrate forming the shallow trench through at least one of the above methods, so that the shallow trench after deposition achieves the effects of high and uniform filling density, few voids, and no voids.

[0114] like Figure 8 As shown, the deposited first material includes a first portion of first material 11-1 located inside the shallow trench and a second portion of first material located on the surface of the first hard mask layer 08 on the semiconductor substrate, also referred to as the first material layer 11-2. Therefore, the first material layer 11-2 may contain particles or undulations, thus requiring removal of the first material layer to achieve a smooth surface. Therefore, the process further includes: removing the first material on the semiconductor substrate, the removal process stopping at the first hard mask layer. The removal of the first material can include at least one of the following methods: removing the first material layer 11-2 on the semiconductor substrate by etching; or removing the first material layer 11-2 on the semiconductor substrate by a polishing process.

[0115] Figure 9 A schematic diagram is shown showing the removal of the first material layer 11-2 on the semiconductor substrate, exposing the first hard mask layer 08. The etching rate of the first material is different from the etching rate of the hard mask layer, and the time to stop the etching process can be determined by the change in the etching rate during the etching of the first material.

[0116] Grinding is a key technology for planarizing the surface of semiconductor substrates through mechanical or chemical mechanical action. It is primarily used to eliminate surface irregularities, improve surface roughness, control material thickness, or achieve global planarization. Grinding processes include, but are not limited to: Mechanical Grinding, Chemical Mechanical Polishing (CMP), and Electrochemical Mechanical Polishing (ECMP). Mechanical Grinding uses diamond or alumina grinding wheels to directly cut the material surface and is suitable for rough grinding of the back side of wafers. Chemical Mechanical Polishing combines chemical etching (oxidants in the slurry) with mechanical friction (polishing pads) to achieve material removal and is used for global planarization of polysilicon layers, copper interconnects, and shallow trenches. Electrochemical Mechanical Polishing introduces an electric field based on Chemical Mechanical Polishing to electrochemically dissolve and assist in material removal, reducing mechanical stress. It is suitable for ultra-thin devices and is mainly used for stress-free polishing of copper interconnects.

[0117] If the first material is polycrystalline silicon, chemical mechanical polishing (also known as chemical mechanical abrasion) is typically used to remove the first material from the semiconductor substrate. This embodiment of the application selects chemical mechanical polishing, which combines chemical reaction and mechanical abrasion to achieve higher flatness and smoothness.

[0118] The first material layer 11-2 and the hard mask layer 08 are different materials. The different materials have the following differences, and the grinding process of the first material can be judged based on the following aspects: (1) Optical endpoint detection: The refractive indices of the first material layer and the hard mask layer are different, and the intensity and wavelength of the reflected light will change. The grinding process of the first material is determined by monitoring the changes in the reflected light generated during the grinding process. (2) Friction monitoring: The friction between the first material layer and the hard mask layer and the grinding head are different. The grinding process of the first material is determined by monitoring the difference in the friction coefficient between the grinding head and the grinding surface. (3) Acoustic endpoint detection: The changes in the sound characteristics of the interface between different materials are monitored by ultrasonic waves or other acoustic methods to determine whether the grinding process of the first material is complete.

[0119] Then, the first hard mask layer on the semiconductor substrate is removed, and the removal process stops at the first passivation oxide layer; polysilicon is then filled on the first passivation oxide layer.

[0120] Figure 10This is a schematic diagram showing the process after removing the first hard mask layer 08 in the fabrication method of the BCD semiconductor device provided in this application embodiment. As mentioned above, the first hard mask layer 08 is a mask layer deposited to form a shallow trench structure, and its thickness and material settings are designed to match the etching depth of the shallow trench or etching process parameters. The function of retaining the first passivation oxide layer is to prevent the silicon surface from being contaminated or oxidized during the subsequent polysilicon filling process, reduce the interface state density, isolate the metal layer, avoid short circuits, and alleviate the mechanical stress inside the device.

[0121] like Figure 11 As shown, polysilicon 12 is filled on the surface of the first passivation oxide layer 07 and on the surface of the shallow trench that has been filled with the first material to form a gate electrode. The first passivation oxide layer 07 serves as the gate dielectric, and the polysilicon covers it to form an electrode, thus forming a complete MOS (Metal Oxide Semiconductor) structure.

[0122] The above describes the process of forming the first trench isolation structure and filling the formed first trench isolation structure with polysilicon.

[0123] Before forming the second trench isolation structure, an interlayer dielectric layer 13 needs to be formed on the first trench isolation structure, such as... Figure 12 As shown, specifically, it includes forming the interlayer dielectric layer 13 on the surface of the first passivation oxide layer 07 and the surface of the polysilicon 12 in a portion of the semiconductor substrate.

[0124] The interlayer dielectric layer can be formed specifically through deposition. It comprises at least one of the following materials: silicon dioxide (SiO2), fluorosilicone glass, carbon-doped oxide or carbon dioxide-like material, or ultra-low k dielectric. Among these, [the following is a continuation of the process]... Figure 12 It can be seen that a first passivation oxide layer 07 and a second epitaxial layer 06 are disposed below the interlayer dielectric layer 13. The first passivation oxide layer 07 is used to protect the second epitaxial layer 06, on which BCD devices, resistors, capacitors, etc. are integrated. A first metal line is disposed above the interlayer dielectric layer 13, and an intermetallic dielectric layer is disposed above the first metal line.

[0125] Therefore, the interlayer dielectric layer is an insulating material that vertically isolates the active devices integrated on the second epitaxial layer from the first metal line, preventing short circuits or signal crosstalk. Subsequent processes may incorporate multiple interlayer dielectric layers, each serving as an insulating material to isolate two vertically adjacent metal interconnects.

[0126] Subsequently, a second trench isolation structure is formed on the semiconductor substrate on which the interlayer dielectric layer is formed. Please refer to [reference needed]. Figures 13 to 15 Describe the formation process of the second trench isolation structure.

[0127] The step of forming the second trench isolation structure on the semiconductor substrate on which the interlayer dielectric layer is formed includes: defining a region on the interlayer dielectric layer where a deep trench needs to be formed by photolithography; performing an etching process on the region on the interlayer dielectric layer where a deep trench needs to be formed to form a deep trench on the semiconductor substrate, wherein the bottom of the deep trench extends to a predetermined depth position of the buffer layer; and depositing a second material on the semiconductor substrate on which the deep trench is formed to obtain the second trench isolation structure.

[0128] like Figure 13 As shown, a second photoresist layer 14 is coated on the interlayer dielectric layer 13 in areas where deep trenches do not need to be etched, thereby defining the areas on the interlayer dielectric layer 13 where deep trenches need to be formed. The second photoresist layer 14 is used to precisely control the etching areas of the deep trenches and protect the parts that do not need to be etched. Figure 13 As shown, according to the required depth and shape of the deep trench, the etching process is used to start etching at the top position corresponding to a portion of the first trench isolation structure on the interlayer dielectric layer 13, forming a deep trench 15 that intersects with a portion of the first trench isolation structure and whose bottom is set at a set depth position of the buffer layer in the semiconductor substrate.

[0129] Then, remove Figure 13 The second photoresist layer 14 is deposited until the surface of the interlayer dielectric layer 13 is exposed. In subsequent steps, a second material is deposited on the deep trench to obtain the second trench isolation structure.

[0130] In the first case, the deposited second material at least fills the deep trench; it also includes: removing the second material from the semiconductor substrate, wherein the removal process stops at the interlayer dielectric layer.

[0131] like Figure 14 As shown, the deposited second material includes a second material located in a first region 16-1 inside the deep trench, and a second material located in a second region 16-2 on the surface of the interlayer dielectric layer 13, also referred to as the second material layer. The second material in the first region 16-1 can fill the internal space of the deep trench. The second material layer may contain particles or undulations, therefore it needs to be removed to make the surface smooth. The second material layer on the semiconductor substrate is removed by an etching process or by a polishing process. Figure 15 A schematic diagram showing the interlayer dielectric layer 13 exposed after the second material layer is removed is presented.

[0132] In addition, a second scenario is included: the deposited second material forms a gap at the central axis of the deep trench; the method further includes: forming a second material oxide layer corresponding to the second material at the gap, the formed second material oxide layer at least filling the gap; and sequentially removing the second material oxide layer and the second material on the semiconductor substrate, the removal process stopping at the interlayer dielectric layer.

[0133] like Figure 16 As shown, the deposited second material includes a second material layer in the third region 17 located inside the deep trench, and a second material layer in the second region 16-2 located on the surface of the interlayer dielectric layer 13. Combined Figure 14 The first case of the second material deposited in the middle and Figure 16 As can be seen from the second case of the second material deposited in the second case, the second material in the third region 17 failed to fill the deep trench with the second material, and a gap 18 was formed at the central axis of the deep trench. The gap 18 extends to the area on the second material layer corresponding to the top position of the deep trench. That is, there is also a gap in the area of ​​the second material layer in the second region 16-2 corresponding to the top position of the deep trench.

[0134] To fill the gaps 18, the deposited second material needs to be oxidized to obtain a second material oxide. This oxide includes the second material oxide distributed on the upper side of the third region 17 inside the deep trench, which can be called the gap oxide layer 19-1, and the second material oxide located on the surface of the second region 16-2, which can be called the second material oxide layer 19-2. Figure 17 As shown.

[0135] Then, the second material oxide layer and the second material layer on the semiconductor substrate are removed sequentially, specifically by etching or polishing. Figure 17 A schematic diagram is shown showing the interlayer dielectric layer 13 exposed after the second material oxide layer and the second material layer are removed.

[0136] This represents a first method of forming a first trench isolation structure and a second trench isolation structure on a semiconductor substrate, wherein the bottom of the trench of the second trench isolation structure is located at a predetermined depth in the buffer layer of the semiconductor substrate.

[0137] Alternatively, a second method can be used to form the first trench isolation structure and the second trench isolation structure on the semiconductor substrate. Specifically, forming the first trench isolation structure and the second trench isolation structure on the semiconductor substrate with the epitaxial layer includes: forming the second trench isolation structure on the semiconductor substrate; forming the first trench isolation structure in a predetermined top region corresponding to the second trench isolation structure; forming an interlayer dielectric layer on the first trench isolation structure; wherein the bottom of the trench of the second trench isolation structure is located at a predetermined depth region of a buffer layer inside the semiconductor substrate.

[0138] First, a second trench isolation structure is formed on the semiconductor substrate. The specific process is as follows:

[0139] A second passivation oxide layer and a second hard mask layer are formed on the epitaxial layer of the semiconductor substrate; a region where a deep trench needs to be formed is defined on the second hard mask layer by photolithography; an etching process is performed on the region where the deep trench needs to be formed on the second hard mask layer to form a deep trench on the semiconductor substrate, wherein the bottom of the deep trench is at a set depth position to the buffer layer; a second material is deposited on the semiconductor substrate where the deep trench is formed to obtain the second trench isolation structure.

[0140] The following combination Figures 18 to 24 Describe it.

[0141] like Figure 18 As shown, a second passivation oxide layer 20 and a second hard mask layer 21 are formed sequentially from bottom to top on the second epitaxial layer 06. These layers help to precisely control the depth and shape of the deep trenches, while protecting the semiconductor substrate from erosion or wear in subsequent process steps. The second passivation oxide layer 20 uses the same material and formation process as the first passivation oxide layer 07, which can be referred to in detail below. The second hard mask layer 21 uses a similar material and formation process as the first hard mask layer 08. The thickness of the second hard mask layer 21 is a mask layer deposited to form the deep trench structure; its thickness and material settings are designed to match the etching depth of the deep trenches or etching process parameters.

[0142] Then, as Figure 19 As shown, a third photoresist layer 22 is coated on the second hard mask layer 21, and the area where a deep trench needs to be formed is defined on the second hard mask layer 21 by exposure and development. According to the depth and shape required for etching the deep trench, a deep trench 15 is formed through the second hard mask layer 21, the second passivation oxide layer 20, the epitaxial layer of the semiconductor substrate, and to a second predetermined depth position of the semiconductor substrate by an etching process.

[0143] After that, remove Figure 19The third photoresist layer 22 is shown until the surface of the second hard mask layer 21 is exposed. A second material is deposited on the semiconductor substrate forming the deep trench to obtain a second trench isolation structure. The second material deposited in the deep trench is an insulating filler material, mainly used to isolate different device areas, reduce crosstalk, and improve the overall performance of the integrated circuit. The second material can be the same insulating filler material as the first material, or it can be a different insulating filler material. The process of depositing the second material in the deep trench and the process of depositing the first material in the shallow trench are mainly aimed at making the interior of the deep trench free of voids.

[0144] The deposition of a second material within a deep trench can include at least the following two scenarios:

[0145] In the first scenario, the deposited second material at least fills the deep trench; the method further includes removing the second material from the semiconductor substrate, the removal process stopping at the second hard mask layer.

[0146] like Figure 20 As shown, the deposited second material includes a second material located in a first region 16-1 inside the deep trench, and a second material located in a fourth region 16-3 on the surface of the second hard mask layer 21, also referred to as the second material layer. It is evident that the second material in the first region 16-1 has filled the space inside the deep trench. The second material layer in the fourth region 16-3 may contain particles or undulations, therefore it is necessary to remove the second material layer to achieve a smooth surface. Therefore, the second material layer on the semiconductor substrate is removed by an etching process or by a polishing process. Figure 21 A schematic diagram showing the second hard mask layer 21 exposed after the second material layer is removed is shown.

[0147] In addition, a second scenario is included: the deposited second material forms a gap at the central axis of the deep trench; the method further includes: forming a second material oxide layer corresponding to the second material at the gap, the formed second material oxide layer at least filling the gap; and sequentially removing the second material oxide layer and the second material on the semiconductor substrate, the removal process stopping at the second hard mask layer.

[0148] like Figure 22 As shown, the deposited second material includes the second material in the third region 17 located inside the deep trench, and the second material in the fourth region 16-3 located on the surface of the second hard mask layer 21, also referred to as the second material layer. This part is related to... Figure 16 The distribution of the second material is similar; relevant details can be found by referring to... Figure 16 The description, Figure 22 Gaps 18 exist both inside the deep trench and on the fourth region 16-3.

[0149] To fill the gaps 18, the deposited second material needs to be oxidized to obtain a second material oxide. This oxide includes the second material oxide distributed on the upper side of the third region 17 inside the deep trench, which can be called the gap oxide layer 19-1, and the second material oxide located on the surface of the fourth region 16-3, which can be called the second material oxide layer 19-2. Figure 23 As shown.

[0150] Then, the second material oxide layer and the second material layer on the semiconductor substrate are removed sequentially, specifically by etching or polishing. Figure 24 A schematic diagram is shown showing the second hard mask layer 21 exposed after the second material oxide layer and the second material layer are removed.

[0151] The above describes the formation process of the second trench isolation structure.

[0152] The following combination Figures 25 to 31 The process of forming the first trench isolation structure is described. Before forming the first trench isolation structure, it is necessary to: sequentially remove the second hard mask layer 21 and the second passivation oxide layer 20; the formation of the first trench isolation structure in the top preset area corresponding to the second trench isolation structure includes: re-forming the third passivation oxide layer 23 and the third hard mask layer 24 on the semiconductor substrate on which the second trench isolation structure is formed; defining the area on the third hard mask layer 24 where a shallow trench needs to be formed by photolithography; performing an etching process on the area on the third hard mask layer 24 where a shallow trench needs to be formed to form the shallow trench, forming the shallow trench on the epitaxial layer of the semiconductor substrate; depositing a first material on the semiconductor substrate on which the shallow trench is formed to obtain the first trench isolation structure.

[0153] Figure 25 This diagram illustrates the re-formation of a third passivation oxide layer 23 and a third hard mask layer 24 on the epitaxial layer of a semiconductor substrate after removing the second hard mask layer 21 and the second passivation oxide layer 20. This helps to precisely control the depth and shape of the deep trench structure while protecting the semiconductor substrate from erosion or wear in subsequent process steps. The third hard mask layer 24 is a mask layer deposited to form a shallow trench structure; its thickness and material settings are designed to match the etching depth of the shallow trench or etching process parameters.

[0154] The following description continues with the example of a deep trench filled with a second material deposited within it. The second material deposited within the deep trench creates a gap at the central axis of the trench, which is the same as the first case of filling the deep trench. The subsequent formation of the first trench isolation structure and the interlayer medium layer is the same.

[0155] Then, as Figure 26 As shown, a fourth photoresist layer 25 is coated on the third hard mask layer 24, and an exposure trap is used to define the area on the third hard mask layer 24 where a shallow trench needs to be formed. According to the depth and shape required for etching the shallow trench, a shallow trench 10 is formed through the third hard mask layer 24, the third passivation oxide layer 23, and to a first predetermined position on the second epitaxial layer 06 of the semiconductor substrate by an etching process.

[0156] After that, remove Figure 26 The fourth photoresist layer 25, as shown, extends until the surface of the third hard mask layer 24 is exposed. A first material is deposited on the semiconductor substrate forming the shallow trench, and the deposited first material at least fills the shallow trench. The shallow trench filled with the first material is a first trench isolation structure.

[0157] like Figure 27 As shown, the deposited first material includes a first portion of first material 11-1 located inside the shallow trench and a second portion of first material located on the surface of the third hard mask layer 24 on the semiconductor substrate, also referred to as the first material layer 11-2. Therefore, the first material layer 11-2 may contain particles or undulations, thus requiring removal of the first material layer to achieve a smooth surface. The process also includes removing the first material from the semiconductor substrate, with the removal process stopping at the third hard mask layer.

[0158] The removal of the first material may include at least one of the following methods: removing the first material layer on the semiconductor substrate by etching; or removing the first material layer on the semiconductor substrate by a polishing process. Figure 28 A schematic diagram is shown showing the removal of the first material layer 11-2 on the semiconductor substrate, exposing the third hard mask layer 24. The etching rate of the first material layer differs from the etching rate of the hard mask layer; the time to stop the etching process can be determined by the change in the etching rate during the etching of the first material layer. In this embodiment, chemical mechanical polishing is selected, which combines chemical reaction and mechanical abrasion to achieve higher flatness and smoothness.

[0159] Then, the third hard mask layer on the semiconductor substrate is removed, while the third passivation oxide layer is retained; polysilicon is filled on the third passivation oxide layer; an interlayer dielectric layer is formed on the first trench isolation structure, including: forming the interlayer dielectric layer on the surface of a portion of the third passivation oxide layer and the surface of the polysilicon on the semiconductor substrate.

[0160] Figure 29The purpose of retaining the third passivation oxide layer 23 in order to remove the third hard mask layer 24 is to prevent the silicon surface from being contaminated or oxidized during the subsequent polysilicon filling process, reduce the interface state density, isolate the metal layer, avoid short circuits, and alleviate the mechanical stress inside the device.

[0161] Figure 30 Polysilicon 12 is filled on the surface of the third passivation oxide layer 23 and on the surface of the shallow trench that has been filled with the first material to form a gate electrode. The third passivation oxide layer serves as the gate dielectric, and the polysilicon covers it to form an electrode, thus forming a complete MOS (Metal Oxide Semiconductor) structure.

[0162] also, Figure 31 A schematic diagram of the formed interlayer dielectric layer 13 is shown. Below the interlayer dielectric layer are a third passivation oxide layer and a second epitaxial layer. The third passivation oxide layer is used to protect the second epitaxial layer, on which BCD devices, resistors, capacitors, etc., are integrated. Above the interlayer dielectric layer is a first metal line, and above the first metal line is an intermetallic dielectric layer.

[0163] Therefore, the interlayer dielectric layer is an insulating material that vertically isolates the active devices integrated on the second epitaxial layer from the first metal line, preventing short circuits or signal crosstalk. Subsequent processes may incorporate multiple interlayer dielectric layers, each serving as an insulating material to isolate two vertically adjacent metal interconnects.

[0164] The above describes the process of forming the first and second trench isolation structures using the second method.

[0165] The method for fabricating a BCD semiconductor device provided in this application first performs ion implantation and thermal annealing processes in a semiconductor substrate to form a buffer layer at a predetermined depth in the semiconductor substrate. Then, an epitaxial layer is formed on the semiconductor substrate, wherein a second epitaxial layer is used to integrate the BCD device, and a first trench isolation structure is formed on the second epitaxial layer of the semiconductor substrate. An interlayer dielectric layer is formed on the second epitaxial layer, using the interlayer dielectric layer to isolate the BCD device from a first metal line above the interlayer dielectric layer in the vertical direction. Deep trenches are etched on the interlayer dielectric layer and filled with a second material to form a second trench isolation structure with a trench depth located at a predetermined depth of the buffer layer in the semiconductor substrate. The first and second trench isolation structures physically isolate the BCD device in the lateral direction. Furthermore, in the above process, the ion implantation and thermal annealing processes are performed first to form the buffer layer in the semiconductor substrate, followed by the formation of the first and second trench isolation structures. This allows the lattice damage caused by the ion implantation process and the repair of the damaged lattice by the thermal annealing process to be performed earlier. Therefore, on the one hand, the thermal annealing process can prevent the resistance value of the polysilicon resistor in the BCD device region from deviating from its set value. On the other hand, performing the thermal annealing process can repair damaged crystal lattices, reduce lattice defects, and improve the breakdown voltage of the second trench isolation structure. Thus, the above methods can improve the breakdown voltage performance of the BCD device. This reduces defects present in the BCD device fabrication process and improves the electrical stability of the BCD device.

[0166] A second embodiment of this application provides a BCD semiconductor device, comprising: a conductive semiconductor substrate, a buffer layer formed in a predetermined depth region of the semiconductor substrate by implanting conductive ions and performing thermal annealing, an epitaxial layer on the semiconductor substrate, a first trench isolation structure and a second trench isolation structure formed on the semiconductor substrate, wherein the second trench isolation structure is used to isolate different BCD devices on the semiconductor substrate, the trench depth of the second trench isolation structure extends at least to the buffer layer, and the buffer layer at the bottom of the second trench isolation structure is used to improve the breakdown voltage performance between BCD devices.

[0167] First, ion implantation and thermal annealing processes are performed on a semiconductor substrate to form a buffer layer at a predetermined depth. Then, an epitaxial layer is formed on the semiconductor substrate for integrating BCD devices. A first trench isolation structure is formed on the epitaxial layer, and a second trench isolation structure, intersecting with a portion of the first trench isolation structure, is formed on the semiconductor substrate. The depth of the second trench isolation structure is greater than that of the first trench isolation structure. The bottom of the trench in the second trench isolation structure is located at the predetermined depth of the buffer layer. This method, by performing the ion implantation and thermal annealing processes beforehand, avoids performing these processes after the formation of the second trench isolation structure and the BCD device. Therefore, it prevents the resistance value of the polysilicon resistor in the BCD device region from deviating from its predetermined value due to thermal annealing. Furthermore, thermal annealing can repair damaged lattices, reduce lattice defects, and improve the breakdown voltage of the second trench isolation structure, thereby preventing the BCD device from breaking down at lower voltages and improving its breakdown voltage performance.

[0168] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for fabricating a BCD semiconductor device, characterized in that, The method includes: Provide conductive semiconductor substrates; An ion implantation process is performed to implant conductive ions into a defined depth region in the semiconductor substrate, followed by thermal annealing to form a buffer layer. An epitaxial layer is formed on the semiconductor substrate on which the buffer layer is formed; A first trench isolation structure and a second trench isolation structure are formed on the semiconductor substrate on which the epitaxial layer is formed, wherein the second trench isolation structure is used to isolate different devices of BCD on the semiconductor substrate; The trench depth of the second trench isolation structure extends at least to the buffer layer, and the buffer layer at the bottom of the second trench isolation structure is used to improve the withstand voltage performance between BCD devices.

2. The method according to claim 1, characterized in that, Prior to performing the ion implantation process, the method further includes forming a protective layer on the semiconductor substrate, wherein the protective layer is a substrate oxide layer.

3. The method according to claim 1, characterized in that, The implantation of conductive ions into a defined depth region in the semiconductor substrate includes: Conductive ions are implanted throughout the entire surface of the semiconductor substrate; or, The target region for conductive ion implantation is defined on the surface of the semiconductor substrate using a photolithography process, and conductive ions are implanted into the target region, which is the region corresponding to the second trench isolation structure.

4. The method according to claim 1, characterized in that, The injected conductive ions include at least one of the following: arsenic, phosphorus, boron, and argon.

5. The method according to claim 2, characterized in that, The formation of an epitaxial layer on the semiconductor substrate on which the buffer layer is formed includes: A first epitaxial layer of the semiconductor substrate is formed on the substrate oxide layer; An N-type buried layer is formed at a designated location on the first epitaxial layer; A second epitaxial layer is formed on the first epitaxial layer and the N-type buried layer.

6. The method according to claim 1, characterized in that, The process of forming a first trench isolation structure and a second trench isolation structure on the semiconductor substrate on which the epitaxial layer is formed includes: The first trench isolation structure is formed on the epitaxial layer of the semiconductor substrate; An interlayer dielectric layer is formed on the first trench isolation structure; A second trench isolation structure is formed on a semiconductor substrate on which the interlayer dielectric layer is formed, wherein the bottom of the trench of the second trench isolation structure is located at a predetermined depth of the cache layer inside the semiconductor substrate.

7. The method according to claim 6, characterized in that, The formation of a first trench isolation structure on the epitaxial layer of the semiconductor substrate includes: A first passivation oxide layer and a first hard mask layer are formed on the epitaxial layer of the semiconductor substrate; The area where shallow trenches need to be formed is defined on the first hard mask layer using photolithography. An etching process is performed on the region on the first hard mask layer where a shallow trench needs to be formed, to form a shallow trench on the epitaxial layer of the semiconductor substrate. A first material is deposited on the semiconductor substrate forming the shallow trench to obtain the first trench isolation structure.

8. The method according to claim 7, characterized in that, The first material and the first hard mask layer on the semiconductor substrate are removed sequentially, and the removal process stops at the first passivation oxide layer; Polycrystalline silicon is filled onto the first passivation oxide layer; The step of forming an interlayer dielectric layer on the first trench isolation structure includes: The interlayer dielectric layer is formed on the surface of the first passivation oxide layer and the surface of the polycrystalline silicon in a portion of the semiconductor substrate.

9. The method according to claim 6, characterized in that, The step of forming the second trench isolation structure on the semiconductor substrate on which the interlayer dielectric layer is formed includes: The area where deep trenches need to be formed is defined on the interlayer dielectric layer using a photolithography process; An etching process is performed on the area on the interlayer dielectric layer where a deep trench needs to be formed, to form a deep trench on the semiconductor substrate, wherein the bottom of the deep trench extends to a predetermined depth position of the buffer layer; A second material is deposited on the semiconductor substrate forming the deep trench to obtain the second trench isolation structure.

10. The method according to claim 9, characterized in that, The deposited second material at least fills the deep trench; The method further includes: removing the second material on the semiconductor substrate, with the removal process stopping at the interlayer dielectric layer.

11. The method according to claim 9, characterized in that, Also includes: The deposited second material forms a gap at the central axis of the deep trench; A second material oxide layer corresponding to the second material is formed at the gap, and the formed second material oxide layer at least fills the gap. The second material oxide layer and the second material on the semiconductor substrate are removed sequentially, and the removal process stops at the interlayer dielectric layer.

12. The method according to claim 1, characterized in that, The process of forming a first trench isolation structure and a second trench isolation structure on the semiconductor substrate on which the epitaxial layer is formed includes: A second trench isolation structure is formed on the semiconductor substrate; The first trench isolation structure is formed in the top preset area corresponding to the second trench isolation structure; An interlayer dielectric layer is formed on the first trench isolation structure; The bottom of the trench in the second trench isolation structure is located at a set depth region of the buffer layer inside the semiconductor substrate.

13. The method according to claim 12, characterized in that, The formation of the second trench isolation structure on the semiconductor substrate includes: A second passivation oxide layer and a second hard mask layer are formed on the epitaxial layer of the semiconductor substrate; The area where deep trenches need to be formed is defined on the second hard mask layer using a photolithography process; An etching process is performed on the area on the second hard mask layer where a deep trench needs to be formed, to form a deep trench on the semiconductor substrate, wherein the bottom of the deep trench extends to a set depth position of the buffer layer. A second material is deposited on the semiconductor substrate forming the deep trench to obtain the second trench isolation structure; The second material on the semiconductor substrate is removed, and the removal process stops at the second hard mask layer.

14. The method according to claim 13, characterized in that, Also includes: The second hard mask layer and the second passivation oxide layer are removed sequentially; The step of forming the first trench isolation structure in the top preset area corresponding to the second trench isolation structure includes: A third passivation oxide layer and a third hard mask layer are re-formed on the semiconductor substrate on which the second trench isolation structure is formed; The area where shallow trenches need to be formed is defined on the third hard mask layer using a photolithography process; An etching process is performed on the region on the third hard mask layer where the shallow trench needs to be formed, and the shallow trench is formed on the epitaxial layer of the semiconductor substrate. A first material is deposited on the semiconductor substrate forming the shallow trench to obtain the first trench isolation structure.

15. The method according to claim 14, characterized in that, Also includes: The first material and the third hard mask layer on the semiconductor substrate are removed sequentially, while the third passivation oxide layer is retained; Polycrystalline silicon is filled onto the third passivation oxide layer; The step of forming an interlayer dielectric layer on the first trench isolation structure includes: The interlayer dielectric layer is formed on the surface of the third passivation oxide layer and the surface of the polycrystalline silicon in a portion of the semiconductor substrate.

16. A BCD semiconductor device, fabricated by any one of the methods of claims 1-15, characterized in that, include: A conductive semiconductor substrate, a buffer layer formed by implanting conductive ions and performing thermal annealing in a predetermined depth region of the semiconductor substrate, an epitaxial layer on the semiconductor substrate, a first trench isolation structure and a second trench isolation structure formed on the semiconductor substrate, wherein the second trench isolation structure is used to isolate different devices of a BCD on the semiconductor substrate, the trench depth of the second trench isolation structure extends at least to the buffer layer, and the buffer layer at the bottom of the second trench isolation structure is used to improve the breakdown voltage performance between BCD devices.

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