Preparation method of gate oxide transition layer for integrated circuit advanced node SiGe channel field effect transistor

Abstract

The invention discloses a gate oxide transition layer preparation method for an integrated circuit advanced node SiGe channel field effect transistor, and belongs to the technical field of semiconductor device preparation. According to the method, for a thermal oxidation step before SiGe channel gate oxide deposition, conventional rapid thermal oxidation annealing is replaced with laser thermal oxidation annealing, and selective thermal oxidation of a logic device area is achieved by adjusting laser beam spots, wavelength and nanosecond pulse parameters. Laser annealing can be completed within milliseconds, germanium within 1 nm on the surface of the SiGe channel is promoted to be analyzed in the form of GeO gas, residual Si forms a pure silicon oxide layer, and a low-germanium SiGe1 layer smaller than or equal to 1 nm and an original SiGe2 layer are sequentially formed below the pure silicon oxide layer. The problems of non-uniform germanium enrichment, GeOx trap defects and non-SiGe region damage caused by conventional high-temperature oxidation are solved, the grid interface state, the carrier mobility and the stability of the field effect transistor are optimized, and the field effect transistor is suitable for manufacturing node devices of 22 nm and below 22 nm.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication technology, and particularly relates to a method for fabricating a gate oxide transition layer for SiGe channel field-effect transistors used in advanced nodes of integrated circuits. Background Technology

[0002] In advanced nodes of integrated circuits, SiGe material has become a key material for channel engineering due to its ability to improve the hole mobility of p-type field-effect transistors. After the SiGe channel is fabricated, it needs to undergo thermal oxidation treatment before gate oxide deposition to form an extremely thin (typically <2nm) silicon oxide layer as a transition layer between the gate oxide and the SiGe channel to optimize interface characteristics.

[0003] In existing technologies, this thermal oxidation step generally employs rapid thermal oxidation annealing, i.e., treatment at temperatures above 900°C in an oxygen atmosphere. However, in a high-temperature, high-oxygen environment, germanium atoms in SiGe are prone to uneven enrichment, and GeO-containing compounds are formed during the oxidation process. x The mixed oxide layer introduces numerous interface trap defects, causing performance degradation in SiGe channels. Simultaneously, the high-temperature, high-oxygen environment can cause oxidation damage or thermal stress accumulation in non-SiGe regions of the chip (such as the silicon-based structure of memory cells), narrowing the process selection window and reducing overall chip yield. Therefore, there is an urgent need for a method that can precisely control the thermal oxidation region, reduce the thermal budget, and avoid GeO... x Improved processes to address defects and meet the stringent requirements of 22nm and below nodes. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing rapid thermal oxidation annealing methods by providing a method for fabricating gate oxide transition layers for SiGe channel field-effect transistors in advanced nodes of integrated circuits, thereby achieving selective, low-damage, and high-purity gate oxide transition layer fabrication.

[0005] The objective of this invention is achieved through the following technical solution: a method for fabricating a gate oxide transition layer for SiGe channel field-effect transistors in advanced nodes of integrated circuits. This method, after the SiGe channel fabrication and before gate oxide deposition, employs laser thermal oxidation annealing instead of conventional rapid thermal oxidation annealing. Specifically, it includes:

[0006] A SiGe channel structure is prepared, wherein the percentage of germanium atoms in the SiGe channel is 25%-60% and the thickness is 15-50 nm, serving as the channel basis for a field-effect transistor.

[0007] Before gate oxide deposition, the SiGe channel is subjected to laser thermal oxidation annealing in a mixed atmosphere of nitrogen and oxygen. This high-temperature oxidation, occurring in an extremely short time (less than 10 ms), preferentially oxidizes Si to form silicon oxide, while the subsequently oxidized germanium can only form GeO, which is then decomposed at high temperature, resulting in high-purity SiO2. Simultaneously, the formation of Si-O bonds significantly reduces the surface energy of the SiGe channel. This thermodynamic driving force causes silicon in the SiGe to move to the surface during annealing, forming a low-germanium region less than 1 nm thick under the SiO2 layer. These two factors greatly improve the interface performance of the channel. Specifically, the oxygen partial pressure in the mixed atmosphere is controlled at 0.1-0.5 atm, and a laser with a wavelength of 200-400 nm is used to irradiate the SiGe channel surface with nanosecond-level pulses. The pulse width is 10-100 ns, and the laser energy density is 0.3-1.5 J / cm². 2 The total annealing time is controlled within 1-10ms, and the thermal oxidation area is limited to the logic device area of ​​the chip by adjusting the laser beam size.

[0008] After laser thermal oxidation annealing, a layered structure is formed on the surface of the SiGe channel: from the surface to the inside, there are pure silicon oxide layer (SiO2), low germanium SiGe layer (SiGe1), and original SiGe layer (SiGe2). The thickness of the pure silicon oxide layer is ≤2nm, the thickness of the SiGe1 layer is ≤1nm, and the percentage of germanium atoms in the SiGe1 layer is 5%-15% lower than that in the SiGe2 layer.

[0009] Furthermore, the wavelength of the laser is selected from 200-400nm, preferably 248nm, 308nm or 355nm, and the laser beam diameter can be adjusted to 5-500μm to achieve selective thermal oxidation of the logic device area and avoid irradiating the non-SiGe area of ​​the chip.

[0010] Furthermore, the local instantaneous temperature during laser action reaches 1000-1200℃, and the heat diffusion depth is ≤10nm, avoiding thermal impact on the substrate and other films below the SiGe channel.

[0011] The core improvement of this invention is the replacement of conventional rapid thermal oxidation annealing with laser thermal oxidation annealing. The technical principle is as follows:

[0012] Selective heating: By adjusting the laser beam size (matching the logic device area), thermal oxidation is performed only on the logic region where the SiGe channel is located, avoiding irradiation of non-SiGe regions;

[0013] Instantaneous high-temperature desorption: Nanosecond-level pulsed laser (pulse width 10-100ns) is used to instantly raise the SiGe surface to 1000-1200℃ within milliseconds (1-10ms), causing germanium within 1nm of the surface to desorb in the form of GeO gas (reaction: 2Ge+O2→2GeO↑), thus avoiding germanium enrichment.

[0014] Formation of pure silicon oxide: After high-temperature desorption, the silicon remaining combines with oxygen to form a pure SiO2 layer. Furthermore, the short-duration laser treatment inhibits the diffusion of germanium atoms into the oxide layer, preventing the spread of GeO. x defect;

[0015] Gradient structure construction: The thermodynamic drive of laser annealing (Si-O bond formation energy is lower than Ge-O bond) causes silicon atoms to migrate to the surface, forming a low-germanium SiGe1 layer (germanium content is 5%-15% lower than the original SiGe2 layer) ≤1nm below the SiO2 layer, thus optimizing the interface quality.

[0016] The present invention also provides a gate stacking structure for a SiGe channel field-effect transistor prepared by the above method, the gate stacking structure comprising:

[0017] Substrate;

[0018] The SiGe2 layer (original SiGe channel) is located on the substrate;

[0019] The SiGe1 layer located on top of the SiGe2 layer (with a germanium atom percentage lower than that of the SiGe2 layer by 5%-15% and a thickness ≤1nm);

[0020] A pure silicon oxide layer (SiO2, thickness ≤2nm, GeO) is located on the SiGe1 layer. x Content ≤0.1%

[0021] The gate oxide layer and gate electrode are located on a pure silicon oxide layer.

[0022] The beneficial effects of this invention are:

[0023] 1. Solved the problem of uneven germanium enrichment and GeO caused by conventional rapid thermal oxidation. x Due to defects, the interface trap density of the pure silicon oxide layer prepared by this method is ≤1×10⁻⁶. 11 cm -2 ·eV -1 The carrier mobility of the device is improved by 15%-25%;

[0024] 2. The selective irradiation of the laser beam protects the non-SiGe channel device area, expanding the process selection window by more than 20%;

[0025] 3. Millisecond-level short-time annealing reduces the thermal budget, avoids thermal impact on the substrate and other film layers, and is compatible with integrated circuit processes at 22nm and below.

[0026] 4. The resulting gradient transition structure optimizes the interface characteristics between the channel and the gate oxide, improves device stability, and is suitable for the manufacture of advanced node logic devices. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flow chart of the laser thermal oxidation annealing process of the present invention;

[0029] Figure 2 This is a schematic diagram of the SiGe channel structure fabricated according to device requirements in this invention;

[0030] Figure 3 This is a schematic diagram of the layered structure of the SiGe channel after laser thermal oxidation according to the present invention;

[0031] Figure 4 This is a schematic diagram of the gate stacking structure after the completion of the device of the present invention;

[0032] Figure 5 The SiO2 layer GeO of the method of this invention and conventional methods x Content comparison chart;

[0033] Figure 6 The diagram shows the voltage-capacitance results of the gate stack in the method of this invention and the conventional method. Detailed Implementation

[0034] The following describes some of the possible embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. It is not intended to identify the key or decisive elements of the present invention or to limit the scope of protection. It is readily understood that, based on the technical solutions of the present invention, those skilled in the art can propose other interchangeable implementations without changing the essential spirit of the present invention. Therefore, the following detailed descriptions and accompanying drawings are merely exemplary illustrations of the technical solutions of the present invention and should not be considered as the entirety of the present invention or as limitations or restrictions on the technical solutions of the present invention.

[0035] Figure 1The process flow diagram for fabricating a SiGe channel gate stack structure based on laser thermal oxidation to prepare a gate oxide transition layer, provided for embodiments of the present invention, specifically includes the following steps:

[0036] First, the fabrication of the SiGe channel includes the following steps:

[0037] (a) An epitaxial SiGe layer is grown on a silicon substrate, wherein the thickness of the SiGe layer is 15-50 nm. In this embodiment, the thickness of the SiGe layer is selected as 20 nm, but it is not limited thereto. In other embodiments, the thickness of the SiGe layer can be adjusted as needed. In addition, the percentage of germanium atoms in the SiGe layer is 25%-60%. In this embodiment, it is selected as 25%, but it is not limited thereto. In other embodiments, the percentage of germanium atoms can be adjusted as needed.

[0038] (b) The desired SiGe channel range and shape are obtained through etching. This region can typically be a planar device structure channel shape or a 3D structure such as a fin shape. In this embodiment, a planar device structure is used, with a length of 1 μm and a width of 200-400 nm. Figure 2 As shown. In other embodiments, the etching shape and size can be adjusted according to device requirements.

[0039] Secondly, the fabrication of the gate stack structure includes the following steps:

[0040] (a) Preparation of the gate oxide transition layer using laser thermal oxidation: The surface was cleaned with a standard RCA solution to remove surface contaminants and activate the surface. The SiGe channel substrate wafer was placed in a laser thermal treatment system, such as a laser annealing furnace. A mixture of oxygen (O2) and nitrogen (N2) with an O2 / N2 ratio of 2000 / 2000 ccm was introduced as the reaction atmosphere. The oxygen pressure was controlled at 0.5 atm. The annealing region was determined using an autofocus system. A 248 nm KrF excimer laser was selected, with a beam diameter of 50 μm and pulse parameters of 50 ns width and 0.5 J / cm². 2 In this embodiment, the total laser action time is 5ms.

[0041] (b) Deposition of high k-value gate oxide layer.

[0042] (c) Gate metal deposition.

[0043] Figure 3 This is a schematic diagram of the layered structure of the SiGe channel after laser thermal oxidation according to the present invention. It includes a SiO2 layer formed after laser thermal oxidation, a SiGe1 region with low germanium concentration, and a raw SiGe2 region.

[0044] Figure 4 This is a schematic diagram of the gate stacking structure after the device gate structure has been fabricated.

[0045] Figure 5 These are X-ray photoelectron spectroscopy (XPS) results of gate oxide transition layers prepared using the method of this invention, the conventional thermal oxidation method, and the method of this invention but with an oxygen partial pressure exceeding 0.5 atm. It can be seen that, compared with the conventional method, the GeO in the gate oxide transition layer prepared using the method of this invention... x The content decreases significantly and can be ignored, but when the oxygen partial pressure is greater than 0.5 atm, GeO... x The content actually increases, which will lead to interface deterioration. Figure 6 To use conventional thermal oxidation method ( Figure 6 (a) in the present invention and the method of the present invention ( Figure 6 (b) shows the preparation of the gate oxide transition layer, and the CV curve of the final gate stack. The results indicate that, compared to conventional thermal oxidation, the method of this invention completely eliminates the CV-hump in the weak inversion region, significantly reduces interface traps, and achieves an interface trap density ≤1×10⁻⁶. 11 cm -2 ·eV -1 .

[0046] It should be noted that in the above-mentioned in-situ germanium enrichment process, the purpose of introducing N2 is to dilute the O2 content. This is because supersaturated O2 provides sufficient oxygen to Si and Ge atoms, causing Ge to oxidize into GeO2 instead of GeO. This results in germanium being unable to be desorbed and will degrade from GeO2 to GeO in subsequent device fabrication or operation. x This leads to a deterioration in device performance.

[0047] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, alterations, deletions of some features, additions of features, or recombinations of features to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the innovative principles of the present invention shall still fall within the scope of the technical solutions of the present invention.

Claims

1. A method for fabricating a gate oxide transition layer for SiGe channel field-effect transistors in advanced nodes of integrated circuits, characterized in that, Includes the following steps: Prepare a SiGe channel structure, wherein the percentage of germanium atoms in the SiGe channel is 25%-60% and the thickness is 15-50 nm; Before gate oxide deposition, the SiGe channel undergoes laser thermal oxidation annealing. The laser thermal oxidation annealing environment is a mixed atmosphere of nitrogen and oxygen, with the oxygen partial pressure controlled at 0.1-0.5 atm. A laser with a wavelength of 200-400 nm is used to irradiate the SiGe channel surface with nanosecond-level pulses. The pulse width is 10-100 ns, and the laser energy density is 0.3-1.5 J / cm². 2 The total annealing time is controlled within 1-10ms, and the thermal oxidation area is limited to the logic device area of ​​the chip by adjusting the laser beam size. After laser thermal oxidation annealing, a layered structure is formed on the surface of the SiGe channel: from the surface to the inside, there are pure silicon oxide layer, low germanium SiGe layer denoted as SiGe1, and original SiGe layer denoted as SiGe2. The thickness of the pure silicon oxide layer is ≤2nm, the thickness of the SiGe1 layer is ≤1nm, and the percentage of germanium atoms in the SiGe1 layer is 5%-15% lower than that in the SiGe2 layer.

2. The method according to claim 1, characterized in that, The laser beam diameter can be adjusted to 5-500μm to achieve selective thermal oxidation of the logic device area and avoid irradiating the non-SiGe areas of the chip.

3. The method according to claim 1, characterized in that, During the laser thermal oxidation annealing process, the local instantaneous temperature reaches 1000-1200℃ when the laser is applied, and the heat diffusion depth is ≤10nm, so as to avoid thermal impact on the substrate and other films below the SiGe channel.

4. The method according to claim 1, characterized in that, The pure silicon oxide layer serves as a transition layer between the gate oxide and the channel, GeO x Content ≤0.1%, surface roughness Ra≤0.2nm, interface trap density≤1×10¹¹cm⁻¹ -2 ·eV -1 .

5. A gate stacking structure for a SiGe channel field-effect transistor prepared by the method according to any one of claims 1-4, characterized in that, include: A substrate, a SiGe2 layer on the substrate, a SiGe1 layer on the SiGe2 layer, a pure silicon oxide layer on the SiGe1 layer, a gate oxide layer on the pure silicon oxide layer, and a gate electrode.

6. The application of the method according to any one of claims 1-4 in integrated circuits at 22nm and below nodes, characterized in that, Used for gate oxide pretreatment of logic region field-effect transistors, compatible with device fabrication processes in non-SiGe regions.

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