Power semiconductor device including beryllium metallization

Abstract

Semiconductor devices and methods are provided. In one example, a semiconductor device includes an active region including one or more active semiconductor cells. The semiconductor device includes a metallization structure on an active region. The metallization structure includes beryllium.

Description

[0001] Priority requirements This application is based on and claims priority to U.S. Patent Application No. 18 / 304,869, filed April 21, 2023. This application claims priority and the entire contents of the referenced application, which are incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to power semiconductor devices. Background Technology

[0003] A wide variety of power semiconductor devices are known in the art, including, for example, power metal-oxide-semiconductor field-effect transistors (“MOSFETs”), insulated-gate bipolar transistors (“IGBTs”), and various other devices. These power semiconductor devices are typically fabricated from wide-bandgap semiconductor materials, such as silicon carbide or gallium nitride-based materials. Hereinafter, the term “wide-bandgap semiconductor” encompasses any semiconductor with a bandgap of at least 1.4 eV. Power semiconductor devices are designed to selectively block or pass large voltages and / or currents. For example, in the blocking state, a power semiconductor device can be designed to withstand potentials of hundreds or thousands of volts. Summary of the Invention

[0004] Various aspects and advantages of embodiments of this disclosure will be set forth in part in the description which follows, or may be learned from the description or by practice of the embodiments.

[0005] One example aspect of this disclosure relates to a semiconductor device. The semiconductor device includes an active region comprising one or more active semiconductor cells. The semiconductor device includes a metallization structure on the active region. The metallization structure includes beryllium.

[0006] Another example aspect of this disclosure relates to a semiconductor device. The semiconductor device includes an active region comprising one or more silicon carbide-based MOSFETs. The semiconductor device includes a metallization structure on the active region. The metallization structure includes bonding pads associated with gate contacts, source contacts, or drain contacts of the semiconductor device. The metallization structure includes beryllium.

[0007] Another example aspect of this disclosure relates to a method. The method includes depositing a metallization structure on an active region comprising one or more wide-bandgap semiconductor cells. The metallization structure comprises beryllium.

[0008] These and other features, aspects, and advantages of the various embodiments will become more readily understood with reference to the following description and the appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the relevant principles. Attached Figure Description

[0009] This specification provides a detailed discussion of the embodiments for those skilled in the art, with reference to the accompanying drawings, wherein: Figure 1 A perspective view of a semiconductor device including a metallized structure according to an exemplary embodiment of the present disclosure is depicted. Figure 2 A cross-sectional view of an example semiconductor device including a metallized structure according to an exemplary embodiment of the present disclosure is depicted; Figure 3 An example metallization structure of a semiconductor device according to an exemplary embodiment of the present disclosure is depicted; Figure 4 An example metallization structure of a semiconductor device according to an exemplary embodiment of the present disclosure is depicted; Figure 5 Depicting Figure 4 A cross-sectional view of a semiconductor device in a semiconductor device; Figure 6 An example semiconductor package depicting a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 7 An example semiconductor package depicting a semiconductor device according to an exemplary embodiment of the present disclosure; and Figure 8 A flowchart depicts an example method according to an example implementation of this disclosure. Detailed Implementation

[0010] Reference will now be made in detail to embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and not by way of limitation of this disclosure. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments without departing from the scope or spirit of this disclosure. For example, a feature partially illustrated or described as one embodiment may be used in conjunction with another embodiment to produce yet another embodiment. Therefore, aspects of this disclosure are intended to cover such modifications and variations.

[0011] Examples of this disclosure relate to semiconductor devices, and more specifically, to semiconductor devices having metallized structures including beryllium (such as beryllium alloys). As used herein, the term "alloy" refers to a mixture of metallic elements.

[0012] "Metalization" is any layer, structure, or other portion of a semiconductor device, semiconductor die, or semiconductor package incorporating metal for thermal and / or electrical conduction. "Metalization" can include, for example, contacts, interconnects, bonding pads, back metallization, metal layers, or metal coatings.

[0013] Semiconductor devices may include, for example, semiconductor dies. A semiconductor die may include one or more active semiconductor regions and one or more metallization structures. An active region may include one or more active semiconductor cells having an individual "unit cell" semiconductor device (such as a MOSFET, Schottky diode, or high electron mobility transistor device (HEMT)). The semiconductor die may be disposed within a semiconductor package. The semiconductor package may include, for example, a housing (e.g., epoxy molding compound (EMC)), a base (such as a lead frame), and connection structures between the semiconductor die and the base (e.g., die attachment material and / or wiring junctions). In some examples, a passivation layer (e.g., silicon nitride and / or polyimide passivation layer) may be disposed on the semiconductor die.

[0014] Semiconductor dies may be based on wide-bandgap semiconductor materials. Wide-bandgap semiconductor materials have a bandgap greater than about 1.40 eV, such as silicon carbide and / or group III nitrides (e.g., gallium nitride). For example, in some examples, the active semiconductor cell may include one or more silicon carbide-based MOSFETs. In some examples, the active semiconductor cell may include one or more silicon carbide-based Schottky diodes. In some examples, the active semiconductor cell may include one or more group III nitride-based transistor devices, such as gallium nitride-based high electron mobility transistor devices. The active semiconductor cell may include other devices, such as other wide-bandgap semiconductor devices, without departing from the scope of this disclosure.

[0015] Metallization structures in semiconductor devices can be used, for example, to provide conductive and / or thermal connections to active regions of the semiconductor device. Metallization structures may include, for example, one or more contacts, interconnects, bonding pads, back layers, metal layers, or metal coatings in the semiconductor device.

[0016] Power semiconductor devices can experience anomalies and / or failures attributable to deformation, delamination, displacement, and movement (e.g., glacial movement) of the copper and / or aluminum metallization structures. Additionally, cracks in the passivation layer of power semiconductor devices can be attributed to thermomechanical stresses on the semiconductor die surface during various reliability tests, such as thermal cycling (TC). Mismatches in the coefficient of thermal expansion (CTE) between the EMC and different portions of the semiconductor die, along with the high-temperature flexural modulus of the EMC, can induce shear stresses from the edges to the center of the semiconductor die, resulting in deformation, delamination, and / or ratcheting of the metallization structure. This can thus provide stress on the passivation layer and ultimately lead to defects or cracks within it.

[0017] In some power semiconductor device packages, aluminum-copper alloys have been introduced as alternative metallization materials to aluminum-based metallization structures. Aluminum-copper alloys exhibit slightly higher resistance to metal deformation and higher resistance to corrosion in the presence of ionic impurities. However, aluminum-copper alloy-based metallization structures can suffer from residual stress, thermal stress relaxation, and accelerated galvanic corrosion of aluminum, particularly at interfaces with interconnect structures such as wiring junctions. Furthermore, CTE mismatch between the metallization structure and other parts of the semiconductor die, including silicon nitride passivation layers or other passivation layers, remains a concern.

[0018] In high-power wiring bonding processes using thicker aluminum wire (e.g., 15 mils or 20 mils) or copper wire to achieve higher current carrying capacity, aluminum-copper alloys are also susceptible to damage. This can lead to further damage to the semiconductor die. For bonding pads with smaller thicknesses (e.g., about 4 µm), the damage may be even more significant. On the other hand, increased metallization pad thickness (e.g., about 5 µm to about 6 µm) can have adverse effects, such as the risk of metal migration. Furthermore, when aluminum-copper alloys are used in metallization structures, copper diffusion into the semiconductor die can cause reliability issues.

[0019] According to an example aspect of this disclosure, a semiconductor device may include a metallization structure. The metallization structure may include beryllium. For example, in some embodiments, the metallization structure may include a beryllium alloy. The metallization structure may include copper and beryllium (e.g., a copper-beryllium alloy). The metallization structure may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0020] In some examples, the metallized structure may include a ternary beryllium alloy. This ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may include cobalt, which can increase the microstructural stability of the metallized structure.

[0021] In some aspects of this disclosure, the metallization structure may be an electrode / contact (e.g., a source, drain, and / or gate contact). In some examples, the metallization structure may be an interconnect. In some examples, the metallization structure may be a bonding pad (e.g., for wiring bonding). In some examples, the metallization structure may provide a back metallization or other metallization layer.

[0022] In some examples, the mechanical and / or electrical properties of the metallized structure can be controlled and / or adjusted by the ratio of beryllium to other metals in the metallized structure. For example, the metallized layer may include about 0.1% to about 3% beryllium, such as about 0.2% to about 2% beryllium, such as about 0.2% to about 0.1% beryllium, such as about 0.2% to about 0.5% beryllium, such as about 0.5% beryllium.

[0023] Beryllium is a low-density metal with high thermal and electrical conductivity, high strength, high fatigue and corrosion resistance, and low response to magnetic fields. Beryllium can also act as a CTE moderator. Beryllium alloys (such as copper-beryllium alloys, aluminum-beryllium alloys, and ternary beryllium alloys) can possess highly stable tensile properties, even at high temperatures (e.g., in the range of approximately 250 °C to approximately 300 °C). The mechanical stability of these alloys remains intact over a wide temperature range, exhibiting inherent resistance to thermal stress relaxation at high temperatures and during various reliability tests (such as TC, high-temperature reverse bias (HTRB) testing, high-voltage-high-humidity high-temperature reverse bias (HV-H3TRB) testing, etc.). This reduces deformation, delamination, and / or ratcheting of the metallized structure, and thus reduces damage to the passivation layer. Furthermore, the corrosion resistance of beryllium metal alloys is expected to exceed that of aluminum and copper.

[0024] Various aspects of this disclosure provide technical effects and benefits. For example, beryllium-incorporated metallization structures according to examples of this disclosure can address various reliability challenges in high-performance semiconductor packages, such as aluminum sputtering, pad pitting, galvanic corrosion, passivation layer cracking, and displacement or deformation of the metallization structure. Metallization structures incorporating beryllium (e.g., beryllium alloys) can exhibit CTE values ​​similar to those of different portions of the semiconductor die, while resisting mechanical stresses imposed by, for example, the encapsulation material (EMC) of the semiconductor package. Furthermore, due to the improved structural robustness of beryllium-incorporated metallization structures, these alloys can increase the reliability of wiring bonding processes and can allow for reduced thickness of the metallization structure (e.g., the thickness of the bonding pads) without the risk of damaging underlying layers in the semiconductor die during wiring bonding processes.

[0025] In some examples, using a metallization structure with beryllium (e.g., a beryllium alloy) instead of aluminum or aluminum-copper alloys can reduce failures during semiconductor device testing. Additionally, this metallization structure can reduce delamination of the metallization structure. In some examples, using a metallization structure with beryllium (e.g., a beryllium alloy) instead of aluminum or aluminum-copper alloys can allow for thicker (e.g., 15 mils or 20 mils) wiring bond integration (Al or Cu wiring bonds) in the semiconductor package. In some examples, using a metallization structure with beryllium (e.g., a beryllium alloy) instead of aluminum or aluminum-copper alloys can enhance the metallization structure's ability to withstand EMC stresses without cracking of the passivation layer. In some examples, using a metallization structure with beryllium (e.g., a beryllium alloy) instead of aluminum or aluminum-copper alloys can reduce copper diffusion into the semiconductor die.

[0026] Additionally, aluminum metallization is typically deposited at temperatures ranging from approximately 400 °C to approximately 450 °C to achieve better film uniformity. However, temperatures of approximately 400 °C or higher can force grain recrystallization and thus growth to larger sizes, resulting in reduced mechanical strength. Adding beryllium can raise the recrystallization temperature by approximately 100 °C or higher, thereby increasing mechanical stability.

[0027] It will be understood that while the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will also be understood that the terms “comprise,” “comprising,” “include,” and / or “including,” when used herein, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be construed as having an idealized or overly formal meaning unless expressly defined herein.

[0030] It will be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or extending "on" another element, it may be directly on or directly extended onto that other element, or an intermediary element may be present. Conversely, when an element is referred to as being "directly on" or "directly" extending "on" another element, no intermediary element is present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to that other element, or an intermediary element may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intermediary element is present.

[0031] Relative terms (such as "below" or "above," or "upper" or "lower," or "horizontal," "lateral," or "vertical") may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to cover different orientations of the device other than those depicted in the figures.

[0032] Embodiments of this disclosure are described herein with reference to cross-sectional illustrations, which are schematic diagrams of idealized embodiments (and intermediate structures) of the invention. For clarity, the thicknesses of the layers and regions in the figures may be exaggerated. Additionally, variations relative to the shapes shown in the figures are expected to be attributable to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be construed as limited to the specific shapes of the regions illustrated herein, but will include shape deviations attributable to, for example, manufacturing processes. Similarly, it will be understood that dimensional variations are expected based on standard deviations during the manufacturing process. As used herein, “approximately” or “about” includes values ​​within 10% of the nominal value.

[0033] The same reference numerals always refer to the same elements. Therefore, other figures can be used to describe the same or similar numbers, even if they are neither mentioned nor described in the corresponding figures. Furthermore, other figures can be used to describe elements not indicated by reference numerals.

[0034] Some embodiments of the invention are described with reference to semiconductor layers and / or regions characterized by having a conductivity type (such as n-type or p-type), where conductivity type refers to the majority carrier concentration in the layer and / or region. Thus, n-type materials have a majority equilibrium concentration of negatively charged electrons, while p-type materials have a majority equilibrium concentration of positively charged holes. A material can be described using "+" or "-". " to indicate (e.g., in N+, N) P+, P N++, N P++, P (etc.) to indicate that it is relatively larger ("+") or smaller ("") compared to another layer or area. The majority carrier concentration is indicated by the sign of the majority carrier concentration. However, this notation does not imply the presence of a specific majority or minority carrier concentration in a layer or region.

[0035] Various aspects of this disclosure are discussed with reference to silicon carbide-based semiconductor structures. Those skilled in the art will understand using the disclosure provided herein that power semiconductor devices according to exemplary embodiments of this disclosure can be used with any semiconductor material, such as other wide-bandgap semiconductor materials, without departing from the scope of this disclosure. Example wide-bandgap semiconductor materials include silicon carbide (e.g., α-silicon carbide with a bandgap of 2.996 eV at room temperature) and group III nitrides (e.g., gallium nitride with a bandgap of 3.36 eV at room temperature).

[0036] Typical embodiments have been disclosed in the accompanying drawings and description, and although specific terminology has been used, it is used only in a general and descriptive sense and not for the purpose of limiting the scope set forth in the following claims.

[0037] Now, with reference to the accompanying drawings, exemplary embodiments of the present disclosure will be described.

[0038] Figure 1 An example semiconductor device 100 according to an exemplary embodiment of the present disclosure is depicted. The semiconductor device 100 may be, for example, a semiconductor die. The semiconductor device 100 may include a semiconductor structure 102 having an active region comprising one or more active semiconductor units (e.g., a silicon carbide-based MOSFET, a silicon carbide-based Schottky diode, a group III nitride-based HEMT, etc.). The semiconductor structure 102 may include a wide-bandgap semiconductor, such as silicon carbide and / or group III nitrides (e.g., GaN, AlGaN, etc.). The semiconductor structure 102 may include one or more epitaxial layers formed on a substrate, such as a silicon carbide substrate.

[0039] Semiconductor device 100 may include one or more metallization structures. These metallization structures may include, for example, bonding pads 104. Bonding pads 104 may be used to form electrical connections to semiconductor device 100 using interconnect structures such as wiring junctions. Bonding pads 104 may be disposed on an adhesion layer 106 to secure bonding pads 104 to semiconductor structure 102, thereby providing, for example, gate connections, source connections, Kelvin connections, sensor connections, or other suitable connections. For example, adhesion layer 106 may be titanium. In some embodiments, bonding pads 104 may have a thickness of about 4 µm or less.

[0040] In some examples, semiconductor device 100 may include a back metallization structure 108 on semiconductor structure 102. In some semiconductor packages, the back metallization structure 108 may be attached to a substrate (e.g., a lead frame of a semiconductor package) using, for example, a die attachment material to provide thermal and / or electrical connections (e.g., drain connections) for semiconductor device 100.

[0041] Semiconductor device 100 may include a passivation layer 110. Bonding pads 104 may be exposed through openings in the passivation layer 110. The passivation layer may include one or more suitable passivation materials, such as silicon nitride. In some examples, the passivation layer 110 may be a polymer, such as polyimide. In some examples, the passivation layer 110 may be SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, or other dielectric materials.

[0042] According to exemplary embodiments of this disclosure, the bonding pad 104 and / or the back metallization structure 108 may include beryllium. For example, the bonding pad 104 and / or the back metallization structure 108 may include beryllium. For example, in some embodiments, the bonding pad 104 and / or the back metallization structure 108 may include a beryllium alloy. The bonding pad 104 and / or the back metallization structure 108 may include copper and beryllium (e.g., a copper-beryllium alloy). The bonding pad 104 and / or the back metallization structure 108 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0043] In some examples, the bonding pad 104 and / or the back metallization structure 108 may include a ternary beryllium alloy. This ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may include cobalt, which can increase the microstructural stability of the metallization structure.

[0044] In an exemplary aspect of this disclosure, the bonding pad 104 and / or the back metallization structure 108 may include about 0.1% to about 3% beryllium, such as about 0.2% to about 2% beryllium, such as about 0.2% to about 0.1% beryllium, such as about 0.2% to about 0.5% beryllium, such as about 0.5% beryllium.

[0045] Figure 2 A cross-sectional view of at least a portion of a semiconductor device 120 according to an exemplary embodiment of the present disclosure is depicted. In some embodiments, Figure 2 The semiconductor device 120 shown may be Figure 1 A single unit cell of the active semiconductor cell of the semiconductor device 100.

[0046] As shown, semiconductor device 120 includes semiconductor structure 122. Semiconductor structure 122 may include one or more wide-bandgap semiconductor materials and may include doped and / or different epitaxial layer structures to form one or more active semiconductor cells for the semiconductor device (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, group III nitride-based HEMTs, etc.). Semiconductor structure 122 may include one or more epitaxial layers formed on a substrate, such as a silicon carbide substrate.

[0047] Semiconductor device 120 may include metallization structures, such as contacts for semiconductor device 120. Figure 2 In the example, the one or more metallization structures may include source contact 124, drain contact 126, and / or gate contact 128. A gate dielectric layer 130 (e.g., silicon dioxide) may be disposed between the gate contact 128 and the semiconductor structure 122. The semiconductor device 120 may include one or more passivation layers (e.g., silicon nitride layer, polyimide layer, etc.). For simplicity, in... Figure 2 These layers are not shown in the diagram.

[0048] According to an exemplary implementation of this disclosure Figure 2 At least a portion of one or more of the metallized structures (including at least a portion of one or more of the source contact 124, drain contact 126, and / or gate contact 128) may include beryllium. For example, in some embodiments, at least a portion of the source contact 124, drain contact 126, and / or gate contact 128 may include a beryllium alloy. At least a portion of the source contact 124, drain contact 126, and / or gate contact 128 may include copper and beryllium (e.g., a copper-beryllium alloy). At least a portion of the source contact 124, drain contact 126, and / or gate contact 128 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0049] In some examples, at least a portion of the source contact 124, drain contact 126, and / or gate contact 128 may comprise a ternary beryllium alloy. The ternary beryllium alloy may comprise aluminum (or copper), beryllium, and a ternary element. The ternary element may comprise silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may comprise cobalt, which can increase the microstructural stability of the metallized structure.

[0050] In an exemplary aspect of this disclosure, at least a portion of the source contact 124, the drain contact 126, and / or the gate contact 128 may include about 0.1% to about 3% beryllium, such as about 0.2% to about 2% beryllium, such as about 0.2% to about 0.1% beryllium, such as about 0.2% to about 0.5% beryllium, such as about 0.5% beryllium.

[0051] Figure 3An example metallization layer of a semiconductor device 140 is depicted, the semiconductor device including a top-side metallization layer 142 on a semiconductor structure 144. The semiconductor device 140 may also include a back-side metallization layer 146. The back-side metallization layer 146 may include a drain attachment pad 148 on the back side of the semiconductor structure 144. The semiconductor structure 144 may include one or more wide-bandgap semiconductor materials and may include doped and / or different epitaxial layer structures to form one or more active semiconductor cells for the semiconductor device (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, group III nitride-based HEMTs, etc.). The semiconductor structure 144 may include one or more epitaxial layers formed on a substrate, such as a silicon carbide substrate.

[0052] The top-side metallization layer 142 may include metallization structures including gate pads 150, gate channels 152, edge termination structures 154, source pads 156, and / or additional bonding pads 158 (e.g., source Kelvin bonding pads or sensor bonding pads). Multiple gate channels 152 (e.g., gate buses) may extend from the gate pads 150 to better distribute gate signals to the outer edges and center of the power semiconductor device 140. The edge termination structures 154 may surround the periphery of the power semiconductor device 140 to buffer the electric field, causing the voltage to decrease with distance.

[0053] Metallization layer 142 may include metallization pads (e.g., gate pad 150 and source pad 156) for power and signal interconnection with other components (e.g., base, lead frame, terminals, etc.), such that metallization layer 142 acts as a bonding layer of power semiconductor device 140. Gate pad 150 and / or source pad 156 may have a thickness of 4 µm or less. Signal interconnection with gate pad 150 may be achieved, for example, using wiring joints. Source pad 156 may be directly on the active region of semiconductor structure 144. Electrical interconnection with source pad 156 may be achieved using jigs or similar attachments that directly solder, sinter, or bond to source pad 156. Source pad 156 may serve as a source contact or other contact (e.g., ohmic contact, Schottky contact, etc.) of a semiconductor cell in the active region of semiconductor structure 144 of power semiconductor device 140.

[0054] The power semiconductor device 140 may include additional bonding pads 156 (e.g., for connection to wiring junctions or other connection structures). The additional bonding pads 156 may be used for, for example, source Kelvin connections and / or sensor connections of the semiconductor device 140.

[0055] According to an exemplary implementation of this disclosure Figure 3At least a portion of one or more of the metallized structures (including at least a portion of one or more of gate pad 150, gate channel 152, edge termination structure 154, source pad 156, additional bonding pad 158, and / or drain attachment pad 148) may include beryllium. For example, in some embodiments, at least a portion of one or more of gate pad 150, gate channel 152, edge termination structure 154, source pad 156, additional bonding pad 158, and / or drain attachment pad 148 may include a beryllium alloy. At least a portion of one or more of gate pad 150, gate channel 152, edge termination structure 154, source pad 156, additional bonding pad 158, and / or drain attachment pad 148 may include copper and beryllium (e.g., a copper-beryllium alloy). At least a portion of one or more of the gate pad 150, gate channel 152, edge termination structure 154, source pad 156, additional bonding pad 158 and / or drain attachment pad 148 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0056] In some examples, at least a portion of one or more of the gate pad 150, gate channel 152, edge termination structure 154, source pad 156, additional bonding pad 158, and / or drain attachment pad 148 may comprise a ternary beryllium alloy. The ternary beryllium alloy may comprise aluminum (or copper), beryllium, and a ternary element. The ternary element may comprise silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may comprise cobalt, which can increase the microstructural stability of the metallized structure.

[0057] In an exemplary aspect of this disclosure, at least a portion of one or more of the gate pad 150, gate channel 152, edge termination structure 154, source pad 156, additional bonding pad 158, and / or drain attachment pad 148 may include about 0.1% to about 3% beryllium, such as about 0.2% to about 2% beryllium, such as about 0.2% to about 0.1% beryllium, such as about 0.2% to about 0.5% beryllium, such as about 0.5% beryllium.

[0058] Figure 4 Example metallization layers of a semiconductor device 160 are depicted, including a plurality of top-side metallization layers on a semiconductor structure 162, including a first metallization layer 164 and a second metallization layer 166 overlapping at least a portion of the first metallization layer 164. An insulating layer 168 may be present between the first metallization layer 164 and the second metallization layer 166.

[0059] A first metallization layer 164 may be on a semiconductor structure 162. The semiconductor structure 162 may include one or more wide-bandgap semiconductor materials and may include doped and / or different epitaxial layer structures to form one or more active semiconductor cells for a semiconductor device (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, group III nitride-based HEMTs, etc.). The semiconductor structure 162 may include one or more epitaxial layers formed on a substrate (such as a silicon carbide substrate).

[0060] The first metallization layer 164 may include metallization structures including gate channels 170 and gate pathways 172. Multiple gate channels 170 (e.g., gate buses) are used to distribute gate signals through the semiconductor device 160. Figure 4 Multiple gate channels 170 in the middle form a gate channel network. Figure 4 The gate channel network in the diagram is a cross-shaped gate channel network. More specifically, the two gate channels may intersect each other in the central portion of the first metallization layer 164 and may be substantially perpendicular to each other. Additionally, the two gate channels may have substantially the same length or may have different lengths. Other suitable gate channel configurations / networks may be used without departing from the scope of this disclosure.

[0061] Gate path 172 can be used to transmit signals to gate channel 170. Gate path 172 may extend through the central portion of semiconductor device 150. However, other suitable gate path configurations and / or locations may be used without departing from the scope of this disclosure.

[0062] An insulating layer 168 may be present on the first metallization layer 164. The insulating layer 168 may include an insulating portion 174. The insulating portion 174 may be a dielectric material (e.g., silicon nitride, polymer, etc.). The insulating portion 174 may be patterned to insulate or shield one or more metallization structures of the first metallization layer 164. More specifically, the insulating portion 174 may be patterned to cover certain structures in the first metallization layer 164 while leaving other features (e.g., portions of the active region of the semiconductor structure 144) uncovered.

[0063] For example, insulating portion 174 may include shielding portion 176 operable to insulate or shield the gate channel 170 of the first metallization layer 164. Insulating portion 174 may be patterned to form source contact opening 178. Source contact opening 178 may accommodate source contacts extending from, for example, source bonding pads 180 on the second metallization layer 166. Insulating portion 174 may include gate pad portion 182. Gate passage 172 may extend through insulating portion 174 of insulating layer 168.

[0064] The second metallization layer 166 may be on the insulating layer 168, such that the insulating layer 168 is between the first metallization layer 164 and the second metallization layer 166. In some embodiments, the second metallization layer 166 may serve as a bonding layer for the semiconductor device 160. Figure 4 In this example, the second metallization layer 166 includes a gate pad 184 at a central edge region of the semiconductor device 160, which may be a package-available location. The second metallization layer 166 may include a planar interconnect structure 186 that electrically connects the gate pad 184 to the gate path 172 and thus to the gate channel 170 of the semiconductor device 160. The second metallization layer 166 may include a large source bonding pad 180. Source contacts can extend from the source pad 180 through source contact openings 178 in the insulating layer 168 to the active region of the semiconductor structure 162 of the semiconductor device 160.

[0065] The second metallization layer 166 can be used for interconnection between the semiconductor device 160 and components in the semiconductor package, including bases, lead frames, terminals, etc. The interconnection method can vary depending on the package type, but can include wiring bonding, soldering, sintering, conductive epoxy resin, or similar conductive materials.

[0066] Semiconductor device 160 may include other structures without departing from the scope of this disclosure. For example, semiconductor device 160 may include a back metallization layer (not shown) that includes drain attachment pads on the back side of semiconductor structure 160. Semiconductor device 160 may include a passivation layer (not shown) on a second metallization layer 166. Semiconductor device 160 may include edge termination structures.

[0067] Figure 5 Depicting along Figure 4 The cross-sectional view of semiconductor device 160 taken by line A-A' in the figure. Figure 5 This is intended to represent structures used for identification and description, and is not intended to represent structures drawn to physical scale. As shown, power semiconductor device 160 includes a first metallization layer 164 on semiconductor structure 162. Semiconductor device 160 includes an insulating layer 168. Semiconductor device 160 includes a second metallization layer 166 (e.g., a bonding layer). For illustrative purposes, certain layer boundaries are shown as dashed lines. Those skilled in the art will understand using the disclosure provided herein that the layers of power semiconductor device 160 may be assembled together to form a composite structure, which may or may not include the discrete layer boundaries in the ultimately assembled semiconductor device 160.

[0068] like Figure 5As shown, the power semiconductor device 160 includes a gate pad 184 and a source pad 180 in a second metallization layer 166. An insulating portion of the insulating layer 168 includes a gate pad portion 182. The first metallization layer 164 includes a gate channel 170. The insulating portion 188 separates the gate channel 170 from other metallization structures (e.g., source contacts). The insulating layer 168 includes source contact openings to accommodate source contacts extending from the source pad 180 to the active region of the semiconductor structure 142.

[0069] According to an exemplary implementation of this disclosure Figure 4 and Figure 5 At least a portion of one or more of the metallized structures (including at least a portion of one or more of the first metallization layer 164 and / or the second metallization layer 166) may include beryllium. For example, in some embodiments, at least a portion of one or more of the first metallization layer 164 and / or the second metallization layer 166 may include a beryllium alloy. At least a portion of one or more of the first metallization layer 164 and / or the second metallization layer 166 may include copper and beryllium (e.g., a copper-beryllium alloy). At least a portion of one or more of the first metallization layer 164 and / or the second metallization layer 166 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0070] In some examples, at least a portion of one or more of the first metallization layer 164 and / or the second metallization layer 166 may comprise a ternary beryllium alloy. The ternary beryllium alloy may comprise aluminum (or copper), beryllium, and a ternary element. The ternary element may comprise silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may comprise cobalt, which can increase the microstructural stability of the metallization structure.

[0071] In an exemplary aspect of this disclosure, at least a portion of one or more of the first metallization layer 164 and / or the second metallization layer 166 may include about 0.1% to about 3% beryllium, such as about 0.2% to about 2% beryllium, such as about 0.2% to about 0.1% beryllium, such as about 0.2% to about 0.5% beryllium, such as about 0.5% beryllium.

[0072] Figure 6An example semiconductor package of a semiconductor device 200 according to an exemplary embodiment of the present disclosure is depicted. The semiconductor device includes a semiconductor die 202. The semiconductor die 202 includes one or more metallization structures, the one or more metallization structures including bonding pads 204. The bonding pads 204 can be coupled to one or more electrical wirings 206 using wiring connections 208. The wiring connections 208 can be aluminum and / or copper. The wiring connections 208 can have a thickness of about 15 mils to about 20 mils (e.g., about 381 μm to about 508 μm). The bonding pads 204 can have a thickness of, for example, about 4 μm or less. A backside metallization layer on the semiconductor die 202 can be coupled to a base 210 (e.g., a lead frame) using, for example, a die attachment material. The base 210 can be coupled to one or more termination structures 212. Encapsulation material 214 (e.g., EMC) may encapsulate semiconductor die 202 (including its metallization structure), wiring junction 208, base 210 and other parts of the semiconductor package.

[0073] According to exemplary embodiments of this disclosure, at least a portion of one or more of the metallization structures of the semiconductor die 202 (including at least a portion of one or more of the bonding pads 204 and / or the back metallization layer) may include beryllium. For example, in some embodiments, the metallization structure of the semiconductor die 202 may include a beryllium alloy. The metallization structure of the semiconductor die 202 may include copper and beryllium (e.g., a copper-beryllium alloy). The metallization structure of the semiconductor die 202 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0074] In some examples, the metallization structure of the semiconductor die 202 may include a ternary beryllium alloy. This ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may include cobalt, which can increase the microstructural stability of the metallization structure.

[0075] In an example aspect of this disclosure, the metallization structure of the semiconductor die 202 may include about 0.1% to about 3% beryllium, such as about 0.2% to about 2% beryllium, such as about 0.2% to about 0.1% beryllium, such as about 0.2% to about 0.5% beryllium, such as about 0.5% beryllium.

[0076] Figure 7 A cross-sectional view of an example semiconductor package of a semiconductor device 220 according to an exemplary embodiment of the present disclosure is depicted. Figure 7This designation is intended to represent structures used for identification and description, and is not intended to represent structures drawn to physical scale. Semiconductor device 220 may include a housing 222. Semiconductor device 220 may include a conductive base 224 (e.g., a patterned conductive base) on which a semiconductor die 226 is mounted (e.g., using a die attachment material). Semiconductor die 226 may include one or more metallization structures, such as bonding pads 228. In some embodiments, semiconductor die 226 may be connected to conductive base 224 using wiring connections 230. Conductive base 224 may be mounted on a base layer 232 (e.g., an insulating layer). Inert gel 234 may fill the space between semiconductor die 226 and housing 222.

[0077] According to exemplary embodiments of this disclosure, at least a portion of one or more of the metallization structures of the semiconductor die 226 (including at least a portion of one or more of the bonding pads 228) may include beryllium. For example, in some embodiments, the metallization structure of the semiconductor die 226 may include a beryllium alloy. The metallization structure of the semiconductor die 226 may include copper and beryllium (e.g., a copper-beryllium alloy). The metallization structure of the semiconductor die 226 may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0078] In some examples, the metallization structure of semiconductor die 226 may include a ternary beryllium alloy. This ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may include cobalt, which can increase the microstructural stability of the metallization structure.

[0079] In an exemplary aspect of this disclosure, the metallization structure of the semiconductor die 226 may include about 0.1% to about 3% beryllium, such as about 0.2% to about 2% beryllium, such as about 0.2% to about 0.1% beryllium, such as about 0.2% to about 0.5% beryllium, such as about 0.5% beryllium.

[0080] Figure 6 and Figure 7 Example semiconductor packages are depicted for illustrative and discussion purposes. Those skilled in the art will understand using the disclosure provided herein that different semiconductor package configurations can be used without departing from the scope of this disclosure.

[0081] Figure 8 A flowchart depicts an example method 240 according to an example implementation of the present disclosure. Figure 8Example process steps are depicted for illustrative and discussion purposes. Those skilled in the art will understand using the disclosure provided herein that process steps in any method described herein can be adapted, modified, or included in the form of steps not shown, omitted, and / or rearranged, without departing from the scope of this disclosure.

[0082] At 242, the method includes depositing a metallization structure on the active region of the semiconductor structure. The semiconductor structure may be a semiconductor structure comprising one or more wide-bandgap semiconductor materials and may include doped and / or different epitaxial layer structures to form one or more active semiconductor cells (e.g., wide-bandgap semiconductor cells) for semiconductor devices (e.g., silicon carbide-based MOSFETs, silicon carbide-based Schottky diodes, group III nitride-based HEMTs, etc.). The metallization structure may be any metallization structure described in this disclosure. As an example, the method may include... Figure 1 Metallization structure 104 is deposited on the active region of semiconductor structure 102.

[0083] According to exemplary embodiments of this disclosure, at least a portion of the metallized structure may include beryllium. For example, at least a portion of the metallized structure may include a beryllium alloy. The metallized structure may include copper and beryllium (e.g., a copper-beryllium alloy). The metallized structure may include aluminum and beryllium (e.g., an aluminum-beryllium alloy).

[0084] In some examples, the metallized structure may include a ternary beryllium alloy. The ternary beryllium alloy may include aluminum (or copper), beryllium, and a ternary element. The ternary element may include silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some embodiments, the ternary element may include cobalt, which can increase the microstructural stability of the metallized structure.

[0085] In an exemplary aspect of this disclosure, the metallized structure may include about 0.1% to about 3% beryllium, such as about 0.2% to about 2% beryllium, such as about 0.2% to about 0.1% beryllium, such as about 0.2% to about 0.5% beryllium, such as about 0.5% beryllium.

[0086] exist Figure 8 At position 244, the method may include depositing a passivation layer on the active region of the semiconductor structure. In some examples, the passivation layer may include silicon nitride. The passivation layer may include a polymer, such as polyimide. In some examples, the passivation layer may be SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, or other dielectric materials. For example, passivation layer 110 may be deposited on... Figure 1 On the semiconductor structure 102.

[0087] exist Figure 8At position 246, the method may include: opening the passivation layer to expose the metallized structure. For example, the method may include: opening the passivation layer 110 to expose... Figure 1 The bonding pad 104 in the middle.

[0088] exist Figure 8 At position 248, the method may include attaching components, including semiconductor structures, metallization structures, and / or passivation layers, to a substrate, such as a lead frame. For example, the method may include attaching... Figure 1 The back metallization structure 108 is attached to the base (e.g., using a die attachment material).

[0089] exist Figure 8 At position 250, the method may include bonding one or more electrical connection structures (e.g., wiring joints) to a metallized structure. For example, a wiring joint may be bonded to... Figure 1 The metallized structure 104 in it.

[0090] exist Figure 8 At position 252, the method may include encapsulating a component comprising a semiconductor structure, a metallization structure, and / or a passivation layer. For example, the component may be encapsulated using EMC.

[0091] Examples of this disclosure are provided below. Features of some examples may be combined with features of other examples without departing from the scope of this disclosure.

[0092] One example aspect of this disclosure relates to a semiconductor device. The semiconductor device includes an active region comprising one or more active semiconductor cells. The semiconductor device includes a metallization structure on the active region. The metallization structure includes beryllium.

[0093] In some examples, the metallization structure is one or more of the contacts, interconnects, or bonding pads of a semiconductor device.

[0094] In some examples, the metallization structure also includes copper. In some examples, the metallization structure includes aluminum.

[0095] In some examples, the metallization structure includes beryllium ranging from about 0.1% to about 3%. In some examples, the metallization structure includes beryllium ranging from about 0.1% to about 3%. In some examples, the metallization structure includes beryllium ranging from about 0.2% to about 0.5%.

[0096] In some examples, the metallized structure comprises a ternary beryllium alloy. In some examples, the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some examples, the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes cobalt.

[0097] In some examples, the metallization structure includes source contacts, drain contacts, or gate contacts for the MOSFET.

[0098] In some examples, the semiconductor device further includes a passivation layer. In some examples, the passivation layer includes silicon nitride. In some examples, the passivation layer includes a polymer. In some examples, the polymer includes polyimide.

[0099] In some examples, the one or more active semiconductor units include wide-bandgap semiconductors. In some examples, the one or more active semiconductor units include one or more silicon carbide-based MOSFETs. In some examples, the one or more active semiconductor units include one or more silicon carbide-based Schottky diodes. In some examples, the one or more active semiconductor units include one or more group III nitride-based high electron mobility transistor devices.

[0100] Another example aspect of this disclosure relates to a semiconductor device. The semiconductor device includes an active region comprising one or more silicon carbide-based MOSFETs. The semiconductor device includes a metallization structure on the active region. The metallization structure includes bonding pads associated with gate contacts, source contacts, or drain contacts of the semiconductor device. The metallization structure includes beryllium.

[0101] In some examples, the metallized structure also includes copper. In some examples, the metallized structure also includes aluminum.

[0102] In some examples, the metallization structure includes beryllium ranging from about 0.1% to about 3%. In some examples, the metallization structure includes beryllium ranging from about 0.1% to about 3%. In some examples, the metallization structure includes beryllium ranging from about 0.2% to about 0.5%.

[0103] In some examples, the metallized structure comprises a ternary beryllium alloy. In some examples, the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some examples, the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes cobalt.

[0104] In some examples, the semiconductor device includes an adhesion layer between the metallized structure and the active region. In some examples, the adhesion layer includes titanium.

[0105] In some examples, the semiconductor device includes a passivation layer. In some examples, the passivation layer includes silicon nitride. In some examples, the passivation layer includes a polymer. In some examples, the polymer includes polyimide.

[0106] In some examples, the semiconductor device includes encapsulation material.

[0107] In some examples, the semiconductor device includes wiring junctions on one or more metallized structures.

[0108] Another example aspect of this disclosure relates to a method. The method includes depositing a metallization structure on an active region comprising one or more wide-bandgap semiconductor cells. The metallization structure comprises beryllium.

[0109] In some examples, the metallization structure is one or more of the contacts, interconnects, or bonding pads of a semiconductor device.

[0110] In some examples, the metallization structure also includes copper. In some examples, the metallization structure includes aluminum.

[0111] In some examples, the metallization structure includes beryllium ranging from about 0.1% to about 3%. In some examples, the metallization structure includes beryllium ranging from about 0.1% to about 3%. In some examples, the metallization structure includes beryllium ranging from about 0.2% to about 0.5%.

[0112] In some examples, the metallized structure comprises a ternary beryllium alloy. In some examples, the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes silver, copper, magnesium, silicon, titanium, vanadium, or zinc. In some examples, the ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes cobalt.

[0113] In some examples, the method may include depositing a passivation layer on the active region. In some examples, the method may include: forming openings in the passivation layer to expose the metallization structure; and attaching one or more electrical connection structures to the metallization structure.

[0114] In some examples, the method may include: attaching a component, which includes an active region and a metallization structure, to a lead frame; and encapsulating the component.

[0115] In some examples, the one or more active semiconductor units include wide-bandgap semiconductors. In some examples, the one or more active semiconductor units include one or more silicon carbide-based MOSFETs. In some examples, the one or more active semiconductor units include one or more silicon carbide-based Schottky diodes. In some examples, the one or more active semiconductor units include one or more group III nitride-based high electron mobility transistor devices.

[0116] While the subject matter has been described in detail with respect to specific exemplary embodiments of the invention, it should be understood that those skilled in the art, upon gaining an understanding of the foregoing, can readily generate changes, modifications, and equivalents of these embodiments. Therefore, the scope of this disclosure is by way of example rather than limitation, and this disclosure does not exclude the inclusion of such modifications, variations, and / or additions to the subject matter, as will be readily understood by those skilled in the art.

Claims

1. A semiconductor device, comprising: An active region includes one or more active semiconductor units; A metallized structure is present on the active region; and The metallized structure includes beryllium.

2. The semiconductor device according to claim 1, wherein, The metallization structure is one or more of the contacts, interconnects, or bonding pads of the semiconductor device.

3. The semiconductor device according to claim 1, wherein, The metallized structure also includes copper.

4. The semiconductor device according to claim 1, wherein, The metallized structure also includes aluminum.

5. The semiconductor device according to claim 1, wherein, The metallized structure comprises beryllium ranging from about 0.1% to about 3%.

6. The semiconductor device according to claim 1, wherein, The metallized structure comprises beryllium ranging from about 0.2% to about 0.5%.

7. The semiconductor device according to claim 1, wherein, The metallized structure includes a ternary beryllium alloy.

8. The semiconductor device according to claim 7, wherein, The ternary beryllium alloy comprises aluminum, beryllium, and ternary elements, wherein the ternary elements include silver, copper, magnesium, silicon, titanium, vanadium, or zinc.

9. The semiconductor device according to claim 7, wherein, The ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes cobalt.

10. The semiconductor device according to claim 1, wherein, The metallization structure includes source contacts, drain contacts, or gate contacts for the MOSFET.

11. The semiconductor device according to claim 1, wherein, The semiconductor device also includes a passivation layer.

12. The semiconductor device according to claim 11, wherein, The passivation layer comprises silicon nitride.

13. The semiconductor device according to claim 11, wherein, The passivation layer comprises a polymer.

14. The semiconductor device according to claim 13, wherein, The polymer includes polyimide.

15. The semiconductor device according to claim 1, wherein, The one or more active semiconductor units include wide-bandgap semiconductors.

16. The semiconductor device according to claim 1, wherein, The one or more active semiconductor units include one or more silicon carbide-based MOSFETs.

17. The semiconductor device according to claim 1, wherein, The one or more active semiconductor units include one or more silicon carbide-based Schottky diodes.

18. The semiconductor device according to claim 1, wherein, The one or more active semiconductor units include one or more group III nitride-based high electron mobility transistor devices.

19. A semiconductor device, comprising: The active region includes one or more silicon carbide-based MOSFETs; A metallization structure, on the active region, includes bonding pads associated with gate contacts, source contacts, or drain contacts for the semiconductor device; and The metallized structure includes beryllium.

20. The semiconductor device according to claim 19, wherein, The metallized structure also includes copper.

21. The semiconductor device according to claim 19, wherein, The metallized structure also includes aluminum.

22. The semiconductor device according to claim 19, wherein, The metallized structure comprises beryllium ranging from about 0.1% to about 3%.

23. The semiconductor device according to claim 19, wherein, The metallized structure comprises beryllium ranging from about 0.2% to about 0.5%.

24. The semiconductor device according to claim 19, wherein, The metallized structure includes a ternary beryllium alloy.

25. The semiconductor device according to claim 24, wherein, The ternary beryllium alloy comprises aluminum, beryllium, and ternary elements, wherein the ternary elements include silver, copper, magnesium, silicon, titanium, vanadium, or zinc.

26. The semiconductor device according to claim 24, wherein, The ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes cobalt.

27. The semiconductor device of claim 19, further comprising an adhesion layer between the metallization structure and the active region.

28. The semiconductor device according to claim 27, wherein, The adhesion layer comprises titanium.

29. The semiconductor device of claim 19, further comprising a passivation layer.

30. The semiconductor device according to claim 29, wherein, The passivation layer comprises silicon nitride.

31. The semiconductor device according to claim 29, wherein, The passivation layer comprises a polymer.

32. The semiconductor device according to claim 31, wherein, The polymer includes polyimide.

33. The semiconductor device according to claim 19 further includes an encapsulation material.

34. The semiconductor device of claim 19, further comprising one or more wiring junctions on the metallized structure.

35. A method comprising: A metallization structure is deposited on an active region comprising one or more wide-bandgap semiconductor cells; and The metallized structure includes beryllium.

36. The method according to claim 35, wherein, The metallized structure includes contacts, interconnects, or bonding pads.

37. The method of claim 36, wherein, The metallized structure includes copper.

38. The method according to claim 36, wherein, The metallized structure includes aluminum.

39. The method according to claim 36, wherein, The metallized structure comprises beryllium ranging from about 0.1% to about 3%.

40. The method of claim 36, wherein, The metallized structure comprises beryllium ranging from about 0.2% to about 0.5%.

41. The method according to claim 36, wherein, The metallized structure includes a ternary beryllium alloy.

42. The method according to claim 41, wherein, The ternary beryllium alloy comprises aluminum, beryllium, and ternary elements, wherein the ternary elements include silver, copper, magnesium, silicon, titanium, vanadium, or zinc.

43. The method according to claim 41, wherein, The ternary beryllium alloy comprises aluminum, beryllium, and a ternary element, wherein the ternary element includes cobalt.

44. The method of claim 35, further comprising: A passivation layer is deposited on the active region.

45. The method of claim 44, further comprising: The passivation layer is opened to expose the metallized structure; and One or more electrical connection structures are joined to the metallized structure.

46. ​​The method of claim 45, further comprising: Attach the component, including the active region and the metallization structure, to the lead frame; and Encapsulate the component.

47. The method of claim 35, wherein, The one or more wide-bandgap semiconductor units include one or more silicon carbide-based MOSFETs.

48. The method according to claim 35, wherein, The one or more wide-bandgap semiconductor units include one or more silicon carbide-based Schottky diodes.

49. The method according to claim 35, wherein, The one or more wide-bandgap semiconductor units include one or more group III nitride-based high electron mobility transistor devices.

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