Silicon pixel detector arrival time measuring circuit and measuring method

Abstract

The invention relates to a silicon pixel detector arrival time measuring circuit and a measuring method, the circuit comprises a pulse control module, a delay chain module, a first counting module and a second counting module, the pulse control module is used for responding to a rising edge signal of an external circuit; a logic high level and a rising edge signal are respectively output to the delay chain module and the first counting module; outputting a logic low level based on the logic high level after multiple times of delay; the delay chain module is used for delaying the input logic high level and logic low level for multiple times; periodic square waves are sent to the first counting module based on the logic level after multiple times of delay; the first counting module is used for counting rising edges of the periodic square waves; and the second counting module is used for judging the arrival position of the rising edge of the periodic square wave based on all the received logic levels. According to the invention, through combination of pulse width control and the delay chain module, time measurement precision and clock frequency are decoupled, and high-precision time measurement of low clock frequency is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of silicon pixel detectors, and particularly relates to a silicon pixel detector arrival time measurement circuit and a measurement method. BACKGROUND

[0002] Silicon pixel detectors have good position resolution and are widely used in accelerator particle physics experiments for track reconstruction. With the development of pixel detectors, silicon pixel detectors have been applied in the field of X-ray imaging. For different application scenarios, silicon pixel detectors not only need high position resolution, but also need high-precision energy measurement and time measurement. Generally, time threshold technology is used to achieve energy measurement. Time threshold technology requires high-precision measurement of rising edge and falling edge arrival time, so high-precision arrival time measurement is one of the important research directions of silicon pixel detectors.

[0003] The traditional method for measuring the arrival time of a silicon pixel detector uses a combination of coarse and fine time-to-digital conversion technology. Coarse counting is achieved by counting the system clock using a counter, and fine counting is achieved by generating a high-frequency clock using a ring voltage-controlled oscillator to achieve more accurate timing. The time precision of this method is determined by the high-frequency clock of the fine counting. The higher the frequency, the higher the time precision of the measurement. However, high clock frequency will result in high power consumption, affecting the service life, and the use of more cables and water cooling systems in detector integration will increase the mass of the detector integration, further exacerbating the problem of ion scattering. SUMMARY

[0004] To solve the problem of high clock frequency and high power consumption in traditional time measurement methods without affecting the accuracy of time measurement, the application provides a silicon pixel detector arrival time measurement circuit in the first aspect, which includes a pulse control module, a delay chain module, a first counting module and a second counting module. The pulse control module is used to respond to the rising edge signal of the external circuit and output a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively. Based on the logic high level after multiple delays, a logic low level is output. The delay chain module is used to delay the input logic high level and logic low level multiple times. Based on the logic level after multiple delays, a periodic square wave with constant frequency is output to the first counting module. The first counting module is used to count the rising edge of the periodic square wave based on the rising edge signal and the logic level after multiple delays. The second counting module is used to respond to the external signal and latch the delay logic level of the delay chain module. Based on all the received logic levels, the arrival position of the rising edge of the periodic square wave is determined.

[0005] In some embodiments of the present application, the pulse control module comprises a multiplexer, a first D flip-flop and an inverter; the multiplexer is configured to output a rising edge signal of an external circuit to a clock terminal of the first D flip-flop and a first counting module, respectively; the first D flip-flop is configured to output a logic high level to a delay chain module based on the input rising edge signal, and output a logic low level to the delay chain module based on an input signal of the inverter; and the inverter is configured to reverse the signal polarity of the delay chain module and adjust the timing of the delay chain.

[0006] Further, the inverter is configured to invert the logic level after multiple delays.

[0007] In some embodiments of the present application, the delay chain module comprises 2N delay units connected in sequence, an output terminal of an Nth delay unit is connected to an input terminal of the pulse control module, and a 2Nth delay unit is connected to the first counting module, wherein N≥1.

[0008] Further, the second counting module comprises 2N+1 latches and a rising edge detection circuit, the 2N+1 latches are configured to latch the logic level of the pulse control module and the logic level of the 2N delay units in response to an external signal, and the rising edge detection circuit is configured to determine the arrival position of the rising edge of the periodic square wave based on the logic level of each delay unit.

[0009] Preferably, the rising edge detection circuit comprises 2N+1 second D flip-flops; a clock terminal of a first second D flip-flop receives the logic level of the pulse control module through a latch; a clock terminal and an input terminal of an N+1th second D flip-flop receive the logic level of an Nth delay unit and an inverted logic level of an N+1th delay unit, respectively.

[0010] In a second aspect of the present application, a measurement method of the silicon pixel detector time-of-arrival measurement circuit provided in the first aspect is provided, comprising: the pulse control module outputs a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively, in response to a rising edge signal of an external circuit; outputs a logic low level based on the logic high level after multiple delays; the delay chain module delays the input logic high level and the logic low level multiple times; outputs a periodic square wave with constant frequency to the first counting module based on the logic level after multiple delays; the first counting module counts the rising edge of the periodic square wave based on the rising edge signal and the logic level after multiple delays; and the second counting module latches each delay logic level of the delay chain module in response to an external signal, and determines the arrival position of the rising edge of the periodic square wave based on all the received logic levels.

[0011] In a third aspect, the present application provides an electronic device, comprising: one or more processors; and a memory storing one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the measurement method of the silicon pixel detector time-of-arrival measurement circuit provided in the second aspect of the present application.

[0012] In a fourth aspect, the present application provides a computer readable medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the measurement method of the silicon pixel detector time-of-arrival measurement circuit provided in the second aspect of the present application.

[0013] The present application has the following beneficial effects: The present application adopts the technology of combining pulse width control and delay chain module, eliminates the relationship between time measurement accuracy and clock frequency, solves the problem that the width of signal pulse is expanded or contracted after multiple cycles in the traditional delay chain module, realizes high-precision time measurement at low clock frequency, and thus realizes low power consumption without affecting the time measurement accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a basic structure schematic diagram of a silicon pixel detector time-of-arrival measurement circuit in some embodiments of the present application; Figure 2 FIG. 2 is a principle schematic diagram of a rising edge detection circuit in some embodiments of the present application; Figure 3 FIG. 3 is a structure schematic diagram of a measurement method of a silicon pixel detector time-of-arrival measurement circuit in some embodiments of the present application; Figure 4 FIG. 4 is a structure schematic diagram of an electronic device in some embodiments of the present application. DETAILED DESCRIPTION

[0015] The principles and features of the present application are described below in conjunction with the accompanying drawings, and the examples are only used to explain the present application and not to limit the scope of the present application.

[0016] REFERENCE Figure 1 AND Figure 2In the first aspect of the present application, a silicon pixel detector time of arrival measurement circuit is provided, comprising a pulse control module, a delay chain module, a first counting module and a second counting module, the pulse control module is used for outputting a logic high level and a rising edge signal to the delay chain module and the first counting module respectively in response to a rising edge signal of an external circuit; a logic low level is outputted based on the logic high level after multiple delays; the delay chain module is used for delaying the input logic high level and the logic low level multiple times; a periodic square wave with constant frequency is outputted to the first counting module based on the logic level after multiple delays; the first counting module is used for counting the rising edge of the periodic square wave based on the rising edge signal and the logic level after multiple delays; the second counting module is used for latching the logic level of each delay of the delay chain module in response to an external signal; and the arrival position of the rising edge of the periodic square wave is determined based on all the received logic levels.

[0017] Specifically, the silicon pixel detector time of arrival measurement circuit comprises a pulse width control module, a delay chain, a coarse counting module (first counting module) and a fine counting module (second counting module). A digital pulse signal is preprocessed before entering the time of arrival measurement circuit, and the rising edge thereof is extracted as a Start signal. The working principle is as follows: before the Start signal enters the time of arrival measurement circuit, all delay units are in an initial state (S0~S n n are low, and the D flip-flop is in a standby state). When the Start signal enters the MUX, the MUX is automatically selected to the other end after delaying for the time of one delay unit, so that the output of the last delay unit of the delay chain is connected together. At this time, the delay chain is closed to form a closed loop state.

[0018] The Start signal generates a high level signal in the delay chain through the D flip-flop and is transmitted. When the high level reaches S N / 2 , it is fed back to the reset end of the D flip-flop while being transmitted backward, so that the D flip-flop is reset and S0 is converted from high level to low level for continuous transmission. When the low level reaches S N / 2 , the D flip-flop returns to the standby state. This process converts the Start signal into a periodic square wave with constant frequency, and the period is the total delay of the delay chain. The larger the total delay of the delay chain, the larger the period, and the lower the power consumption of the circuit. The rising edge of the square wave passes through the end of the delay chain once, and the counter is flipped once to complete coarse counting.

[0019] It can be understood that the top signal is generated by an external timing circuit and is synchronized with the external timing circuit clock, when the stop signal arrives, the D flip-flop mounted below the delay unit immediately locks the state of each delay unit and sends the data to the rising edge detection circuit to complete the fine counting. Subsequently, the delay chain is reset and the whole measurement process is completed. Through the combination of coarse counting and fine counting, the arrival time measurement circuit realizes high-precision measurement of the arrival time of the rising edge of the start.

[0020] Exemplarily, the delay unit includes an FPGA-based internal delay chain unit, a clock phase interpolation unit, an ASIC delay unit or a digital logic gate delay unit; the delay chain is constructed by using the inherent propagation delay of the digital logic gate (such as an inverter, a buffer), and the resolution is close to the delay of a single gate circuit (about 0.5 ns), which needs to be improved in accuracy by cascading or calibration.

[0021] In some embodiments of the present application, the pulse control module includes a multiplexer, a first D flip-flop and an inverter; the multiplexer is used to output the clock end of the first D flip-flop and the first counting module in response to the rising edge signal of the external circuit; the first D flip-flop is used to output a logic high level to the delay chain module based on the input rising edge signal, and output a logic low level to the delay chain module based on the input signal of the inverter; the inverter is used for signal polarity inversion of the delay chain module and timing adjustment of the delay chain.

[0022] Specifically, the pulse width control module is composed of MUX, D flip-flop and inverter, which is used for the control of the cycle pulse width, controls the pulse width, and at the same time eliminates the problem that the width of the signal pulse will be expanded or contracted after the pulse in the delay chain is circulated for many times.

[0023] In some embodiments of the present application, the delay chain module includes 2N delay units connected in sequence, the output end of the Nth delay unit is connected with the input end of the pulse control module, and the 2Nth delay unit is connected with the first counting module, wherein N≥1.

[0024] Further, the second counting module includes 2N+1 latches and a rising edge detection circuit, the 2N+1 latches are used to latch the logic level of the pulse control module and the logic level of the 2N delay units in response to the external signal; the rising edge detection circuit is used to judge the arrival position of the rising edge of the periodic square wave based on the logic level of each delay unit.

[0025] Preferably, the rising edge detection circuit comprises 2N+1 second D flip-flops; the clock end of the first second D flip-flop receives the logic level of the pulse control module through a latch; the clock end and the input end of the N+1 second D flip-flop receive the logic level of the Nth delay unit and the inverted logic level of the N+1th delay unit, respectively.

[0026] Specifically, the fine counter (the second counting module) is composed of D flip-flops and a rising edge detection circuit, the D flip-flops complete the data latching of the output of each delay unit of the delay chain, and the rising edge detection circuit is used to solve the problem that the rising edge of the Start signal cannot be directly determined to which delay unit it is transmitted due to the simultaneous output of high levels of multiple D flip-flops.

[0027] It can be understood that the rising edge detection circuit used in the present application can directly determine to which delay unit the rising edge of the Start signal is transmitted. The rising edge detection circuit is composed of multiple D flip-flops and inverters, as shown in Figure 2 , which is an example of a delay chain composed of four delay units, a rising edge discrimination circuit is formed by connecting an inverter to the input end of the D flip-flop, and the two adjacent signals (for example, Q1-Q0) in the fine counting are connected to the clock end and the input end of the discrimination circuit, respectively, so that the discrimination output can be achieved. The specific position of the signal delay can be clearly determined by the output waveform, as shown in Figure 2 , which shows that the signal delay has reached the second delay unit (Q_S2), thereby achieving the fine counting measurement of the signal delay.

[0028] Embodiment 2 Referring to Figure 3 , the second aspect of the present application provides a measurement method of the time-of-arrival measurement circuit of the silicon pixel detector, comprising: S100. The pulse control module outputs a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively, in response to the rising edge signal of the external circuit; outputs a logic low level based on the logic high level after multiple delays; S200. The delay chain module delays the input logic high level and the logic low level multiple times; outputs a periodic square wave with a constant frequency to the first counting module based on the logic level after multiple delays; S300. The first counting module counts the rising edge of the periodic square wave based on the rising edge signal and the logic level after multiple delays; S400. The second counting module latches the logic level of each delay of the delay chain module in response to the external signal; determines the arrival position of the rising edge of the periodic square wave based on all the received logic levels.

[0029] Further, in step S100, the output of the logic low level based on the logic high level after multiple delays comprises resetting the logic high level after multiple delays and outputting a logic low level.

[0030] Example 3 With reference to Figure 4 In a third aspect, the present application provides an electronic device, comprising: one or more processors; and a memory device storing one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of the second aspect of the present application.

[0031] The electronic device 500 can include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 501 that can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 502 or loaded into a random access memory (RAM) 503 from a memory device 508. Various programs and data required for operation of the electronic device 500 are also stored in the RAM 503. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0032] Generally, the following devices can be connected to the I / O interface 505: input devices 506 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a memory device 508 including, for example, a hard disk, etc.; and a communication device 509. The communication device 509 can allow the electronic device 500 to communicate wirelessly or wired with other devices to exchange data. Although Figure 4 The electronic device 500 is shown with various devices, but it should be understood that not all of the shown devices are required to be implemented or present. More or fewer devices can alternatively be implemented or present. Figure 4 Each block shown in the flowchart of

[0033] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for executing the methods illustrated by the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by the communication device 509, or installed from the storage device 508, or installed from the ROM 502. When the computer program is executed by the processing device 501, the above-mentioned functions defined in the methods of embodiments of the present disclosure are executed. It should be noted that the computer readable medium described in embodiments of the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In embodiments of the present disclosure, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, device or apparatus. In embodiments of the present disclosure, the computer readable signal medium can include a data signal carried in a baseband or as part of a carrier wave, in which the computer readable program code is carried. Such a propagated data signal can take a variety of forms, including but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate or transport a program for use by or in connection with an instruction execution system, device or apparatus. The program code contained on the computer readable medium can be transmitted by any suitable medium, including but not limited to, wire, cable, RF (radio frequency), or the like, or any suitable combination of the above.

[0034] The computer readable medium described above can be included in the electronic device described above; or can exist separately from the electronic device and not be assembled into the electronic device. The computer readable medium described above carries one or more computer programs, which, when executed by the electronic device, cause the electronic device to: Computer program code for carrying out operations of embodiments of the present disclosure can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++, Python, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0035] The computer program instructions can also be loaded onto a computer or other programmable information processing apparatus to cause a series of operations to be performed on the computer or other programmable information processing apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable information processing apparatus implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0036] The above description is only preferred embodiments of the present application, not to limit the present application, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A silicon pixel detector time-of-arrival measurement circuit, comprising a pulse control module, a delay chain module, a first counting module and a second counting module, characterized in that, the pulse control module is configured to output a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively, in response to a rising edge signal of an external circuit; and output a logic low level based on the logic high level after multiple delays; the delay chain module is configured to delay the input logic high level and the logic low level multiple times; and output a periodic square wave with a constant frequency to the first counting module based on the logic levels after multiple delays; the first counting module is configured to count rising edges of the periodic square wave based on the rising edge signal and the logic levels after multiple delays; the second counting module is configured to latch each delay logic level of the delay chain module in response to an external signal; and determine the arrival position of the rising edge of the periodic square wave based on all the received logic levels.

2. The silicon pixel detector time-of-arrival measurement circuit of claim 1, wherein, the pulse control module comprises a multiplexer, a first D flip-flop and an inverter; the multiplexer is configured to output a clock signal of the first D flip-flop and the first counting module, respectively, in response to the rising edge signal of the external circuit; the first D flip-flop is configured to output the logic high level to the delay chain module based on the input rising edge signal; and output the logic low level to the delay chain module based on the input signal of the inverter; the inverter is configured to reverse the signal polarity of the delay chain module and adjust the timing of the delay chain.

3. The silicon pixel detector time-of-arrival measurement circuit of claim 2, wherein, the inverter is configured to invert the logic levels after multiple delays.

4. The silicon pixel detector time-of-arrival measurement circuit of claim 1, wherein, the delay chain module comprises 2N delay units connected in sequence, an output terminal of an Nth delay unit is connected to an input terminal of the pulse control module, and a 2Nth delay unit is connected to the first counting module, wherein N≥1.

5. The silicon pixel detector time-of-arrival measurement circuit of claim 4, wherein, the second counting module comprises 2N+1 latches and a rising edge detection circuit, the 2N+1 latches are configured to latch the logic levels of the pulse control module and the 2N delay units in response to an external signal; the rising edge detection circuit is configured to determine the arrival position of the rising edge of the periodic square wave based on the logic levels of each delay unit. 6.The silicon pixel detector time-of-arrival measurement circuit of claim 5, characterized in that, the rising edge detection circuit comprises 2N+1 second D flip-flops; a clock terminal of a first second D flip-flop receives the logic level of the pulse control module through a latch; a clock terminal and an input terminal of an N+1th second D flip-flop receive the logic level of an Nth delay unit and an inverted logic level of an N+1th delay unit, respectively.

7. A measurement method based on the silicon pixel detector time-of-arrival measurement circuit of claim 1, characterized in that, including: the pulse control module is configured to output a logic high level and a rising edge signal to the delay chain module and the first counting module, respectively, in response to a rising edge signal of an external circuit; the logic low level is output based on the logic high level after multiple delays; the delay chain module is configured to delay the input logic high level and the logic low level multiple times; and output a periodic square wave with a constant frequency to the first counting module based on the logic levels after multiple delays; the first counting module is configured to count rising edges of the periodic square wave based on the rising edge signal and the logic levels after multiple delays; The second counting module latches each delayed logic level of the delay chain module in response to an external signal; and determines a position of an arrival of a rising edge of a periodic square wave based on all the received logic levels.

8. The method of measuring of a silicon pixel detector time of flight circuit according to claim 7, characterized in that, The outputting of the logic low level based on the logic high level after multiple delays comprises: Resetting the logic high level after the secondary delay and outputting a logic low level.

9. An electronic device comprising: one or more processors; a storage device for storing one or more programs, which when executed by the one or more processors, cause the one or more processors to implement the measurement method of the silicon pixel detector time-of-arrival measurement circuit according to any one of claims 7 to 8.

10. A computer readable medium having stored thereon a computer program, wherein, The computer program, when executed by a processor, implements the measurement method of the silicon pixel detector time-of-arrival measurement circuit according to any one of claims 7 to 8.

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