Low dropout linear regulator and overshoot suppression method thereof

By introducing a power transistor, an error amplifier, and a sampling comparator into the LDO regulator, and controlling the on-resistance of the power transistor by comparing the dynamic current with the reference current, the overshoot problem during LDO regulator startup is solved, achieving a simple circuit design and low-power overshoot suppression effect.

CN121165871APending Publication Date: 2025-12-19晶艺半导体有限公司
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Patent Information

Application Number
CN202511281600.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-09-09
Publication Date
2025-12-19

AI Technical Summary

Technical Problem

LDO regulators suffer from output voltage overshoot and oscillation during startup, which severely affects the lifespan of digital circuits and may even cause device breakdown.

Method used

A low-dropout linear regulator is employed, comprising a power transistor, an error amplifier, and a sampling comparator unit. By comparing the dynamic current in the sampling error amplifier with the reference current, the on-resistance of the power transistor is controlled to suppress overshoot.

Benefits of technology

It achieves effective suppression of overshoot voltage during LDO regulator startup, with a simple circuit structure, no increase in static power consumption, and good overshoot suppression effect.

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Abstract

The invention provides an LDO (Low Dropout Regulator) and an overshoot suppression method thereof. The LDO comprises a power transistor, an error amplifier, a first transistor and a sampling comparison unit. The first end and the second end of the power transistor serve as the input end and the output end of the LDO respectively. The error amplifier amplifies an error between a feedback signal representing an output voltage signal of the LDO and a reference voltage signal, and sends an error amplification result to the control end of the power transistor. The sampling comparison unit is used for sampling dynamic current in the error amplifier, comparing a dynamic current sampling value with reference current and then outputting a current adjusting signal, and when the dynamic current sampling value is larger than the reference current, the current adjusting signal is used for conducting the first transistor so as to reduce the on-resistance of the power transistor. According to the scheme, the overshoot voltage can be suppressed in the LDO starting process or the load changing process. The circuit structure is simple, static power consumption is not increased, and the overshoot suppression effect is good.
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Citation Information

Patent Citations

  • Method and circuit for inhibiting overshoot of LDO output voltage

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  • Voltage stabilizer with low power consumption and high power ripple rejection ratio

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  • Low dropout linear regulator circuit, power supply and electronic equipment

    CN119105599A

  • Constant voltage power supply device

    JP2005174208A

  • Voltage regulator

    JP2007128292A