Self-biased reference current source circuit

Abstract

The invention relates to the technical field of integrated circuit design, and provides a self-biased reference current source circuit which comprises a starting circuit and a reference current circuit. The starting circuit adopts a PMOS (P-channel Metal Oxide Semiconductor) tube (MP1-MP3) and an NMOS (N-channel Metal Oxide Semiconductor) tube (MN1-MN2) of which the grid electrodes are grounded, and an inverted tube of which the size ratio of MP1 to MP2 is 1.5: 20, so that the reference current circuit can be quickly helped to get rid of a degeneracy point and the continuous power consumption is reduced; the reference current generating circuit is composed of low-voltage cascode current mirrors (MP4-MP7, R1), triodes (Q1-Q2) and an NMOS tube (MN3), the cascode structure improves output impedance to shield power supply voltage fluctuation, and self-bias stable reference current is achieved through positive feedback. The problems that an existing reference current source is difficult to start, high in power consumption and sensitive to power supply voltage are solved, the temperature coefficient of the reference current can be lower than + / -50 ppm / DEG C, the power supply voltage rejection ratio can be increased by 20 dB or above, and the reference current source is suitable for high-precision analog chips.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more particularly to a self-biased reference current source circuit, especially to a reference current source circuit used in a signal processing unit of a charging pile testing equipment. Background Technology

[0002] The reference current source is the "cornerstone" of analog circuits, and its stability directly determines the performance of the entire circuit system. The core objective of the reference current source is to generate a stable current with high accuracy, low temperature coefficient, and insensitivity to changes in power supply voltage, thereby providing a precise and stable reference signal for other modules and ensuring that each circuit unit operates accurately under preset conditions.

[0003] Reference current source circuits in the prior art, such as Figure 1 As shown, the PMOS transistors positioned above are of the same size, M P1 M can be copied proportionally P2 The current in the branch is determined by the resistor R, which is used to determine the value of the reference current. The NMOS transistor M is located below. N1 and M N2 The ratio is 1:K. Existing reference current source circuits suffer from the following drawbacks: They have a "degeneracy point," i.e., a zero-current operating point, and may fall into a zero-current state after power-on, unable to autonomously enter normal operating mode; they are highly sensitive to power supply fluctuations, employing a common current mirror structure with low output impedance, failing to effectively shield the impact of power supply voltage fluctuations on the reference current; adding a conventional startup circuit may increase power consumption; and their self-biasing capability is weak, with the stability of the reference current depending on the matching of the NMOS transistor's gate-source voltage and resistor, significantly affected by process and temperature parameters, making long-term stable current output difficult. Therefore, a reference current source circuit that can solve the problems of "difficult startup, power supply sensitivity, high power consumption, and poor stability" is urgently needed. Summary of the Invention

[0004] To overcome the problems of difficult startup, power sensitivity, high power consumption, and poor stability in existing reference current source circuits, this invention proposes a self-biased reference current source circuit. By designing an efficient startup circuit, it helps the reference current generation circuit overcome the degeneracy point and reduces the continuous power consumption of the startup branch. Simultaneously, it increases the output impedance of the reference current generation circuit, shielding it from power supply voltage fluctuations and reducing power sensitivity. Furthermore, it sets a self-biased stable reference current, mitigating the influence of process technology and temperature on the current and improving current accuracy. The specific technical solution is as follows: A self-biased reference current source circuit includes a startup circuit and a reference current circuit; The first input end and the second input end of the starting circuit are connected with VDD; the first output end is connected with the reference current circuit, for starting the reference current circuit and getting rid of the merger point; the third input end is respectively connected with the drain of PMOS M P9 , the drain and the gate of NMOS M N4 , and the gate of NMOS M N5 , for starting the reference current circuit and then self-disconnecting; the first output end is connected with the reference current circuit, and the second output end is grounded. The first input end and the second input end of the reference current circuit are connected with VDD, the first output end is connected with the gate of PMOS M P8 , the second output end is connected with the gate of PMOS M P9 , and the third output end and the fourth output end are grounded. It further comprises PMOS M P8 , PMOS M P9 , NMOS M N4 , and NMOS M N5 ; wherein the drain of PMOS M P8 is connected with VDD, the source is connected with the source of PMOS M P9 ; the drain of PMOS M P9 is respectively connected with the drain and the gate of NMOS M N4 , and the gate of NMOS M N5 ; the source of NMOS M N4 is grounded, and the gate is connected with the gate of NMOS M N5 ; the source of NMOS M N5 is grounded, and the drain is connected with the load.

[0005] Further, the starting circuit comprises PMOS M P1 , PMOS M P2 , PMOS M P3 , NMOS M N1 , and NMOS M N2 ; the source of PMOS M P1 is the first input end of the starting circuit, the source of PMOS M P3 is the second input end of the starting circuit, the gate of NMOS M N1 is the third input end of the starting circuit, the source of NMOS M N2 is the first output end of the starting circuit, and the source of NMOS M N1 is the second output end of the starting circuit.

[0006] Further, in the starting circuit, the source of PMOS M P1 is connected with VDD, the gate is grounded, and the drain is connected with PMOS MP2 The source of the PMOS transistor; P2 The gate is grounded, and the drain is connected to the NMOS transistor M. N2 Gate of NMOS transistor M N1 The drain of the PMOS transistor; P3 The source is connected to VDD, the gate is grounded, and the drain is connected to the NMOS transistor M. N2 The drain of the NMOS transistor; N1 The gates of the two transistors are respectively connected to the PMOS transistor M. P9 The drain of the NMOS transistor M N4 The drain and gate of the NMOS transistor M N5 The gate of the NMOS transistor M N1 The source electrode is grounded.

[0007] Furthermore, the reference current circuit includes resistors R1, R2, and R3, transistors Q1 and Q2, and a PMOS transistor M. P4 PMOS transistor M P5 PMOS transistor M P6 PMOS transistor M P7 NMOS transistor M N3 Among them, PMOS transistor M P4 PMOS transistor M P5 PMOS transistor M P6 PMOS transistor M P7 Resistor R1 forms a low-voltage common-source cascode current mirror.

[0008] Furthermore, in the reference current circuit, the PMOS transistor M P4 The source of the PMOS transistor serves as the first input terminal of the reference current circuit; P6 The source of the PMOS transistor serves as the second input terminal of the reference current circuit; P4 The gate of the PMOS transistor M is connected P6 The gate of the circuit is connected to the PMOS transistor M as the first output terminal of the reference current circuit. P8 The gate of the PMOS transistor; P5 The gate of the PMOS transistor M is connected P7 The gate of the PMOS transistor is connected as the second output terminal. P9 The gate of the NMOS transistor; one end of R3 is connected to R2, and the other end serves as the third output terminal of the reference current circuit; NMOS transistor M N3 The source of the transistor serves as the fourth output terminal of the reference current circuit; NMOS transistor M N2 The source of the circuit is used as the first output terminal of the startup circuit, and is connected to the PMOS transistor M. P7 The drain of transistor Q1, the base of transistor Q2, and the emitter of transistor Q2.

[0009] Furthermore, PMOS transistor MThe source of the MOS transistor M P4 connects with the drain of the PMOS transistor M P5 The source and the gate of the MOS transistor M P6 connect with the drain of the PMOS transistor M P8 The gate of the MOS transistor M P5 connects with the drain of the PMOS transistor M P5 The gate of the MOS transistor M P7 connects with the drain of the PMOS transistor M P9 The gate of the MOS transistor M P6 connects with the drain of the PMOS transistor M P7 The source of the MOS transistor M P7 connects with the drain of the NMOS transistor M N2 The source of the MOS transistor M P5 connects with the drain of the PMOS transistor M P7 The gate of the MOS transistor M P7 connects with the drain of the NMOS transistor M N2 The source of the MOS transistor M P7 connects with the drain of the NMOS transistor M N2 The source of the MOS transistor M N3 The drain and the gate of the MOS transistor M N3 The drain of the MOS transistor M N3 connects with the source of the NMOS transistor M

[0010] Further, the MOS transistor M P1 and the PMOS transistor M P2 are all length-to-width ratio transistors.

[0011] Further, the MOS transistor M P1 and the PMOS transistor M P2 have a length-to-width ratio of 1.5:20.

[0012] Further, the low-voltage common-source common-gate current mirror includes two branches, the currents of the two branches are respectively denoted as I1 and I2, and I1=I2; the reference current circuit is self-biased through positive feedback, the positive feedback is that the current I1 is copied as I2 by the low-voltage common-source common-gate current mirror, I2 flows through the transistor Q2 and the NMOS tube M N3 The voltage V GSN3 that determines I1 is generated later BE2 V GSN3 and V BE2 act on I1, form positive feedback, realize self-biasing of the circuit, so that I1=I2 and greater than 0; V GSN3 is the gate voltage of the NMOS tube M N3 , and V BE2 is the base-emitter voltage of the transistor Q2.

[0013] According to any of the above embodiments, the present application has at least the following beneficial effects: Reliable start and low power consumption, by setting the starting circuit, and using the inverse tube (MP1, MP2) to reduce the current consumption of the normally open branch to the minimum, the reference current circuit can be quickly driven out of the degenerate point, and the starting success rate is high; Low power supply sensitivity, the output impedance of the low-voltage common-source common-gate current mirror in the reference current circuit is significantly higher than that of the ordinary current mirror, which can effectively shield the influence of power voltage fluctuation on the reference current; High current stability, the self-biasing structure balances the influence of PVT parameter changes through positive feedback, the temperature coefficient of the reference current can be reduced to below ±50ppm / ℃, and the current fluctuation caused by process deviation is less than 10%.

[0014] Strong compatibility: the circuit adopts low-voltage design (adapted to 1.8V~5V power supply), can be integrated into various analog chips, and does not require additional peripheral circuits, and has high integration. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a reference current source circuit in the prior art.

[0016] Figure 2 is a self-biasing reference current source circuit schematic diagram of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the present application will be described clearly and completely below in combination with the drawings in the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0018] In the prior art, the reference current source circuit as shown in Figure 1 adopts PMOS tubes with the same size, so that MP1 can copy the current of the branch where MP2 is located in the same proportion, and then the resistance R is used to determine the value of the generated reference current. The ratio of the NMOS tubes MN1 and MN2 is 1:K, so the gate-source voltage VGS of MN1 and MN2 is shown in formula (1): Formula (1) Formula (1) is expanded to obtain formula (2): Formula (2) In formula (2), μ n is the electron mobility, Cox is the gate oxide capacitance density of the transistor, and the influence of the body effect is ignored. The expression of the output current I OUT is shown in formula (3): Formula (3) In formula (3), if the channel length modulation effect is ignored, the reference current generated by the circuit is irrelevant to the power supply voltage, and is related to the process parameters and temperature.

[0019] The core of the present application is to improve the reference current source circuit as shown in Figure 1 , and a self-biased reference current source circuit is proposed, as shown in Figure 2 .

[0020] In the Figure 2 , the self-biased reference current source circuit includes a starting circuit and a reference current circuit. The starting circuit includes VDD, PMOS tube M P1 , PMOS tube M P2 , PMOS tube M P3 , NMOS tube M N1 , NMOS tube M N2 . The source of PMOS tube M P1 serves as the first input end of the starting circuit, the source of PMOS tube M P3 serves as the second input end of the starting circuit, the gate of NMOS tube M N1 serves as the third input end of the starting circuit, the source of NMOS tube M N2 serves as the first output end of the starting circuit, and the source of NMOS tube M N1 serves as the second output end of the starting circuit. The source of PMOS tube M P1 is connected to VDD, the gate is grounded, and the drain is connected to the source of PMOS tube M P2 ; the gate of PMOS tube M P2 is grounded, and the drain is connected to the gate of NMOS tube M N2 and the gate of NMOS tube MN1 drain of PMOS transistor M P3 source of PMOS transistor M N2 drain of NMOS transistor M N1 gate of PMOS transistor M P9 drain of NMOS transistor M N4 drain and gate of PMOS transistor M N5 gate of NMOS transistor M N1 source of NMOS transistor M

[0021] The starting circuit helps the reference current circuit to get rid of the degenerate point (zero current) and quickly enter the correct working state during the power-on process of the circuit. PMOS transistor M P1 -M P3 gate is grounded, and during the power-on process of the circuit, when the power supply voltage is greater than the threshold voltage of PMOS transistor M P1 -M P3 turns on, the gate voltage of M N2 will be pulled up to VDD by M P1 and M P2 , so that M N2 turns on. After that, M N2 extracts current from M P3 and injects it into the branch where transistor Q2 is located, helping the reference current circuit to start. After the circuit starts, the voltage at point A will rise, causing M N1 to turn on, M N1 pulls down the gate voltage of M N2 , and the gate voltage of M N2 is lower than the source voltage, causing it to turn off, and the circuit completes the start. It should be noted that the branch where M P1 is located is always on and will continuously consume current. Therefore, in the present application, M P1 and M P2 use inverse transistors with a length greater than a width (1.5:20) to reduce current consumption.

[0022] The reference current circuit includes resistors R1, R2, R3, transistors Q1, Q2, PMOS transistors M P4 , PMOS transistor M P5 , PMOS transistor M P6 , PMOS transistor M P7 , NMOS transistor M N3 , wherein PMOS transistor M P4 , PMOS transistor M P5 , PMOS transistor M P6 , PMOS transistor M P7 , and resistor R1 form a low-voltage cascode current mirror. In the reference current circuit, PMOS transistor MP4 The source of the PMOS transistor serves as the first input terminal of the reference current circuit; P6 The source of the PMOS transistor serves as the second input terminal of the reference current circuit; P4 The gate of the PMOS transistor M is connected P6 The gate of the circuit is connected to the PMOS transistor M as the first output terminal of the reference current circuit. P8 The gate of the PMOS transistor; P5 The gate of the PMOS transistor M is connected P7 The gate of the PMOS transistor is connected as the second output terminal. P9 The gate of the NMOS transistor; one end of R3 is connected to R2, and the other end serves as the third output terminal of the reference current circuit; NMOS transistor M N3 The source of the transistor serves as the fourth output terminal of the reference current circuit; NMOS transistor M N2 The source of the circuit is used as the first output terminal of the startup circuit, and is connected to the PMOS transistor M. P7 The drain of transistor Q1, the base of transistor Q2, and the emitter of transistor Q2. PMOS transistor M... P4 The source is connected to VDD, and the drain is connected to the PMOS transistor M. P5 The source and gate are respectively connected to the PMOS transistor M. P6 The gate of the PMOS transistor M P8 The gate of the PMOS transistor M P5 The drain of the PMOS transistor, one end of resistor R1; PMOS transistor M P5 The gates of the two transistors are respectively connected to the PMOS transistor M. P7 The gate of the PMOS transistor M P9 The gate of the transistor, the other end of resistor R1, and the emitter of transistor Q1; PMOS transistor M P6 The source is connected to VDD, and the drain is connected to the PMOS transistor M. P7 The source of the PMOS transistor; P7 The drains of the two transistors are connected to the NMOS transistor M. N2 The source of transistor Q1, the base of transistor Q2, and the emitter of transistor Q2 are connected to the other end of resistor R1 and PMOS transistor M. P5 Gate connection, PMOS transistor M P7 The gate of transistor Q1 and the base of transistor Q1 are respectively connected to PMOS transistor M. P7 The drain of the NMOS transistor M N2 The source of transistor Q1 is connected to the emitter of transistor Q2, and the collector of transistor Q1 is connected to the base of transistor Q2 and one end of resistor R2, respectively; the emitter of transistor Q2 is connected to PMOS transistor M. P7 The drain of the NMOS transistor M N2The source of the NMOS tube M, the base of the transistor Q1, and the base of the transistor Q2 are respectively connected to one end of the resistor R2, the collector of the transistor Q1, and the collector of the transistor Q2, the drain and the gate of the NMOS tube M N3 are connected to the gate of the NMOS tube M, the other end of the resistor R2 is connected to the resistor R3 and then to the ground, and the drain of the NMOS tube M N3 is connected to the gate and the collector of the transistor Q2, and the source of the NMOS tube M N3 is connected to the ground.

[0023] The reference current circuit is used to generate a stable reference current. In the reference current generating circuit, the PMOS tube M P4 -M P7 and the resistor R1 constitute a low-voltage cascode current mirror, which ensures that the currents of the left and right branches are equal, and the cascode structure can increase the output impedance of the circuit, thereby shielding the power supply voltage to a certain extent. Neglecting the base current of the BJT, the current flowing through Q1 can be represented as: Formula (4) In formula (4), V GSN3 is the gate-source voltage of MN3, V BE2 is the base-emitter voltage of Q2, V BE2 , V GSN3 and I2 can be written as: Formula (5) Formula (6) In formula (5), VT is the thermal voltage, and IS is the reverse saturation current of the BJT. By substituting formula (4) and (5) into formula (6), we can obtain: Formula (7) Since the upper current mirror structure causes the current I1 to be copied as I2, I2 flows through Q2 and M N3 , and then generates the voltage V GSN3 and V BE2 that determine the current I1, this positive feedback relationship can make the circuit self-bias.

[0024] The self-biased reference current source circuit further comprises a PMOS tube M P8 , a PMOS tube M P9 , an NMOS tube M N4 , and an NMOS tube M N5 ; wherein the drain of the PMOS tube M P8 is connected to VDD, and the source of the PMOS tube M P9 is connected to the source of the PMOS tube M P9 ; the drain of the PMOS tube M N4 is respectively connected to the drain and the gate of the NMOS tube M N5the source of NMOS transistor M N4 the source of NMOS transistor M N5 the source of NMOS transistor M N5 the source of NMOS transistor M

[0025] The above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those ordinarily skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A self-biased reference current source circuit, comprising: The starting circuit and the reference current circuit are connected to VDD at the first input and the second input of the starting circuit, and connected to the reference current circuit at the first output of the starting circuit, so as to start the reference current circuit and get rid of the merger point. The first output of the starting circuit is connected to the reference current circuit, and the second output is grounded. The third input end is connected with the drain of PMOS M P9 , the drain and the gate of NMOS M N4 , and the gate of NMOS M N5 , for starting the reference current circuit and self-disconnecting. The first output of the starting circuit is connected to the reference current circuit, and the second output is grounded. The first input terminal and the second input terminal of the reference current circuit are connected with VDD, the first output terminal is connected with the gate of PMOS transistor M P8 , the second output terminal is connected with the gate of PMOS transistor M P9 , and the third output terminal and the fourth output terminal are grounded. Also included is PMOS transistor M P8 , PMOS transistor M P9 , NMOS transistor M N4 , NMOS transistor M N5 ; Wherein, the drain of PMOS transistor M P8 is connected with VDD, the source of PMOS transistor M P9 ; the drain of PMOS transistor M P9 is connected with the drain and gate of NMOS transistor M N4 , the gate of NMOS transistor M N5 ; the source of NMOS transistor M N4 is connected with ground, the gate of NMOS transistor M N5 ; the source of NMOS transistor M N5 is connected with ground, the drain of NMOS transistor M .

2. The self-biased reference current source circuit of claim 1, wherein, The startup circuit includes a PMOS transistor M. P1 PMOS transistor M P2 PMOS transistor M P3 NMOS transistor M N1 NMOS transistor M N2 PMOS transistor M P1 The source of the PMOS transistor M is used as the first input terminal of the startup circuit. P3 The source of the NMOS transistor M is used as the second input terminal of the startup circuit. N1 The gate of the NMOS transistor serves as the third input terminal of the startup circuit. N2 The source of the NMOS transistor serves as the first output terminal of the startup circuit. N1 The source is used as the second output terminal of the startup circuit.

3. The self-biased reference current source circuit of claim 2, wherein, In the starting circuit, the source of PMOS M P1 is connected with VDD, the gate is grounded, and the drain is connected with the source of PMOS M P2 ; the gate of PMOS M P2 is grounded, and the drain is connected with the gate of NMOS M N2 and the drain of NMOS M N1 ; the source of PMOS M P3 is connected with VDD, the gate is grounded, and the drain is connected with the drain of NMOS M N2 ; the gate of NMOS M N1 is connected with the drain of PMOS M P9 , the drain of NMOS M N4 , and the gate of NMOS M N5 ; and the source of NMOS M N1 is grounded.

4. The self-biased reference current source circuit of claim 3, wherein, The reference current circuit comprises resistors R1, R2, R3, transistors Q1, Q2, PMOS M P4 , PMOS M P5 , PMOS M P6 , PMOS M P7 , NMOS M N3 , wherein PMOS M P4 , PMOS M P5 , PMOS M P6 , PMOS M P7 , and resistor R1 constitute a low-voltage cascode current mirror.

5. The self-biased reference current source circuit of claim 4, wherein, The source of PMOS M P4 is the first input terminal of the reference current circuit; the source of PMOS M P6 is the second input terminal of the reference current circuit; the gate of PMOS M P4 is connected with the gate of PMOS M P6 and is the first output terminal of the reference current circuit; the gate of PMOS M P8 is connected with the gate of PMOS M P5 and is the second output terminal of the reference current circuit; the gate of PMOS M P7 is connected with the gate of PMOS M P9 and is the third output terminal of the reference current circuit; one end of R3 is connected with R2 and the other end is the fourth output terminal of the reference current circuit; the source of NMOS M N3 is the fourth output terminal of the reference current circuit; the source of NMOS M N2 is the first output terminal of the starting circuit and is connected with the drain of PMOS M P7 , the base of triode Q1 and the emitter of triode Q2 respectively.

6. The self-biased reference current source circuit of claim 5, wherein, The source of PMOS transistor M P4 is connected to VDD, and the drain is connected to the source of PMOS transistor M P5 , and the gate is connected to the source of PMOS transistor M P6 , and the gate is connected to the source of PMOS transistor M P8 , and the gate is connected to the source of PMOS transistor M P5 , and the drain is connected to one end of resistor R1; the gate of PMOS transistor M P5 is connected to the gate of PMOS transistor M P7 , and the gate is connected to the gate of PMOS transistor M P9 , and the gate is connected to the gate of PMOS transistor M P6 , and the source is connected to VDD, and the drain is connected to the source of PMOS transistor M P7 ; the source of PMOS transistor M P7 is connected to the source of NMOS transistor M N2 , and the drain is connected to the base of transistor Q1 and the emitter of transistor Q2; the emitter of transistor Q1 is connected to the other end of resistor R1 and the gate of PMOS transistor M P5 ; the gate of PMOS transistor M P7 is connected to the base of transistor Q1, and the base of transistor Q2 is connected to the drain of PMOS transistor M P7 , and the source is connected to the source of NMOS transistor M N2 , and the emitter is connected to the base of transistor Q2 and one end of resistor R2; the emitter of transistor Q2 is connected to the drain of PMOS transistor M P7 , and the source is connected to the source of NMOS transistor M N2 , and the base is connected to one end of resistor R2 and the collector of transistor Q1; the base of transistor Q2 is connected to the collector of transistor Q1, and the collector of transistor Q2 is connected to the drain and gate of NMOS transistor M N3 ; the other end of resistor R2 is connected to resistor R3, which is then connected to ground; the drain of NMOS transistor M N3 is connected to the gate and the collector of transistor Q2, and the source of NMOS transistor M N3 is connected to ground.

7. The self-biased reference current source circuit of claim 6, wherein, The MOS transistor M P1 The PMOS transistor M P2 are all length greater than width inverters.

8. The self-biased reference current source circuit of claim 7, wherein, The MOS transistor M P1 , the PMOS transistor M P2 The length and width of the size ratio is 1.5:

20.

9. The self-biased reference current source circuit of claim 8, wherein, The low-voltage cascode current mirror comprises two branches, with currents in the two branches denoted as I1 and I2, respectively, and I1 = I2. The reference current circuit achieves self-biasing through positive feedback, wherein the positive feedback is as follows: current I1 is replicated into I2 by the low-voltage cascode current mirror, and I2 flows through transistor Q2 and NMOS transistor M. N3 Then a voltage V is generated to determine I1. GSN3 and V BE2 V GSN3 and V BE2 The feedback effect acts on I1, forming positive feedback and achieving self-biasing of the circuit, making I1 = I2 and greater than 0; V GSN3 For NMOS transistor M N3 Gate voltage, V BE2 This is the base-emitter voltage of transistor Q2.

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