Lockstep core processor, lockstep core reset circuit, and electronic device

Abstract

The application relates to the chip architecture technical field and provides a lockstep core processor, a lockstep core reset circuit and electronic equipment. A clock reset control circuit in a check core delays a system reset signal and inputs the system reset signal to a system reset logic circuit, so that the system reset logic circuit has the same reset delay time and input signal delay time when performing reset processing. The check core can be reset after completing the same operation as the main core, so that the problem of inconsistent reset time points of the check core and the main core during local reset, inconsistent storage contents of non-reset registers and lock loss alarm is avoided, and the safety is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip architecture, in particular to a lockstep core processor, a lockstep core reset circuit and an electronic device. BACKGROUND

[0002] In some chips with high functional safety requirements, lockstep core technology is one of the most common design methods. A lockstep core is composed of two identical CPU (Central Processing Unit) cores, which execute the same instruction sequence, but the operation of one core is slower than the other core by several clock cycles. After executing the same instruction sequence, the output signals of the two cores are sent to a comparator for comparison. If the two are the same, it means that the core is working properly, and if they are different, it means that the core is not working properly, and an out-of-lock alarm is outputted.

[0003] There are usually multiple reset sources in a CPU core. Taking a commonly used ARM core as an example, most of the registers in the core are connected to a system reset, and a small part of the registers are connected to a POR (Power On Reset). The system reset is a local reset, and the POR reset is a global reset. When a system reset occurs while the CPU is writing a POR register, the write operation will be interrupted, which may cause the faster core (the main core) to complete the write operation, and the slower core (the verification core) to not complete the write operation for the lockstep core. Finally, after the system reset is completed, the values of the POR registers of the two cores are different, and if the lockstep core performs a read operation on the POR register, the outputs of the two cores will be different, triggering an out-of-lock alarm. To solve this problem, the commonly used solution is to write and then read the registers by a software program after the system reset, which avoids the out-of-lock alarm. However, the above processing increases the complexity of software development and has certain safety hazards.

[0004] There are signal paths between the system reset registers and the POR registers in the CPU core, such as the path from the R to Q end of the flip-flop Q1 to the D end of the flip-flop Q2 in FIG. 1. The static timing analysis function of the chip back-end EDA tool cannot guarantee the timing quality of such paths, and timing violation problems are prone to occur. To solve this problem, the commonly used solution is to find out such signal paths one by one, and manually constrain, optimize and adjust the delay of the paths to make the paths meet the timing requirements and avoid reset timing violations. However, with the increasing complexity of chips, there are usually several hundred to several thousand such paths. The above solution undoubtedly greatly increases the workload of the chip back-end, and it is easy to miss some paths, which cannot guarantee the reliability. Figure 1 SUMMARY

[0005] ​The embodiment of the present application provides a lockstep core processor, a lockstep core reset circuit and an electronic device, a clock reset control circuit in a check core delays a system reset signal and inputs the system reset signal to a system reset logic circuit, so that the system reset logic circuit is reset for the same time as the input signal delay time when resetting, the check core can be reset after completing the same operation as the main core, and therefore, the problem of inconsistent reset time points of the check core and the main core during local reset, inconsistent storage contents of non-reset registers and lock loss alarm is avoided, and safety is improved.

[0006] The first aspect of the embodiment of the present application provides a lockstep core processor, comprising an input signal delay unit, a main core and a check core for executing the same instruction sequence, the input signal delay unit is connected to an input end of the check core and is used for delaying an input signal relative to the main core by a plurality of clock periods;

[0007] The main core and the check core respectively comprise:

[0008] At least one clock reset control circuit, an input end of the clock reset control circuit is connected to an initial system reset signal and a clock signal, and a system reset input signal is output;

[0009] A system reset logic circuit, an input end of the system reset logic circuit is connected to an output end of at least one clock reset control circuit, the system reset logic circuit is used for receiving the system reset input signal, and the system reset logic circuit is reset when the system is reset, and a signal / data output by the system reset logic circuit is connected to a power-on reset logic circuit;

[0010] The number of delay clock periods of the system reset input signal output by the clock reset control circuit of the check core is the same as the number of delay clock periods of the input signal delay unit, and the system reset input signal output by the clock reset control circuit of the main core is a signal without delay processing.

[0011] In one possible implementation, the main core and the check core respectively further comprise:

[0012] At least one clock shutdown module, an input end of the clock shutdown module is connected to an output end of at least one clock reset control circuit, the clock shutdown module is used for receiving a clock shutdown control signal output by the clock reset control circuit, and a target clock signal after a preset clock period is shielded during the validity of the clock shutdown control signal is output;

[0013] A power-on reset logic circuit, an input end of the power-on reset logic circuit is connected to an output end of at least one clock shutdown module, the power-on reset logic circuit is used for receiving the target clock signal, and the power-on reset logic circuit is used for sampling a signal / data output by the system reset logic circuit based on the target clock signal.

[0014] In a possible implementation, the at least one clock shutdown module has an input end connected to an output end of the at least one clock reset control circuit through a logic OR gate, and the number of clock shutdown modules is the same as the number of clock signals in the lockstep core.

[0015] In a possible implementation, the first clock reset control circuit in the check core includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop, a first inverter, and a first logic AND gate, wherein a D end of the first flip-flop is connected to a high level, an R end of the first flip-flop is connected to a system reset signal port, and a Q end of the first flip-flop is connected to a D end of the second flip-flop.

[0016] A clock signal end of the first flip-flop, a clock signal end of the second flip-flop, a clock signal end of the third flip-flop, a clock signal end of the fourth flip-flop, and a clock signal end of the fifth flip-flop are connected to a clock signal input end, and an R end of the second flip-flop, an R end of the third flip-flop, an R end of the fourth flip-flop, and an R end of the fifth flip-flop are connected to a POR reset signal input end.

[0017] A Q end of the second flip-flop is connected to a D end of the third flip-flop, a Q end of the third flip-flop is connected to a D end of the fourth flip-flop, a Q end of the fourth flip-flop is connected to a system reset signal output port, an input end of the first inverter, and a D end of the fifth flip-flop, an output end of the first inverter and a Q end of the fifth flip-flop are respectively connected to input ends of the first logic AND gate, and the first logic AND gate outputs a clock shutdown control signal.

[0018] In a possible implementation, the clock shutdown module includes a second inverter and a clock shutdown unit, wherein an output end of the second inverter is connected to an enable end of the clock shutdown unit, and an input end of the second inverter is configured to receive the clock shutdown control signal.

[0019] The clock shutdown control signal is transmitted to the enable end of the clock shutdown unit through the second inverter, a clock signal input end of the clock shutdown unit is configured to receive a clock signal, and an output end of the clock shutdown unit outputs a target clock signal after a preset clock period is shielded during a valid period of the clock shutdown control signal.

[0020] In a possible implementation, the second clock reset control circuit in the main core includes a sixth flip-flop, a seventh flip-flop, an eighth flip-flop, a third inverter, and a second logic AND gate, wherein a D end of the sixth flip-flop is connected to a high level, an R end of the sixth flip-flop is connected to a system reset signal port, and a Q end of the sixth flip-flop is connected to a D end of the seventh flip-flop.

[0021] The clock signal port of the sixth flip-flop, the clock signal port of the seventh flip-flop, and the clock signal port of the eighth flip-flop are connected with the clock signal input port, and the R port of the seventh flip-flop and the R port of the eighth flip-flop are connected with the POR reset signal input port;

[0022] The Q port of the seventh flip-flop is connected with the D port of the eighth flip-flop, the system reset signal output port, and the input port of the third inverter, the output port of the third inverter and the Q port of the eighth flip-flop are respectively connected with the input ports of the second logic AND gate, and the second logic AND gate outputs a clock-off control signal.

[0023] In a possible implementation, the number of clock reset control circuits is the same as the number of non-power-on reset sources.

[0024] The second aspect of the embodiments of the present application provides a lockstep core reset circuit, and the chip includes a circuit board and the lockstep core processor as any one of the first aspect, and the lockstep core processor is arranged on the circuit board.

[0025] The third aspect of the embodiments of the present application provides an electronic device, and the electronic device includes a shell and the lockstep core reset circuit as the second aspect, and the lockstep core reset circuit is arranged in the shell.

[0026] The embodiments of the present application have at least the following beneficial effects:

[0027] The system reset signal is input to the system reset logic circuit after being delayed by the clock reset control circuit in the verification core, so that the system reset logic circuit has the same delay time when performing the reset processing as the input signal delay time, and the verification core can complete the same operation as the main core before being reset, thereby avoiding the problem of inconsistent reset time points of the verification core and the main core during local reset, inconsistent storage contents of the non-reset register, and loss of lock alarm, and improving the safety.

[0028] The clock signal of the non-reset circuit is turned off during local reset, thereby avoiding the problem of timing during reset. The workload of chip back-end timing constraints is greatly reduced, and the chip reliability is improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0030] Figure 1 A signal path schematic diagram in the prior art is provided for the embodiments of the present application.

[0031] Figure 2 A structure schematic diagram of a lockstep core processor is provided for the embodiments of the present application.

[0032] Figure 3 Another structure schematic diagram of a lockstep core processor is provided for the embodiments of the present application.

[0033] Figure 4 A structure schematic diagram of a first clock reset control circuit is provided for the embodiments of the present application.

[0034] Figure 5 A structure schematic diagram of a first clock shutdown module is provided for the embodiments of the present application.

[0035] Figure 6 A structure schematic diagram of a second clock reset control circuit is provided for the embodiments of the present application.

[0036] Figure 7 A signal waveform diagram is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0038] The terms “first”, “second”, and the like in the specification and claims of the present application and the above drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed or can optionally include other steps or units inherent to the process, method, product, or device.

[0039] In the present application, “embodiments” are mentioned, which means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in the present application can be combined with other embodiments.

[0040] The lockstep core processor provided by the embodiment of the present application can input the system reset signal delayed by the clock reset control circuit in the check core to the system reset logic circuit, so that the reset delay time and the input signal delay time are the same when the system reset logic circuit performs the reset processing, the check core can complete the same operation as the main core before being reset, and thus the problem of inconsistent reset time points of the check core and the main core during local reset, inconsistent storage contents of the non-reset register and lock loss alarm are avoided, and the safety is improved. Meanwhile, the clock shutdown module can output the clock shutdown control signal to the clock shutdown module when outputting the delayed system reset signal, the clock shutdown module outputs the target clock signal after shielding the preset clock period during the effective period of the clock shutdown control signal to instruct the power-on reset logic circuit to perform the sampling processing on the signal / data output by the system reset logic circuit according to the target clock signal, and thus the preset clock period is shielded in the target clock signal, the power-on reset logic circuit does not perform the sampling processing on the signal / data output by the system reset logic circuit in the shielded preset clock period, and thus the timing error is avoided, and the reliability of the chip is further improved.

[0041] The lockstep core processor of the embodiment of the present application is introduced as follows. The lockstep core processor includes an input signal delay unit, a main core and a check core for executing the same instruction sequence, the input signal delay unit is connected to the input end of the check core and is used for delaying the input signal by a plurality of clock periods relative to the main core;

[0042] The main core and the check core respectively include:

[0043] At least one clock reset control circuit, the input end of the clock reset control circuit is connected to the initial system reset signal and the clock signal, and the clock reset control circuit outputs the system reset input signal;

[0044] A system reset logic circuit, the input end of the system reset logic circuit is connected to the output end of the at least one clock reset control circuit, the system reset logic circuit is used for receiving the system reset input signal, the system reset logic circuit is reset during the system reset, and the signal / data output by the system reset logic circuit is connected to the power-on reset logic circuit;

[0045] The number of delay clock periods of the system reset input signal output by the clock reset control circuit of the check core is the same as the number of delay clock periods of the input signal delay unit, and the system reset input signal output by the clock reset control circuit of the main core is the signal without delay processing.

[0046] Specifically, the main core and the check core respectively further include:

[0047] at least one clock shutdown module, an input end of which is connected to an output end of the at least one clock reset control circuit, for receiving a clock shutdown control signal output by the clock reset control circuit and outputting a target clock signal after a preset clock period is shielded during a valid period of the clock shutdown control signal;

[0048] a power-on reset logic circuit, an input end of which is connected to an output end of the at least one clock shutdown module, for receiving the target clock signal and sampling a signal / data output by the system reset logic circuit based on the target clock signal.

[0049] The at least one clock shutdown module, an input end of which is connected to an output end of the at least one clock reset control circuit through a logic OR gate, the number of clock shutdown modules is the same as the number of clock signals in the lockstep core. The number of clock reset control circuits is consistent with the number of reset sources (non-power-on reset sources), and the reset source has its corresponding clock source. For example, if there is one reset source (non-power-on reset source), there is one clock reset control circuit, and if there are two reset sources (non-power-on reset sources), there are two clock reset control circuits. The clock shutdown modules in the main core and the check core can adopt the same circuit structure.

[0050] The input signal delay unit delays the input signal by 2 clock periods relative to the main core, and of course can be other time periods, such as 1, 3 or more clock periods, which are only examples and are not limited. When the clock shutdown module outputs the target clock signal after shielding the preset clock period during the valid period of the clock shutdown control signal, the preset clock period is set by an empirical value or historical data.

[0051] Specifically, as shown in Figure 2 , as shown in Figure 2 , a schematic diagram of a lockstep core processor including one clock reset control circuit in a main core and a check core is shown. The lockstep core processor includes an input signal delay unit 1, an output signal delay unit 8, a main core CPU0, a check core CPU1 and a comparator 6, a signal input port of the lockstep core processor is connected to a signal input port of the main core CPU0 and a signal input port of the check core CPU1 through the input signal delay unit 1, an output port of the check core CPU1 is connected to a first input port of the comparator 6, and a signal output port of the main core CPU0 is connected to a second input port of the comparator 6 through the output signal delay unit 8;

[0052] The check core CPU1 includes a first clock reset control circuit 2, a first system reset logic circuit 3, a first clock shutdown module 4 and a first power-on reset logic circuit 5, wherein,

[0053] The first input port of the first clock reset control circuit 2 is configured to receive a system reset signal, the clock signal input port of the first clock reset control circuit 2 is connected with the clock signal input port of the first clock gating module 4, the clock gating control signal output port of the first clock reset control circuit 2 is connected with the input port of the clock gating module, the system reset signal output port of the first clock reset control circuit 2 is connected with the signal input port of the first system reset logic circuit 3, the output port of the first clock gating module 4 is connected with the clock signal input port of the first system reset logic circuit 3 and the clock signal input port of the first power-on reset logic circuit 5, and the control signal output port of the first system reset logic circuit 3 is connected with the control signal input port of the first power-on reset logic circuit 5.

[0054] The first clock reset control circuit 2 is configured to output the system reset signal after delay to the first system reset logic circuit 3 after receiving the system reset signal, and the clock period of the system reset signal delayed by the first clock reset control circuit 2 is the same as the clock period of the input signal delayed by the input signal delay unit 1 and the clock period of the output signal of the main core CPU 0 delayed by the output signal delay unit 8.

[0055] The first system reset logic circuit 3 performs system reset processing after receiving the delayed system reset signal.

[0056] The first clock reset control circuit 2 is further configured to output the first clock gating control signal to the first clock gating module 4 when outputting the delayed system reset signal, the first clock gating module 4 is configured to output the target clock signal after masking the preset clock period during the clock gating control signal is valid to the first power-on reset logic circuit 5 after receiving the first clock gating control signal, and the first power-on reset logic circuit 5 receives the target clock signal and samples the signal / data output by the first system reset logic circuit 3 based on the target clock signal. The clock period of the system reset signal delayed by the first clock reset control circuit 2 can be multiple clock periods, which can be set according to the use requirement, for example, the clock period of the signal delayed can be 2 clock periods, 4 clock periods, etc.

[0057] Specifically, the main core CPU0 includes a second clock reset control circuit 11, a second system reset logic circuit 7, a second clock-off module 10 and a second power-on reset logic circuit 9. The first input port of the second clock reset control circuit 11 is configured to receive a system reset signal. The clock signal input port of the second clock reset control circuit 11 is connected with the clock signal input port of the second clock-off module 10. The clock-off control signal output port of the second clock reset control circuit 11 is connected with the input port of the clock-off module. The system reset signal output port of the second clock reset control circuit 11 is connected with the signal input port of the second system reset logic circuit 7. The output port of the second clock-off module 10 is connected with the clock signal input port of the second system reset logic circuit 7 and the clock signal input port of the second power-on reset logic circuit 9. The control signal output port of the second system reset logic circuit 7 is connected with the control signal input port of the second power-on reset logic circuit 9. The first system reset logic circuit 3 and the second system reset logic circuit 7 can be general system reset logic circuits. The first power-on reset logic circuit 5 and the second power-on reset logic circuit 9 can be general power-on reset logic circuits. Figure 2 The signal flow direction shown in the figure includes the related signal flow direction of the system reset signal and the control signal. The related modules for processing the input signal are not shown.

[0058] In the specific work of the lockstep core processor, the input signal is continuously processed and the processed signal is output. When the system reset is encountered, the main core CPU0 and the check core CPU1 will receive the system reset signal. After receiving the system reset signal, the second clock reset control circuit 11 in the main core CPU0 does not perform delay processing on the system reset signal, and directly transmits the system reset signal to the second system reset logic circuit 7 (at the same time, the second clock-off control signal is output to the second clock-off module 10). After receiving the system reset signal, the second system reset logic circuit 7 performs reset processing, and the output signal / data becomes a reset state. At the same time, the second clock-off module 10 outputs the target clock signal after shielding the preset clock period during the effective period of the clock-off control signal after receiving the clock-off control signal, to indicate that the second power-on reset logic circuit 9 samples and processes the signal / data output by the second system reset logic circuit 7 according to the target clock signal. Since the preset clock period is shielded in the target clock signal, the second power-on reset logic circuit 9 will not sample and process the signal / data output by the system reset logic circuit during the shielding preset clock period, so that the timing error in the main core CPU0 can be avoided, and the reliability is improved.

[0059] The first clock reset control circuit 2 in the check kernel CPU 1 is used to output the system reset signal to the first system reset logic circuit 3 after delaying the system reset signal after receiving the system reset signal (at the same time, output the first clock shutdown control signal to the first clock shutdown module 4), and the first system reset logic circuit 3 performs system reset processing after receiving the delayed system reset signal, and the output signal / data becomes a reset state. Since the reset delay time and the input signal delay time are the same, the check kernel CPU 1 can be reset after the same operation on the input signal as the main kernel CPU 0, so as to avoid the problem of inconsistent register storage content caused by the lockstep core not being reset during local reset, thereby improving safety. At the same time, the first clock shutdown module 4 outputs the target clock signal after receiving the clock shutdown control signal, and the target clock signal is shielded for a preset clock period during the effective period of the clock shutdown control signal, so as to instruct the first power-on reset logic circuit 5 to sample and process the signal / data output by the first system reset logic circuit 3 according to the target clock signal. Since the target clock signal shields the preset clock period, the first power-on reset logic circuit 5 will not sample and process the signal / data output by the system reset logic circuit during the shielded preset clock period, thereby avoiding the occurrence of timing in the check kernel CPU 1, and improving reliability.

[0060] When there are multiple reset sources and clock sources, corresponding clock reset control circuits, clock shutdown modules and clock sources are designed for multiple reset sources to perform corresponding delay reset processing after the reset signal is sent by the reset source, so as to improve the overall reliability.

[0061] As shown in Figure 3 There are reset source A and reset source B, and clock / reset control circuit_A and clk1 clock shutdown module are designed for reset source A, and clock / reset control circuit_B and clk0 clock shutdown module are designed for reset source B. When the clock / reset control circuit_A and the clock / reset control circuit_B are circuits in the check kernel, their circuit structures are the same as those of the first clock reset control circuit; when the clock / reset control circuit_A and the clock / reset control circuit_B are circuits in the main kernel, their circuit structures are the same as those of the second clock reset control circuit. Similarly, the circuit structure of the clk0 clock shutdown module and the clk1 clock shutdown module is the same as that of the first clock shutdown module.

[0062] The clk0 clock shutdown module is connected to the output terminals of the clock / reset control circuit_A and the clock / reset control circuit_B through a logic OR gate, and the clk1 clock shutdown module is connected to the output terminals of the clock / reset control circuit_A and the clock / reset control circuit_B through a logic OR gate. Specifically, during operation, after A_reset_b arrives, the clock / reset control circuit_A outputs a clock shutdown control signal, and at the same time, clock shutdown control signals A_clk1_off and A_clk0_off are generated, which are input to the corresponding clk0 clock shutdown module and clk1 clock shutdown module through the corresponding logic OR gate, respectively. The clk0 clock shutdown module and the clk1 clock shutdown module output the target clock signal after a preset clock period is shielded during the valid period of the clock shutdown control signal, and finally the power-on reset circuit receives the target signal and performs corresponding processing.

[0063] In one possible implementation, please refer to Figure 4 , Figure 4 The embodiment of the present application provides a structural diagram of a first clock reset control circuit 2. As shown in the figure, Figure 4 The first clock reset control circuit 2 comprises a first flip-flop T1, a second flip-flop T2, a third flip-flop T3, a fourth flip-flop T4, a fifth flip-flop T5, a first inverter 21 and a first logic AND gate 22, wherein the D terminal of the first flip-flop T1 is connected to a high level, the R terminal of the first flip-flop T1 is connected to a system reset signal port, and the Q terminal of the first flip-flop T1 is connected to the D terminal of the second flip-flop T2.

[0064] The clock signal port of the first flip-flop T1, the clock signal port of the second flip-flop T2, the clock signal port of the third flip-flop T3, the clock signal port of the fourth flip-flop T4 and the clock signal port of the fifth flip-flop T5 are connected to a clock signal input port, and the R terminal of the second flip-flop T2, the R terminal of the third flip-flop T3, the R terminal of the fourth flip-flop T4 and the R terminal of the fifth flip-flop T5 are connected to a POR reset signal input port.

[0065] The Q terminal of the second flip-flop T2 is connected to the D terminal of the third flip-flop T3, the Q terminal of the third flip-flop T3 is connected to the D terminal of the fourth flip-flop T4, the Q terminal of the fourth flip-flop T4 is connected to a system reset signal output port, an input port of the first inverter 21 and a D terminal of the fifth flip-flop T5, and the output port of the first inverter 21 and the Q terminal of the fifth flip-flop T5 are respectively connected to the input terminals of the first logic AND gate 22, and the first logic AND gate 22 outputs a first clock shutdown control signal.

[0066] The system reset signal port is used for outputting a system reset signal (low level effective), the second flip-flop T2 is used for output sampling of the first flip-flop T1; the third flip-flop T3 and the fourth flip-flop T4 are cascaded, which are used for delaying the output of the second flip-flop T2 for several clock cycles, the Q end of the fourth flip-flop T4 outputs the delayed system reset signal (low level effective), and the delayed system reset signal is input into the first inverter 21, and the output signal of the fifth flip-flop T5 is input into the first logic AND gate 22, so as to generate the first clock-off control signal, which is then transmitted to the first clock-off module 4 for subsequent processing. Of course, the first clock reset control circuit 2 can also adopt other circuit structures to output the system reset signal and the clock-off control signal meeting the requirements, which is not limited here. The flip-flop in the embodiment of the application can adopt a general flip-flop.

[0067] In one possible implementation, please refer to Figure 5 , Figure 5 The embodiment of the application provides a structural diagram of the first clock-off module 4. As shown in the figure, Figure 5 The first clock-off module 4 comprises a second inverter 41 and a clock-off unit 42, wherein the output end of the second inverter 41 is connected with the enable end of the clock-off unit 42, and the input end of the second inverter 41 is used for receiving the clock-off control signal.

[0068] The clock-off control signal is transmitted to the enable end of the clock-off unit 42 through the second inverter 41, the clock signal input port of the clock-off unit 42 is used for receiving the clock signal, and the output end of the clock-off unit 42 outputs the target clock signal after a preset clock period is shielded during the effective period of the clock-off control signal.

[0069] Of course, when the clock-off unit 42 does not receive the system reset signal, the output end of the clock-off unit 42 is used for outputting the clock signal without off processing to the first system reset logic circuit 3 and the first power-on reset logic circuit 5.

[0070] The preset clock period can be set by actual use demand, or can be set by experience value or historical data. The circuit structure of the second clock reset control circuit 11 is the same as that of the first clock reset control circuit 2.

[0071] In one possible implementation, please refer to Figure 6 , Figure 6 The embodiment of the application provides a structural diagram of the second clock reset control circuit 11. As shown in the figure, Figure 6As shown, the second clock reset control circuit 11 comprises a sixth flip-flop T6, a seventh flip-flop T7, an eighth flip-flop T8, a third inverter 110 and a second logic AND gate 111, wherein the D end of the sixth flip-flop T6 is connected to a high level, the R end of the sixth flip-flop T6 is connected to a system reset signal port, the Q end of the sixth flip-flop T6 is connected to the D end of the seventh flip-flop T7;

[0072] The clock signal port of the sixth flip-flop T6, the clock signal port of the seventh flip-flop T7 and the clock signal port of the eighth flip-flop T8 are connected to a clock signal input port, the R end of the seventh flip-flop T7 and the R end of the eighth flip-flop T8 are connected to a POR reset signal input port;

[0073] The Q end of the seventh flip-flop T7 is connected to the D end of the eighth flip-flop T8, a system reset signal output port and the input port of the third inverter 110, the output port of the third inverter 110 and the Q end of the eighth flip-flop T8 are respectively connected to the input ends of the second logic AND gate, and the second logic AND gate outputs a second clock-off control signal.

[0074] The seventh flip-flop T7 is used for sampling the output of the sixth flip-flop T6, and the seventh flip-flop T7 outputs a system reset signal without delay. After the system reset signal without delay passes through the third inverter 110, and the output signal of the eighth flip-flop T8 passes through the second logic AND gate, the second clock-off control signal is obtained. Of course, the second clock reset control circuit 11 can also adopt other circuit structures for outputting a system reset signal and a clock-off control signal meeting the requirements, which is not limited here.

[0075] Please refer to Figure 7 , Figure 7 A signal waveform diagram is provided for the embodiments of the present application. As shown in Figure 7As shown, for CPU0, when the system reset occurs, sys_rst_b (the system reset signal received by the main core) is pulled low at time 0, system_reset_b (the system reset signal output by the second clock reset control circuit) is pulled low at time 1, and then cpu0_clk_off (the second clock off control signal) is pulled high for one clock period, and the corresponding cpu0_gated_clk (the output signal of the second clock gating module) is gated off for one clock period after system_reset_b is pulled low. The second power-on reset logic circuit 9 in CPU0 does not sample the input signal that changes due to the system reset because it does not receive the clock signal, and thus there is no risk of metastability. For CPU1, when the system reset occurs, sys_rst_b (the system reset signal received by the verification core) is pulled low at time 0, delayed_reset_b (the delayed system reset signal) is pulled low at time 3, and then cpu1_clk_off (the output signal of the first clock gating module) is pulled high for one clock period, and the corresponding cpu1_gated_clk (the output signal of the first clock gating module) is gated off for one clock period after delayed_reset_b is pulled low. The power-on reset logic circuit in CPU1 does not sample the input signal that changes due to the system reset because it does not receive the clock signal, and thus there is no risk of metastability. In addition, delayed_reset_b is delayed by two clock periods compared to system_reset_b, which ensures that the verification core CPU1 and the main core CPU0 are reset after completing the same operation, and the data stored by the power-on reset logic circuits of the verification core CPU1 and the main core CPU0 will also be the same, that is, the verification core CPU1 and the lockstep core are in the same state after the system reset, and there is no problem of unexpected loss of lock.

[0076] In one specific implementation, a lockstep core reset circuit is also provided, which includes a circuit board and a lockstep core processor as described in any of the preceding embodiments, and the lockstep core processor is arranged on the circuit board.

[0077] In one specific implementation, an electronic device is also provided, which includes a housing and a lockstep core reset circuit as described in any of the preceding embodiments, and the lockstep core reset circuit is arranged in the housing.

[0078] In the above embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0079] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments is only a logical function division, and there can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, or the among different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0080] The above has introduced the embodiments of the present application in detail, and the specific examples are applied to the present application to explain the principles and implementation manners of the present application. The above embodiment description is only used to help understand the method of the present application and its core idea; meanwhile, for the general skilled in the art, according to the idea of the present application, the specific implementation manner and application range will have changes, and the above description should not be understood as the limitation of the present application.

Claims

1. A lockstep core processor, comprising: The input signal delay unit is connected to the input end of the check core, and is used to delay the input signal relative to the main core by a plurality of clock cycles; The main core and the check core respectively comprise: At least one clock reset control circuit, which is connected to the initial system reset signal and the clock signal, and outputs a system reset input signal; A system reset logic circuit, which is connected to the output end of the clock reset control circuit, receives the system reset input signal, and is reset during system reset, and outputs a signal / data connected to the power-on reset logic circuit; The clock reset control circuit of the check core outputs a system reset signal, which has the same number of delayed clock cycles as the input signal delay unit, and the clock reset control circuit of the main core outputs a system reset input signal which is not delayed. The main core and the check core respectively further comprise: At least one clock-off module, which is connected to the output end of the clock reset control circuit, receives the clock-off control signal output by the clock reset control circuit, and outputs a target clock signal after a preset clock cycle during which the clock-off control signal is valid; A power-on reset logic circuit, which is connected to the output end of the clock-off module, receives the target clock signal, and samples the signal / data output by the system reset logic circuit based on the target clock signal.

2. The lockstep core processor of claim 1, wherein, The input end of the clock-off module is connected to the output end of the clock reset control circuit through a logic OR gate, and the number of clock-off modules is the same as the number of clock signals in the lockstep core.

3. The lockstep core processor of any of claims 1-2, wherein, The first clock reset control circuit in the check core comprises a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop, a first inverter, and a first logic AND gate, wherein the D end of the first flip-flop is connected to a high level, the R end of the first flip-flop is connected to a system reset signal port, and the Q end of the first flip-flop is connected to the D end of the second flip-flop; The clock signal port of the first flip-flop, the clock signal port of the second flip-flop, the clock signal port of the third flip-flop, the clock signal port of the fourth flip-flop, and the clock signal port of the fifth flip-flop are connected to a clock signal input port, and the R end of the second flip-flop, the R end of the third flip-flop, the R end of the fourth flip-flop, and the R end of the fifth flip-flop are connected to a POR reset signal input port; The Q end of the second flip-flop is connected to the D end of the third flip-flop, the Q end of the third flip-flop is connected to the D end of the fourth flip-flop, the Q end of the fourth flip-flop is connected to a system reset signal output port, an input port of a first inverter, and a D end of a fifth flip-flop, the output port of the first inverter and the Q end of the fifth flip-flop are respectively connected to the input ends of a first logic AND gate, and the first logic AND gate outputs a clock-off control signal.

4. The lockstep core processor of claim 3, wherein, The clock-off module comprises a second inverter and a clock-off unit, wherein an output end of the second inverter is connected with an enable end of the clock-off unit, and an input end of the second inverter is used for receiving a clock-off control signal; The clock-off control signal is transmitted to the enable end of the clock-off unit through the second inverter, a clock signal input port of the clock-off unit is used for receiving a clock signal, and an output end of the clock-off unit outputs a target clock signal after a preset clock period is shielded during a valid period of the clock-off control signal.

5. The lockstep core processor of claim 4, wherein, The second clock reset control circuit in the main core comprises a sixth flip-flop, a seventh flip-flop, an eighth flip-flop, a third inverter and a second logic AND gate, wherein a D end of the sixth flip-flop is connected with a high level, an R end of the sixth flip-flop is connected with a system reset signal port, and a Q end of the sixth flip-flop is connected with a D end of the seventh flip-flop; A clock signal port of the sixth flip-flop, a clock signal port of the seventh flip-flop and a clock signal port of the eighth flip-flop are connected with a clock signal input port, and an R end of the seventh flip-flop and an R end of the eighth flip-flop are connected with a POR reset signal input port; A Q end of the seventh flip-flop is connected with a D end of the eighth flip-flop, a system reset signal output port and an input port of the third inverter, an output port of the third inverter and a Q end of the eighth flip-flop are respectively connected with input ends of the second logic AND gate, and the second logic AND gate outputs a clock-off control signal.

6. The lockstepped core processor of claim 4 or 5, wherein, The number of clock reset control circuits is the same as the number of non-power-on reset sources.

7. A lockstep core reset circuit, comprising: The lockstep core reset circuit comprises a circuit board and the lockstep core processor according to any one of claims 1-6, and the lockstep core processor is arranged on the circuit board.

8. An electronic device, comprising: The electronic device comprises a shell and the lockstep core reset circuit according to claim 7, and the lockstep core reset circuit is arranged in the shell. The electronic device comprises a shell and the lockstep core reset circuit according to claim 7, and the lockstep core reset circuit is arranged in the shell.

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