A processor pipeline apparatus and instruction processing method

Abstract

The embodiment of the present application provides a processor pipeline device and an instruction processing method, the processor pipeline device comprises a branch prediction unit, a fetch unit, a decoding unit and a compression detection subunit, the branch prediction unit predicts a jump direction and a jump target address of a branch instruction in a CPU front end, the branch prediction unit comprises a branch target buffer BTB, the compression detection subunit detects whether N fetch blocks after a jump target contain a jump instruction, when the N fetch blocks do not contain the jump instruction, the N fetch blocks are compressed into one entry of the branch target buffer BTB, N is a natural number greater than 1; when the entry is used to predict a branch corresponding to the jump target, multi-tick access is performed according to a maximum fetch bandwidth of the branch prediction unit. The processor pipeline device provided by the embodiment of the present application can perform compressed access when subsequent prediction is performed, and the bandwidth of the prediction unit is improved.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and in particular to a processor pipeline device and instruction processing method. Background Technology

[0002] The Central Processing Unit (CPU), also commonly known as a processor, is the core component of a processor-based system. Processors are found in various fields, including but not limited to mobile communication devices, smart computing terminals, intelligent driving control, and smart home appliances, and are widely used in various computing devices to perform computing tasks for various applications. With the explosive growth of artificial intelligence and the deepening of the Internet of Things (IoT) concept of interconnected everything, processors that combine high-performance computing and low power consumption have become the cornerstone of control centers sought after in various fields.

[0003] Faced with increasingly complex usage scenarios and real-time control requirements, processors often need to run more complex applications than ever before. In these complex control applications, branch instructions will account for a higher proportion of the total program instructions. Branch instructions can change the computer's default behavior of processing instructions sequentially, causing the program to begin processing different instruction sequences at a different branch target address than the next instruction following the branch instruction.

[0004] In modern processor design, the processor front-end primarily handles instruction fetching and branch prediction. In traditional coupled processor architectures, the fetch and branch prediction pipelines are fully coupled. This leads to cavitation during instruction fetching when a branch prediction error occurs, or pipeline stalls when there are icache misses or TLB misses, preventing further branch prediction. Therefore, a decoupled fetch architecture is introduced to decouple instruction fetching and branch prediction. However, this decoupled architecture requires the bandwidth of the branch prediction unit to be greater than that of the fetch unit to effectively improve the front-end's fetch bandwidth. Simply increasing the prediction access bandwidth is insufficient; the access bandwidth of a series of predictors, such as the Branch Target Buffer (BTB) and the conditional branch predictor, needs to be increased synchronously. Furthermore, due to branch jumps, the actual bandwidth improvement is not significant. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a processor pipeline apparatus and instruction processing method to solve some or all of the above-mentioned problems.

[0006] According to a first aspect of the present invention, a processor pipeline apparatus is provided, the processor pipeline apparatus including a branch prediction unit, an instruction fetch unit, a decoding unit, and a compression detection subunit;

[0007] The branch prediction unit predicts the jump direction and target address of the branch instruction in the CPU front end. The branch prediction unit includes a branch target buffer (BTB), which is used to cache known branch instruction addresses and their target addresses. The instruction fetch unit reads the instruction from memory according to the target address given by the branch prediction unit, and then passes it to the subsequent decoding unit.

[0008] The compression detection subunit detects whether the N fetch blocks behind the jump target address of the fetch block where the jump instruction is located contain a jump instruction. If the N fetch blocks do not contain a jump instruction, the N fetch blocks are compressed into an entry of the branch target buffer BTB, where N is a natural number greater than 1.

[0009] When the branch prediction unit uses this entry to predict the corresponding branch, it performs multi-step access according to the maximum fetch bandwidth of the branch prediction unit.

[0010] According to a second aspect of the present invention, a processor pipeline instruction processing method is provided, wherein the processor pipeline apparatus includes a branch prediction unit, an instruction fetch unit, a decoding unit, and a compression detection subunit; the method includes:

[0011] The compression detection subunit detects whether the N fetch blocks behind the jump target address B of the fetch block (A) where the jump instruction is located contain a jump instruction;

[0012] When the N fetch blocks do not contain jump instructions, the N fetch blocks are compressed into one entry of the branch target buffer (BTB), where N is a natural number greater than 1.

[0013] When the branch prediction unit uses this entry to predict the corresponding branch, it performs multi-step access according to the maximum fetch bandwidth of the branch prediction unit.

[0014] The processor pipeline device provided in this embodiment of the invention, which implements BTB compression, requires the joint implementation of a compression detection subunit and the BTB. The compression detection subunit needs to detect whether there is a sequential access pattern of multiple fetch blocks after the target address of a jump instruction, where no jump instruction is present. When this pattern is met, it is recorded in the BTB. The BTB needs to record this type of access for the compressed sequence by expanding or reusing some information fields. During subsequent prediction, when this prediction flag is detected, compressed access is performed, improving the bandwidth of the prediction unit. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0016] Figure 1 A schematic diagram of one embodiment of the processor pipeline device provided in this invention;

[0017] Figure 2 A schematic diagram of another embodiment of the processor pipeline device provided in this invention;

[0018] Figure 3 This is a schematic diagram of an application scenario of the processor pipeline device provided in an embodiment of the present invention;

[0019] Figure 4 A schematic diagram of another embodiment of the processor pipeline device provided in this invention;

[0020] Figure 5 A flowchart of one embodiment of the processor pipeline instruction processing method provided by the present invention;

[0021] Figure 6 A flowchart of another embodiment of the processor pipeline device instruction processing method provided in this invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0023] The following explains some of the technologies described in this application.

[0024] Decoupled architecture: To improve front-end fetch bandwidth and solve pipeline stall problems caused by simultaneous fetching and prediction, an architecture that separates prediction and fetching is typically used in ultra-high-performance processors.

[0025] Fetch bandwidth: The number of instruction bytes or instructions that a processor can fetch from the instruction cache (I-Cache) and deliver to the next pipeline stage per clock cycle.

[0026] Branch Target Buffer (BTB): A cache that stores the addresses of known branch instructions and their target addresses.

[0027] Fetch Block: Refers to the smallest granularity of instruction fetch access, usually N=^m. A fetch block refers to a continuous segment of instructions that is fetched at one time to fill the cache or supply the decoder. It bridges the "memory width" and the "processor issue width" and is a common means for the CPU front end to improve bandwidth and hide latency.

[0028] Branch prediction: Branch prediction is a crucial technique in modern processors used to improve instruction pipeline efficiency. In programs, conditional jump statements (such as if, for, while, etc.) frequently occur, causing branches in the program's execution flow. When executing these branch instructions, the processor cannot immediately know which instruction will be executed next because the condition may not yet be calculated. To avoid pipeline stalls, the processor predicts in advance which branch is more likely to be adopted and then continues executing instructions in that direction.

[0029] The Fetch Target Queue (FTQ) is a buffer queue between the Branch Processing Unit (BPU) and the Instruction Fetch Unit (IFU) in the processor microarchitecture. The FTQ is the scheduling and replay buffer on the "branch prediction → instruction fetch" path, which allows the prediction, instruction fetch and training steps to be performed with high bandwidth and in order.

[0030] In related technologies, such as ARM's 2-taken branch technology, jump information is compressed. "2-taken branch" refers to the ability to predict and execute two "taken" branch instructions in parallel per clock cycle. The CPU can "jump twice" in one cycle, and both jumps are predicted to "occur." When consecutive jumps are detected, the target addresses of the two consecutive jump instructions are compressed into a single BTB entry. During access, the CPU directly jumps to the target address of the second branch for instruction fetching, thereby increasing the access bandwidth of the branch prediction unit without increasing the main path predictor's access bandwidth. However, it cannot effectively accelerate sequential access sequences, thus failing to improve bandwidth.

[0031] This invention provides a processor pipeline device, such as... Figure 1As shown, the processor pipeline device 100 includes a front-end processing module and a back-end processing module. The front-end processing module 110 and the back-end processing module 120 of the processor are the two major parts that functionally divide the out-of-order pipeline.

[0032] The front-end processing module 110 is the core module in the processor responsible for instruction preprocessing. Its main task is to fetch instructions from memory or cache, decode them into executable micro-operations (μops), and reduce pipeline stalls through branch prediction technology. The efficiency of the front-end directly affects the overall performance of the CPU, especially in high-frequency and complex instruction sets (such as x86), where the design of the front-end is particularly critical. Typically, the front-end processing module includes an instruction fetch unit and a decoding unit.

[0033] The backend processing module 120 is responsible for instruction scheduling, execution, and writing back operation results. The backend module includes execution units, retirement units, etc.

[0034] like Figure 2 As shown, in one embodiment of the present invention, the front-end processing module 110 includes a branch prediction unit, an instruction fetching unit, and a decoding unit, and the processor pipeline device 100 further includes a compression detection subunit; in this embodiment, the branch target buffer (BTB) is located within the branch prediction unit; and the compression detection subunit is located within the instruction fetching unit.

[0035] The branch prediction unit predicts the jump direction and target address of the branch instruction in the CPU front end. The branch prediction unit includes a branch target buffer (BTB), which is used to cache known branch instruction addresses and their target addresses. The instruction fetch unit reads the instruction from memory according to the target address given by the branch prediction unit, and then passes it to the subsequent decoding unit.

[0036] The compression detection subunit detects whether the N fetch blocks behind the jump target address B of the fetch block (A) where the jump instruction is located contain a jump instruction. If the N fetch blocks do not contain a jump instruction, the N fetch blocks are compressed into an entry of the branch target buffer BTB, where N is a natural number greater than 1.

[0037] When the branch prediction unit uses this entry to predict the corresponding branch, it performs multi-step access according to the maximum fetch bandwidth of the branch prediction unit.

[0038] like Figure 3 As shown, for the non-sequential access branch target buffer BTB in related technologies, A is the fetch block where the detection is located, and its target address is B. If address A jumps to address B (address B is located on the fetch block with the starting address aligned with address C), the mapping relationship A->B is stored in the entry of BTB.

[0039] In the embodiment provided by the present invention, the compression detection subunit detects whether the N fetch blocks behind the jump target address B of the fetch block (A) where the jump instruction is located contain a jump instruction. When the N fetch blocks do not contain a jump instruction, the compression detection subunit compresses them into an entry in the BTB. When the fetch unit uses this entry to predict the A branch, it can perform multi-step access according to the maximum fetch bandwidth of the prediction unit, thereby significantly improving the prediction bandwidth.

[0040] More specifically, the compression detection subunit detects whether the N instruction fetch blocks behind the jump target contain jump instructions, which can be achieved in the following way:

[0041] The backend information of all N instruction fetch blocks is scanned to check whether they contain jump instructions. The instruction block information is obtained by decoding the instructions through the decoding unit.

[0042] For example, if the normal fetch bandwidth of a branch prediction unit is 2, and after A jumps to B, there are N subsequent sequential fetch blocks (N>1), then:

[0043] When N≤3, after the jump, a maximum of four instruction fetch blocks (B, C+FB, C+2*FB, and C+3*FB) can be accessed once. B and C+FB do not require further access to BTB for branch prediction because these addresses are already considered to have no branch instructions, thus not increasing the access bandwidth of the main path predictor. In other words, when N≤3, the instruction segment corresponding to the jump target address B and the next instruction segment are executed without accessing the branch target buffer BTB for branch prediction.

[0044] When a jump is followed by consecutive non-jump instruction fetch blocks and N>3, a special flag is used to record this situation if the instruction fetch block address meets certain conditions. When this flag is detected, instruction blocks with a fetch bandwidth greater than the normal fetch bandwidth are created for multiple consecutive cycles, potentially enabling multiple cycles of instruction fetching at a rate greater than the normal fetch bandwidth.

[0045] The Branch Target Buffer (BTB) expands or reuses some information fields in the compressed entries (for example, if the high-order addresses of instruction blocks are the same, the stored content can be reused; for different types of compression, the same field is used for recording) to record this type of access. The BTB marks fetch blocks that meet the compression conditions by recording accesses of different jump instruction types, indicating that this is a compressed access. This allows the branch prediction unit to perform a compressed access if it finds the prediction mark during subsequent predictions.

[0046] The processor pipeline device provided in this embodiment of the invention, which implements BTB compression, requires the joint implementation of a compression detection subunit and the BTB. The compression detection subunit needs to detect whether there is a sequential access pattern for multiple fetch blocks after the target address of the jump instruction. When this condition is met, the BTB is recorded. The BTB needs to expand or reuse some information fields on this compressed sequence. During subsequent prediction, when this prediction marker is found, compressed access is performed, thereby improving the bandwidth of the prediction unit.

[0047] like Figure 4 As shown, in another embodiment of the present invention, the front-end processing module 110 includes a branch prediction unit, an instruction fetching unit, and a decoding unit, and the processor pipeline device 100 further includes a compression detection subunit; in this embodiment, the branch target buffer (BTB) is located within the branch prediction unit; the compression detection subunit is located within the retirement unit of the back-end processing module 120.

[0048] Preferably, the processor pipeline apparatus further includes an instruction fetch target queue for temporarily storing the instruction fetch target addresses predicted by the branch prediction unit and sending the instruction fetch target addresses to the instruction fetch unit in sequence.

[0049] In this embodiment, the compression detection subunit processes compression commands in a manner similar to... Figure 2 The illustrated embodiment is the same, so it will not be described in detail. However, placing the compression detection subunit within the retirement unit of the backend processing module may lead to prediction errors when the instruction fetching unit performs predictions for conditional jump instruction types, which may not actually jump. Placing it within the retirement unit makes the judgment on whether to jump more accurate, but it increases the maintenance overhead of the entire link.

[0050] like Figure 5 As shown, this embodiment of the invention also provides a processor pipeline instruction processing method, which can be applied to... Figure 2 or Figure 4 In the apparatus shown, the method may include:

[0051] S501: The compression detection subunit detects whether the N instruction fetching blocks at the back end of the jump target contain jump instructions;

[0052] S502: When the N fetch blocks do not contain jump instructions, the N fetch blocks are compressed into one entry of the branch target buffer BTB, where N is a natural number greater than 1;

[0053] S503: When the branch prediction unit uses this entry to predict the corresponding branch, it performs multi-step access according to the maximum fetch bandwidth of the branch prediction unit.

[0054] When N≤3, the instruction segment corresponding to the jump target address B and the next instruction segment do not access the branch target buffer BTB for branch prediction.

[0055] In an optional implementation, step S501: the compression detection subunit detects whether the N instruction fetch blocks behind the jump target contain jump instructions, which may further include:

[0056] The backend information of all N instruction fetch blocks is scanned to check whether they contain jump instructions. The instruction block information is obtained by decoding the instructions through the decoding unit.

[0057] Figure 6 A flowchart of another embodiment of the processor pipeline device instruction processing method provided by the present invention. In an optional embodiment, after step S501, the method further includes:

[0058] When the N instruction fetch blocks contain jump instructions, the following processing is performed:

[0059] S504: If the compression detection subunit detects that the N instruction fetch blocks behind the jump target contain jump instructions, it does not perform compression and skips this action.

[0060] The processor pipeline device provided in this embodiment of the invention, which achieves BTB compression, requires the joint implementation of a compression detection subunit and the BTB. In the compression detection subunit, it is necessary to detect whether there is a sequential access scenario where no jump instruction is present in the multi-fetch block following the target address of the jump instruction. When this scenario is met, the BTB is trained.

[0061] The branch target buffer (BTB) expands or reuses some information fields for the compressed entries, records accesses of different jump instruction types, and marks fetch blocks that meet the compression conditions to indicate that they are compressed accesses, so that the branch prediction unit can perform compressed accesses in subsequent predictions.

[0062] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of the present invention can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0063] The methods described above according to embodiments of the present invention can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded over a network. Thus, the methods described herein can be stored as software processing on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the business object switching method described herein. Furthermore, when a general-purpose computer accesses code used to implement the business object switching method shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the business object switching method shown herein.

[0064] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments of the present invention.

[0065] The above embodiments are only used to illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A processor pipeline device, characterized in that, The processor pipeline device includes a branch prediction unit, an instruction fetch unit, a decoding unit, and a compression detection subunit; The branch prediction unit predicts the jump direction and target address of the branch instruction in the CPU front end. The branch prediction unit includes a branch target buffer (BTB), which is used to cache known branch instruction addresses and their target addresses. The instruction fetch unit reads the instruction from memory according to the target address given by the branch prediction unit, and then passes it to the subsequent decoding unit. The compression detection subunit detects whether the N fetch blocks behind the jump target address of the fetch block where the jump instruction is located contain a jump instruction. If the N fetch blocks do not contain a jump instruction, the N fetch blocks are compressed into an entry of the branch target buffer BTB, where N is a natural number greater than 1. When the branch prediction unit uses this entry to predict the corresponding branch, it performs multi-step access according to the maximum fetch bandwidth of the branch prediction unit.

2. The apparatus as claimed in claim 1, characterized in that, Also includes: The instruction fetch target queue is used to temporarily store the instruction fetch target addresses predicted by the branch prediction unit, and to send the instruction fetch target addresses to the instruction fetch unit in sequence.

3. The apparatus as described in claim 1, characterized in that, The compression detection subunit is located within the instruction fetching unit.

4. The apparatus as claimed in claim 1, characterized in that, The processor pipeline device also includes a retirement unit, and the compression detection subunit is located within the retirement unit.

5. The apparatus as claimed in claim 1, characterized in that, When the compression detection subunit detects that the N instruction fetch blocks behind the jump target contain jump instructions, it does not perform compression and skips this action.

6. The apparatus as claimed in claim 1, characterized in that, The compression detection subunit determines whether the N backend instruction fetch blocks contain jump instructions in the following manner: The backend scans all N fetch block information to check if they contain jump instructions. The fetch block information is obtained by decoding the instructions through the decoding unit.

7. The apparatus as claimed in claim 1, characterized in that, The branch target buffer (BTB) marks the fetch blocks that meet the compression conditions for the compressed entries, indicating that this is a compressed access.

8. The apparatus as claimed in claim 1, characterized in that, When N≤3, the instruction segment corresponding to the jump target address B and the next instruction segment do not access the branch target buffer BTB for branch prediction.

9. A processor pipeline instruction processing method, applied to a processor pipeline apparatus according to any one of claims 1-8, characterized in that, The processor pipeline includes a branch prediction unit, an instruction fetch unit, a decoding unit, and a compression detection subunit; the method includes: The compression detection subunit detects whether the N fetch blocks behind the jump target address of the fetch block where the jump instruction is located contain a jump instruction; When the N fetch blocks do not contain jump instructions, the N fetch blocks are compressed into one entry of the branch target buffer (BTB), where N is a natural number greater than 1. When the branch prediction unit uses this entry to predict the corresponding branch, it performs multi-step access according to the maximum fetch bandwidth of the branch prediction unit.

10. The method as described in claim 9, characterized in that, The compression detection subunit detects whether the N instruction fetch blocks behind the jump target contain jump instructions, and further includes: The backend scans all N fetch block information to check if they contain jump instructions. The fetch block information is obtained by decoding the instructions through the decoding unit.

11. The method as described in claim 9, characterized in that, Also includes: When the N instruction fetch blocks contain jump instructions, the following processing is performed: When the N instruction fetch blocks behind the jump target contain jump instructions, compression is not performed and the action is skipped.

12. The method as described in claim 9, characterized in that, The branch target buffer (BTB) marks the fetch blocks that meet the compression conditions for the compressed entries, indicating that this is a compressed access.

13. The method as described in claim 9, characterized in that, When N≤3, the instruction segment corresponding to the jump target address B and the instruction segment following it do not access the branch target buffer BTB for branch prediction.

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