Method and device for realizing bidirectional transmission of data frame between FPGA and CPU based on shared memory mechanism

Abstract

The application discloses a kind of based on shared memory mechanism and realizes FPGA and CPU data frame bidirectional transceiving method and device, the method is divided out in CPU and set size RAM space as shared memory, shared memory includes FPGA / CPU control register and corresponding read-write address space;FPGA is connected with CPU by SBD bus, after both sides power-on initialization is completed, according to control register state, read-write data in corresponding address space.The application improves bidirectional transmission speed without increasing cost and power consumption, solves the problems such as low transmission rate, unable to meet real-time and performance requirements when low-speed interface such as UART, SPI is used between existing low-end FPGA and CPU.

Description

Technical Field

[0001] This invention relates to the field of computer network communication technology, and specifically to a method and apparatus for bidirectional transmission and reception of data frames between FPGA and CPU based on a shared memory mechanism. Background Technology

[0002] In current embedded systems applications, collaboration between CPUs and FPGAs is widespread, and various communication methods exist, including high-speed interfaces such as PCIe, SRIO, SGMII, GMII, and RGMII, as well as low-speed interfaces like I2C, SPI, and UART. Using high-speed interfaces places certain demands on the configuration of both the CPU and FPGA; otherwise, low-end CPUs and FPGAs may not support high-speed interfaces. Using low-speed interfaces, on the other hand, has lower configuration requirements for both the CPU and FPGA, making it easier to use in low-power, low-cost application environments.

[0003] Choosing a relatively low-end CPU and FPGA hardware architecture and using UART, SPI, and I2C interfaces for data transmission is a common practice. However, the data transmission rate is a significant bottleneck when using UART, SPI, and I2C interfaces for communication. UART typically has a maximum baud rate of only 921,000, SPI can reach 20 Mbps, and I2C has a transmission capability of only Kbps. For applications with high real-time requirements and specific transmission performance requirements, using low-speed UART, SPI, and I2C is unlikely to meet the needs.

[0004] Therefore, how to invent a method for bidirectional transmission and reception of data frames between FPGA and CPU based on a shared memory mechanism, and improve the bidirectional transmission speed without increasing cost and power consumption, has become an urgent problem to be solved. Summary of the Invention

[0005] To address this issue, the present invention provides a method and apparatus for bidirectional transmission and reception of data frames between FPGA and CPU based on a shared memory mechanism, which solves the problem that the transmission rate is low and cannot meet the real-time and performance requirements when existing low-end FPGAs and CPUs use low-speed interfaces such as UART and SPI.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for bidirectional data frame transmission and reception between FPGA and CPU based on a shared memory mechanism, comprising:

[0007] A RAM space of a set size is allocated in the CPU as shared memory; the shared memory is then divided into FPGA control registers, CPU control registers, FPGA write / CPU read address space, and CPU write / FPGA read address space.

[0008] Based on the shared memory, the FPGA and CPU are connected via the SBD bus;

[0009] The FPGA is powered on and reset, and its internal modules and interfaces are initialized. The CPU control register is read cyclically through the SBD bus, and the interaction status is determined according to the read content. If the CPU control register

[14] is 0, the data to be sent is written into the FPGA write / CPU read address space, and the transmission length and write completion flag of the FPGA control register are set. The write completion flag is reset after the CPU sets the read completion flag. If the CPU control register

[15] is 1, the data is read from the CPU write / FPGA read address space, and the read completion flag of the FPGA control register is set. The read completion flag is reset after the CPU resets the write completion flag.

[0010] The CPU is powered on and reset, and initializes the operating parameters, interface and cache space; through the SBD bus, the FPGA control register is read in a loop, and the interaction status is determined according to the read content: if the FPGA control register

[15] is 1, then data is read from the FPGA write / CPU read address space, and the CPU control register read completion flag is set; after the FPGA resets the write completion flag, the read completion flag is reset; if the FPGA control register

[14] is 0, then the data to be sent is written into the CPU write / FPGA read address space, and the transmission length and write completion flag of the CPU control register are set; after the FPGA sets the read completion flag, the write completion flag is reset.

[0011] As a preferred embodiment of the bidirectional data frame transmission and reception method between FPGA and CPU based on the shared memory mechanism, the SBD bus includes the following signals: sbd_addr, sbd_dbus, sbd_clk, sbd_cen, sbd_wen, sbd_oen, and sbd_size.

[0012] As a preferred embodiment of the bidirectional data frame transmission and reception method between FPGA and CPU based on the shared memory mechanism, the FPGA control register

[15] is the FPGA write completion flag; the FPGA control register

[14] is the FPGA read completion flag; the FPGA control register [13:0] is the FPGA transmission data length; the CPU control register

[15] is the CPU write completion flag; the CPU control register

[14] is the CPU read completion flag; and the CPU control register [13:0] is the CPU transmission data length.

[0013] As a preferred embodiment of the bidirectional data frame transmission and reception method between FPGA and CPU based on the shared memory mechanism, the address space of the FPGA control register is 0x0000-0x0001; the address space of the CPU control register is 0x0002-0x0003; the FPGA write address space is 0x0004-0x3fff; the CPU read address space is also 0x0004-0x3fff; the CPU write address space is 0x4000-0x7fff; and the FPGA read address space is also 0x4000-0x7fff.

[0014] As a preferred solution for implementing bidirectional data frame transmission and reception between FPGA and CPU based on shared memory mechanism, the data length written by FPGA to the starting address space of 0x0004 shall not exceed 0x3ffc bytes; the data length written by CPU to the starting address space of 0x4000 shall not exceed 0x4000 bytes.

[0015] This invention also provides a device for bidirectional transmission and reception of FPGA and CPU data frames based on a shared memory mechanism. Based on the above method for bidirectional transmission and reception of FPGA and CPU data frames based on a shared memory mechanism, it includes:

[0016] A shared memory partitioning unit is used to partition a set size of RAM space in the CPU as shared memory; the shared memory is divided into FPGA control registers, CPU control registers, FPGA write / CPU read address space, and CPU write / FPGA read address space;

[0017] The SBD bus connection unit is used to connect the FPGA and the CPU via the SBD bus based on the shared memory.

[0018] The FPGA data processing unit is used to power-on reset the FPGA and initialize the internal modules and interfaces; it reads the CPU control register cyclically through the SBD bus and determines the interaction status based on the read content; if the CPU control register

[14] is 0, the data to be sent is written into the FPGA write / CPU read address space, and the transmission length and write completion flag of the FPGA control register are set; the write completion flag is reset after the CPU sets the read completion flag; if the CPU control register

[15] is 1, the data is read from the CPU write / FPGA read address space, and the read completion flag of the FPGA control register is set; the read completion flag is reset after the CPU resets the write completion flag;

[0019] The CPU data processing unit is used to reset the CPU upon power-on and initialize the operating parameters, interface, and cache space; it reads the FPGA control register cyclically through the SBD bus and determines the interaction status based on the read content: if the FPGA control register

[15] is 1, it reads data from the FPGA write / CPU read address space and sets the CPU control register read completion flag; after the FPGA resets the write completion flag, it resets the read completion flag; if the FPGA control register

[14] is 0, it writes the data to be sent into the CPU write / FPGA read address space and sets the transmission length and write completion flag of the CPU control register; after the FPGA sets the read completion flag, it resets the write completion flag.

[0020] As a preferred solution for implementing a bidirectional data frame transceiver device between FPGA and CPU based on a shared memory mechanism, the SBD bus connection unit includes the following SBD bus signals: sbd_addr, sbd_dbus, sbd_clk, sbd_cen, sbd_wen, sbd_oen, and sbd_size.

[0021] As a preferred embodiment of a bidirectional data frame transceiver device for FPGA and CPU based on a shared memory mechanism, in the FPGA data processing unit and the CPU data processing unit, the FPGA control register

[15] is the FPGA write completion flag; the FPGA control register

[14] is the FPGA read completion flag; the FPGA control register [13:0] is the FPGA transmission data length; the CPU control register

[15] is the CPU write completion flag; the CPU control register

[14] is the CPU read completion flag; and the CPU control register [13:0] is the CPU transmission data length.

[0022] As a preferred embodiment of a bidirectional data frame transceiver device between FPGA and CPU based on a shared memory mechanism, in the shared memory partitioning unit, the address space of the FPGA control register is 0x0000-0x0001; the address space of the CPU control register is 0x0002-0x0003; the FPGA write address space is 0x0004-0x3fff; the CPU read address space is also 0x0004-0x3fff; the CPU write address space is 0x4000-0x7fff; and the FPGA read address space is also 0x4000-0x7fff.

[0023] As a preferred embodiment of a bidirectional data frame transceiver device for FPGA and CPU based on a shared memory mechanism, in the FPGA data processing unit, the length of data written by the FPGA to the 0x0004 starting address space does not exceed 0x3ffc bytes.

[0024] In the CPU data processing unit, the length of data written by the CPU to the starting address space of 0x4000 does not exceed 0x4000 bytes.

[0025] The present invention has the following advantages: The present invention divides 32K RAM space in the CPU as shared memory; divides the shared memory into FPGA control register, CPU control register, FPGA write / CPU read address space and CPU write / FPGA read address space; based on the shared memory, the FPGA and CPU are connected through the SBD bus; the FPGA is powered on and reset and initializes the internal modules and interfaces; through the SBD bus, the CPU control register is read in a loop, and the interaction status is determined according to the read content; if the CPU control register

[14] is 0, the data to be sent is written into the FPGA write / CPU read address space, and the transmission length and write completion flag of the FPGA control register are set; after the CPU sets the read completion flag, the write completion flag is reset; if the CPU control register

[15] is 1, the data to be sent is written from the CPU write / FPGA read address space. Read the data and set the read completion flag of the FPGA control register; reset the read completion flag after the CPU resets the write completion flag; power on the CPU and initialize the running parameters, interface and cache space; read the FPGA control register cyclically through the SBD bus and determine the interaction status according to the read content: if the FPGA control register

[15] is 1, read the data from the FPGA write / CPU read address space and set the read completion flag of the CPU control register; reset the read completion flag after the FPGA resets the write completion flag; if the FPGA control register

[14] is 0, write the data to be sent into the CPU write / FPGA read address space and set the transmission length and write completion flag of the CPU control register; reset the write completion flag after the FPGA sets the read completion flag. This invention, without increasing hardware costs and power consumption, achieves data and state separation by dividing and partitioning shared memory of a CPU into different sizes, constructing an efficient transmission channel via the SBD bus, and ensuring reliable interaction through dual control register synchronization. This design solves the problem of low transmission rate and inability to meet real-time requirements when low-end FPGAs and CPUs use low-speed interfaces such as UART and SPI, improves bidirectional transmission rate, effectively avoids data loss and overwriting, and is suitable for low-power, low-cost embedded scenarios, balancing high-speed transmission and reliable performance. Attached Figure Description

[0026] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0027] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0028] Figure 1 This is a flowchart illustrating the method for bidirectional data frame transmission and reception between FPGA and CPU based on a shared memory mechanism, as provided in Embodiment 1 of the present invention.

[0029] Figure 2 This is a schematic diagram of the CPU and FPGA system composition in the method for bidirectional transmission and reception of FPGA and CPU data frames based on shared memory mechanism provided in Embodiment 1 of the present invention;

[0030] Figure 3 This is a schematic diagram of the FPGA logic processing flow in the method for bidirectional transmission and reception of FPGA and CPU data frames based on shared memory mechanism provided in Embodiment 1 of the present invention.

[0031] Figure 4 This is a schematic diagram of the CPU logic processing flow in the method for bidirectional transmission and reception of FPGA and CPU data frames based on shared memory mechanism provided in Embodiment 1 of the present invention;

[0032] Figure 5 This is a schematic diagram of the architecture of the bidirectional data frame transceiver device based on shared memory mechanism provided in Embodiment 2 of the present invention. Detailed Implementation

[0033] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Example 1

[0035] See Figure 1 Embodiment 1 of the present invention provides a method for bidirectional transmission and reception of data frames between FPGA and CPU based on a shared memory mechanism, comprising the following steps:

[0036] S1. Allocate 32K RAM space in the CPU as shared memory; divide the shared memory into FPGA control register, CPU control register, FPGA write / CPU read address space and CPU write / FPGA read address space;

[0037] S2. Based on the shared memory, connect the FPGA and the CPU via the SBD bus;

[0038] S3. The FPGA is powered on and reset, and its internal modules and interfaces are initialized. The CPU control register is read in a loop through the SBD bus, and the interaction status is determined according to the read content. If the CPU control register

[14] is 0, the data to be sent is written into the FPGA write / CPU read address space, and the transmission length and write completion flag of the FPGA control register are set. The write completion flag is reset after the CPU sets the read completion flag. If the CPU control register

[15] is 1, the data is read from the CPU write / FPGA read address space, and the read completion flag of the FPGA control register is set. The read completion flag is reset after the CPU resets the write completion flag.

[0039] S4. The CPU is powered on and reset, and the operating parameters, interface and cache space are initialized. The FPGA control register is read in a loop through the SBD bus, and the interaction status is determined according to the read content: if the FPGA control register

[15] is 1, data is read from the FPGA write / CPU read address space, and the CPU control register read completion flag is set; the read completion flag is reset after the FPGA resets the write completion flag; if the FPGA control register

[14] is 0, the data to be sent is written into the CPU write / FPGA read address space, and the transmission length and write completion flag of the CPU control register are set; the write completion flag is reset after the FPGA sets the read completion flag.

[0040] In this embodiment, a system integrating a bidirectional data frame transmission and reception method for FPGA and CPU based on a shared memory mechanism is as follows: Figure 2 As shown, the system employs a collaborative approach between the FPGA and CPU. The FPGA handles the main SBD interface control, slave SBD interface control, FIFO buffering, and AXI bus control; the CPU handles the AHB slave module, 32K shared memory block, slave SBD interface control, AHB-to-SBD interface conversion, and main SBD interface control. The system comprises the following components:

[0041] CPU (A001): It communicates with the kernel via the AHB bus and provides shared memory RAM blocks; it transmits and receives data with A002 via the SBD bus interface.

[0042] FPGA (A002): Provides a standard AXI stream bus interface for the FPGA, buffers data packets through FIFO, and transmits and receives data through the SBD bus interface and A001.

[0043] In this embodiment, in step S1, 32K RAM space is allocated in the CPU as shared memory; the shared memory is divided into FPGA control register, CPU control register, FPGA write / CPU read address space and CPU write / FPGA read address space;

[0044] Specifically, the FPGA control register

[15] is the FPGA write completion flag; the FPGA control register

[14] is the FPGA read completion flag; the FPGA control register [13:0] is the FPGA data transmission length; the CPU control register

[15] is the CPU write completion flag; the CPU control register

[14] is the CPU read completion flag; and the CPU control register [13:0] is the CPU data transmission length.

[0045] The address space of the FPGA control register is 0x0000-0x0001; the address space of the CPU control register is 0x0002-0x0003; the FPGA write address space is 0x0004; the CPU read address space is 0x3fff; the CPU write address space is 0x4000; and the FPGA read address space is 0x7fff.

[0046] Specifically, as shown in Table 1:

[0047]

[0048]

[0049] Table 1 Shared Memory Address Allocation

[0050] In this embodiment, in step S2, the FPGA and CPU are connected via the SBD bus based on the shared memory;

[0051] The SBD bus includes: a 15-bit address signal sbd_addr, a 16-bit bidirectional data signal sbd_dbus, a clock signal sbd_clk, a low-active enable signal sbd_cen, a low-active write enable signal sbd_wen, a high-active output enable signal sbd_oen, and a 2-bit width selection signal sbd_size, which together form the hardware channel for data transmission between the two.

[0052] Specifically, as shown in Table 2:

[0053]

[0054] Table 2 Shared Memory Address Allocation

[0055] In this embodiment, in step S3, the FPGA is powered on and reset, and its internal modules and interfaces are initialized; the CPU control register is read cyclically through the SBD bus, and the interaction status is determined according to the read content; if the CPU control register

[14] is 0, the data to be sent is written into the FPGA write / CPU read address space, and the transmission length and write completion flag of the FPGA control register are set; the write completion flag is reset after the CPU sets the read completion flag; if the CPU control register

[15] is 1, the data is read from the CPU write / FPGA read address space, and the read completion flag of the FPGA control register is set; the read completion flag is reset after the CPU resets the write completion flag;

[0056] Specifically, the FPGA processing flow is as follows: Figure 3 As shown:

[0057] S001: After power-on, the reset is completed, the internal modules and interfaces of the FPGA are initialized, and the next step is to proceed to S002;

[0058] S002: In the initial state,

[15] and

[14] in the FPGA control register are set to 0;

[0059] S003: Read the CPU control register. If

[14] is 0, jump to S101. If

[15] is 1, jump to S201. Otherwise, continue reading the CPU control register.

[0060] S101: Write data of length L to be sent into the data space starting at address 0x0004, where L does not exceed 0x3ffc bytes;

[0061] S102: Fill the length L of the data transmitted in this FPGA control register [13:0], and set

[15] in the FPGA control register to 1;

[0062] S103: Read the CPU control register. If

[14] is 1, continue to the next step; otherwise, read the CPU control register continuously until

[14] is 1, then continue to the next step.

[0063] S104: Set

[15] in the FPGA control register to 0;

[0064] S105: When sending data again, start from S003;

[0065] S201: Retrieve the [13:0] records from the control register as the length value L;

[0066] S202: Read data of length L starting from address 0x4000;

[0067] S203: Set

[14] in the FPGA control register to 1;

[0068] S204: Read the CPU control register. If

[15] is 0, jump to S205; otherwise, keep polling the controller.

[0069] S205: Set

[14] in the FPGA control register to 0;

[0070] S206: Jump back to S003.

[0071] In this embodiment, in step S4, the CPU is powered on and reset, and the operating parameters, interface and cache space are initialized; the FPGA control register is read cyclically through the SBD bus, and the interaction status is determined according to the read content: if the FPGA control register

[15] is 1, data is read from the FPGA write / CPU read address space, and the CPU control register read completion flag is set; the read completion flag is reset after the FPGA resets the write completion flag; if the FPGA control register

[14] is 0, the data to be sent is written into the CPU write / FPGA read address space, and the transmission length and write completion flag of the CPU control register are set; the write completion flag is reset after the FPGA sets the read completion flag.

[0072] Specifically, the CPU processing flow is as follows: Figure 4 As shown:

[0073] S401: After power-on, complete the reset, initialize the operating parameters, interfaces, buffer space, etc., and then proceed to S402.

[0074] S402: In the CPU control register,

[15] is set to 0 and

[14] is set to 0;

[0075] S403: Read whether FPGA control register

[15] is 1. If

[15] is 1, jump to S501. If

[14] is 0, jump to S601. Otherwise, continue reading FPGA control register.

[0076] S501: Read the FPGA control register [13:0] and record it as the length value L;

[0077] S502: Read data of length L starting from address 0x0004;

[0078] S503: Set

[14] in the CPU control register to 1;

[0079] S504: Poll the FPGA control register until

[15] is 0;

[0080] S505: Set

[14] in the CPU control register to 0;

[0081] S506: Transmission complete, jump back to S403;

[0082] S601: Write data of length L to be sent into the data space starting at address 0x4000, where L does not exceed 0x4000 bytes;

[0083] S602: Set

[15] to 1 in the CPU control register, and fill in the length L of the data to be transmitted in [13:0];

[0084] S603: Poll the FPGA control register until

[14] is 1;

[0085] S604: Set

[15] to 0 and clear [13:0] to 0 in the CPU control register;

[0086] S605: Poll the FPGA control register until

[14] is 0;

[0087] S606: Transmission complete, jump back to S403.

[0088] The application scenarios of this invention are as follows:

[0089] This invention is applicable to embedded scenarios requiring low power consumption, low cost, and certain data transmission rates and real-time performance. Examples include bidirectional real-time transmission of sensor data and control commands between low-end FPGAs and CPUs in industrial control; efficient interaction of device status data and control signals in smart home systems; and rapid transmission and processing of image data acquired by the front-end FPGA to the CPU in security monitoring scenarios. It can also be used for low-power data interaction between FPGAs and CPUs in portable smart devices, achieving 300Mbps bidirectional high-speed and reliable transmission without increasing hardware costs or power consumption, thus meeting the requirements of these scenarios.

[0090] It should be noted that the method of this disclosure embodiment can be executed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this disclosure embodiment, and the multiple devices will interact with each other to complete the method described.

[0091] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0092] Example 2

[0093] See Figure 5 Embodiment 2 of the present invention also provides a bidirectional data frame transceiver device for FPGA and CPU based on a shared memory mechanism, comprising:

[0094] The shared memory partitioning unit 001 is used to partition 32K RAM space in the CPU as shared memory; the shared memory is divided into FPGA control register, CPU control register, FPGA write / CPU read address space and CPU write / FPGA read address space;

[0095] SBD bus connection unit 002 is used to connect the FPGA and the CPU via the SBD bus based on the shared memory;

[0096] FPGA data processing unit 003 is used to power-on reset the FPGA and initialize the internal modules and interfaces; through the SBD bus, it cyclically reads the CPU control register and determines the interaction status based on the read content; if the CPU control register

[14] is 0, it writes the data to be sent into the FPGA write / CPU read address space and sets the transmission length and write completion flag of the FPGA control register; after the CPU sets the read completion flag, it resets the write completion flag; if the CPU control register

[15] is 1, it reads data from the CPU write / FPGA read address space and sets the read completion flag of the FPGA control register; after the CPU resets the write completion flag, it resets the read completion flag.

[0097] The CPU data processing unit 004 is used to reset the CPU upon power-on and initialize the operating parameters, interface, and cache space; it reads the FPGA control register cyclically through the SBD bus and determines the interaction status based on the read content: if the FPGA control register

[15] is 1, it reads data from the FPGA write / CPU read address space and sets the CPU control register read completion flag; after the FPGA resets the write completion flag, it resets the read completion flag; if the FPGA control register

[14] is 0, it writes the data to be sent into the CPU write / FPGA read address space and sets the transmission length and write completion flag of the CPU control register; after the FPGA sets the read completion flag, it resets the write completion flag.

[0098] In this embodiment, the SBD bus in the SBD bus connection unit 002 includes the following signals: sbd_addr, sbd_dbus, sbd_clk, sbd_cen, sbd_wen, sbd_oen, and sbd_size.

[0099] In this embodiment, in the FPGA data processing unit 003 and the CPU data processing unit 004, the FPGA control register

[15] is the FPGA write completion flag; the FPGA control register

[14] is the FPGA read completion flag; the FPGA control register [13:0] is the FPGA transmission data length; the CPU control register

[15] is the CPU write completion flag; the CPU control register

[14] is the CPU read completion flag; and the CPU control register [13:0] is the CPU transmission data length.

[0100] In this embodiment, in the shared memory partitioning unit 001, the address space of the FPGA control register is 0x0000-0x0001; the address space of the CPU control register is 0x0002-0x0003; the FPGA write address space is 0x0004-0x3fff; the CPU read address space is 0x0004-0x3fff; the CPU write address space is 0x4000-0x7fff; and the FPGA read address space is 0x4000-0x7fff.

[0101] In this embodiment, the length of data written by the FPGA to the 0x0004 starting address space in the FPGA data processing unit 003 does not exceed 0x3ffc bytes;

[0102] In the CPU data processing unit 004, the length of data written by the CPU to the starting address space of 0x4000 does not exceed 0x4000 bytes.

[0103] It should be noted that the information interaction and execution process between the modules of the above system are based on the same concept as the method embodiment in Embodiment 1 of this application, and the resulting technical effects are the same as those in the method embodiment of this application. For details, please refer to the description in the method embodiment shown above in this application, and it will not be repeated here.

[0104] Example 3

[0105] Embodiment 3 of the present invention provides a non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores program code for implementing a bidirectional data frame transmission and reception method for FPGA and CPU based on a shared memory mechanism, the program code including instructions for executing the bidirectional data frame transmission and reception method for FPGA and CPU based on a shared memory mechanism as described in Embodiment 1 or any possible implementation thereof.

[0106] Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives, SSDs).

[0107] Example 4

[0108] Embodiment 4 of the present invention provides an electronic device, including: a memory and a processor;

[0109] The processor and the memory communicate with each other via a bus; the memory stores program instructions that can be executed by the processor, and the processor can call the program instructions to execute the bidirectional data frame transmission and reception method for FPGA and CPU based on a shared memory mechanism, as described in Embodiment 1 or any possible implementation thereof.

[0110] Specifically, a processor can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. This memory can be integrated into the processor or located outside the processor and exist independently.

[0111] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable system. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0112] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing systems. They can be centralized on a single computing system or distributed across a network of multiple computing systems. Optionally, they can be implemented using program code executable by a computing system, thereby storing them in a storage system for execution by the computing system. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0113] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A method for bidirectional data frame transmission and reception between FPGA and CPU based on a shared memory mechanism, characterized in that, include: A set size of RAM space is allocated in the CPU as shared memory; the shared memory is divided into FPGA control register, CPU control register, FPGA write or CPU read address space and CPU write or FPGA read address space; Based on the shared memory, the FPGA and CPU are connected via the SBD bus; The FPGA is powered on and reset, and its internal modules and interfaces are initialized. The CPU control register is read cyclically via the SBD bus, and the interaction status is determined based on the read content. If the CPU read completion flag in the CPU control register is 0, the data to be sent is written to the FPGA write or CPU read address space, and the transmission length and write completion flag of the FPGA control register are set. The write completion flag is reset after the CPU sets the read completion flag. If the CPU write completion flag in the CPU control register is 1, data is read from the CPU write or FPGA read address space, and the read completion flag of the FPGA control register is set. The CPU will reset the write completion flag and then reset the read completion flag. The CPU is powered on and reset, and initializes the operating parameters, interfaces and cache space. The FPGA control register is read cyclically through the SBD bus, and the interaction status is determined according to the read content: if the FPGA write completion flag of the FPGA control register is 1, data is read from the FPGA write or CPU read address space, and the CPU control register read completion flag is set. After the FPGA resets the write completion flag, reset the read completion flag. If the FPGA read completion flag in the FPGA control register is 0, the data to be sent is written into the CPU write or FPGA read address space, and the transmission length and write completion flag of the CPU control register are set; the write completion flag is reset after the FPGA sets the read completion flag.

2. The method for bidirectional transmission and reception of data frames between FPGA and CPU based on shared memory mechanism according to claim 1, characterized in that, The SBD bus includes the following signals: sbd_addr, sbd_dbus, sbd_clk, sbd_cen, sbd_wen, sbd_oen, and sbd_size.

3. The method for bidirectional transmission and reception of FPGA and CPU data frames based on shared memory mechanism according to claim 2, characterized in that, The address space of the FPGA control register is 0x0000-0x0001; the address space of the CPU control register is 0x0002-0x0003; the FPGA write address space is 0x0004-0x3fff; the CPU read address space is also 0x0004-0x3fff; the CPU write address space is 0x4000-0x7fff; and the FPGA read address space is also 0x4000-0x7fff.

4. The method for bidirectional transmission and reception of FPGA and CPU data frames based on shared memory mechanism according to claim 3, characterized in that, The length of data written to the FPGA starting address space (0x0004) shall not exceed 0x3ffc bytes; the length of data written to the CPU starting address space (0x4000) shall not exceed 0x4000 bytes.

5. A bidirectional data frame transceiver device for FPGA and CPU based on a shared memory mechanism, employing the bidirectional data frame transceiver method for FPGA and CPU based on a shared memory mechanism as described in any one of claims 1-4, characterized in that, include: A shared memory partitioning unit is used to partition a set size of RAM space in the CPU as shared memory; the shared memory is divided into FPGA control registers, CPU control registers, FPGA write or CPU read address space, and CPU write or FPGA read address space. The SBD bus connection unit is used to connect the FPGA and the CPU via the SBD bus based on the shared memory. The FPGA data processing unit is used for FPGA power-on reset and initialization of internal modules and interfaces; it cyclically reads the CPU control register through the SBD bus and determines the interaction status based on the read content; if the CPU read completion flag of the CPU control register is 0, it writes the data to be sent into the FPGA write or CPU read address space and sets the transmission length and write completion flag of the FPGA control register; it resets the write completion flag after the CPU sets the read completion flag; if the CPU write completion flag of the CPU control register is 1, it reads data from the CPU write or FPGA read address space and sets the read completion flag of the FPGA control register. The CPU will reset the write completion flag and then reset the read completion flag. The CPU data processing unit is used for CPU power-on reset and initialization of operating parameters, interfaces and cache space; it reads the FPGA control register cyclically through the SBD bus and determines the interaction status based on the read content: if the FPGA write completion flag of the FPGA control register is 1, it reads data from the FPGA write or CPU read address space and sets the CPU control register read completion flag. After the FPGA resets the write completion flag, reset the read completion flag. If the FPGA read completion flag in the FPGA control register is 0, the data to be sent is written into the CPU write or FPGA read address space, and the transmission length and write completion flag of the CPU control register are set; the write completion flag is reset after the FPGA sets the read completion flag.

6. The bidirectional data frame transceiver device for FPGA and CPU based on shared memory mechanism according to claim 5, characterized in that, The SBD bus connection unit includes the following SBD bus signals: sbd_addr, sbd_dbus, sbd_clk, sbd_cen, sbd_wen, sbd_oen, and sbd_size.

7. The bidirectional data frame transceiver device for FPGA and CPU based on shared memory mechanism according to claim 6, characterized in that, In the shared memory partitioning unit, the address space of the FPGA control register is 0x0000-0x0001; the address space of the CPU control register is 0x0002-0x0003; the FPGA write address space is 0x0004-0x3fff; the CPU read address space is also 0x0004-0x3fff; the CPU write address space is 0x4000-0x7fff; and the FPGA read address space is also 0x4000-0x7fff.

8. The bidirectional data frame transceiver device for FPGA and CPU based on shared memory mechanism according to claim 7, characterized in that, In the FPGA data processing unit, the length of data written by the FPGA to the 0x0004 starting address space does not exceed 0x3ffc bytes. In the CPU data processing unit, the length of data written by the CPU to the starting address space of 0x4000 does not exceed 0x4000 bytes.

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