Compound chip flip airtight packaging preparation method and packaged chip
By etching the cavity and electroplating solder on the silicon-based adapter board, combined with flip-chip sealing and plastic encapsulation protection, the problem of insufficient hermeticity of packaged chips is solved, achieving a small package with high reliability and flexibility.
Patent Information
- Application Number
- CN202511312118.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-15
- Publication Date
- 2025-12-19
AI Technical Summary
The existing technology cannot meet the airtightness requirements while ensuring the smallest possible packaged chip size.
Grooves are etched into a silicon-based adapter to form cavities that match the number of compound chips. Solder is electroplated around the cavities and on the top of the silicon pillars. The compound chips are then sealed using a flip-chip method and double-sealed using molding compound.
It achieves hermeticity of the chip in a small package, reduces signal transmission attenuation and interference, improves signal integrity, adapts to different needs, reduces production costs and R&D cycle, and prevents chip oxidation and corrosion.
Smart Images
Figure CN121171901A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor packaging, in particular to a compound chip flip airtight packaging preparation method and a packaged chip. BACKGROUND
[0002] With the rapid development of communication systems, higher requirements are put forward for the size, performance and reliability of electronic components. Advanced packaging technology represented by chip flip uses vertical stacking to replace the horizontal layout of chips, achieving high-density heterogeneous integration of multiple chips with different functions, greatly reducing the packaging area. At the same time, micro-bumps are used as communication connection links between chips to reduce signal transmission length and parasitic effects caused by high-frequency environment, which can be applied to high-frequency and high-speed packaging scenarios. With the rapid development of high-density packaging, a series of reliability problems have also emerged. The protection of the surface of the packaged chip and the failure of the micro-bump have become factors restricting the reliability of the product. The open structure of the flip chip requires the subsequent assembly components to be airtight. How to achieve airtight packaging of flip chips with the smallest volume is one of the problems that need to be solved. SUMMARY
[0003] The present application provides a compound chip flip airtight packaging preparation method and a packaged chip to solve the problem that the airtightness requirement of the packaged chip cannot be met while ensuring the smallest volume of the packaged chip in the prior art.
[0004] In a first aspect, the present application provides a compound chip flip airtight packaging preparation method, comprising:
[0005] According to the number of compound chips to be packaged, grooves are etched on the top surface of the silicon-based adapter board to obtain silicon-based adapter board cavities consistent with the number of compound chips to be packaged, each silicon-based adapter board cavity containing a plurality of silicon pillars corresponding to the chip function points or contact points of the corresponding compound chip;
[0006] Electroplating solder around each silicon-based adapter board cavity and at the top end of each silicon pillar;
[0007] Each compound chip is sealed and installed on the corresponding silicon-based adapter board cavity in a flip manner, and the back surface of each packaged compound chip is plasticized using plastic sealing material. One side of the compound chip with chip function points or contact points is opposite to the back surface of the compound chip.
[0008] In a second aspect, the present application provides a packaged chip prepared by the compound chip flip airtight packaging preparation method of the first aspect.
[0009] This application provides a method for fabricating a flip-chip hermetic package for compound chips and a packaged chip. The method involves etching grooves on the top surface of a silicon-based interposer according to the number of compound chips to be packaged, resulting in a silicon-based interposer cavity matching the number of compound chips to be packaged. Each silicon-based interposer cavity contains multiple silicon pillars corresponding to the chip function points or ground points of the corresponding compound chip. Solder is electroplated around the perimeter of each silicon-based interposer cavity and at the top of each silicon pillar. Each compound chip is flip-chip sealed onto the corresponding silicon-based interposer cavity, and the back side of each packaged compound chip is encapsulated using molding compound. The side of the compound chip with the chip function points or ground points faces the back side of the compound chip. This application sets silicon pillars corresponding to the functional points or ground points of the compound chip in the cavity of the silicon-based adapter board, realizing a precise point-to-point connection between the chip and the adapter board. This design greatly shortens the signal transmission path and reduces signal attenuation and interference during transmission. Especially for high-frequency radio frequency circuits, it can effectively improve signal integrity and transmission quality, making the chip perform better in high-speed data transmission and processing. In addition, according to the number of compound chips to be packaged, a corresponding number of cavities are etched on the silicon-based adapter board. This fabrication method has strong customization flexibility and can meet the diverse needs of different customers and application scenarios for the number and specifications of chips. It does not require large-scale process adjustments and equipment modifications, reducing production costs and shortening the R&D cycle. At the same time, by flip-chip sealing the compound chip on the cavity of the silicon-based adapter board and using molding compound to encapsulate the back of the chip, a double-sealed protection structure is formed, which effectively prevents external moisture, oxygen and corrosive gases from entering the chip and prevents the chip from failing due to oxidation, corrosion and other reasons. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in this application, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 This is a schematic flowchart of the compound chip flip-chip hermetic packaging preparation method provided in the embodiments of this application;
[0012] Figure 2 This is a schematic diagram of the structure of the packaged chip prepared by the compound chip flip-chip hermetic packaging method provided in the embodiments of this application;
[0013] Figure 3 This is a three-dimensional structural diagram of the top surface of the silicon-based adapter provided in the embodiments of this application;
[0014] Figure 4 is a structural schematic diagram of the back of the silicon-based adapter plate provided by the embodiment of the present application;
[0015] Figure 5 is a structural schematic diagram of the compound chip provided by the embodiment of the present application;
[0016] Figure 6 is a three-dimensional structural diagram of the heat dissipation cold plate provided by the embodiment of the present application.
[0017] Wherein, 1 is plastic sealing material, 2 is silicon-based adapter plate, 3 is heat dissipation cold plate, 4-6 are all compound chips, 21 is sealing ring solder for silicon-based adapter plate cavity, 22 is solder interconnecting with compound chip radio frequency pad, 23 is silicon-based adapter plate cavity, 24 is silicon column, 25 is BGA pad, 26 is TSV hole, 51 is compound substrate, 52 is compound chip sealing ring, and 53 is compound chip radio frequency pad. DETAILED DESCRIPTION
[0018] In the following description, specific details are set forth such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, persons skilled in the art will understand that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
[0019] In order to make the objectives, technical schemes and advantages of the present application clearer, the following will be described by specific embodiments in conjunction with the accompanying drawings.
[0020] In order to solve the problem that the air tightness requirement of the packaged chip cannot be met when the volume of the packaged chip is guaranteed to be the smallest in the prior art, the present application provides a compound chip flip-chip air-tight packaging preparation method, which realizes the vertical stacking of the chip and the air tightness of the product, and further provides a manufacturing scheme of the packaging structure.
[0021] Figure 1 The implementation flowchart of the compound chip flip-chip air-tight packaging preparation method provided by the embodiment of the present application is described in detail as follows:
[0022] In step 101, according to the number of compound chips to be packaged, grooves are etched on the top surface of the silicon-based adapter plate to obtain silicon-based adapter plate cavities consistent with the number of compound chips to be packaged, and each silicon-based adapter plate cavity contains a plurality of silicon columns corresponding to the chip function points or contact points of the corresponding compound chip.
[0023] In the embodiment of the present application, according to the number of compound chips required for the prepared packaged chip, grooves are etched on the top surface of the silicon-based adapter board to obtain a corresponding number of silicon-based adapter board cavities. It should be noted that while etching the grooves, corresponding silicon pillars are also etched in the corresponding silicon-based adapter board cavities according to the positions of the chip functional points or contact points (i.e., the positions of the radio frequency pads of the compound chips) on each compound chip.
[0024] For example, referring to Figure 2 , 2 is a silicon-based adapter board, and 4-6 are compound chips. When the packaged chip requires 3 compound chips, grooves are etched on the top surface of the silicon-based adapter board 2 according to the size of each compound chip to obtain a silicon-based adapter board cavity corresponding to the compound chip 4, a silicon-based adapter board cavity corresponding to the compound chip 5, and a silicon-based adapter board cavity corresponding to the compound chip 6, respectively.
[0025] For example, according to the positions of the chip functional points or contact points of the compound chip 4, the compound chip 5, and the compound chip 6, corresponding silicon pillars are etched in the corresponding silicon-based adapter board cavities. For example, referring to Figure 3 , taking the compound chip 6 as an example, 23 is a silicon-based adapter board cavity corresponding to the compound chip 6, and 24 is a silicon pillar in the silicon-based adapter board cavity 23. When the compound chip 6 uniformly distributes 6 chip functional points or contact points, corresponding silicon pillars 24 are etched in the silicon-based adapter board cavity 23 according to the positions of the corresponding points.
[0026] The embodiment of the present application provides silicon pillars corresponding to the functional points or contact points of the compound chips in the silicon-based adapter board cavities, which realizes accurate point-to-point connection between the chips and the adapter board. This design greatly shortens the signal transmission path, reduces the attenuation and interference of the signal in the transmission process, especially for high-frequency radio frequency circuits, which can effectively improve the integrity and transmission quality of the signal, so that the chip performs better in high-speed data transmission and processing.
[0027] In addition, the embodiment of the present application etches a corresponding number of cavities on the silicon-based adapter board according to the number of compound chips required for packaging, and this preparation method has strong customization flexibility. It can meet the diversified needs of chip quantity and specifications of different customers and different application scenarios without the need for large-scale process adjustment and equipment modification, thereby reducing production cost and research and development period.
[0028] In a possible implementation, etching grooves on the top surface of the silicon-based adapter board according to the number of compound chips required for packaging to obtain silicon-based adapter board cavities consistent with the number of compound chips required for packaging can include:
[0029] According to the number of compound chips to be packaged, a dry etching method is used to etch and groove on the top surface of the silicon interposer to obtain silicon interposer cavities consistent with the number of compound chips to be packaged.
[0030] Optionally, a dry etching method is used to etch and groove on the top surface of the silicon interposer according to the size of the corresponding compound chip to obtain the corresponding silicon interposer cavity.
[0031] Correspondingly, the silicon column in each silicon interposer cavity is also realized by a dry etching method.
[0032] In step 102, solder is electroplated around each silicon interposer cavity and on the top end of each silicon column.
[0033] In the embodiment of the present application, before flip-chip sealing, solder is electroplated around each silicon interposer cavity and on the top end of each silicon column. The electroplated solder includes sealing ring solder for the silicon interposer cavity and solder for interconnection with the radio frequency pads of the compound chip.
[0034] For example, referring to FIG. 2, Figure 3 As shown in FIG. 2, 21 is the sealing ring solder for the silicon interposer cavity 23, 22 is the solder for interconnection with the radio frequency pads of the compound chip, and the top end of the silicon column 24 also has the solder 22 for interconnection with the radio frequency pads of the compound chip. Therefore, before flip-chip sealing, solder is electroplated around the silicon interposer cavity 23, on the top end of the silicon column 24, and in the silicon interposer cavity 23 at positions corresponding to the radio frequency pads of the compound chip.
[0035] The purpose of electroplating solder on the top end of the silicon column is to interconnect with the grounding point or functional point of the compound chip.
[0036] The embodiment of the present application electroplated solder around the silicon interposer cavity and on the top end of the silicon column, and then formed the solder joint through the flip-chip sealing process. This solder joint structure has high mechanical strength and thermal stability, and can withstand the thermal stress and mechanical stress generated by the chip during operation, reducing the occurrence of faults such as solder joint cracking and falling off. Moreover, the process of electroplating solder can accurately control the composition and thickness of the solder, optimize the performance of the solder joint, improve the reliability and durability of the solder joint, and ensure long-term stable operation of the chip.
[0037] In a possible implementation, the back surface of the silicon interposer is provided with BGA pads; before electroplating solder around each silicon interposer cavity and on the top end of each silicon column, the method can further include:
[0038] The position of each silicon column is found on the BGA pad, and a TSV hole is prepared for each silicon column to realize the interconnection between the top surface and the back surface of the silicon interposer.
[0039] Optionally, since the BGA is a key conductive area for connecting the BGA packaging device and the printed circuit board (PCB) in the electronic packaging technology, the design thereof directly affects the signal transmission, heat dissipation performance and soldering reliability, therefore, as shown in Figure 4 , the embodiment of the present application is provided with the BGA pad 25 on the back surface of the silicon adapter board, and the BGA pad 25 is obtained by electroplating.
[0040] Then the position of each silicon column is determined on the BGA pad 25, and the TSV hole of each silicon column is prepared to realize the interconnection of the top surface and the back surface of the silicon adapter board, and ensure the air tightness of the packaged chip. Wherein, the TSV hole is prepared by etching the silicon base material and electroplating copper. For example, as shown in Figure 3 , 26 is the TSV hole, i.e. the TSV hole prepared in each silicon column 24.
[0041] Wherein, the material of the BGA pad can be nickel gold.
[0042] The embodiment of the present application realizes the air tight packaging of multiple compound chips by adopting the slotted silicon adapter board flip-chip mode based on the chip heterogeneous integration technology and the compound chip and pre-sealing ring structure, and the packaging has the advantages of small volume, high reliability and high integration. The subsequent packaging structure is assembled with the motherboard through the BGA on the back surface of the silicon adapter board.
[0043] In step 103, each compound chip is sealed and mounted on the corresponding silicon adapter board cavity by flip-chip mode, and the back surface of each packaged compound chip is plastic encapsulated by using plastic encapsulating material. The side with chip functional points or grounding points of the compound chip is opposite to the back surface of the compound chip.
[0044] In the embodiment of the present application, the side with chip functional points or grounding points of each compound chip is sealed and mounted on the corresponding silicon adapter board cavity by flip-chip mode. Then, in order to protect each exposed compound chip (i.e. the back surface of each compound chip is exposed after flip-chip installation), the compound chip is plastic encapsulated by using plastic encapsulating material to realize the protection of the compound chip.
[0045] For example, as shown in Figure 5 , the structure of the compound chip 4-6 includes: compound base material 51, compound chip sealing ring 52 and compound chip radio frequency pad 53. The compound base material 51 can be GaAs or GaN, and the compound chip sealing ring 52 and the compound chip radio frequency pad 53 are electroplated gold layers.
[0046] For example, as shown in Figure 2 , Figure 3 and Figure 5As shown, the compound chip 6 is taken as an example, the compound chip 6 is mounted on the silicon-based adapter plate cavity 23 by flip-chip sealing. The compound chip sealing ring 52 is welded with the sealing ring solder 21, and the compound chip radio frequency pad 53 is welded with the solder 22 interconnecting the compound chip radio frequency pad, thereby forming a packaged chip with a sealing layer.
[0047] The embodiment of the present application seals the compound chip on the silicon-based adapter plate cavity by flip-chip sealing, and uses plastic sealing material to seal the back of the chip, thereby forming a double-sealing protection structure, effectively preventing the outside moisture, oxygen and corrosive gas from entering the chip, and preventing the chip from failing due to oxidation and corrosion.
[0048] In addition, the embodiment of the present application integrates multiple process steps such as etching, grooving, electroplating solder, flip-chip sealing and plastic sealing in a complete preparation process, thereby reducing intermediate links and process conversion, and improving production efficiency.
[0049] In a possible implementation, the flip-chip sealing of each compound chip on the corresponding silicon-based adapter plate cavity can include:
[0050] The flip-chip sealing of each compound chip with the chip functional point or the grounding point on the corresponding silicon-based adapter plate cavity is achieved by hot-press welding.
[0051] Optionally, the flip-chip sealing of the compound chip with the chip functional point or the grounding point on the corresponding silicon-based adapter plate cavity is achieved by hot-press welding, and the radio frequency circuit region of the compound chip (i.e. the region containing the chip functional point or the grounding point) is located in the silicon-based adapter plate cavity, and the periphery of the compound chip circuit pattern region is provided with an airtight metal ring corresponding to the silicon adapter plate sealing ring solder.
[0052] For example, referring to Figure 2 , Figure 3 and Figure 5 , the radio frequency circuit region of the compound chip 6 is located in the silicon-based adapter plate cavity 23, thereby forming an airtight cavity, and further playing a protection role for the chip circuit pattern of the compound chip 6. The silicon column 24 is welded with part of the compound chip radio frequency pad 53 through the solder 22 interconnecting the compound chip radio frequency pad, thereby playing a role of increasing the connection strength.
[0053] In a possible implementation, the plastic sealing material used in the embodiment of the present application is related to the material and heat resistance of the compound chip.
[0054] The embodiment of the application is based on electronic product assembly technology, and can effectively complete airtight packaging of multiple chips on the basis of minimizing the packaging size, and meanwhile, effectively set a heat dissipation path, and has certain popularization potential in engineering application field.
[0055] In a possible implementation, before the back surface of each packaged compound chip is molded with plastic sealing material, the method further includes:
[0056] When there is a compound chip that needs to be cooled, a heat dissipation cold plate is bonded to the back surface of the compound chip that needs to be cooled by using bonding material, so as to cool the compound chip that needs to be cooled.
[0057] Optionally, for the compound chip that needs to be cooled in the packaged chip, in the embodiment of the application, a heat dissipation cold plate that can dissipate heat needs to be bonded to the back surface of the compound chip that needs to be cooled, and the heat dissipation cold plate needs to be bonded by using specific bonding material. Referring to Figure 6 , a heat dissipation cold plate provided by the embodiment of the application has a structure of a cuboid.
[0058] In the embodiment of the application, the material of the heat dissipation cold plate can be aluminum alloy or copper, and the surface of the heat dissipation cold plate needs to be gold-plated.
[0059] The bonding material in the embodiment of the application can be nano-silver glue with high thermal conductivity.
[0060] The height of the heat dissipation cold plate in the embodiment of the application is flush with the height of the plastic sealing material.
[0061] For example, referring to Figure 2 and Figure 6 , 1 is plastic sealing material, and 3 is a heat dissipation cold plate. Taking a compound chip 6 as an example, when the compound chip 6 in the packaged chip is a compound chip with high power dissipation requirement, a heat dissipation cold plate 3 is installed on the back surface of the compound chip 6 by using high-thermal-conductivity nano-silver glue. After the heat dissipation cold plate is bonded, the back surfaces of the compound chips 4-6 are molded and protected by using plastic sealing, and the height of the plastic sealing material 1 is flush with the height of the installed heat dissipation cold plate 3.
[0062] In a possible implementation, referring to Figure 2 , the position of the silicon-based adapter board 2 that is not slotted is electroplated with metal for wiring.
[0063] The application provides a preparation method of a compound chip flip-down airtight packaging, which comprises the following steps: etching grooves on the top surface of a silicon-based adapter board according to the number of compound chips to be packaged, so as to obtain silicon-based adapter board cavities consistent with the number of the compound chips to be packaged, wherein each silicon-based adapter board cavity contains a plurality of silicon columns corresponding to the chip functional points or contact points of the corresponding compound chip; electroplating solder around each silicon-based adapter board cavity and on the top end of each silicon column; sealing and mounting each compound chip on the corresponding silicon-based adapter board cavity in a flip-down mode, and plastic sealing the back surface of each packaged compound chip by using plastic sealing material, wherein the side of the compound chip with the chip functional points or contact points is opposite to the back surface of the compound chip. The silicon columns corresponding to the chip functional points or contact points of the compound chip are arranged in the silicon-based adapter board cavities, so that the point-to-point connection between the chip and the adapter board is realized. This design greatly shortens the signal transmission path, reduces the attenuation and interference of the signal in the transmission process, especially for high-frequency radio frequency circuits, can effectively improve the signal integrity and transmission quality, and makes the chip perform better in high-speed data transmission and processing. In addition, the corresponding number of cavities is etched on the silicon-based adapter board according to the number of compound chips to be packaged. This preparation method has strong customization flexibility, can meet the diversified needs of different customers and different application scenarios for the number and specifications of chips, does not need large-scale process adjustment and equipment modification, reduces the production cost and shortens the research and development cycle. Meanwhile, the compound chip is sealed on the silicon-based adapter board cavity in a flip-down mode, and the back surface of the chip is plastic sealed by using plastic sealing material, so that a double-sealing protection structure is formed, which effectively prevents the moisture, oxygen and corrosive gas in the outside from entering the chip, and prevents the chip from being invalid due to oxidation and corrosion.
[0064] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the application.
[0065] The following is an embodiment of the packaged chip of the application, and for details not described in detail, reference can be made to the corresponding method embodiment described above.
[0066] Figure 2 A structure schematic diagram of a packaged chip prepared by using the compound chip flip-down airtight packaging preparation method provided by the embodiment of the application is shown, only the parts related to the embodiment of the application are shown for the convenience of description, and the details are as follows:
[0067] As Figure 2As shown, the packaged chip includes plastic sealing material 1, silicon-based adapter plate 2, heat dissipation cold plate 3, and compound chips 4-6. The compound chips 4-6 are mounted on the top surface of the silicon-based adapter plate 2 in a flip-chip manner, the heat dissipation cold plate 3 is bonded to the back surface of the compound chip 6 with high power dissipation requirement, and the plastic sealing material 1 protects the back surface of the compound chips 4-6. The height of the plastic sealing material 1 is flush with the height of the heat dissipation cold plate 3.
[0068] The application provides a packaged chip prepared by the flip-chip hermetic packaging method of the compound chip as described above. The specific preparation method is as follows: according to the number of compound chips to be packaged, grooves are etched on the top surface of the silicon-based adapter plate to obtain silicon-based adapter plate cavities consistent with the number of compound chips to be packaged, each silicon-based adapter plate cavity contains a plurality of silicon columns corresponding to the chip functional points or contact points of the corresponding compound chip; solder is electroplated on the periphery of each silicon-based adapter plate cavity and the top end of each silicon column; each compound chip is mounted on the corresponding silicon-based adapter plate cavity in a flip-chip manner, and the back surface of each packaged compound chip is sealed with plastic sealing material. The side of the compound chip with chip functional points or contact points is opposite to the back surface of the compound chip. The silicon columns corresponding to the functional points or contact points of the compound chip are arranged in the silicon-based adapter plate cavities, realizing accurate point-to-point connection between the chip and the adapter plate. This design greatly shortens the signal transmission path, reduces the attenuation and interference of the signal in the transmission process, especially for high-frequency radio frequency circuits, effectively improves the signal integrity and transmission quality, and makes the chip perform better in high-speed data transmission and processing. In addition, according to the number of compound chips to be packaged, a corresponding number of cavities are etched on the silicon-based adapter plate. This preparation method has strong customization flexibility and can meet the diversified needs of different customers and different application scenarios for the number and specifications of chips without the need for large-scale process adjustment and equipment modification, reducing production costs and shortening the research and development cycle. At the same time, the compound chip is sealed on the silicon-based adapter plate cavity in a flip-chip manner, and the back surface of the chip is sealed with plastic sealing material, forming a double-sealing protection structure that effectively prevents external moisture, oxygen, and corrosive gases from entering the chip, preventing the chip from failing due to oxidation, corrosion, etc.
[0069] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.
Claims
1. A method for fabricating a flip-chip hermetic package for a compound chip, characterized in that, The method comprises the following steps: According to the number of compound chips to be packaged, grooves are etched on the top surface of the silicon-based adapter board to obtain silicon-based adapter board cavities consistent with the number of compound chips to be packaged, each of which contains a plurality of silicon columns corresponding to the chip functional points or contact points of the corresponding compound chip; Solder is electroplated around each silicon-based adapter board cavity and on the top end of each silicon column; Each compound chip is mounted on the corresponding silicon-based adapter board cavity by flip-chip sealing, and the back surface of each packaged compound chip is plasticized using plasticizing material, with the side of the compound chip with chip functional points or contact points being opposite to the back surface of the compound chip.
2. The method of claim 1, wherein the method further comprises: Before the back surface of each packaged compound chip is plasticized using plasticizing material, the method further comprises the following steps: When there is a compound chip that needs to be cooled, a heat dissipation cold plate is attached to the back surface of the compound chip that needs to be cooled using adhesive material to cool the compound chip.
3. The method of claim 2, wherein the method further comprises: The material of the heat dissipation cold plate is aluminum alloy or copper. The adhesive material is high-thermal-conductivity nano-silver glue.
4. The method of claim 2, wherein the method further comprises: The height of the plasticizing material is consistent with the height of the heat dissipation cold plate.
5. The method of claim 1, wherein the method further comprises: providing a compound wafer; and forming a plurality of compound chips on the compound wafer. According to the number of compound chips to be packaged, grooves are etched on the top surface of the silicon-based adapter board to obtain silicon-based adapter board cavities consistent with the number of compound chips to be packaged, which comprises the following steps: According to the number of compound chips to be packaged, grooves are etched on the top surface of the silicon-based adapter board to obtain silicon-based adapter board cavities consistent with the number of compound chips to be packaged, which comprises the following steps:
6. The method of claim 1, wherein the method further comprises: The back surface of the silicon-based adapter board is provided with a BGA pad; before the solder is electroplated around each silicon-based adapter board cavity and on the top end of each silicon column, the method further comprises the following steps: The position of each silicon column is found on the BGA pad, and a TSV hole is prepared for each silicon column to achieve the interconnection between the top surface and the back surface of the silicon-based adapter board.
7. The method of claim 6, wherein the method further comprises: The material of the BGA pad is nickel gold.
8. The method of claim 6, wherein the method further comprises: The TSV hole is filled with electroplated copper.
9. The method of claim 1, wherein the method further comprises: providing a compound chip; and providing a gas-tight package. Each compound chip is mounted on the corresponding silicon-based adapter board cavity by flip-chip sealing, which comprises the following steps: Each compound chip with chip functional points or contact points is flip-chip soldered in the corresponding silicon-based adapter board cavity using hot-press soldering.
10. A packaged chip, comprising: The packaged chip is prepared by the flip-chip airtight packaging method of the compound chip according to any one of claims 1 to 9.