Semiconductor chip and method of mounting the same

Abstract

The application belongs to the technical field of semiconductor, and discloses a semiconductor chip and a mounting method thereof. The semiconductor chip comprises a substrate, a chip functional layer, an insulating layer, a plastic encapsulation body and a plurality of first mounting sites. A plurality of first grooves are formed on two opposite sides of the substrate. The first mounting sites are arranged at two ends of the chip functional layer. The plastic encapsulation body covers the chip functional layer. The first mounting sites extend out of the plastic encapsulation body. Part of the plastic encapsulation body extends into the first grooves. The semiconductor chip of the application forms mechanical engagement by extending part of the plastic encapsulation body into the grooves when the plastic encapsulation body is formed, thereby significantly improving the bonding strength between the plastic encapsulation body and the substrate. In addition, the first mounting sites are directly arranged at the two ends of the chip functional layer and extend out of the plastic encapsulation body, so that the traditional independent pins are not needed. The semiconductor chip can be adapted to a more efficient welding process to reduce false welding and missed welding. The risk of electrostatic breakdown caused by accidental touch is reduced, and the reliability and safety of the semiconductor chip are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a semiconductor chip and a mounting method thereof. BACKGROUND

[0002] In the field of semiconductor chip manufacturing, there are multiple technical pain points in the production and use of semi-encapsulated products. In the plastic packaging link, in the traditional structure, the plastic package and the substrate are connected only by surface bonding, lacking effective mechanical engagement structure, resulting in weak bonding force between the two. This structure is easily affected by temperature cycling (thermal expansion and contraction difference caused by alternating high and low temperatures), vibration impact (such as mechanical vibration during equipment operation), etc. in the subsequent use of the chip, the plastic package and the substrate are prone to relative displacement or even separation, which not only damages the sealing performance of the plastic package, causing external moisture and impurities to invade the functional layer of the chip, but also may pull the connection between the functional layer of the chip and the mounting site, causing electrical faults such as poor contact and signal interruption, seriously affecting product reliability.

[0003] At the same time, the plastic packaging process of semi-encapsulated products itself also has problems: in order to prevent glue overflow, the industry generally uses a top pin to press against the front surface of the substrate to promote the bonding of the back surface of the substrate to the mold cavity, but due to the thickness tolerance of the substrate which needs to meet the industry standard of ±10%, the uneven stress of the top pin pressure will cause stress between the substrate and the functional layer of the chip, the mounting site, and further cause cracks in the insulating layer, further aggravating the risk of product failure.

[0004] In addition, the traditional semiconductor chip with pins has significant defects in installation and manufacturing: it relies on wave soldering during installation, which is low in efficiency and prone to false welding and missed welding, affecting the stability of connection with the control board; special pins need to be purchased and cutting and forming equipment needs to be equipped during manufacturing, increasing material and equipment costs; and the exposed pins are prone to electrostatic breakdown due to accidental touch, threatening the quality and safety of the chip. SUMMARY

[0005] The present application aims to improve at least one technical problem in the background art.

[0006] The first aspect of the present application provides a semiconductor chip, comprising:

[0007] a substrate, one side of the substrate serving as a layout surface, a plurality of first grooves being formed on two opposite sides of the substrate and extending towards the interior of the substrate;

[0008] a chip functional layer, the chip functional layer being arranged on the layout surface;

[0009] an insulating layer, the insulating layer being arranged between the chip functional layer and the substrate;

[0010] A plurality of first mounting sites, the first mounting sites are arranged at both ends of the chip functional layer, and the first mounting sites are electrically connected with the chip functional layer;

[0011] A plastic package, the plastic package covers the chip functional layer, the first mounting sites extend out of the plastic package, and part of the plastic package extends into the first groove.

[0012] The semiconductor chip of the first aspect of the present application has the following advantages: the semiconductor chip of the present application sets the first groove on the opposite side of the substrate, so that part of the plastic package extends into the groove to form mechanical engagement when the plastic package is formed, which significantly improves the bonding strength of the plastic package and the substrate, effectively resists the separation trend under temperature cycling and vibration impact, and avoids the plastic package from falling off or sealing failure. At the same time, this firm combination reduces the dependence on the pressure of the top needle, reduces the uneven stress caused by the thickness tolerance of the substrate, thereby protecting the insulating layer from stress damage and avoiding insulation failure. In addition, the first mounting sites are directly arranged at both ends of the chip functional layer and extend out of the plastic package, without the need for traditional independent pins, which can adapt to more efficient welding process to reduce false welding and leakage, and also saves the procurement and processing links of the pins to reduce costs, and reduces the risk of electrostatic breakdown caused by accidental touch, thereby improving the reliability and safety of the semiconductor chip.

[0013] Further, the first groove includes a transverse segment and a longitudinal segment that are in communication with each other, the transverse segment extends along the width direction of the substrate, and the longitudinal segment extends along the thickness direction of the substrate.

[0014] Further, the first mounting sites are arranged at intervals.

[0015] Further, the substrate is a metal substrate, and a heat dissipation structure is formed on the side away from the arrangement surface, and the heat dissipation structure is fixedly connected with the substrate.

[0016] Further, the heat dissipation structure is an array of heat dissipation fins, and the heat dissipation fins are fixedly connected with the substrate.

[0017] Further, the chip functional layer includes a circuit wiring layer and a circuit component assembly, the circuit wiring layer is arranged on the arrangement surface, the insulating layer is arranged between the circuit wiring layer and the substrate, the first mounting sites are arranged at both ends of the circuit wiring layer, the first mounting sites are electrically connected with the circuit wiring layer, and the circuit component assembly is arranged on the circuit wiring layer, and the circuit component assembly is electrically connected with the circuit wiring layer.

[0018] Further, a green oil layer is arranged on the circuit wiring layer, and the green oil layer is used to protect the circuit wiring layer.

[0019] Further, first threaded holes are formed at both ends of the substrate, the first threaded holes penetrating the substrate along the thickness direction of the substrate.

[0020] The second aspect of the present application provides a mounting method of the semiconductor chip, the electric control board is provided with a semiconductor chip mounting hole, the electric control board is provided with a plurality of second mounting sites corresponding to the first mounting site, the second mounting sites are located on both sides of the semiconductor chip mounting hole, and the mounting method comprises the following steps:

[0021] The solder paste is coated on the first mounting site;

[0022] The semiconductor chip is aligned with the semiconductor chip mounting hole, and the first mounting site is aligned with the second mounting site;

[0023] The semiconductor chip is mounted on the electric control board;

[0024] The mounting of the semiconductor chip on the electric control board is completed through reflow soldering.

[0025] The mounting method of the semiconductor chip of the second aspect of the present application has the following advantages: in the mounting of the semiconductor chip, the solder paste is first coated on the first mounting site, then the semiconductor chip mounting hole on the electric control board is aligned with the corresponding second mounting site, and finally the assembly is completed through reflow soldering. Compared with the traditional wave soldering process, reflow soldering is more suitable for the operation requirements of the automatic production line, and can significantly improve the assembly efficiency. Through quantitative coating of the solder paste, the problems of poor welding such as virtual welding and missed welding can be effectively reduced, and the stability of the connection between the semiconductor chip and the electric control board is further enhanced. The mounting method does not need to perform additional processing on the traditional pins, greatly simplifies the mounting steps, reduces the dependence on special equipment for pin processing, and thus realizes cost saving. In addition, the mounting site is more uniformly stressed during the reflow soldering process, which can reduce the internal stress concentration of the chip caused by the mounting operation, and improve the reliability of the overall installation.

[0026] Further, first threaded holes are formed at both ends of the substrate, the first threaded holes penetrating the substrate along the thickness direction of the substrate, the electric control board is provided with second threaded holes corresponding to the first threaded holes, and the electric control board further comprises screws; after the reflow soldering is completed, the screws are screwed through the first threaded holes and the second threaded holes to complete the mounting of the semiconductor chip on the electric control board. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1A schematic view of a structure of a semiconductor chip according to an embodiment;

[0029] Figure 2 A schematic view of a structure of a semiconductor chip according to an embodiment, in which a plastic package is hidden;

[0030] Figure 3 A top view of a semiconductor chip according to an embodiment;

[0031] Figure 4 A schematic view of a heat dissipation structure of a semiconductor chip according to an embodiment;

[0032] Figure 5 A schematic view of a structure of an electric control board according to an embodiment;

[0033] Figure 6 A schematic view of a semiconductor chip mounted on an electric control board according to an embodiment.

[0034] In the drawings: 100 - substrate; 101 - first groove; 1011 - transverse section; 1012 - longitudinal section; 102 - heat dissipation fin; 103 - first threaded hole; 200 - insulating layer; 300 - circuit wiring layer; 400 - first mounting site; 501 - component; 502 - high-power component; 503 - surface mount resistor; 504 - surface mount capacitor; 505 - heat sink; 506 - electric wire; 600 - plastic package; 700 - semiconductor chip; 800 - electric control board; 801 - semiconductor chip mounting hole; 802 - second mounting site; 803 - second threaded hole. DETAILED DESCRIPTION

[0035] Embodiments of the present application are described below in detail, examples of which are shown in the drawings, in which the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0036] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as a limitation of the present application, which does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation.

[0037] In the description of the present application, unless otherwise explicitly limited, the words such as arrangement, installation, connection, etc. should be understood broadly, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0038] The following will be described in combination with Figures 1 to 6Embodiments of the present application are described.

[0039] Embodiments of the present application provide a semiconductor chip, comprising:

[0040] a substrate 100, one side of the substrate 100 serving as a layout surface, a plurality of first grooves 101 being formed on two opposite sides of the substrate 100 and extending to the interior of the substrate 100;

[0041] a chip functional layer, disposed on the layout surface;

[0042] an insulating layer 200, disposed between the chip functional layer and the substrate 100;

[0043] a plurality of first mounting sites 400, disposed at the two ends of the chip functional layer, electrically connected to the chip functional layer;

[0044] a plastic encapsulation 600, covering the chip functional layer, the first mounting sites 400 extending out of the plastic encapsulation 600, and part of the plastic encapsulation 600 extending into the first grooves 101.

[0045] The substrate 100 in this embodiment serves as a basic support carrier of the semiconductor chip, provides a mounting reference surface for the subsequent functional layer, and has a first groove 101 extending to the inside at both ends of the two opposite sides of the substrate 100. The groove is used to reserve the embedding space of the plastic package 600, and the physical engagement with the plastic package 600 enhances the connection stability of the two, avoiding the plastic package 600 from falling off due to thermal expansion and contraction or external force in use. The chip functional layer is arranged on the arrangement surface and is the core unit for realizing the electrical function of the chip. The insulating layer 200 is used to realize electrical isolation and prevent the conductive structure of the chip functional layer from directly contacting the substrate 100 (especially the metal substrate) to cause short circuit, and can also assist in buffering the stress caused by the difference in thermal expansion coefficient between the two. The first mounting point 400 in this embodiment is located at both ends of the chip functional layer and is electrically connected to the functional layer, which is the interface for connecting the semiconductor chip and the external circuit (such as the electronic control board 800), and realizes the signal and current transmission between the chip and the external circuit through welding and other methods. This structural design avoids the problem of cracking of the insulating layer 200 caused by stress concentration due to the thickness tolerance between the substrate 100 and the pin in the plastic packaging process of the traditional semiconductor chip with pin, and significantly enhances the operation reliability of the semiconductor chip. Secondly, since no pin structure needs to be additionally provided, during the manufacturing process of the semiconductor chip, neither special pin materials need to be purchased nor cutting and bending processing of the pin needs to be performed by configuring a cutting and forming equipment, thereby effectively reducing the material procurement cost and equipment investment cost in the manufacturing stage of the semiconductor chip and optimizing the overall production cost structure. Furthermore, the design without pin can avoid the problem of electrostatic breakdown of the chip functional layer caused by accidental contact with the pin during transportation and production operation, greatly reduces the risk of electrostatic breakdown, and further improves the safety of the semiconductor chip during transportation and production.

[0046] Further, the first groove 101 includes a transverse segment 1011 and a longitudinal segment 1012 that are in communication with each other, the transverse segment 1011 extends along the width direction of the substrate 100, and the longitudinal segment 1012 extends along the thickness direction of the substrate 100.

[0047] The first groove 101 in the embodiment is formed by the transverse section 1011 and the longitudinal section 1012 in communication with each other. In the embodiment, the transverse section 1011 and the longitudinal section 1012 in communication with each other form a "T-shaped" composite groove structure. In other embodiments, an "L-shaped" composite groove structure can also be formed. Compared with a single-direction groove, the composite groove structure increases the contact area of the plastic package 600 and the substrate 100, can constrain the plastic package 600 from two dimensions of width and thickness, reduces the risk of loosening of the plastic package 600 due to temperature cycling, vibration and other working conditions, and improves the reliability of the semiconductor chip.

[0048] Further, the first mounting sites 400 are arranged at intervals.

[0049] The core purpose of arranging the first mounting sites 400 at intervals in the embodiment is to ensure the electrical reliability and process realizability of the semiconductor chip and external interface. From the perspective of electrical performance, the interval can avoid signal interference (such as crosstalk) between adjacent mounting sites. Especially for high-frequency signal transmission scenarios, the interval design can reduce parasitic capacitance and inductance, and ensure the accuracy and integrity of signal transmission. From the process perspective, the interval reserves operation space for subsequent soldering operations (such as reflow soldering), prevents solder overflow from causing short circuits between adjacent mounting sites, and facilitates post-soldering detection (such as AOI detection), thereby improving packaging yield.

[0050] Further, the substrate 100 is a metal substrate, and a heat dissipation structure is formed on the side away from the arrangement surface, and the heat dissipation structure is fixedly connected with the substrate 100.

[0051] In the embodiment, the substrate 100 is made of a metal material with high thermal conductivity (such as an aluminum substrate 100 or a copper substrate 100). Compared with a traditional ceramic substrate 100 or a resin substrate 100, the metal substrate can quickly conduct the heat generated by the functional layer of the chip, avoiding local accumulation of heat in the functional layer. The heat dissipation structure in the embodiment is arranged on the side of the substrate 100 away from the arrangement surface, which can avoid structural interference with the functional layer and the insulating layer 200 on the arrangement surface, while ensuring that the heat dissipation path is independent. The heat dissipation structure and the substrate 100 are fixedly connected (which can be welded, screwed, or bonded with thermal conductive glue), ensuring that they are closely attached to reduce the contact thermal resistance, so that the heat conducted by the substrate 100 is efficiently transferred to the heat dissipation structure and then dissipated to the environment.

[0052] Further, the heat dissipation structure is an array of heat dissipation fins 102, and the heat dissipation fins 102 are fixedly connected with the substrate 100.

[0053] The heat dissipation structure in the embodiment is arrayed heat dissipation fins 102. Compared with a whole heat dissipation block, the arrayed heat dissipation fins 102 can increase the heat dissipation area on one hand, and the gaps between the fins can significantly increase the contact area between the heat dissipation structure and air; on the other hand, the fins can promote air flow, and the gaps between the fins provide channels for air convection. In a natural convection scenario, hot air can rise along the gaps, and cold air can be supplemented to the bottom. In a forced air cooling scenario, air flow can smoothly pass through the gaps between the fins, thereby taking away more heat.

[0054] Further, the chip functional layer comprises a circuit wiring layer 300 and a circuit component assembly, the circuit wiring layer 300 is arranged on the arrangement surface; the insulating layer 200 is arranged between the circuit wiring layer 300 and the substrate 100; the first mounting site 400 is arranged at two ends of the circuit wiring layer 300, the first mounting site 400 is electrically connected with the circuit wiring layer 300; the circuit component assembly is arranged on the circuit wiring layer 300, and the circuit component assembly is electrically connected with the circuit wiring layer 300.

[0055] The chip functional layer in the embodiment includes a circuit wiring layer 300 and a circuit component assembly, wherein the circuit wiring layer 300 is arranged on the layout surface of the substrate 100 and is formed by etching a copper foil layer according to a preset circuit pattern, and the circuit wiring layer 300 is responsible for connecting the circuit component assembly and the first mounting site 400 to realize current distribution and signal transmission. The insulating layer 200 is arranged between the circuit wiring layer 300 and the substrate 100, and the core function is to isolate the circuit wiring layer 300 and the substrate 100 (especially the metal substrate) to prevent short circuit. The first mounting site 400 is located at both ends of the circuit wiring layer 300, which is equivalent to the “external interface” of the circuit wiring layer 300, and the signals and currents of the wiring layer are transmitted to the external circuit through the site, or the power supply and control signals of the external circuit are received. The circuit component assembly includes a chip resistor 503, a chip capacitor 504, a component 501, and a high-power component 502; wherein the component 501 and the high-power component 502 are composed of the required chips of various internal functional circuits of the semiconductor chip, and a heat sink 505 is further arranged between the high-power component 502 and the circuit wiring layer 300. The heat sink 505 in the embodiment is a copper heat sink 505 with a silver-plated surface. Copper has excellent heat conduction performance and can quickly absorb the heat generated by the high-power component 502 and transfer it to the substrate 100. The silver-plated surface not only enhances the conductivity of the heat sink 505, but also improves its corrosion resistance and oxidation resistance, prolonging the service life of the heat sink 505; the chip resistor 503 is connected at the IGBT chip gate in the semiconductor chip to limit the switching speed by limiting the current; the chip capacitor 504 plays a role in filtering, coupling, and bootstrap in the semiconductor chip. The circuit component assembly and the circuit wiring layer 300 are connected by a wire 506. In the embodiment, the wire 506 is a copper wire 506, and in other embodiments, gold wire 506, aluminum wire 506, etc. can also be selected.

[0056] Further, the circuit wiring layer 300 is provided with a green oil layer, and the green oil layer is used to protect the circuit wiring layer 300.

[0057] In the embodiment, the green oil layer has three functions: first, to avoid scratching and wear of the circuit wiring layer 300 in subsequent processes; second, insulation protection to isolate dust, moisture, and external impurities in the air, preventing short circuit caused by impurity adhesion, especially preventing corrosion of the wire in a humid environment; third, oxidation protection to prevent the circuit wiring layer 300 from being exposed to air and oxidizing, avoiding the formation of an oxide layer that reduces the conductivity.

[0058] Further, first threaded holes 103 are provided at both ends of the substrate 100, and the first threaded holes 103 penetrate the substrate 100 along the thickness direction of the substrate 100.

[0059] The first threaded hole 103 in the embodiment is used to fix the semiconductor chip and external circuit (such as the electric control board 800) (which can be fixed by screwing). The first threaded hole 103 is arranged at both ends of the substrate 100, so that the fixing force is evenly distributed at both end regions of the substrate 100, avoiding the bending deformation of the substrate 100 caused by uneven stress due to single-point fixing.

[0060] The manufacturing method of the semiconductor chip in the embodiment includes the following steps:

[0061] The first groove 101 is arranged on both opposite sides of the substrate 100;

[0062] The heat dissipation structure is formed on the opposite side of the arrangement surface of the substrate 100;

[0063] The insulation layer 200 is laminated with the copper foil to obtain a laminated semi-finished product, and then the laminated semi-finished product is laminated with the substrate 100, wherein one side of the insulation layer 200 in the laminated semi-finished product faces the arrangement surface of the substrate 100;

[0064] The copper foil layer is etched to obtain the circuit wiring layer 300;

[0065] The first mounting site 400 is arranged on the circuit wiring layer 300;

[0066] The green oil layer is formed on the surface of the circuit wiring layer 300, and the green oil layer avoids the preset position of the circuit component assembly and the first mounting site 400;

[0067] The substrate 100 is placed on the carrier, tin paste is brushed at the preset position of the circuit component assembly, and the circuit component assembly is mounted on the preset position by the automatic crystal mounting device;

[0068] The carrier carrying the substrate 100 enters the reflow furnace to weld all the circuit component assemblies to the corresponding preset positions, weld the first pin on the pad, and detect the welding quality of the circuit component assembly by the visual inspection device;

[0069] The cleaning method of spraying and ultrasonic cleaning is used to remove the flux and aluminum scraps and other foreign matters remaining on the substrate 100;

[0070] The circuit component assembly and the circuit wiring layer 300 are electrically connected by the wire 506;

[0071] Plastic packaging is performed to form a plastic package 600;

[0072] The electrical parameter test is completed to obtain the semiconductor chip.

[0073] The embodiment also provides the mounting method of the semiconductor chip, the electric control board 800 is provided with the semiconductor chip mounting hole 801, the electric control board 800 is provided with a plurality of second mounting sites 802 corresponding to the first mounting site 400, and the second mounting site 802 is located on the two sides of the semiconductor chip mounting hole 801;The electric control board 800 is provided with the second threaded hole 803 corresponding to the first threaded hole 103, and the electric control board 800 also includes a screw;The mounting method includes the following steps:

[0074] The solder paste is coated on the first mounting site 400;

[0075] The semiconductor chip 700 is aligned with the semiconductor chip mounting hole 801, and the first mounting site 400 is aligned with the second mounting site 802;

[0076] The semiconductor chip 700 is mounted on the electric control board 800;

[0077] Through reflow soldering, and the screw is screwed through the first threaded hole 103 and the second threaded hole 803, the mounting of the semiconductor chip 700 on the electric control board 800 is completed.

[0078] The mounting method of the semiconductor chip on the electric control board 800 provided by the embodiment is based on the foregoing semiconductor chip without a traditional pin structure, and the first mounting site 400 of the chip is connected by cooperating with the second mounting site 802 of the electric control board 800, and the mounting process adopts a reflow soldering process. The process is highly compatible with the core process of SMT (surface mount technology), and can be carried out synchronously with the mounting process of other mounting devices on the electric control board 800, without the need to separately set up a chip mounting link.

[0079] The embodiment replaces the plug-in wave soldering process of the traditional semiconductor chip with pins with the SMT process, can realize rapid positioning and placement of the semiconductor chip relying on automatic mounting equipment, does not need manual assistance for alignment, significantly compresses the time consumption of the mounting process, and effectively improves the overall assembly efficiency of the electric control board. Meanwhile, the solder paste used in the mounting of the embodiment can be tin paste or spot silver glue;In the reflow soldering link, the solder paste is uniformly dissolved after high-temperature action and solidification, and can form a stable electrical connection and mechanical fixing structure between the first mounting site 400 and the second mounting site 802. Compared with the problem that the wave soldering is easily affected by the flowability of the solder, this mode can more effectively reduce the problems of poor welding such as virtual welding and missed welding, further enhance the stability of the connection between the semiconductor chip and the electric control board 800, and reduce the maintenance cost in the later period.

[0080] The preferred embodiments of the present application have been disclosed with specific reference to a preferred embodiment. A person with ordinary skill in the art understands that variations in, or modifications to, the preferred embodiments can be made without departing from the spirit and scope of the present application, which is defined by the following claims.

Claims

1. A method for mounting a semiconductor chip, characterized in that, The semiconductor chip includes: A substrate, one side of which is used as a mounting surface, and a plurality of first grooves are formed on two opposite sides of the substrate, the first grooves extending into the interior of the substrate; A chip functional layer is disposed on the arrangement surface; An insulating layer is disposed between the chip functional layer and the substrate; A plurality of first mounting sites are disposed at both ends of the chip functional layer and are electrically connected to the chip functional layer; A molding compound that covers the chip functional layer, wherein the first mounting point extends out of the molding compound, and a portion of the molding compound extends into the first groove; The semiconductor chip is mounted on an electronic control board, which has semiconductor chip mounting holes and a plurality of second mounting points corresponding to the first mounting points. The second mounting points are located on both sides of the semiconductor chip mounting holes. The semiconductor chip mounting method includes the following steps: Apply solder paste to the first mounting point; Align the semiconductor chip with the semiconductor chip mounting hole, and align the first mounting point with the second mounting point; The semiconductor chip is mounted on the electronic control board; Reflow soldering is used to form a stable electrical connection and mechanical fixing structure between the first mounting point and the second mounting point, thereby completing the installation of the semiconductor chip on the electronic control board.

2. The method for mounting a semiconductor chip according to claim 1, characterized in that, The first groove includes a transverse segment and a longitudinal segment that are interconnected, the transverse segment extending along the width direction of the substrate and the longitudinal segment extending along the thickness direction of the substrate.

3. The method for mounting a semiconductor chip according to claim 1, characterized in that, Several first mounting sites are spaced apart.

4. The method for mounting a semiconductor chip according to claim 1, characterized in that, The substrate is a metal substrate, and a heat dissipation structure is formed on the side away from the arrangement surface. The heat dissipation structure is fixedly connected to the substrate.

5. The method for mounting a semiconductor chip according to claim 4, characterized in that, The heat dissipation structure consists of an array of heat dissipation fins, which are fixedly connected to the substrate.

6. The method for mounting a semiconductor chip according to claim 1, characterized in that, The chip functional layer includes a circuit wiring layer and a circuit component assembly. The circuit wiring layer is disposed on the arrangement surface. The insulating layer is disposed between the circuit wiring layer and the substrate. The first mounting points are disposed at both ends of the circuit wiring layer and are electrically connected to the circuit wiring layer. The circuit component assembly is disposed on the circuit wiring layer and is electrically connected to the circuit wiring layer.

7. The method for mounting a semiconductor chip according to claim 6, characterized in that, The circuit wiring layer is provided with a green solder mask layer, which is used to protect the circuit wiring layer.

8. The method for mounting a semiconductor chip according to claim 1, characterized in that, The substrate has first threaded holes at both ends, and the first threaded holes penetrate the substrate along the thickness direction of the substrate.

9. A method for mounting a semiconductor chip as described in claim 8, characterized in that, After the semiconductor chip is installed on the control board by reflow soldering, the method further includes the step of threading a screw through the first threaded hole and threading it into the second threaded hole.

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