Chip socket assembly for semiconductor chip testing and semiconductor chip testing device

Abstract

Disclosed are a chip socket assembly for testing a semiconductor chip and a semiconductor chip testing apparatus, the chip socket assembly for testing a semiconductor chip comprising: a chip guide member having a chip guide hole for inserting and guiding a chip having a plurality of bumps and a plurality of pads formed on one surface side; a bump guide member having at least one bump guide hole for guiding at least a portion of positions of the plurality of bumps and at least one pad exposure hole for exposing at least a portion of the plurality of pads; an intermediate fastening member having an opening for exposing at least a part of one surface of the chip on which the plurality of bumps and the plurality of pads are formed; and a chip socket substrate on one surface side of which a plurality of probes that are in contact with at least a part of the plurality of pads are formed.

Description

Technical Field

[0001] This invention relates to a mechanism and apparatus for testing semiconductor components / electronic components, and more specifically to a chip socket assembly for testing semiconductor chips and an apparatus including the same. Background Technology

[0002] Semiconductor components (e.g., semiconductor chips) formed by high-density integration of microelectronic circuits require testing during or after the manufacturing process to ensure proper functioning of the electronic circuitry. For example, the electrical characteristics of semiconductor components can be tested using a semiconductor test socket device. When checking the electrical characteristics of semiconductor components using a semiconductor test socket device, the conductive terminals of the socket (i.e., probes) and the conductive terminals of the semiconductor component need to be accurately aligned and connected.

[0003] However, with the rapid development of semiconductor technology, the size and pitch of the electrode pads (terminals) of semiconductor components are constantly decreasing, making it more difficult to accurately align and connect the probes of the test socket device to the electrode pads of the semiconductor component. For example, the pad pitch of next-generation semiconductor chips is expected to decrease to less than about 65 μm, thus requiring the development of test solutions capable of handling such fine pitches.

[0004] The components of the socket assembly are manufactured with machining tolerances, and the semiconductor elements are also manufactured with specified dimensional tolerances. The dimensions of the main areas of the socket assembly need to be designed with a slight margin to account for the dimensional tolerance range of the semiconductor elements. Therefore, due to these tolerances, it can be difficult to ensure alignment tolerances corresponding to the very small spacing between the tiny electrodes of the semiconductor elements. Furthermore, the reference for forming (setting) the probes for aligning the socket assembly differs from the reference for aligning the components and semiconductor elements of the socket assembly, making it even more difficult to align the probes and pads.

[0005] Therefore, there is a need to develop devices and technologies that can overcome the above problems while reducing the alignment tolerances (errors) of electrical testing connections to accommodate the fine electrode spacing of semiconductor devices. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] The technical problem to be solved by the present invention is to provide a chip socket assembly for semiconductor chip testing, which can correspond to the miniaturization of the electrode (pad) spacing of semiconductor chips (components) and reduce the tolerance (error) of connection alignment for electrical testing.

[0008] Furthermore, the technical problem to be solved by the present invention is to provide a chip socket assembly for semiconductor chip testing, which can improve the alignment accuracy of semiconductor chips by applying bump guide function.

[0009] Furthermore, the technical problem to be solved by the present invention is to provide a chip socket assembly for semiconductor chip testing, which improves the alignment accuracy between the probe and the pad by using a plurality of alignment pins disposed on the chip socket substrate as coordinate references for probe bonding and as references for aligning semiconductor elements.

[0010] Furthermore, the technical problem to be solved by the present invention is to provide a semiconductor chip testing apparatus including the above-mentioned semiconductor chip testing chip socket assembly.

[0011] The technical problem to be solved by the present invention is not limited to the above-mentioned problem, and other problems not mentioned can be understood by those skilled in the art from the following description.

[0012] (II) Technical Solution

[0013] According to one embodiment of the present invention, a chip socket assembly for semiconductor chip testing is provided, comprising: a chip guiding member having a chip guiding hole for inserting and guiding a chip having a plurality of bumps and a plurality of pads formed on one side; a bump guiding member contacting or adjacent to the chip guiding member and having at least one bump guiding hole for guiding at least a portion of the plurality of bumps and at least one pad exposure hole for exposing at least a portion of the plurality of pads; an intermediate fastening member disposed opposite to the chip guiding member across the bump guiding member and having an opening for exposing at least a portion of one side of the chip having the plurality of bumps and the plurality of pads; and a chip socket substrate coupled to the intermediate fastening member and having a plurality of probes formed on one side contacting at least a portion of the plurality of pads.

[0014] The bump guide member can be combined with the chip guide member, and the intermediate fastening member can be combined with the chip guide member through the bump guide member.

[0015] The bump guiding member may include a first bump guiding hole, which is used to expose a first group of bumps among the plurality of bumps and guide the position of the first group of bumps.

[0016] The bump guide member may further include a second bump guide hole, which is used to expose a second group of bumps among the plurality of bumps and guide the position of the second group of bumps. The second bump guide hole may be spaced apart from the first bump guide hole.

[0017] The bump guide member can be an insulating film member.

[0018] The bump guide member may comprise at least one of polymer materials and ceramic materials.

[0019] The intermediate fastening member may be provided with multiple fastening elements that can move up and down elastically, and the chip guiding member may be provided with multiple fastening holes, wherein the multiple fastening elements are fastened to the multiple fastening holes.

[0020] The plurality of fastening elements may include plungers.

[0021] The combined structure of the chip guiding member and the bump guiding member can move elastically up and down relative to the intermediate fastening member coupled to the combined structure.

[0022] A plurality of alignment pins are provided on one side of the chip socket substrate on which the plurality of probes are formed. When the chip guide member, the bump guide member and the intermediate fastening member are assembled to the chip socket substrate, the plurality of alignment pins can be used as alignment references.

[0023] The chip guiding member, the bump guiding member, and the intermediate fastening member may each have a plurality of alignment guiding holes for insertion of the plurality of alignment pins.

[0024] The plurality of probes can be formed by bonding on one side of the chip socket substrate using the plurality of alignment pins as coordinate references.

[0025] The chip includes high bandwidth memory (HBM).

[0026] According to another embodiment of the present invention, a semiconductor chip testing apparatus is provided, including the above-described semiconductor chip testing chip socket assembly.

[0027] (III) Beneficial Effects

[0028] According to embodiments of the present invention, a chip socket assembly for semiconductor chip testing can be realized, which can correspond to the miniaturization of the electrode (pad) spacing of semiconductor chips (elements) and reduce the tolerance (error) of connection alignment for electrical testing.

[0029] According to one embodiment of the present invention, a chip socket assembly for semiconductor chip testing can be implemented, which improves the alignment accuracy of the semiconductor chip by applying a bump guide function. The chip is first aligned by guiding the periphery of the semiconductor chip, and then precisely aligned by using a bump guide member to guide the bump group of the semiconductor chip. Therefore, the alignment accuracy of the chip relative to the test probe can be significantly improved.

[0030] Furthermore, according to one embodiment of the present invention, a chip socket assembly for semiconductor chip testing can be implemented. By using a plurality of alignment pins disposed on the chip socket substrate as coordinate references for probe bonding and as references for aligning semiconductor components, the alignment accuracy between probes and pads can be improved. Since the coordinate references used for probe bonding and the components of the chip socket assembly can be the same as the references used for aligning the semiconductor chip, the alignment accuracy between probes and pads can be significantly improved.

[0031] By applying the chip socket assembly according to embodiments of the present invention, a semiconductor chip testing apparatus can be realized, which can easily evaluate the electrical characteristics of next-generation semiconductor chips (devices) with fine electrode (pad) spacing.

[0032] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the technical concept and scope of the present invention. Attached Figure Description

[0033] Figure 1 This is an exploded perspective view illustrating a chip socket assembly for semiconductor chip testing according to an embodiment of the present invention.

[0034] Figure 2 This is a schematic plan view of a chip that can be used in a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0035] Figure 3 and Figure 4 This is a schematic cross-sectional view of a portion of a chip that can be used in a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0036] Figure 5 This is a plan view showing a chip socket substrate applicable to a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0037] Figure 6 This is a plan view showing a chip guide member and a bump guide member of a chip socket assembly for semiconductor chip testing that can be applied to an embodiment of the present invention.

[0038] Figure 7 This is a plan view showing an intermediate fastening member applicable to a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0039] Figures 8 to 10 This is a schematic cross-sectional view illustrating the process of guiding a chip and placing it in a placement portion using a chip socket assembly for semiconductor chip testing according to an embodiment of the present invention.

[0040] Figure 11 and Figure 12 This is a schematic cross-sectional view illustrating the process of placing a chip in a placement section using a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0041] Figure 13 This is an exploded perspective view used to illustrate a semiconductor chip test chip socket assembly according to a comparative example.

[0042] Figure 14 It shows the basis Figure 13 A plan view of the chip socket substrate of the comparative example chip socket assembly.

[0043] Figure 15 It shows the basis Figure 13 A plan view of the chip guide board of a comparative example chip socket assembly.

[0044] Figure 16 and Figure 17 It is a cross-sectional diagram used to illustrate the process of placing a chip in the placement section using a semiconductor chip test chip socket assembly according to a comparative example, and to explain the problems therein. Detailed Implementation

[0045] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0046] Figure 1 This is an exploded perspective view of a chip socket assembly for semiconductor chip testing according to an embodiment of the present invention.

[0047] Reference Figure 1 According to an embodiment of the present invention, a chip socket assembly for semiconductor chip testing may include a chip guiding member 100, a bump guiding member 200, an intermediate fastening member 300, and a chip socket substrate 400.

[0048] The chip guide member 100 may have a chip guide hole 110 for inserting and guiding a chip (semiconductor chip). The chip may be a chip with multiple bumps and multiple pads (electrode pads) formed on one side. The chip may also be referred to as a die. For example, the chip may have a quadrilateral shape, and the chip guide hole 110 may have a shape suitable for inserting the chip. The chip guide member 100 may have a plate-like or frame-like shape surrounding the chip guide hole 110. The chip guide member 100 may serve to initially guide and align the chip, and may also serve to place the chip on the bump guide member 200.

[0049] The bump guide member 200 may be disposed opposite to the chip guide member 100. The bump guide member 200 may be in contact with or adjacent to the chip guide member 100. The bump guide member 200 may be disposed on the lower surface of the chip guide member 100. The bump guide member 200 may have at least one bump guide hole 210 for guiding at least a portion of the plurality of bumps and at least one pad exposure hole 220 for exposing at least a portion of the plurality of pads. More than one bump guide hole 210 or more pad exposure holes 220 may be formed. The bump guide member 200 may be relatively thin, in the form of a film or plate. The bump guide member 200 can guide the bumps of the chip using the bump guide hole 210, thereby performing a second guidance and alignment of the chip. The chip may be mounted on the bump guide member 200. The bump guide member 200 may be an insulator.

[0050] The intermediate fastening member 300 may be disposed opposite to the chip guide member 100, with the bump guide member 200 in between. Therefore, the bump guide member 200 may be disposed between the chip guide member 100 and the intermediate fastening member 300. The intermediate fastening member 300 may be disposed below the bump guide member 200, i.e., on the lower surface side. The intermediate fastening member 300 may have an opening 310 for exposing at least a portion of one side of the chip on which the plurality of bumps and pads are formed. For example, the opening 310 may have a generally quadrilateral shape. The intermediate fastening member 300 may have a plate-like or frame-like structure surrounding the opening 310. The intermediate fastening member 300 may be coupled to at least one of the chip guide member 100 and the bump guide member 200.

[0051] According to one example, the bump guide member 200 can be coupled to the chip guide member 100, and the intermediate fastening member 300 can be coupled to the chip guide member 100 through the bump guide member 200. The bump guide member 200 can be coupled to the chip guide member 100 and contact the lower surface of the chip guide member 100. The coupled structure (first coupled structure) formed by the chip guide member 100 and the bump guide member 200 can be coupled to the intermediate fastening member 300. The intermediate fastening member 300 can be coupled to the lower surface side of the first coupled structure.

[0052] The chip socket substrate 400 can be coupled to the intermediate fastening member 300. The chip socket substrate 400 can be coupled to the lower surface of the intermediate fastening member 300. A coupling structure (second coupling structure) formed by the chip guide member 100, the bump guide member 200, and the intermediate fastening member 300 can be coupled to the chip socket substrate 400. The chip socket substrate 400 may include a printed circuit board (PCB). The chip socket substrate 400 can serve to electrically connect the chip to a test board. Furthermore, the chip socket substrate 400 can serve to convert the fine electrode spacing of the chip to the normal spacing of the test board. A plurality of probes 450 can be formed (set) on one side (upper surface) of the chip socket substrate 400, contacting at least a portion of a plurality of pads formed on the chip. The plurality of probes 450 can serve to electrically connect the chip to the chip socket substrate 400. In other words, the chip and the printed circuit board of the chip socket substrate 400 can be electrically connected via the plurality of probes 450.

[0053] The intermediate fastening member 300 serves to maintain a predetermined distance between the chip socket substrate 400 and the bump guide member 200. At least a portion of the plurality of probes 450 can be inserted into the opening 310 of the intermediate fastening member 300. The plurality of probes 450 can be disposed in the area corresponding to the opening 310. The plurality of probes 450 can be connected to the pads (electrode pads) of the chip through the opening 310.

[0054] According to one embodiment, the bump guide member 200 may include a first bump guide hole 210a, which exposes a first group of bumps among the plurality of bumps and guides the position of the first group of bumps. The first bump guide hole 210a serves to expose the first group of bumps and guide their position. When two or more bumps in the first group that are located at the edge (periphery) contact the portion of the bump guide member 200 corresponding to the border of the first bump guide hole 210a, the position of the first group of bumps can be adjusted, and ultimately the position of the chip can be adjusted. In other words, when the first group of bumps enters the interior of the first bump guide hole 210a, the position of the first group of bumps can be adjusted, thereby adjusting the position of the chip.

[0055] Furthermore, the bump guide member 200 may further include a second bump guide hole 210b, which exposes a second group of bumps among the plurality of bumps and guides the position of the second group of bumps. The second bump guide hole 210b may be spaced apart from the first bump guide hole 210a. The second bump guide hole 210b serves to expose the second group of bumps and guide their position. When two or more bumps located at the edge (periphery) of the second group of bumps contact the portion of the bump guide member 200 corresponding to the border of the second bump guide hole 210b, the position of the second group of bumps can be adjusted, and ultimately the position of the chip can be adjusted. In other words, when the second group of bumps enters the interior of the second bump guide hole 210b, the position of the second group of bumps can be adjusted, thereby adjusting the position of the chip.

[0056] When the chip position is finely adjusted (guided) using the mutually spaced first bump guide holes 210a and second bump guide holes 210b, the chip position can be aligned more accurately and precisely. The chip position adjustment characteristics can be further improved when two or more bump guide holes are used to guide the chip position in multiple areas. However, depending on the situation, only one bump guide hole may be used, or three or more bump guide holes may be used. The number and arrangement of the bump guide holes 210 and pad exposure holes 220 shown here are merely examples and can be varied.

[0057] According to one embodiment, the bump guide member 200 may be an insulating film member. In this case, as a non-limiting example, the thickness of the bump guide member 200 may be approximately 10 mm or less. The bump guide member 200 may comprise at least one of a polymer material and a ceramic material. The bump guide member 200 may be formed from a polymer material or a ceramic material. As a non-limiting example, the polymer material may include polyimide (PI), polytetrafluoroethylene (PTFE), etc. The bump guide member 200 may preferably have suitable strength and elasticity. For example, openings such as the bump guide hole 210 and the pad exposure hole 220 may be precisely formed by laser processing. Alternatively, the bump guide member 200 may also be precisely manufactured using micro-electromechanical system (MEMS) processes.

[0058] According to one embodiment, the intermediate fastening member 300 may be provided with a plurality of fastening elements 330 that can move up and down elastically, and the chip guide member 100 may be provided with a plurality of fastening holes 130, wherein the plurality of fastening elements 330 are fastened to the plurality of fastening holes 130. The fastening elements 330 can be introduced from the lower part of their corresponding fastening holes 130 and fastened into them. Furthermore, the bump guide member 200 may include a through hole 230, through which the fastening elements 330 can pass and be fastened into the fastening holes 130.

[0059] For example, the multiple fastening elements 330 may include plungers. A plunger may be a component that moves elastically up and down. An elastic body such as a spring may be disposed inside the plunger. According to one example, the plunger may be a fixed plunger, but is not limited thereto.

[0060] The intermediate fastening member 300 and the chip guiding member 100 can be coupled together via multiple fastening elements 330, and the chip guiding member 100 can elastically move up and down relative to the intermediate fastening member 300. More specifically, the coupled structure (first coupled structure) formed by the chip guiding member 100 and the bump guiding member 200 can be coupled to the intermediate fastening member 300 via multiple fastening elements 330, and the first coupled structure can elastically move up and down relative to the coupled intermediate fastening member 300. In the state where the first coupled structure is coupled to the intermediate fastening member 300, the first coupled structure can be slightly separated from the main body of the intermediate fastening member 300. That is, in the state where the first coupled structure is coupled to the intermediate fastening member 300, the bump guiding member 200 can be slightly separated from the main body of the intermediate fastening member 300. At this time, by pressing the chip guiding member 100 downward from above, the first coupled structure can move downward, and the bump guiding member 200 can approach or contact the intermediate fastening member 300. Furthermore, when the downward pressure on the chip guide member 100 is released, the gap between the bump guide member 200 and the intermediate fastening member 300 can be increased again. In this way, the connection and non-connection between the chip's pads and the probes 450 can be controlled. However, the specific configuration and related operation of the above-described plurality of fastening elements 330 are merely examples and can vary depending on the circumstances.

[0061] According to a specific embodiment, the lower surface of the chip guiding member 100 may be provided with multiple guide pins 105, the bump guiding member 200 may form multiple through guide holes 205, and the intermediate fastening member 300 may form multiple guide holes 305. Furthermore, the bump guiding member 200 may form multiple through holes 235, and the chip guiding member 100 may form multiple insertion holes corresponding to the multiple through holes 235. By providing the bump guiding member 200 on the lower surface of the chip guiding member 100, with the guide pins 105 passing through the through guide holes 205, fasteners such as bolts can be inserted from below the through holes 235 into the through holes 235 and the insertion holes. In this way, the chip guiding member 100 and the bump guiding member 200 can be joined. The lower part of the fastener such as the bolt can be inserted into the groove 335 formed in the intermediate fastening member 300. After the chip guiding member 100 and the bump guiding member 200 are joined to form a first joining structure, the intermediate fastening member 300 can be joined to the first joining structure. At this point, the guide pin 105 can be inserted into the guide hole 305. In addition, the fastening element 330 can pass through the through hole 230 and be fastened into the fastening hole 130.

[0062] According to one embodiment, a plurality of alignment pins 440 may be provided on one side of a chip socket substrate 400 on which a plurality of probes 450 are formed. Three or more alignment pins 440 may be provided. The plurality of alignment pins 440 may be located outside the plurality of probes 450. The plurality of alignment pins 440 may be cylindrical. For example, the plurality of alignment pins 440 may have cylindrical, square, or polygonal shapes. The plurality of alignment pins 440 may be manufactured using micro-electromechanical system (MEMS) technology or using general manufacturing processes. When using MEMS technology, the accuracy of the plurality of alignment pins 440 can be further improved.

[0063] When the chip guide member 100, the bump guide member 200, and the intermediate fastening member 300 are assembled onto the chip socket substrate 400, a plurality of alignment pins 440 can be used as alignment references. When the bonding structure (second bonding structure) formed by combining the chip guide member 100, the bump guide member 200, and the intermediate fastening member 300 is bonded to the chip socket substrate 400, the plurality of alignment pins 440 can be used as alignment references. Relatedly, each of the chip guide member 100, the bump guide member 200, and the intermediate fastening member 300 can form a plurality of alignment guide holes 140, 240, and 340 into which the plurality of alignment pins 440 are inserted. The chip guide member 100 can form a plurality of first alignment guide holes 140, the bump guide member 200 can form a plurality of second alignment guide holes 240, and the intermediate fastening member 300 can form a plurality of third alignment guide holes 340. When multiple alignment pins 440 are inserted into multiple first to third alignment guide holes 140, 240, 340, alignment can be achieved between the chip socket substrate 400 and the second bonding structure. Therefore, assembly tolerances between components can be reduced.

[0064] Multiple probes 450 can be bonded to one side of the chip socket substrate 400 using multiple alignment pins 440 as coordinate references. In other words, in the bonding process of bonding multiple probes 450 to one side of the chip socket substrate 400, the multiple alignment pins 440 can be used as coordinate references. Therefore, the multiple alignment pins 440 can be used both as a reference for determining the bonding position of the multiple probes 450 and as an alignment reference for aligning the chip guide member 100, bump guide member 200, and intermediate fastening member 300 on the chip socket substrate 400. The reference used for bonding the multiple probes 450 and the reference used for determining the chip alignment position can be the same. In this way, since the coordinate reference for probe bonding can be the same as the reference for aligning the components of the chip socket assembly and the semiconductor chip, the alignment accuracy between the probes 450 and the chip pads can be significantly improved.

[0065] Furthermore, the chip socket substrate 400 may be provided with multiple through holes 445, and the intermediate fastening member 300 may be provided with multiple insertion holes 345 corresponding to the multiple through holes 445. In a non-limiting example, after the second coupling structure is provided on the chip socket substrate 400, fasteners such as bolts can be inserted into the insertion holes 345 from below the chip socket substrate 400 through the through holes 445, thereby fastening the chip socket substrate 400 and the intermediate fastening member 300 together.

[0066] Figure 2 This is a schematic plan view of a chip C10 that can be used in a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0067] Reference Figure 2 Multiple bumps and multiple pads (electrode pads) can be formed on one side (e.g., the lower surface) of the chip C10. At least one bump forming region and at least one pad forming region can be provided on one side of the chip C10. The multiple bumps can be arranged in an array in the bump forming region, and the multiple pads can be arranged in an array in the pad forming region. Figure 2 The number and location of the bump formation area and pad formation area shown are just examples and can be varied.

[0068] Figure 3 and Figure 4 This is a schematic cross-sectional view of a portion of a chip C10 that can be used in a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0069] Reference Figure 3 and Figure 4 The bump BP1 can be configured to protrude from one side (e.g., the lower surface) of the chip C10. As a non-limiting example, the protrusion length of the bump BP1 can be tens of nm or more, several μm or more, or tens of μm or more. Figure 3 As shown, pad PD1 can be formed by recessing into one side of chip C10, or as... Figure 4 As shown, it is formed to protrude from one side relative to chip C10. In Figure 4 In this case, the protrusion height of pad PD1 can also be lower than that of bump BP1. Bump BP1 can be a regular bump type or a ball type.

[0070] As a non-restrictive example, Figures 2 to 4The exemplary chip C10 described herein may be high-bandwidth memory (HBM) or include HBM. In the case of next-generation HBM chips, the pad pitch is expected to decrease to below approximately 65 μm. The chip socket assembly according to embodiments of the present invention can have a configuration and characteristics corresponding to the fine pitch of next-generation HBM chips and provide a precise and accurate test solution. However, the types of chips applicable to embodiments of the present invention are not limited to HBM and various variations are possible.

[0071] Figure 5 This is a plan view showing a chip socket substrate 400 applicable to a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0072] Reference Figure 5 The chip socket substrate 400 can have, for example, Figure 1 The aforementioned configuration allows for the formation (disposition) of a plurality of probes 450 on one side (upper surface) of the chip socket substrate 400. Furthermore, a plurality of alignment pins 440 can be disposed on the same side of the chip socket substrate 400 where the probes 450 are formed. The alignment pins 440 can be disposed outside the probes 450. The probes 450 can be formed on one side of the chip socket substrate 400 by bonding, utilizing the alignment pins 440 as coordinate references. That is, in the bonding process of bonding a plurality of probes 450 to one side of the chip socket substrate 400, the alignment pins 440 can be used as coordinate references.

[0073] Figure 6 This is a plan view showing a chip guide member 100 and a bump guide member 200 applicable to a chip socket assembly for semiconductor chip testing according to an embodiment of the present invention.

[0074] Reference Figure 6 The diagram shows a combined structure (first combined structure) formed by combining a chip guide member 100 and a bump guide member 200. The chip guide member 100 may have a plurality of first alignment guide holes 140, and the bump guide member 200 may have a plurality of second alignment guide holes 240.

[0075] Figure 7 This is a plan view showing an intermediate fastening member 300 applicable to a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0076] Reference Figure 7 The intermediate fastening member 300 may have multiple third alignment guide holes 340.

[0077] For reference Figures 5 to 7As described above, after bonding multiple probes 450 onto a chip socket substrate 400 using multiple alignment pins 440 as references, chip guide members 100, bump guide members 200, and intermediate fastening members 300 can be assembled on the chip socket substrate 400 using the same multiple alignment pins 440 as references. For example, a combined structure (second combined structure) formed by combining chip guide members 100, bump guide members 200, and intermediate fastening members 300 can be combined on the chip socket substrate 400 using multiple alignment pins 440 as references. In this way, the coordinate reference for probe bonding and the component assembly reference of the chip socket assembly can be the same, thus significantly improving the connection (contact) accuracy between the probes 450 and the chip pads.

[0078] Figures 8 to 10 This is a schematic cross-sectional view illustrating the process of guiding a chip and placing it in a placement portion using a chip socket assembly for semiconductor chip testing according to an embodiment of the present invention.

[0079] Reference Figure 8 Chip C10 can be inserted into the chip guide hole 110 of chip guide member 100 and guided and aligned for the first time. Chip guide member 100 can guide chip C10 with the periphery of chip C10 as a reference.

[0080] Reference Figure 9 The bump BP1 of chip C10 can enter the bump guide hole 210 of the bump guide member 200, and its position is precisely guided, thereby guiding and aligning the position of chip C10 a second time. When two or more bumps located at the edge (periphery) of bump BP1 contact the portion of the bump guide member 200 corresponding to the border of the bump guide hole 210, the position of bump BP1 can be adjusted, thereby adjusting the position of chip C10. In other words, the position of chip C10 can be precisely adjusted based on the position of bump BP1.

[0081] Reference Figure 10 Chip C10 can be mounted on bump guide member 200. Probe 450 can contact pad PD1 of chip C10 through pad exposure hole 220. The shape of probe 450 shown here is only an example and can vary. The end (i.e., tip) of actual probe 450 can have a width smaller than that of pad PD1.

[0082] According to embodiments of the present invention, by using the bump guide member 200 to precisely guide and align the position of the chip C10 with the bump BP1 as a reference, the alignment characteristics between the pad PD1 and the probe 450 of the chip C10 can be improved. Furthermore, the position of the probe 450 is also aligned with the position of the bump guide member 200 during component assembly, thus improving the alignment and contact characteristics between the pad PD1 and the probe 450, and consequently, the related electrical characteristics. Therefore, even for semiconductor chips with fine pad pitches, electrical testing can be easily performed.

[0083] Figure 11 and Figure 12 This is a schematic cross-sectional view illustrating the process of placing a chip in a placement section using a semiconductor chip test chip socket assembly according to an embodiment of the present invention.

[0084] Reference Figure 11 and Figure 12 The assembled chip socket assembly may include a chip guide member 100, a bump guide member 200, an intermediate fastening member 300, and a chip socket substrate 400. A plurality of probes 450 may be provided on the chip socket substrate 400. As a non-limiting example, a predetermined pickup device (or pickup and placement device) may be used to insert the chip C10 into the chip guide hole of the chip socket assembly. The chip C10 may be placed on the bump guide member 200.

[0085] According to embodiments of the present invention, a semiconductor chip testing apparatus can be provided, including a chip socket assembly for semiconductor chip testing according to the above embodiments. The remaining components of the semiconductor chip testing apparatus, except for the chip socket assembly, can follow the configuration of a general testing apparatus. The chip socket assembly can be applied to various devices and can be moved while holding the chip (die). In this respect, the chip socket assembly can also be referred to as a die carrier socket.

[0086] Figure 13 This is an exploded perspective view used to illustrate a semiconductor chip test chip socket assembly according to a comparative example.

[0087] Reference Figure 13According to the comparative example, the semiconductor chip test chip socket assembly can be composed of a chip guide plate 10 and a chip socket substrate 20. The chip guide plate 10 may have chip guide holes 11 for chip insertion and guidance. Furthermore, a plurality of guide pins 13 may be provided on the lower surface of the chip guide plate 10. The upper surface of the chip socket substrate 20 may be provided with a plurality of probes 25 that contact at least a portion of a plurality of pads formed on the chip. Furthermore, the upper surface of the chip socket substrate 20 may be provided with a plurality of alignment pads 22 serving as bonding position references for the plurality of probes 25. Additionally, the chip socket substrate 20 may have a plurality of guide holes 23 for inserting the plurality of guide pins 13 of the chip guide plate 10.

[0088] exist Figure 13 In the comparative example, the alignment between the chip guide plate 10 and the chip socket substrate 20 can be performed using the guide pins 13 and guide holes 23 as references. On the other hand, the bonding positions of the plurality of probes 25 can be determined using the plurality of alignment pads 22 as coordinate references. Thus, since the reference for determining the bonding positions of the plurality of probes 25 and the reference for aligning the chip guide plate 10 and the chip socket substrate 20 are different from each other, the alignment accuracy between the chip pads and the probes 25 may be reduced. Furthermore, in this comparative example, the chip is guided only by its periphery; therefore, due to component processing tolerances and chip manufacturing tolerances, it is difficult to precisely and accurately align the chip position relative to the probes.

[0089] Figure 14 It shows the basis Figure 13 A plan view of the chip socket substrate 20 of the comparative example chip socket assembly.

[0090] Reference Figure 14 According to the comparative example, the chip socket substrate 20 of the chip socket assembly can have, as follows: Figure 13 The aforementioned configuration. A plurality of probes 25 may be provided on the upper surface of the chip socket substrate 20. A plurality of alignment pads 22 may be provided on the upper surface of the chip socket substrate 20, serving as bonding position references for the plurality of probes 25. Furthermore, the chip socket substrate 20 may have a plurality of guide holes 23 for inserting a chip guide plate (…). Figure 13 10) multiple guide pins ( Figure 13 (13).

[0091] Figure 15 It shows the basis Figure 13 A plan view of the chip guide board 10 of the comparative example chip socket assembly.

[0092] Reference Figure 15 According to the comparative example, the chip guide plate 10 of the chip socket assembly may include a plurality of guide pins 13 disposed on its lower surface.

[0093] In the comparative example, multiple alignment pads 22 can be used as coordinate references to bond multiple probes 25 onto the chip socket substrate 20. After bonding the multiple probes 25, the chip guide plate 10 and the chip socket substrate 20 can be assembled with the guide pins 13 and guide holes 23 as references. However, since the references (position references) for bonding the multiple probes 25 are different from the references (position references) for component assembly, misalignment may occur between the contact between the probes 25 and the chip pads after assembly.

[0094] Figure 16 and Figure 17 It is a cross-sectional diagram used to illustrate the process of placing a chip in the placement section using a semiconductor chip test chip socket assembly according to a comparative example, and to explain the problems therein.

[0095] Reference Figure 16 and Figure 17 According to a comparative example, the chip socket assembly may include a chip guide plate 10 and a chip socket substrate 20 assembled therewith. A plurality of probes 25 may be provided on the chip socket substrate 20. A chip C1 can be inserted into the chip guide hole of the chip socket assembly.

[0096] In the comparative example, chip C1 is guided only with its periphery as a reference. In this case, alignment problems may occur depending on the dimensions (peripheral dimensions) of chip C1. Specifically, when the dimensions of chip C1 are at or near the minimum of its permissible tolerance, a relatively large gap may occur between chip C1 and the chip guide plate 10 within a loosely designed chip guide hole. As a result, alignment problems may occur between the pads of chip C1 and the probe 25. The contact between the pads of chip C1 and the probe 25 may be unstable, making accurate electrical testing difficult.

[0097] However, according to embodiments of the present invention, the following can be overcome. Figures 13 to 17 Problems and limitations of the chip socket assembly shown in the comparative example.

[0098] As described above, according to embodiments of the present invention, a chip socket assembly for semiconductor chip testing can be realized, capable of miniaturizing the electrode (pad) spacing of semiconductor chips (elements) and reducing the tolerances (errors) of connection alignment for electrical testing. According to one embodiment of the present invention, a chip socket assembly for semiconductor chip testing can be realized, which improves the alignment accuracy of the semiconductor chip by applying a bump guide function. The chip is first aligned by guiding the periphery of the semiconductor chip, and then precisely aligned by guiding the bump group of the semiconductor chip using a bump guide member, thus significantly improving the alignment accuracy of the chip relative to the test probe. Furthermore, according to one embodiment of the present invention, a chip socket assembly for semiconductor chip testing can be realized, which improves the alignment accuracy between the probe and the pad by using multiple alignment pins disposed on the chip socket substrate as coordinate references for probe bonding and as references for semiconductor element alignment. Since the coordinate references used for probe bonding can be the same as the references used for aligning the components of the chip socket assembly and the semiconductor chip, the alignment accuracy between the probe and the pad can be significantly improved. By applying the chip socket assembly according to embodiments of the present invention, a semiconductor chip testing apparatus can be realized, which can easily evaluate the electrical characteristics of next-generation semiconductor chips (devices) with fine electrode (pad) spacing.

Claims

1. A chip socket assembly for semiconductor chip testing, comprising: A chip guiding component having a chip guiding hole for inserting and guiding a chip having multiple bumps and multiple pads formed on one side; A bump guiding member is disposed in contact with or adjacent to the chip guiding member, and has at least one bump guiding hole for guiding at least a portion of the locations of the plurality of bumps and at least one pad exposure hole for exposing at least a portion of the plurality of pads. An intermediate fastening member is disposed opposite to the chip guiding member, separated by the bump guiding member, and has an opening for exposing at least a portion of one side of the chip on which the plurality of bumps and the plurality of pads are formed; as well as The chip socket substrate is coupled to the intermediate fastening member and has a plurality of probes formed on one side that contact at least a portion of the plurality of pads.

2. The chip socket assembly for semiconductor chip testing according to claim 1, wherein, The bump guiding member is combined with the chip guiding member. The intermediate fastening member is connected to the chip guiding member through the bump guiding member.

3. The chip socket assembly for semiconductor chip testing according to claim 1, wherein, The bump guide member includes a first bump guide hole, which is used to expose a first group of bumps among the plurality of bumps and guide the position of the first group of bumps.

4. The chip socket assembly for semiconductor chip testing according to claim 3, wherein, The bump guiding member further includes a second bump guiding hole, which is used to expose a second group of bumps among the plurality of bumps and guide the position of the second group of bumps. The second protrusion guide hole is spaced apart from the first protrusion guide hole.

5. The chip socket assembly for semiconductor chip testing according to claim 1, wherein, The bump guide component is an insulating film component.

6. The chip socket assembly for semiconductor chip testing according to claim 1, wherein, The bump guide member comprises at least one of a polymer material and a ceramic material.

7. The chip socket assembly for semiconductor chip testing according to claim 1, wherein, The intermediate fastening member is provided with multiple fastening elements that can move up and down elastically. The chip guiding component is provided with multiple fastening holes, and the multiple fastening elements are fastened to the multiple fastening holes.

8. The chip socket assembly for semiconductor chip testing according to claim 7, wherein, The plurality of fastening elements include plungers.

9. The chip socket assembly for semiconductor chip testing according to claim 1, wherein, The combined structure of the chip guiding member and the bump guiding member moves elastically up and down relative to the intermediate fastening member coupled to the combined structure.

10. The chip socket assembly for semiconductor chip testing according to claim 1, wherein, A plurality of alignment pins are provided on one side of the chip socket substrate on which the plurality of probes are formed. When the chip guide member, the bump guide member, and the intermediate fastening member are assembled to the chip socket substrate, the plurality of alignment pins serve as alignment references.

11. The chip socket assembly for semiconductor chip testing according to claim 10, wherein, The chip guiding member, the bump guiding member, and the intermediate fastening member each have a plurality of alignment guiding holes for insertion of the plurality of alignment pins.

12. The chip socket assembly for semiconductor chip testing according to claim 10, wherein, The plurality of probes are formed by bonding on one side of the chip socket substrate, using the plurality of alignment pins as coordinate references.

13. The chip socket assembly for semiconductor chip testing according to claim 1, wherein, The chip includes a high-bandwidth memory.

14. A semiconductor chip testing apparatus, comprising a chip socket assembly for semiconductor chip testing according to any one of claims 1 to 13.

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