Digital signal data acquisition method and system based on chip test

Abstract

The invention is suitable for the technical field of semiconductor chip testing, and provides a digital signal data acquisition method and system based on chip testing, and the method comprises the steps: a semiconductor testing machine generates and issues a global trigger instruction at a time, and achieves the unified driving of multiple pins based on a digital signal sequence through a first trigger instruction facing a tested chip, starting sampling and digitization of corresponding electric signals by a second trigger instruction oriented to the data sending equipment, aggregating the electric signals according to a test session, and sending the aggregated electric signals to the data processing equipment; the data processing equipment carries out parallel calculation on the received digital signal sampling data and caches a result; and the semiconductor test machine obtains the instruction through the test result and carries out asynchronous backward reading. Therefore, control, acquisition and calculation are decoupled and can be propelled in an overlapped manner, serial waiting and instruction round-trip are reduced, the test time can be shortened, and throughput and resource utilization rate are improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor chip testing technology, and in particular relates to a digital signal data acquisition method and system based on chip testing. Background Technology

[0002] In mass production and factory testing of liquid crystal display (LCD) chips, a set of preset digital drive signals is often used as a quantitative indicator of display capability. Each digital drive signal level corresponds to a desired voltage range. By measuring and recording the actual voltage of each target pin of the chip under test under different digital drive signals, digital signal sampling data can be generated to determine whether the performance meets the standards.

[0003] Current digital signal testing generally adopts a linear process: the semiconductor tester selects the pins one by one in a predetermined order, drives the chip under test at each target digital drive signal level and reads the corresponding voltage value, and then the recorded data is handed over to the host software for calculation and judgment. This process is repeated on all pins and all digital drive signal levels until completion.

[0004] The core problem facing this linear process is that the overall test duration increases significantly with the number of pins and the number of digital drive signal levels, making it difficult to compress the cycle time and limit throughput, thus making it difficult to meet the efficiency requirements of high-batch test scenarios. Summary of the Invention

[0005] In view of this, embodiments of this application provide a digital signal data acquisition method and system based on chip testing. It can realize parallel acquisition and asynchronous computation and feedback of multi-pin, multi-digit signals, significantly shortening test time and improving throughput and resource utilization.

[0006] A first aspect of this application provides a digital signal data acquisition method based on chip testing, applied to a digital signal data acquisition system based on chip testing. The digital signal data acquisition system includes a semiconductor tester and a data processing device. The semiconductor tester includes a main control application program and a data transmission device. The method includes: The main control application generates and issues global trigger instructions, which include at least: a first trigger instruction for the chip under test and a second trigger instruction for the data transmission device. The first trigger instruction is used to instruct the target pin of the chip under test to be driven in parallel based on a digital signal sequence. The second trigger instruction is used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence to obtain digital signal sampling data. The digital signal sampling data of the same test session are aggregated and sent to the data processing device. The data processing device performs parallel calculations on the received digital signal sampling data and caches the corresponding test results; In response to the test result retrieval instruction from the main control application, the data processing device asynchronously returns the test result.

[0007] In this embodiment, the main control application running on the semiconductor test machine generates and issues global trigger commands in one go. Simultaneously, the first trigger command for the chip under test drives multiple pins in a unified manner according to the digital signal sequence. The second trigger command for the data transmission device initiates sampling and digitization of the corresponding electrical signals, aggregates them according to the test session, and sends them to the data processing device. The data processing device performs parallel calculations on the received digital signal sampling data and caches the results. The main control application then obtains instructions through the test results for asynchronous readback. This decouples control, acquisition, and calculation, allowing them to be performed in an overlapping manner, reducing serial waiting and command round trips, thus achieving the beneficial effects of shortening test time, improving throughput, and increasing resource utilization.

[0008] In one possible implementation, the digital signal data acquisition system further includes a data acquisition device, and the second trigger command is further used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence, and send the obtained digital signal sampling data to the data acquisition device; The method further includes: The data acquisition device aggregates digital signal sampling data from the same test session and sends the aggregated digital signal sampling data to the data processing device.

[0009] In one possible implementation, the pins of the data transmitting device are connected one-to-one with the target pins of the chip under test; the method further includes: In response to the acquisition configuration command of the main control application, the data processing device parses the acquisition configuration in the acquisition configuration command, determines the list of pins participating in the sampling, and forwards it to the data acquisition device, so that the data acquisition device can determine whether the collection of digital signal sampling data is completed according to the pin list, and aggregate the digital signal sampling data if it is completed. In response to the acquisition command of the main control application, the data processing device acquires digital signal sampling data corresponding to the current test session from the data acquisition device, performs parallel calculations on the digital signal sampling data based on the specifications and trigger parameters of the chip under test, and caches the corresponding test results.

[0010] In one possible implementation, before the global trigger command is generated and issued by the main control application, the method further includes: The main control application loads the specifications of the chip under test and presets the trigger parameters of the display interface. The trigger parameters include at least a target pin list and a digital signal sequence. Configure the sampling parameters of the data transmission device, wherein the sampling parameters include at least the sampling rate and / or the sampling period; The main control application sends the acquisition configuration associated with this test session to the data processing device. The acquisition configuration includes at least a list of channels participating in the acquisition.

[0011] In one possible implementation, the main control application communicates with the data transmission device via a bus device, and the generation and issuance of global trigger commands by the main control application includes: The first trigger command is issued by the main control application to cause the target pin of the chip under test to synchronously switch to the corresponding digital signal level. The main control application sends the second trigger command to the data transmission device to start sampling and digitization processing according to the preset sampling frequency and sampling period; The main control application sends the acquisition configuration to the data processing device via the network. The acquisition configuration includes at least a list of pins participating in the sampling, which is used for subsequent forwarding and aggregation.

[0012] In one possible implementation, after the first trigger command and the second trigger command are issued, the method further includes: The data transmitting device samples and digitizes the analog voltage on the sampling channel that is electrically connected to the target pin to obtain digital signal sampling data, and temporarily stores the digital signal sampling data in a local cache. When sampling a full digital signal sequence for the same target pin, the data transmitting device sends the digital signal sampling data corresponding to the target pin to the data acquisition device via a high-speed transmission link after adding a CRC16 check value.

[0013] In one possible implementation, the method further includes: The data acquisition device listens to the CRC16 encoded digital signal sampling data stream from the data transmission device and performs integrity verification based on the corresponding CRC16 check value; When all data packets corresponding to the target pins related to this test session are complete, full digital signal sampling data is generated and sent to the data processing device via a high-speed link; The full set of digital signal sampling data and the test results calculated based on the full set of digital signal sampling data are temporarily stored in the data processing device until the test results are sent to the main control application in response to the test result acquisition instruction of the main control application.

[0014] In one possible implementation, during the global triggering and sampling process, the main control application issues a result acquisition instruction at any time node, and the data processing device asynchronously returns serialized structured data associated with the test identifier. The structured data includes at least: the measured values ​​of each target pin under each digital signal level and a pass and / or fail list. The main control application generates waveforms and / or CSV documents for analysis and tracing based on the structured data.

[0015] A second aspect of this application provides a digital signal data acquisition system based on chip testing. The digital signal data acquisition system includes a semiconductor tester and a data processing device. The semiconductor tester includes a main control application program and a data transmission device. The main control application is used to generate and issue global trigger instructions. The global trigger instructions include at least: a first trigger instruction for the chip under test and a second trigger instruction for the data transmission device. The first trigger instruction is used to instruct the target pins of the chip under test to be driven sequentially according to the digital signal sequence. The second trigger instruction is used to instruct the data transmission device to sample and digitize the electrical signals of the target pins under the digital signal sequence to obtain digital signal sampling data. The digital signal sampling data of the same test session are aggregated and sent to the data processing device. The data transmitting device is used to receive the second trigger instruction from the main control application, sample and digitize the electrical signal of the target pin under the digital signal sequence to obtain digital signal sampling data, and aggregate the digital signal sampling data of the same test session and send it to the data processing device. The data processing device is used to perform parallel calculations on the received digital signal sampling data and cache the corresponding test results; in response to the test result acquisition instruction of the main control application, the data processing device asynchronously returns the test results.

[0016] In one possible implementation, the digital signal data acquisition system further includes a data acquisition device, and the second trigger command is further used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence, and send the obtained digital signal sampling data to the data acquisition device; The data acquisition device is used to aggregate digital signal sampling data from the same test session and send the aggregated digital signal sampling data to the data processing device.

[0017] A third aspect of this application provides a digital signal data acquisition device based on chip testing. The device is configured in a digital signal data acquisition system, which includes a semiconductor tester and a data processing device. The semiconductor tester includes a main control application program and a data transmission device. The device includes: The instruction issuing module is used to generate and issue global trigger instructions through the main control application. The global trigger instructions include at least: a first trigger instruction for the chip under test and a second trigger instruction for the data sending device. The first trigger instruction is used to instruct the target pin of the chip under test to be driven in parallel based on a digital signal sequence. The second trigger instruction is used to instruct the data sending device to sample and digitize the electrical signal of the target pin under the digital signal sequence to obtain digital signal sampling data. The digital signal sampling data of the same test session are aggregated and sent to the data processing device. The parallel testing module is used by the data processing device to perform parallel calculations on the received digital signal sampling data and cache the corresponding test results; The result acquisition module is used to respond to the test result acquisition command of the main control application and to return the test result asynchronously by the data processing device.

[0018] A fourth aspect of this application provides a semiconductor testing apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described in the first aspect above.

[0019] A fifth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described in the first aspect. A sixth aspect of this application provides a computer program product that, when run on a semiconductor testing device, causes the semiconductor testing device to perform the steps of the method described in the first aspect.

[0020] For the beneficial effects of the second to sixth aspects mentioned above, please refer to the first aspect mentioned above, which will not be repeated here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a digital signal data acquisition system based on chip testing provided in an embodiment of this application; Figure 2 This is a schematic diagram of another digital signal data acquisition system based on chip testing provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a digital signal data acquisition method based on chip testing provided in an embodiment of this application; Figure 4 This is a flowchart illustrating another digital signal data acquisition method based on chip testing provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a digital signal data acquisition device based on chip testing provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of the semiconductor testing equipment provided in the embodiments of this application. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0029] In mass production and factory testing of liquid crystal display (LCD) chips, a set of preset digital drive signals is often used as a quantitative indicator of display capability. Each digital drive signal level corresponds to a desired voltage range. By measuring and recording the actual voltage of each target pin of the chip under test under different digital drive signals, digital signal sampling data can be generated to determine whether the performance meets the standards.

[0030] Current digital signal testing generally adopts a linear process: the semiconductor tester selects the pins one by one in a predetermined order, drives the chip under test at each target digital drive signal level and reads the corresponding voltage value, and then the recorded data is handed over to the host software for calculation and judgment. This process is repeated on all pins and all digital drive signal levels until completion.

[0031] The core problem with this linear process is that the overall test duration increases significantly with the number of pins and the number of digital drive signal levels. Moreover, the instructions are issued serially, so it is necessary to wait for the instructions to finish executing before exiting. This makes it difficult to compress the cycle time and limits the throughput, making it difficult to meet the efficiency requirements of high-batch testing scenarios.

[0032] To address the aforementioned issues, this application provides a digital signal data acquisition method and system based on chip testing. In this method, the main control application generates and issues a global trigger command in one go. Simultaneously, a first trigger command for the chip under test drives multiple pins in a unified manner according to the digital signal sequence. A second trigger command for the data transmitting device initiates sampling and digitization of the corresponding electrical signals, aggregates them according to the test session, and sends them to the data processing device. The data processing device performs parallel calculations on the received digital signal sampling data and caches the results. The main control application then obtains instructions through the test results for asynchronous readback. This decouples control, acquisition, and calculation, allowing them to be performed in an overlapping manner, reducing serial waiting and instruction round trips, thus achieving the beneficial effects of shortening test time, improving throughput, and increasing resource utilization.

[0033] The following describes in detail, with reference to the accompanying drawings, the digital signal data acquisition method, system, apparatus, semiconductor testing equipment, storage medium, and computer program based on chip testing provided in the embodiments of this application.

[0034] Figure 1 A schematic diagram of a digital signal data acquisition system based on chip testing, according to an embodiment of this application, is shown. The system includes a semiconductor testing machine and a data processing device. The semiconductor testing machine includes a main control application program and a data transmission device. Their connection relationships and main data / control flow are shown in the figure.

[0035] Main control application: Used to generate and issue global trigger commands, as well as issue acquisition commands and result acquisition commands in subsequent stages. The global trigger commands include at least: The first trigger instruction for the chip under test is used to instruct the target pin of the chip under test to be driven in parallel based on a digital signal sequence; The second trigger command for the data transmitting device is used to instruct the data transmitting device to sample and digitize the electrical signal of the target pin in the digital signal sequence.

[0036] The semiconductor tester can communicate with the chip under test via a display interface (preferably MIPI); with the data transmission device via a local bus; and with the data processing device via a network interface. These interface types are merely examples, and this application does not limit the implementation of the interfaces.

[0037] Data transmitting device: Its multiple sampling pins are connected one-to-one with the target pins of the chip under test. Under the control of a second trigger command, the data transmitting device samples and digitizes the electrical signals of the target pins in a digital signal sequence to obtain digital signal sampling data; after aggregating the data at the same test session granularity, it sends the full amount of digital signal sampling data to the data processing device. The data transmitting device can set up a local buffer queue to temporarily store the sampling results; in an optional implementation, the transmitted data may include a test session identifier and an integrity verification field (such as a CRC check value).

[0038] Data processing equipment: This equipment receives digital signal sampling data from the data transmitting equipment, performs parallel computations on the data to generate test results, and caches the results for later querying. Upon receiving a result retrieval instruction from the main control application, it asynchronously returns the result data corresponding to the current test session to the main control application. To ensure throughput, the data processing equipment can partition and process data in parallel by pin and / or by digital signal sequence level. Caching and parallel strategies do not constitute limitations on this invention.

[0039] The chip under test (DUT) is used to drive the target pins in parallel based on a digital signal sequence and output corresponding electrical signals under the control of the first trigger command, for sampling by the data transmission device. The specific model of the DUT and the number of digital signal levels are not limited.

[0040] The working process of the system in the embodiments of this application is described in detail below: First, the main control application completes test preparation, such as loading the specifications of the chip under test, generating a target pin list and digital signal sequence, and then issues a global trigger command all at once: the first trigger command (preferably via MIPI) causes the target pins of the chip under test to be driven in parallel according to the digital signal sequence, and the second trigger command (via the local bus) causes the data transmitting device to start sampling and digitization on the corresponding channel and aggregate them according to the same test session; at the same time, the main control application can send the acquisition configuration to the data processing device via the network, which includes the session identifier and the list of pins participating in sampling. Next, the data transmitting device samples, digitizes, and buffers the electrical signals at each digital signal level locally, aggregates them according to the session, and sends the digital signal sampling data (carrying the session identifier, and if necessary, timestamp / checksum fields) to the data processing device; the data processing device performs parallel calculations on the received data according to pins and / or digital signal levels and caches the results. During this process, the main control application can continue to execute other test items and issue acquisition / result acquisition instructions at the required time points. The data processing device asynchronously returns structured results based on the session identifier, such as the measurement values ​​and judgments of each pin and each digital signal level, for generating waveforms or CSV, thereby achieving decoupling and at least partially overlapping execution of the triggering, sampling and calculation stages.

[0041] It should be noted that the arrows in the diagram only indicate the main control and data flow; the specific timing and distribution details can be configured according to the testing requirements.

[0042] It should also be noted that the specific implementations of the display interface, bus, and network (such as MIPI, Ethernet, fiber optic, etc.) can be replaced without affecting the functionality of this system.

[0043] In this embodiment, a global trigger command is generated and issued once by the main control application, which, together with the data sending device sampling locally and uploading data by session aggregation, the data processing device performing parallel calculations and caching of results in partitioned areas, and the main control asynchronous readback, constructs a decoupled and overlapping processing chain of control-sampling-computation. Compared with the linear pin-by-pin and level-by-level approach, this method can significantly compress test time, improve link and computing power utilization and overall throughput in multi-pin × multi-digit signal level scenarios. At the same time, it reduces the interaction and synchronization waiting between the main control and peripherals, reduces CPU usage, and enhances data consistency and traceability through session-level aggregation (and optional identifier / time information).

[0044] As one possible implementation scheme, Figure 2 This illustration shows a schematic diagram of another digital signal data acquisition system based on chip testing provided in an embodiment of this application. The system includes a semiconductor tester, a data processing device, and a data acquisition device. The semiconductor tester includes a main control application program and a data transmission device. The connections are as follows: the semiconductor tester communicates with the chip under test (via a display interface), the data transmission device (via a local bus), and the data processing device (via a network interface); the data processing device communicates with the data acquisition device via a high-speed transmission link (e.g., fiber optic or Ethernet with speeds of at least ten gigabits per second); and multiple sampling pins of the data transmission device are connected one-to-one with the target pins of the chip under test.

[0045] The main control application generates and issues global trigger commands, including a first trigger command for the chip under test (instructing the target pins to be driven in parallel according to the digital signal sequence) and a second trigger command for the data transmission device (instructing sampling and digitization to be started on the corresponding channel). In addition, the main control application also issues acquisition configuration, acquisition commands, and result acquisition commands to the data processing device. The acquisition configuration includes at least a test identifier and a list of pins participating in the sampling.

[0046] Data transmission device: Based on the second trigger command, it samples and digitizes the electrical signals of the target pin at each digital signal level to obtain digital signal sampling data; it can be cached locally and actively pushed to the data acquisition device through a high-speed transmission link after completing the full digital signal sequence of a single pin.

[0047] Data acquisition equipment: listens to data streams from multiple data transmission device pins and performs session-level aggregation; performs integrity verification (e.g., using 16-bit cyclic redundancy check) and packet reordering on the received data; when completion conditions are met (e.g., complete by pin, complete by digital signal level, or time window expires), it forms full digital signal sampling data and sends it to the data processing equipment.

[0048] Data processing equipment: Receives and caches full digital signal sampling data from the data acquisition equipment; upon receiving the acquisition command from the main control application, it performs parallel calculations on the data according to the specifications of the chip under test and trigger parameters to generate test results and caches them; upon receiving the result retrieval command, it asynchronously returns structured result data corresponding to the test identifier (e.g., measured values ​​of each digital signal level for each pin and a pass / fail list). Simultaneously, the data processing equipment is also responsible for forwarding acquisition-related commands from the main control application to the data acquisition equipment, enabling the data acquisition equipment to define the aggregation scope and submission conditions accordingly.

[0049] The specific implementation process of this embodiment will be described in detail below: First, the main control application completes test preparation (loading specifications, generating a target pin list and digital signal sequence, configuring the sampling parameters of the data transmission device), and issues a global trigger command all at once: the first trigger command drives the target pins of the chip under test sequentially according to the digital signal sequence; the second trigger command causes the data transmission device to start sampling and digitization in the corresponding channel; simultaneously, the main control application sends the acquisition configuration to the data processing device, which parses it and forwards it to the data acquisition device. Subsequently, the data transmission device samples, digitizes, and temporarily stores the electrical signals at each digital signal level locally, and actively pushes the completed full digital signal sequence of a single pin to the data acquisition device; the data acquisition device performs integrity verification and aggregation on the data streams from multiple pins, and sends the full digital signal sampling data to the data processing device through a high-speed transmission link when the completion conditions are met. During this process, the data processing device can first cache data. When the main control application issues a data acquisition command, the data processing device retrieves the cached data, performs parallel calculations on a pin-by-pin and / or digital signal basis, and generates test results. Subsequently, the main control application issues a result acquisition command at the required time, and the data processing device asynchronously returns structured results (which may include waveform data or an index of a comma-separated value format file if necessary) for recording and analysis. The triggering, sampling, and calculation stages described above are decoupled from each other and can at least partially overlap, thereby improving overall efficiency.

[0050] It should be noted that the display interface type, transmission medium, integrity verification method, and parallel computing and caching strategy can all be selected or replaced according to the test scenario without affecting the functional implementation of this embodiment.

[0051] Compared to the previous embodiment, this embodiment adds a data acquisition device between the data sending device and the data processing device. This device centrally performs session-level aggregation, integrity verification (e.g., 16-bit cyclic redundancy check), and packet reordering. The data is then sent up according to completion conditions such as "all pins are complete / all digital signal levels are complete / time window expires," allowing the data processing device to perform parallel computation on only clean, full-volume data. This reduces the link and computational load between the data sending and processing devices, decreases packet loss and retransmission, and reduces latency fluctuations, improving stability and traceability. Furthermore, it supports parallel access and batch submission from multiple data sending devices, and the uplink can centrally use high-speed transmission media, further improving overall throughput and scalability.

[0052] In another possible implementation, the digital signal data acquisition system may employ the following alternative structures or schemes to achieve the same technical objective as the main scheme: In this scheme, the wired communication link (e.g., fiber optic link) between the data transmitting device and the data processing device can be replaced with a millimeter-wave wireless transmission link (e.g., a 60GHz high-frequency channel). This scheme is suitable for testing environments with rotating screens or where wired connections are difficult, and can improve the flexibility of system deployment. However, when transmitting large amounts of data, it may be necessary to combine it with a data compression scheme to avoid increasing transmission time.

[0053] In this scheme, the data transmitting device can pre-execute basic algorithms locally, such as determining whether each digital signal data is within the voltage range of the corresponding digital signal level, and filtering qualified data locally, uploading only abnormal data or statistical results to the data processing device. This scheme can significantly reduce data transmission volume and improve link bandwidth utilization, but it requires integrating a card control algorithm module into the data transmitting device.

[0054] In this scheme, the data processing device consists of a computing cluster composed of multiple independent nodes. Different nodes are responsible for processing digital signal data from different pin ranges. For example, the first data processing node processes pins 1 to 128, and the second data processing node processes pins 129 to 256. This scheme can effectively reduce the processing time of a single node and improve the overall computing power in scenarios with large amounts of data, but it increases the complexity of the link from the data sending device to multiple data processing nodes.

[0055] This application is not limited to the specific embodiments described above, and all equivalent substitutions within the spirit and protection scope of this invention are included.

[0056] It should be noted that the "digital signal data" mentioned in this application is a general term for the response characteristic data of the chip under test at a preset digital signal level. In the mass production and factory testing scenarios of liquid crystal display (LCD) driver chips, the digital signal data can specifically be grayscale data, and the digital signal level can correspond to each grayscale level in the LCD display. In other types of chips or other test items, the digital signal data can also be test data in different forms such as voltage, current, encoded values, and timing parameters, and the digital signal level can be configured according to specific test specifications. This application does not limit the specific physical meaning of digital signal data and digital signal level, but allows for definition and expansion according to different application scenarios to adapt to various semiconductor testing needs.

[0057] In the following specific embodiments, a liquid crystal display driver chip is used as an example. The "digital signal data" mentioned above is specifically grayscale test data, and the "digital signal level" is specifically each grayscale level, to illustrate the technical solution of this application. It should be understood that this embodiment is only used to illustrate the technical concept of this application and does not constitute a limitation on the specific form of digital signal data and digital signal levels. [Jing Li 1] See Figure 3 This document illustrates a flowchart of a digital signal data acquisition method based on chip testing, provided in an embodiment of this application. This method can be applied to the aforementioned... Figure 1 The digital signal data acquisition system based on chip testing is shown; such as Figure 3 As shown, the method may include the following steps: Step 301: Generate and issue a global trigger command through the main control application.

[0058] The global trigger instruction is a set of combined instructions generated once by the main control application and directed to multiple objects. It is used to initiate the triggering and sampling of a test session and may include a first trigger instruction, a second trigger instruction, and a collection configuration instruction.

[0059] The first trigger instruction is directed at the chip under test, instructing its target pins to be driven in parallel based on the data signal level. That is, when testing the LCD driver chip, it is driven in parallel according to a preset grayscale sequence.

[0060] The second trigger command is directed to the data transmission device, instructing it to start sampling and digitizing the electrical signal of the target pin in the corresponding channel, and then send the aggregated data according to the same test session.

[0061] The system collects configuration commands and control information for the data processing equipment. It records the test session identifier, the list of pins involved in the sampling, time parameters, etc., to facilitate subsequent data processing and result reading.

[0062] Test session identifier, used to uniquely identify a complete trigger and sampling process.

[0063] In this embodiment of the application, taking the chip under test as a liquid crystal display driver chip as an example, the main control application loads the specification parameters of the chip under test, generates the target pin list and grayscale sequence for this test, and sets the necessary time parameters (such as synchronization flag, duration of each grayscale, time window, etc.); at the same time, it configures the sampling parameters of the data transmission device (such as sampling frequency, sampling period) and forms a list of pins participating in the sampling.

[0064] The main control application assembles global trigger instructions based on the above parameters, which include at least: a first trigger instruction, a second trigger instruction, and a data acquisition configuration instruction, and writes a test session identifier to associate data and results in subsequent stages.

[0065] The first trigger command is sent to the chip under test through a display interface (such as a display link that conforms to the mobile industry processor interface standard) to drive the target pin to output electrical signals in parallel according to the grayscale sequence; The second trigger command is sent to the data transmission device via the local bus to start sampling and digitization of the corresponding channel and aggregate according to the test session; The data acquisition configuration is sent to the data processing device via the network interface to record the parameters of this session and forward them to other devices when needed.

[0066] The master application receives execution confirmations from each device; if no confirmation is received within the preset time window, it can resend or terminate the current session according to the policy.

[0067] For example, taking a liquid crystal display driver chip as an example for testing, 64 target pins are selected, with a grayscale sequence of 0 to 255 levels, and the holding time of each level is 50 microseconds. The main control application generates a test session identifier "09-16-01" and assembles global trigger instructions: The first trigger instruction specifies the target pin list and grayscale sequence, and sets a synchronization flag to achieve simultaneous effect; The second trigger command instructs the data transmission device to sample and digitize the above 64 pins at a sampling frequency of 5 MHz / second, with the sampling period and hold duration matched, and aggregated according to "single pin full grayscale" as the smallest unit. The system collects and records the test session identifier, a list of 64 pins involved in the sampling, and the time window.

[0068] Subsequently, the semiconductor testing machine sends three types of information to the chip under test, the data transmission device, and the data processing device via the display interface, local bus, and network interface, respectively, completing step 301 and entering the subsequent data sampling and processing stage. The above values ​​are for illustrative purposes only and can be adjusted according to actual chip specifications and production line requirements; they do not constitute a limitation.

[0069] In one possible implementation, the digital signal data acquisition system further includes a data acquisition device, and the second trigger command is further used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence, and send the obtained digital signal sampling data to the data acquisition device. In this embodiment of the application, the digital signal data acquisition method further includes: The data acquisition equipment aggregates the digital signal sampling data of the same test session and sends the aggregated digital signal sampling data to the data processing equipment.

[0070] Taking grayscale digital signal data as an example, during the specific execution process, after the main control application issues the second trigger command, the data transmitting device samples the electrical signal of the target pin of the chip under test in the grayscale sequence according to the command requirements and completes the digitization processing. The obtained grayscale sampled data is not directly sent to the data processing device, but is first sent to the data acquisition device. The data acquisition device receives grayscale sampled data from multiple data transmitting device channels and performs unified aggregation at the same test session granularity. To ensure the integrity and reliability of the data, the data acquisition device can also perform integrity verification (such as 16-bit cyclic redundancy check) and data order sorting during the aggregation process, thereby ensuring the correctness and timing consistency of the aggregated data.

[0071] Once the data acquisition device confirms that it has completed the aggregation of all target pins and grayscale level data required for this session, it sends the generated full grayscale sampling data to the data processing device via a high-speed transmission link. After receiving the full grayscale sampling data, the data processing device performs parallel calculations according to the chip specifications and trigger parameters, and caches the calculation results locally for the main control application to read asynchronously later via result retrieval commands.

[0072] By introducing a data acquisition device between the data transmission device and the data processing device, this embodiment can achieve intermediate data aggregation and verification, reduce the burden on the data processing device to directly deal with multiple raw data streams, improve the stability and accuracy of overall data transmission, and ensure the integrity and traceability of the final calculation results.

[0073] In one possible implementation, before the master application generates and issues the global trigger command, the following steps are also included: The main control application loads the specifications of the chip under test and presets the trigger parameters of the display interface. The trigger parameters include at least the target pin list and digital signal sequence. Configure the sampling parameters of the data transmission device, including at least the sampling rate and / or sampling period; The main control application sends the acquisition configuration associated with this test session to the data processing device. The acquisition configuration includes at least a list of channels participating in the acquisition.

[0074] Among them, the trigger parameters are a set of parameters used to guide the chip under test to execute digital signal driving, including at least a target pin list and a digital signal sequence (optionally including synchronization identifier, holding time of each digital signal level (e.g., holding time of each gray level) etc.).

[0075] Among them, the sampling parameters are a set of parameters used to guide the data transmission device to perform sampling and digitization, including at least the sampling rate and / or sampling period (optionally including quantization bit width, trigger delay, time window, etc.).

[0076] Among them, the data acquisition configuration is the control information sent by the main control application to the data processing device to identify and constrain the data aggregation range of this test session. It includes at least a list of channels participating in the acquisition (optionally including test session identifier, time window, completion conditions, etc.).

[0077] A test session refers to a complete test process of "trigger-sampling-computation-readback", which can be distinguished and traced by a unique session identifier.

[0078] In this embodiment, taking digital signal data as grayscale data as an example, the main control application reads the specification file of the chip under test and parses basic information such as the range of sampleable pins, the number of grayscale levels, and the recommended voltage range. Based on the test task, target pins are selected, and a target pin list is generated. The grayscale sequence (e.g., from low to high or a sampling sequence) is determined according to the specifications or task requirements, and a synchronization flag and the holding time for each grayscale level are configured if necessary. For the data transmitting device, a sampling rate and / or sampling period matching this trigger are set, and the mapping relationship between the target pins and sampling channels is completed (for subsequent data aggregation and tracing). The main control application generates a collection configuration associated with this test session, at least writing the list of channels participating in the collection (consistent with the target pin list or a subset as needed), and optionally writing the test session flag, time window, and completion conditions. This collection configuration is then sent to the data processing device via the network interface for subsequent data aggregation control and result association. The main control application can wait for confirmation of readiness from the data transmitting device and the data processing device; once confirmation is complete, the subsequent step of "generating and issuing a global trigger command" is performed.

[0079] For example, in a mass production sampling inspection, 64 target pins are selected for testing, and a grayscale sequence of 256 levels is set. To ensure sufficient sampling of the gradient changes, the main control application sets the trigger parameters as follows: the target pin list is the selected 64 pins, the grayscale sequence switches sequentially from lowest to highest, and the holding time for each grayscale level is 50 microseconds. For the data transmission device, the sampling parameters are configured to a sampling period of five million samples per second, and a "target pin" is established. The sampling channels are mapped one-to-one. Subsequently, the main control application generates the acquisition configuration, writes the list of participating channels (sixty-four channels) and the identifier of this test session, and sends it to the data processing device via the network interface; the data processing device returns a confirmation that "acquisition configuration has been loaded." At this point, the preliminary preparations are complete, and the system can enter the global triggering phase. The main control application sends the first trigger command and the second trigger command to the chip under test and the data sending device respectively, initiating the grayscale acquisition process for this session. The specific values ​​and fields mentioned above are only examples and can be adjusted according to the specifications of the chip under test and the production line cycle time requirements.

[0080] In one possible implementation, the main control application communicates with the data transmission device via a bus device, and the main control application generates and issues global trigger commands, including: The main control application sends a first trigger command to cause the target pin of the chip under test to synchronously switch to the corresponding digital signal level. The main control application sends a second trigger command to the data transmission device to start sampling and digitization processing according to the preset sampling frequency and sampling period; The main control application sends the acquisition configuration to the data processing device via the network. The acquisition configuration includes at least a list of pins that participate in the sampling, which is used for subsequent forwarding and aggregation.

[0081] For example, taking digital signal data as grayscale data, in a test of full grayscale acquisition of 32 target pins, the main control application generates global trigger commands. The first trigger command drives all 32 target pins of the chip under test to switch to grayscale levels simultaneously. The second trigger command is sent to the data transmission device via the bus, requiring it to acquire data at a sampling frequency of 5 MHz and a sampling period of 50 microseconds. Simultaneously, the main control application sends the acquisition configuration to the data processing device, including a list of the 32 participating pins and a session identifier. After performing sampling and digitization, the data transmission device aggregates the acquired grayscale sampling data by session, and the data processing device ultimately performs calculations and caches the results.

[0082] In this way, the main control application communicates directly with the data transmission device at high speed via the bus, ensuring the timeliness of triggering and sampling. At the same time, the acquisition configuration is handed over to the data processing device for unified management through the network, so that the whole system can achieve a reasonable division of labor between control and data processing, and improve the collaborative efficiency of acquisition and processing.

[0083] Step 302: The data processing device performs parallel calculations on the received digital signal sampling data and caches the corresponding test results.

[0084] In one possible implementation, the data processing device initiates a data processing flow after receiving digital signal sampling data transmitted from the data transmitting device or the data acquisition device.

[0085] Parallel computing refers to dividing the received full digital signal sampling data according to the pin dimension or digital signal level dimension, and executing the computing tasks in parallel through multi-core processing units or multi-threading mechanisms to accelerate the overall computing speed.

[0086] Caching test results refers to temporarily storing the calculated results in the cache or database of the data processing device, for later use in waiting for subsequent queries, calls, or readbacks.

[0087] In this embodiment, taking digital signal data as grayscale data as an example, the data processing device first decodes and organizes the received data packets, removes redundant information, and maps the data to the corresponding test batch according to the session identifier. According to a preset strategy, the full grayscale sampling data is divided into a two-dimensional matrix of "target pin × grayscale level," with each partition processed in parallel by different computing cores. On each computing core, an algorithm matching the specifications of the chip under test is executed, such as voltage range determination, outlier identification, or deviation statistics, to obtain the pass / fail result for each pin at each grayscale level. The calculation results output by each core are summarized into structured data, such as a table format of "pin number—grayscale level—measured voltage—judgment result." Result caching: The integrated test results are written to a local cache queue or database and associated with the test session identifier, waiting for the main control application to call them later through a result retrieval command.

[0088] For example, in a test session containing 64 target pins and 256 grayscale levels, the data processing device receives approximately 16,384 voltage sample values. The system divides this data into 64 task partitions based on the pin dimension, with calculations distributed among 8 parallel processing cores, each processing data from 8 pins simultaneously. Each core performs voltage range comparison and anomaly marking operations, with an average computation time controlled within 20 milliseconds. Upon completion, the data processing device integrates all calculation results into a structured report, including the voltage measurement values ​​of each pin at each grayscale level and pass / fail markings. This report is then bound to the test session identifier and temporarily stored in a cache queue. Subsequently, when the main control application issues a result retrieval command, the data processing device can asynchronously return this report, ensuring that the main control device does not need to wait for calculation completion during the test, thus improving the overall system throughput and response speed.

[0089] Specifically, in one possible implementation, the method further includes: In response to the acquisition configuration command from the main control application, the data processing device parses the acquisition configuration in the acquisition configuration command, determines the list of pins participating in the sampling, and forwards it to the data acquisition device, so that the data acquisition device can determine whether the collection of digital signal sampling data is complete based on the pin list, and aggregate the digital signal sampling data if it is complete. In response to the acquisition command from the main control application, the data processing device obtains the digital signal sampling data corresponding to the current test session from the data acquisition device, performs parallel calculations on the digital signal sampling data based on the specifications and trigger parameters of the chip under test, and caches the corresponding test results.

[0090] In this embodiment, taking grayscale data as digital signal data as an example, the pins of the data transmitting device correspond one-to-one with the target pins of the chip under test. After the main control application issues the acquisition configuration command, the data processing device parses the command, determines the list of pins that need to participate in sampling, and forwards the pin list to the data acquisition device. Based on this, the data acquisition device determines whether the sampling data of the current session is complete. When it is determined that the sampling of all target pins has been completed, the grayscale sampling data of this session is aggregated, and the aggregated data is sent to the data processing device. Subsequently, when the main control application issues an acquisition command, the data processing device obtains the complete grayscale sampling data corresponding to this test session from the data acquisition device, and performs parallel calculations in combination with the specifications and trigger parameters of the chip under test, caching the calculation results for subsequent use.

[0091] In one possible implementation, after the first trigger command and the second trigger command are issued, the method further includes: The data transmitting device samples and digitizes the analog voltage on the sampling channel that is electrically connected to the target pin to obtain digital signal sampling data, and temporarily stores the digital signal sampling data in the local cache; When sampling a full digital signal level sequence for the same target pin, the data transmitting device sends the digital signal sampling data corresponding to the target pin to the data acquisition device via a high-speed transmission link after adding a CRC16 check value.

[0092] In another possible implementation, the method further includes: The data acquisition device listens to the grayscale sampled data stream encoded by CRC16 from the data transmission device and performs integrity verification based on the corresponding CRC16 check value; When all data packets corresponding to the target pins related to this test session are complete, full digital signal sampling data is generated and sent to the data processing device via a high-speed link; The data processing device temporarily stores the full amount of digital signal sampling data and the test results calculated based on the full amount of digital signal sampling data until it responds to the test result acquisition instruction of the main control application and sends the test results to the main control application.

[0093] This implementation method ensures the accuracy and reliability of data entering subsequent processing by performing CRC16 verification on the digital signal sampling data stream at the data acquisition device side. Furthermore, it guarantees session-level data consistency by generating and uploading the full set of digital signal sampling data only after confirming the integrity of all target pin data. This eliminates the need for the data processing device to handle fragmented data packets, enabling centralized parallel computation and result caching. This not only improves overall processing efficiency but also reduces the system error rate. Simultaneously, the data processing device temporarily stores the full data and test results, providing good traceability of the testing process and supporting flexible result retrieval by the main control application. Overall, this significantly enhances the system's reliability, stability, and usability.

[0094] Step 303: In response to the test result retrieval instruction from the main control application, the data processing device asynchronously returns the test results.

[0095] In this embodiment, after the data processing device completes parallel computation of the full set of digital signal sampling data and caches the corresponding results, it does not immediately return the results to the main control application. Instead, it waits for the main control application to issue a test result retrieval instruction at an appropriate time. Upon receiving the retrieval instruction, the data processing device retrieves the corresponding test results from its local cache based on the test session identifier carried in the instruction and returns them to the main control application asynchronously.

[0096] During this process, the main control application can execute other test tasks while waiting for results, without being blocked on a single session, thereby improving the parallelism and utilization of the overall system test. The returned test results are usually presented in the form of structured data, such as a table containing "pin number - digital signal range - measured voltage - judgment result", and waveform files or data indexes can be attached if necessary for subsequent plotting and analysis.

[0097] For example, taking digital signal data as grayscale data, in a test session containing 64 pins and 256 grayscale levels, the data processing device completes parallel processing of approximately 16,384 sampled data points and caches the results along with the test session identifier. Subsequently, the main control application issues a test result retrieval command after 200 milliseconds. The data processing device immediately retrieves the cache and asynchronously returns the complete test results for the session, based on which the main control application generates waveforms and reports.

[0098] In this way, step 303 decouples computation and control, allowing the main control application to flexibly schedule the test sequence, while the data processing equipment ensures that the results are returned asynchronously on demand, thereby improving the overall throughput, real-time performance and scalability of the system.

[0099] In one possible implementation, during the global triggering and sampling process, the main control application issues a result acquisition instruction at any time node, and the data processing device asynchronously returns serialized structured data associated with the test identifier. The structured data includes at least: the measured values ​​of each target pin under each digital signal level and a pass and / or fail list. The master application generates waveforms and / or CSV documents for analysis and tracing based on structured data.

[0100] Through the above method implementation, the main control application generates and issues a global trigger command at once. Simultaneously, the first trigger command for the chip under test drives multiple pins in a unified manner according to the digital signal sequence. The second trigger command for the data transmission device initiates the sampling and digitization of the corresponding electrical signals, aggregates them according to the test session, and sends them to the data processing device. The data processing device performs parallel calculations on the received digital signal sampling data and caches the results. The main control application then obtains instructions through the test results for asynchronous readback. This decouples control, acquisition, and calculation and allows them to be carried out in an overlapping manner, reducing serial waiting and command round trips, thus achieving the beneficial effects of shortening test time, improving throughput, and increasing resource utilization.

[0101] See Figure 4 The diagram illustrates a flowchart of another digital signal data acquisition method based on chip testing provided in this application embodiment.

[0102] In practice, this method involves the main control application running on the semiconductor test machine calling the processor to execute the corresponding steps.

[0103] like Figure 4 As shown, this method is completed collaboratively by the main control application, the LCD chip (the chip under test), the data sending equipment (DSQ), the data acquisition equipment (DAQ), and the data processing unit (DPU).

[0104] Taking grayscale data as an example, at the start of the test, the main control application sends trigger commands to each module. Specifically: a first trigger command is sent to the LCD chip, causing its target pins (LCD pins 1 to N) to generate corresponding voltage signals according to a preset grayscale sequence; a second trigger command is sent to the data transmission device, containing sampling specifications to control the data transmission device to acquire the aforementioned voltage signals according to the set sampling frequency and period; and a command containing sampling configuration is sent to the data processing device. The DPU parses this command and forwards it to the data acquisition device, enabling it to know the list of target pins to be acquired in this session.

[0105] During the triggering phase, the data transmitting device samples and digitizes the pin voltages connected to the LCD pins, and pushes the resulting grayscale sampled data to the data acquisition device via a high-speed transmission link. The data acquisition device receives and aggregates the sampled data reported by multiple data transmitting devices and performs data integrity verification. Once it is confirmed that all target pin data related to this session has been collected, the full amount of grayscale sampled data is sent to the data processing device.

[0106] At the same time, the data processing device, as an intermediate control node, is also responsible for receiving information containing the sampling range of the data acquisition device from the main control application and forwarding it to the data acquisition device, thereby realizing the precise division of sampling tasks and the determination of completion conditions.

[0107] After the triggering operation is completed, the main control application sends a data acquisition command. Upon receiving the command, the data processing device obtains the full grayscale sampling data corresponding to this test session from the data acquisition device, and performs parallel calculations in conjunction with the specifications and triggering parameters of the LCD chip to finally obtain the voltage performance of each pin at different grayscale levels and the result of whether it is qualified.

[0108] While the data processing device is performing calculations, the main control application can continue to run other test items without being blocked. When the main control application issues a command to retrieve results, the data processing device retrieves the corresponding results from the cache according to the test session identifier and asynchronously returns them to the main control application via network communication (e.g., Socket-based transmission) for plotting waveforms or generating reports.

[0109] By Figure 4 The process shown in this embodiment achieves end-to-end decoupling of "triggering—acquisition—computation—feedback," eliminating the need for the main control application to synchronously wait for acquisition and computation to complete, thus improving overall testing efficiency and system throughput. Simultaneously, the introduction of data acquisition equipment ensures the integrity and consistency of sampled data, while the parallel computing and asynchronous caching mechanisms of the data processing equipment significantly reduce CPU load and enhance the traceability of test results.

[0110] See Figure 5 The diagram shows a schematic of a digital signal data acquisition device based on chip testing provided in an embodiment of this application; for ease of explanation, only the parts related to the embodiments of this application are shown.

[0111] The chip-based digital signal data acquisition device 500 may specifically include: The instruction issuing module 501 is used to generate and issue global trigger instructions through the main control application. The global trigger instructions include at least: a first trigger instruction for the chip under test and a second trigger instruction for the data transmitting device. The first trigger instruction is used to instruct the target pins of the chip under test to be driven sequentially according to the digital signal sequence. The second trigger instruction is used to instruct the data transmitting device to sample and digitize the electrical signals of the target pins under the digital signal sequence to obtain digital signal sampling data. The digital signal sampling data of the same test session are aggregated and sent to the data processing device. The parallel test module 502 is used by the data processing device to perform parallel calculations on the received digital signal sampling data and cache the corresponding test results. The result acquisition module 503 is used to respond to the test result acquisition command of the main control application and return the test result asynchronously by the data processing device.

[0112] In this embodiment of the application, where the digital signal data acquisition system further includes a data acquisition device, and the second trigger instruction is further used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence, and send the obtained digital signal sampling data to the data acquisition device, the digital signal data acquisition device 500 based on chip testing may further include: The data aggregation module is used to aggregate digital signal sampling data from the same test session by the data acquisition device, and then send the aggregated digital signal sampling data to the data processing device.

[0113] In this embodiment of the application, where the pins of the data transmitting device are connected one-to-one with the target pins of the chip under test, the digital signal data acquisition device 500 based on chip testing may further include: The first instruction response module is used to respond to the acquisition configuration instruction of the main control application. The data processing device parses the acquisition configuration in the acquisition configuration instruction, determines the list of pins participating in the sampling, and forwards it to the data acquisition device so that the data acquisition device can determine whether the collection of digital signal sampling data is completed according to the pin list, and aggregate the digital signal sampling data if it is completed. The second instruction response module is used to respond to the acquisition instructions of the main control application. The data processing device obtains the digital signal sampling data corresponding to the current test session from the data acquisition device, performs parallel calculations on the digital signal sampling data based on the specifications and trigger parameters of the chip under test, and caches the corresponding test results.

[0114] In this embodiment of the application, the digital signal data acquisition device 500 based on chip testing may further include: The parameter preset module is used to load the specifications of the chip under test by the main control application and preset the trigger parameters of the display interface. The trigger parameters include at least the target pin list and digital signal sequence. The sampling configuration module is used to configure the sampling parameters of the data transmission device. The sampling parameters include at least the sampling rate and / or the sampling period. The data acquisition configuration distribution module is used by the main control application to distribute the data acquisition configuration associated with this test session to the data processing device. The data acquisition configuration includes at least a list of channels participating in the data acquisition.

[0115] In this embodiment, the main control application and the data transmission device communicate via a bus device, and the instruction issuing module 501 can also be used for: The main control application sends a first trigger command to cause the target pin of the chip under test to synchronously switch to the corresponding digital signal level. The main control application sends a second trigger command to the data transmission device to start sampling and digitization processing according to the preset sampling frequency and sampling period; The main control application sends the acquisition configuration to the data processing device via the network. The acquisition configuration includes at least a list of pins that participate in the sampling, which is used for subsequent forwarding and aggregation.

[0116] In this embodiment of the application, the instruction issuing module 501 can also be used for: The data transmitting device samples and digitizes the analog voltage on the sampling channel that is electrically connected to the target pin to obtain digital signal sampling data, and temporarily stores the digital signal sampling data in the local cache; When sampling a full digital signal sequence for the same target pin, the data transmitting device sends the digital signal sampling data corresponding to the target pin to the data acquisition device via a high-speed transmission link after adding a CRC16 check value.

[0117] In this embodiment of the application, the digital signal data acquisition device 500 based on chip testing may further include: The monitoring module is used by the data acquisition device to monitor the CRC16 encoded digital signal sampling data stream from the data transmission device and perform integrity verification based on the corresponding CRC16 check value. The generation module is used to generate full digital signal sampling data when all data packets corresponding to the target pins related to this test session are complete, and then send them to the data processing device via a high-speed link. The instruction response module is used to temporarily store the full digital signal sampling data and the test results calculated based on the full digital signal sampling data in the data processing device until it responds to the test result acquisition instruction of the main control application and sends the test results to the main control application.

[0118] In this embodiment of the application, during the global triggering and sampling process of the digital signal data acquisition device 500 based on chip testing, the main control application sends a result acquisition instruction at any time node, and the data processing device asynchronously returns serialized structured data associated with the test identifier. The structured data includes at least: the measured value of each target pin under each digital signal level and the pass and / or fail list. The master application generates waveforms and / or CSV documents for analysis and tracing based on structured data.

[0119] The digital signal data acquisition device 500 based on chip testing provided in this application embodiment can be applied to the digital signal data acquisition method based on chip testing provided in the foregoing embodiment. For details, please refer to the description of the digital signal data acquisition method based on chip testing provided in the above embodiment, which will not be repeated here.

[0120] See Figure 6 This diagram illustrates the structure of a semiconductor testing device provided in an embodiment of this application. Figure 6 As shown, the semiconductor testing equipment 600 of this embodiment includes: at least one processor 610 ( Figure 6Only one is shown in the diagram), memory 620, and computer program 621 stored in memory 620 and executable on at least one processor 610. When processor 610 executes computer program 621, it implements the steps in the above-described embodiments of the digital signal data acquisition method based on chip testing.

[0121] The semiconductor testing equipment 600 can be a server, physical server, or computing device, etc. This semiconductor testing equipment may include, but is not limited to, a processor 610 and a memory 620. Those skilled in the art will understand that... Figure 6 This is merely an example of semiconductor test equipment 600 and does not constitute a limitation on semiconductor test equipment 600. It may include more or fewer components than shown, or combine certain components, or use different components.

[0122] The processor 610 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0123] In some embodiments, the memory 620 may be an internal storage unit of the semiconductor testing equipment 600, such as a hard disk or memory of the semiconductor testing equipment 600. In other embodiments, the memory 620 may be an external storage device of the semiconductor testing equipment 600, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the semiconductor testing equipment 600. Furthermore, the memory 620 may include both internal and external storage units of the semiconductor testing equipment 600. The memory 620 is used to store operating systems, applications, bootloaders, data, and other programs, such as the program code of computer programs. The memory 620 can also be used to temporarily store data that has been output or will be output.

[0124] In specific implementations, the processor 610, memory 620, and computer program 621 described in the embodiments of this application can execute the embodiments of the digital signal data acquisition method based on chip testing of this application, which will not be repeated here.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0126] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0127] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0128] In the embodiments provided in this application, it should be understood that the disclosed apparatus / semiconductor testing equipment and methods can be implemented in other ways. For example, the apparatus / semiconductor testing equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0129] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0130] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0131] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0132] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device can implement the steps in the various method embodiments described above.

[0133] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A digital signal data acquisition method based on chip testing, applied to a digital signal data acquisition system based on chip testing, characterized in that, The digital signal data acquisition system includes a semiconductor testing machine and a data processing device; the semiconductor testing machine includes a main control application program and a data transmission device; the method includes: The main control application generates and issues global trigger instructions, which include at least: a first trigger instruction for the chip under test and a second trigger instruction for the data transmission device. The first trigger instruction is used to instruct the target pin of the chip under test to be driven in parallel based on a digital signal sequence. The second trigger instruction is used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence to obtain digital signal sampling data. The digital signal sampling data of the same test session are aggregated and sent to the data processing device. The data processing device performs parallel calculations on the received digital signal sampling data and caches the corresponding test results; In response to the test result retrieval instruction from the main control application, the data processing device asynchronously returns the test result.

2. The method as described in claim 1, characterized in that, The digital signal data acquisition system further includes a data acquisition device, and the second trigger command is also used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence, and send the obtained digital signal sampling data to the data acquisition device; The method further includes: The data acquisition device aggregates digital signal sampling data from the same test session and sends the aggregated digital signal sampling data to the data processing device.

3. The method as described in claim 2, characterized in that, The pins of the data transmitting device are connected one-to-one with the target pins of the chip under test; the method further includes: In response to the acquisition configuration command of the main control application, the data processing device parses the acquisition configuration in the acquisition configuration command, determines the list of pins participating in the sampling, and forwards it to the data acquisition device, so that the data acquisition device can determine whether the collection of digital signal sampling data is completed according to the pin list, and aggregate the digital signal sampling data if it is completed. In response to the acquisition command of the main control application, the data processing device acquires digital signal sampling data corresponding to the current test session from the data acquisition device, performs parallel calculations on the digital signal sampling data based on the specifications and trigger parameters of the chip under test, and caches the corresponding test results.

4. The method as described in claim 1, characterized in that, Before generating and issuing the global trigger command through the main control application, the process also includes: The main control application loads the specifications of the chip under test and presets the trigger parameters of the display interface. The trigger parameters include at least a target pin list and a digital signal sequence. Configure the sampling parameters of the data transmission device, wherein the sampling parameters include at least the sampling rate and / or the sampling period; The main control application sends the acquisition configuration associated with this test session to the data processing device. The acquisition configuration includes at least a list of channels participating in the acquisition.

5. The method as described in claim 2, characterized in that, The main control application communicates with the data transmission device via a bus device. The generation and issuance of global trigger commands by the main control application includes: The first trigger command is issued by the main control application to cause the target pin of the chip under test to synchronously switch to the corresponding digital signal level. The main control application sends the second trigger command to the data transmission device to start sampling and digitization processing according to the preset sampling frequency and sampling period; The main control application sends the acquisition configuration to the data processing device via the network. The acquisition configuration includes at least a list of pins participating in the sampling, which is used for subsequent forwarding and aggregation.

6. The method as described in claim 5, characterized in that, After the first trigger command and the second trigger command are issued, the method further includes: The data transmitting device samples and digitizes the analog voltage on the sampling channel that is electrically connected to the target pin to obtain digital signal sampling data, and temporarily stores the digital signal sampling data in a local cache. When sampling a full digital signal sequence for the same target pin, the data transmitting device sends the digital signal sampling data corresponding to the target pin to the data acquisition device via a high-speed transmission link after adding a CRC16 check value.

7. The method as described in claim 6, characterized in that, The method further includes: The data acquisition device listens to the CRC16 encoded digital signal sampling data stream from the data transmission device and performs integrity verification based on the corresponding CRC16 check value; When all data packets corresponding to the target pins related to this test session are complete, full digital signal sampling data is generated and sent to the data processing device via a high-speed link; The full set of digital signal sampling data and the test results calculated based on the full set of digital signal sampling data are temporarily stored in the data processing device until the test results are sent to the main control application in response to the test result acquisition instruction of the main control application.

8. The method according to any one of claims 1 to 7, characterized in that, During the global triggering and sampling process, the main control application issues a result acquisition instruction at any time node, and the data processing device asynchronously returns serialized structured data associated with the test identifier. The structured data includes at least: the measured values ​​of each target pin under each digital signal level and a pass and / or fail list. The main control application generates waveforms and / or CSV documents for analysis and tracing based on the structured data.

9. A digital signal data acquisition system based on chip testing, characterized in that, The digital signal data acquisition system includes a semiconductor testing machine and a data processing device. The semiconductor testing machine includes a main control application program and a data transmission device. The main control application is used to generate and issue global trigger instructions. The global trigger instructions include at least: a first trigger instruction for the chip under test and a second trigger instruction for the data transmission device. The first trigger instruction is used to instruct the target pin of the chip under test to be driven in parallel based on a digital signal sequence. The second trigger instruction is used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence to obtain digital signal sampling data. The digital signal sampling data of the same test session is aggregated and sent to the data processing device. The data transmitting device is used to receive the second trigger instruction from the main control application, sample and digitize the electrical signal of the target pin under the digital signal sequence to obtain digital signal sampling data, and aggregate the digital signal sampling data of the same test session and send it to the data processing device. The data processing device is used to perform parallel calculations on the received digital signal sampling data and cache the corresponding test results; in response to the test result acquisition instruction of the main control application, the data processing device asynchronously returns the test results.

10. The digital signal data acquisition system as described in claim 9, characterized in that, The digital signal data acquisition system further includes a data acquisition device, and the second trigger command is also used to instruct the data transmission device to sample and digitize the electrical signal of the target pin under the digital signal sequence, and send the obtained digital signal sampling data to the data acquisition device; The data acquisition device is used to aggregate digital signal sampling data from the same test session and send the aggregated digital signal sampling data to the data processing device.

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