Dynamic compensation system and method for constant-temperature crystal oscillator timekeeping system
By using a hardware system composed of FPGA and satellite timing module, combined with dynamic compensation and reverse compensation coefficients, the problems of complex temperature-controlled crystal oscillator compensation circuit and long discipline time are solved, and rapid discipline and long-term high-precision timekeeping are achieved.
Patent Information
- Application Number
- CN202511093066.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-06
- Publication Date
- 2025-12-19
AI Technical Summary
Existing temperature-controlled crystal oscillator compensation circuits are complex, costly, and require a long training time, which cannot meet the needs of rapid training and long-term high-precision timekeeping.
The hardware module, consisting of an FPGA, a satellite timing module, and a temperature-controlled crystal oscillator, achieves rapid taming of the temperature-controlled crystal oscillator and long-term high-precision timekeeping through a combination of difference calculation, dynamic compensation, and reverse compensation coefficients.
It enables rapid completion of timekeeping training for the temperature-controlled crystal oscillator, meeting the high-precision and rapid timekeeping requirements after the satellite timekeeping module loses lock, reducing training time and hardware costs, and improving time resolution and timekeeping accuracy.
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Figure CN121173263A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of time synchronization technology, and specifically relates to a dynamic compensation system and method for a temperature-controlled crystal oscillator timekeeping system. Background Technology
[0002] High-precision timekeeping systems typically consist of temperature-compensated crystal oscillators (TCXOs), oven-controlled crystal oscillators (OCXOs), chip atomic clocks, and disciplined clocks. Crystal oscillators are susceptible to aging and environmental temperature fluctuations, causing their output frequency to drift, making them unsuitable for direct application in high-precision synchronization. Chip atomic clocks and disciplined clocks are expensive, consume a lot of power, and have long discipline times. Temperature-compensated crystal oscillators have significant temperature drift and insufficient accuracy. Precision oven-controlled crystal oscillators, on the other hand, are small in size, have low temperature drift, and moderate power consumption, allowing them to be embedded in systems requiring timekeeping. However, they still suffer from time deviation issues due to the decay of the oven-controlled crystal over time.
[0003] Common methods for temperature-controlled crystal oscillator (TCXO) compensation typically consist of components such as a voltage-controlled temperature-controlled crystal oscillator (VOCXO), a phase detector, a loop filter or filtering algorithm, a regulator (often based on a PI controller), a DAC, and a satellite timing module. The advantage of this approach is that it can achieve high-stability frequency output while maintaining timekeeping. The disadvantages are that the circuit is complex, requiring a high-precision DAC, a high-power power supply, and control circuitry, resulting in high cost, large size, and a long training time. It cannot meet the requirements for rapid training and long-term high-precision timekeeping. Summary of the Invention
[0004] The purpose of this invention is to provide a dynamic compensation system and method for a thermostatic crystal oscillator timekeeping system, which solves the technical problems of existing thermostatic crystal oscillator compensation circuits being complex, costly, bulky, and requiring a long training time.
[0005] This invention is achieved using the following technical solution: A dynamic compensation system for a temperature-controlled crystal oscillator timekeeping system includes a hardware module; The hardware module includes an FPGA, a satellite timing module, and a temperature-controlled crystal oscillator. The FPGA internally includes a clock management module, a main control module, an interpolation calculation module, and a message parsing module; The main control module includes a delay module, a set duration counting module, a division operation module, and a timekeeping module; The timekeeping module includes a second counter, a DPPS generator, a compensation module, a dynamic compensation coefficient ROM, and a reverse compensation coefficient ROM. The satellite timing module has time message and PPS output functions. The temperature-controlled crystal oscillator is used to provide a highly stable clock signal. The satellite timing module transmits the time message to the message parsing module, transmits the PPS output of the satellite timing module to the main control module, and transmits the highly stable clock signal of the temperature-controlled crystal oscillator to the clock management module. The clock management module multiplies the clock signal and then transmits it to the main control module. The main control module obtains the reverse compensation coefficient through the difference calculation module and stores it in the reverse compensation coefficient ROM. The main control module generates the dynamic compensation coefficient according to the set duration counting module and stores it in the dynamic compensation coefficient ROM. The satellite timing module transmits the second pulse (PPS) signal to the delay module. After the delay module finishes counting, the processed signal is transmitted to the timekeeping module through the set duration counting module and the division operation module. The timekeeping module retrieves the dynamic compensation coefficient and the reverse compensation coefficient through the compensation module to compensate the DPPS generated by the DPPS generator and obtain the compensated DPPS.
[0006] A dynamic compensation method for a thermostatic crystal oscillator timekeeping system, implemented through the aforementioned dynamic compensation system for a thermostatic crystal oscillator timekeeping system, includes the following steps; Step 1: Test the time decay characteristics of the thermostatic crystal oscillator after power-on and store the test data in the reverse compensation coefficient ROM. This test data can reflect the decay characteristics of the thermostatic crystal oscillator as time changes. Step 2: The FPGA uses the clock management module to multiply the clock output of the thermostatic crystal oscillator to generate a high-frequency system operating clock signal, thereby improving the time resolution. Step 3: The satellite timing module outputs a second pulse (PPS) and a message with time information for time synchronization. Step 4: The FPGA uses the pulse-per-second (PPS) to perform delay counting, waiting for the thermostatic crystal oscillator to enter a stable working state; Step 5: After the delay ends, the high-frequency system operating clock is incremented within the set duration. Step 6: After the set duration ends, the accumulated count value is divided by the division operation module. The divisor is the set duration, the quotient is the output count reference value of the disciplined second pulse DPPS, and the remainder is the total time deviation value within the set duration. The division operation module transmits the calculation result signal to the timekeeping module. Step 7: The tamed second pulse DPPS compensates for the time deviation value according to the set duration. Based on the periodic dynamic deviation compensation, the compensation module queries the data of the inverse compensation coefficient ROM of the isothermal crystal oscillator attenuation characteristic according to the time change to perform inverse compensation, thereby ensuring the timekeeping accuracy over a long period of time. Step 8: After the timekeeping system outputs the disciplined second pulse DPPS, it enters the timekeeping phase. The satellite time synchronization module will not affect the operation of the timekeeping system after losing lock. The timekeeping system will automatically update the time information according to the disciplined second pulse DPPS and output the time information in the set format through the serial port.
[0007] In a further preferred embodiment, the isothermal crystal oscillator dynamic compensation coefficient is generated according to a set duration and stored in the dynamic compensation coefficient ROM. The timekeeping system cyclically calls the compensation coefficient every second according to the set duration for dynamic compensation. The compensation coefficient is evenly distributed within the set duration period to avoid the accumulation of time deviation.
[0008] More preferably, the method for obtaining the reverse compensation coefficient of the isothermal crystal oscillator decaying over time is to calculate the time difference between the second pulse PPS output by the satellite timing module and the uncompensated disciplined second pulse DPPS in real time by the difference calculation module inside the FPGA in chronological order, and store the increment of the time difference before and after in chronological order into the reverse compensation coefficient ROM.
[0009] More preferably, the delay counting duration depends on the steady-state operating characteristics of the isothermal crystal oscillator.
[0010] In a further preferred embodiment, step one also includes testing the temperature-controlled crystal oscillator to enter a stable working state.
[0011] A further preferred option is to set the duration to an integer power of 2.
[0012] A further optimized setting is a duration of 256 seconds.
[0013] In a further preferred embodiment, the position of the evenly distributed dynamic compensation coefficient ROM is found by querying the remainder. The DPPS periodically outputs a second pulse according to the output count reference value. At the same time, the dynamic deviation coefficient is polled and set every second within a set time period for compensation. If it is 0, it remains unchanged. If it is 1, an additional count pulse is added, thereby reducing the dynamic deviation of the DPPS every second.
[0014] This invention enables rapid timekeeping training of a temperature-controlled crystal oscillator (TCS), meeting the high-precision, rapid timekeeping requirements after a satellite timing module loses lock. The invention utilizes the FPGA and the satellite timing module's pulse-per-second (PPS) to accumulate and count the output pulses of the TCS. Then, a second-level division operation is performed on the count value after a set duration is completed. The quotient corresponds to the trained PPS count value, and the remainder is periodically and evenly distributed to the PPS counter through a dynamic compensation coefficient. This effectively reduces the dynamic deviation of the PPS output after training. Simultaneously, long-term reverse compensation is performed on the attenuation characteristics of the TCS, achieving long-term timekeeping accuracy. This method reduces the training time of the TCS, enabling rapid, long-term, high-precision timekeeping applications. The timekeeping control program can be embedded into the hardware system, saving space and hardware costs.
[0015] This invention utilizes an FPGA clock management module to multiply the frequency of a high-frequency operating clock, and then improves time resolution by increasing the counting duration. The counting result over a set duration is divided to generate a docile DPPS count value and the total time deviation within the set duration period. This deviation is then evenly distributed to the DPPS count value according to the set duration period via a dynamic compensation coefficient ROM for compensation, effectively improving the time accuracy of the docile second pulse DPPS. Addressing the time decay characteristics of the temperature-controlled crystal oscillator, a difference calculation module between the PPS and DPPS output from the satellite timing module records the decay characteristic parameters and stores them in a reverse compensation coefficient ROM. The DPPS count value is further inversely compensated using a time decay coefficient on top of the dynamic deviation compensation, enabling long-term, high-precision timekeeping second pulse DPPS signal output. During the timekeeping phase, the DPPS can further update and output time information without being affected by a loss of lock in the satellite timing module. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This diagram illustrates the hardware system composition of Embodiment 1 of the present invention.
[0019] Figure 2 This is a flowchart illustrating the workflow of Embodiment 2 of the present invention.
[0020] Figure 3 This refers to the remainder compensation uniform distribution method of Embodiment 4 of the present invention.
[0021] Figure 4 This is a comparison diagram showing the compensation process before and after in Embodiment 5 of the present invention. Detailed Implementation
[0022] To better understand the above-mentioned objectives, features, and advantages of the present invention, the solutions of the present invention will be further described below. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.
[0023] In this description, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. It should also be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joint" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.
[0024] Many specific details are set forth in the following description in order to provide a full understanding of the invention, but the invention may also be practiced in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of the invention, and not all embodiments.
[0025] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0026] Example 1: A dynamic compensation system for a temperature-controlled crystal oscillator timekeeping system, comprising a hardware module; The hardware module includes an FPGA, a satellite timing module, and a temperature-controlled crystal oscillator; The FPGA internally includes a clock management module, a main control module, an interpolation calculation module, a message parsing module, and a discipline time update module; Message parsing module: The FPGA obtains the time message from the satellite timing module through the serial port and parses it into the specified format of year, month, day, hour, minute, and second time information.
[0027] Clock management module: used to multiply the output clock of the thermostatic crystal oscillator to generate a high-frequency system operating frequency, thereby improving time resolution and reducing counting errors in the timekeeping system.
[0028] The main control module includes a delay module, a set duration counter module, a division operation module, and a timekeeping module; Delay module: Used to wait for the thermostatic crystal oscillator to enter a steady-state working state, so that the thermostatic crystal oscillator is in a relatively stable initial working state.
[0029] The duration counting module is used to accumulate counts for N seconds after the clock frequency is multiplied. By increasing the counting duration, the requirement for the high-frequency clock operating frequency is reduced. Under a fixed clock frequency, the time counting error can be reduced by extending the counting duration (i.e., accumulating counts for more clock cycles), thereby improving the output time accuracy of the disciplined second pulse DPPS.
[0030] The division module is used to calculate the total time deviation between the DPPS output count reference value and the set duration by accumulating the count value over a set duration of N seconds. The quotient is the DPPS count reference value, and the remainder is the total time deviation value within the set duration period. The timekeeping module includes a second counter, a DPPS generator, a compensation module, a dynamic compensation coefficient ROM, and a reverse compensation coefficient ROM; Dynamic compensation coefficient ROM: The coefficients stored in the constant temperature crystal oscillator dynamic compensation are pre-calculated and stored in the dynamic compensation coefficient ROM based on the possible time deviations within the N-second set duration period (i.e., all remainders generated by division operations based on the set duration period).
[0031] Reverse compensation coefficient ROM: Used to store the time-dependent decay characteristic parameters of the isothermal crystal oscillator output by the difference calculation module, and is used by the timekeeping system to perform reverse compensation on the long-term decay characteristics of the isothermal crystal oscillator.
[0032] The compensation module includes invoking a dynamic compensation coefficient to evenly distribute the compensation amount according to a set duration, effectively reducing the short-term dynamic time deviation of the disciplined second pulse output; simultaneously, it invokes a reverse compensation coefficient to correct the long-term time decay characteristics of the temperature-controlled crystal oscillator, ensuring that the timekeeping system maintains high accuracy over a longer period. The two compensation methods work together to stabilize the short-term dynamic performance of the second pulse while guaranteeing the long-term accuracy of the timekeeping system.
[0033] The satellite timing module has time message and PPS output functions. The temperature-controlled crystal oscillator is used to provide a highly stable clock signal. The satellite timing module transmits the time message to the message parsing module, transmits the PPS output of the satellite timing module to the main control module, and transmits the highly stable clock signal of the temperature-controlled crystal oscillator to the clock management module. The clock management module multiplies the clock signal before transmitting it to the main control module; The main control module obtains the attenuation characteristic compensation value of the constant temperature crystal oscillator over time through the difference calculation module and stores it in the reverse compensation coefficient ROM. The dynamic compensation coefficient is designed in advance according to the set duration and stored in the dynamic compensation coefficient ROM. The satellite time synchronization module transmits the second pulse (PPS) signal to the delay module. After the delay module finishes counting, the signal is transmitted to the timekeeping module through the set duration counting module and the division operation module. The timekeeping module ensures long-term timekeeping accuracy by reading the reverse compensation coefficient and performing reverse compensation, and achieves short-term high-precision timekeeping by reading the dynamic compensation coefficient generated in advance and stored in the dynamic compensation coefficient ROM. That is, the timekeeping module obtains the compensated DPPS after simultaneously retrieving the dynamic compensation coefficient and the reverse compensation coefficient through the compensation module.
[0034] Example 2: A dynamic compensation method for a thermostatic crystal oscillator timekeeping system, implemented through the aforementioned dynamic compensation system for a thermostatic crystal oscillator timekeeping system, includes the following steps; Step 1: Test the time decay characteristics of the thermostatic crystal oscillator after power-on and store the test data in the reverse compensation coefficient ROM. This test data can reflect the decay characteristics of the thermostatic crystal oscillator as time changes. In application, the time decay characteristics of the output clock of the thermostatic crystal oscillator after power-on are tested. The compensation module can use the test data to reverse the decay characteristics of the thermostatic crystal oscillator as time changes, thereby achieving high-precision timekeeping over a long period of time.
[0035] Step 2: The FPGA uses the clock management module to multiply the clock output of the thermostatic crystal oscillator to generate a high-frequency system operating clock signal, thereby improving the time resolution. Step 3: The satellite timing module outputs a second pulse (PPS) and a message with time information for time synchronization. When in use, after receiving satellite signals, the satellite timing module generates a pulse-per-second (PPS) signal that can be used for time synchronization, and simultaneously outputs time message information. The FPGA's internal message parsing module then generates time information in a specified format (year, month, day, hour, minute, second).
[0036] Step 4: The FPGA uses the pulse-per-second (PPS) to perform delay counting, waiting for the thermostatic crystal oscillator to enter a stable working state; In application, the delay module enters the delay program after acquiring the PPS signal. The delay length depends on the steady-state working time of the thermostatic crystal oscillator after power-on, so as to ensure that the thermostatic crystal oscillator enters a relatively stable working state.
[0037] Step 5: After the delay ends, the high-frequency system clock is incremented within the set time. The delay count is determined by the steady-state working time parameter of the isothermal crystal oscillator and is set in advance in the timekeeping system. It should be noted that the steady-state operating time parameter of the thermostatic crystal oscillator can be found in the manual. For greater accuracy, this embodiment selects to obtain the parameter by testing with a frequency meter. After testing, the steady-state operating time of the thermostatic crystal oscillator used in this embodiment is 100s.
[0038] In application, after the delay module finishes its delay counting, it counts using the high-frequency system clock within a set duration of N (N represents the set duration) second pulses (PPS), thereby obtaining the accumulated count value of the high-frequency system clock within a time length of N seconds.
[0039] Specifically, in this embodiment, after the delay ends, a cumulative counting phase of N seconds is initiated. The set duration is typically selected as an integer multiple of the PPS period, preferably a power of 2 (e.g., 64 s, 128 s, 256 s, etc.). A longer duration results in higher dynamic compensation accuracy, but also a longer training time, requiring more storage space for the dynamic compensation coefficients. Therefore, the set duration must be selected based on the timekeeping system's comprehensive requirements for both timekeeping accuracy and resource utilization. In this embodiment, the set duration is 256 seconds.
[0040] It should be noted that in subsequent steps, this accumulated count value is used to generate the count reference value for the tamed second pulse DPPS. The purpose is to improve the timekeeping accuracy of the tamed DPPS. The larger the set time length N, the smaller the average time error on the single tamed second pulse DPPS output, and the higher the timekeeping accuracy. However, the required dynamic compensation coefficient ROM is also larger.
[0041] Step 6: After the set duration ends, the division operation module performs a division operation on the accumulated count value. The divisor is the set duration, the quotient is the output count reference value of the disciplined second pulse DPPS, and the remainder is the total time deviation value within the set duration. The division operation module transmits the processed signal to the timekeeping module.
[0042] In application, after the high-frequency system clock accumulated count for N PPS set durations is completed, the FPGA uses the division operation module to perform a division operation on the high-frequency system clock accumulated count value for the N second pulse PPS time length. The divisor is the number of second pulse PPS within the set duration, N. The quotient is used as the output count reference value of the disciplined second pulse DPPS in the timekeeping module. The remainder is the total time deviation value within N seconds.
[0043] In other words, after the N-second set duration of cumulative counting is completed, the division operation module performs the operation with N as the divisor. The quotient is the DPPS count reference value of the disciplined second pulse, and the remainder is the total time deviation within the set duration. The compensation module periodically reads the compensation coefficient in the dynamic compensation coefficient ROM at second intervals according to the set duration to perform compensation, thereby realizing high-precision dynamic compensation of DPPS output time.
[0044] Step 7: The tamed second pulse DPPS compensates for the time deviation value according to the set duration. Based on the periodic dynamic deviation compensation, the compensation module queries the data of the inverse compensation coefficient ROM of the isothermal crystal oscillator attenuation characteristic according to the time change to perform inverse compensation, thereby ensuring the timekeeping accuracy over a long period of time.
[0045] When in use, after the division operation of the accumulated count value for the set duration is completed, the rising edge of the next PPS begins to discipline the second pulse DPPS and output it synchronously through the DPPS generator. At the same time, the dynamic compensation coefficient and the reverse compensation coefficient are read in each second pulse cycle to ensure the timekeeping accuracy over a long period of time. The disciplined time information is also automatically updated every second. The satellite time synchronization module will no longer participate in the time information update after this.
[0046] To improve the accuracy of dynamic compensation, the time deviation value of N seconds needs to be evenly distributed in chronological order throughout the entire set duration period. The specific distribution value can be queried in the dynamic compensation coefficient memory ROM through the remainder. The disciplined second pulse DPPS periodically outputs second pulses according to the counting reference value. At the same time, within the N-second set duration period, the dynamic deviation compensation value is polled second by second for compensation. If the compensation value is 0, it remains unchanged; if it is 1, an additional counting pulse is added, thereby reducing the dynamic deviation of DPPS every second. Since the remainder is caused by integer division, the dynamic compensation within a set duration period can only eliminate the time deviation caused by the remainder within a set duration period. Therefore, dynamic compensation is required within each set duration period.
[0047] Step 8: After the timekeeping system outputs the disciplined second pulse DPPS, it enters the timekeeping phase. The satellite time synchronization module will not affect the operation of the timekeeping system after losing lock. The timekeeping system will automatically update the time information according to the disciplined second pulse DPPS and output the time information in the set format through the serial port.
[0048] The FPGA includes a discipline time update module. In application, after the N-second timekeeping discipline is completed (i.e. after the division operation module calculates), the LOCK signal generated and the disciplined second pulse DPPS output by the timekeeping system are used to discipline the time update module. The satellite time synchronization module will no longer participate in the work of the timekeeping system. The timekeeping system will automatically update the time information according to the disciplined second pulse DPPS and output the time information in the user-defined format through the serial port.
[0049] Example 3: The dynamic compensation coefficient of the isothermal crystal oscillator is generated according to the set duration and stored in the dynamic compensation coefficient ROM. The timekeeping system calls the compensation coefficient in a cycle of seconds according to the set duration to perform dynamic compensation. The compensation coefficient is evenly distributed within the set duration period to avoid the accumulation of time deviation.
[0050] In application, the dynamic compensation coefficient of the constant temperature crystal oscillator needs to be generated in advance according to the N-second set duration and stored in the dynamic compensation coefficient ROM. The timekeeping system periodically calls the dynamic compensation coefficient for dynamic compensation according to the N-second set duration. The dynamic compensation coefficient needs to be evenly distributed within the set duration to improve the dynamic compensation accuracy.
[0051] The dynamic compensation coefficient of the temperature-controlled crystal oscillator is pre-calculated and stored in the dynamic compensation coefficient ROM based on all possible time deviations within a set duration of N seconds (i.e., all remainders generated by dividing the accumulated count value according to the set duration). During system operation, the corresponding dynamic compensation coefficient is called according to the remainder output by the division module, and the compensation value is evenly distributed per second within the N-second duration.
[0052] In implementation, taking a set duration N=256 seconds as an example, the divisor in the division operation is 256, and the remainder compensation range is 0-255 clock cycles, totaling 256 possible compensation coefficients. One remainder compensation requires 256 bits, corresponding to a 256-second cycle, which is 32 bytes of storage space. The 256 remainder combinations require 8192 bytes of storage space, as shown in the following example: (1) If the remainder after division is 1, then the compensation value within 256 seconds is the count value of one clock cycle. Therefore, the 256-second duration corresponds to 256 bits, with one 1 and 255 0s. The 128th bit is selected as 1, with 127 0s before and 128 0s after it. The compensation coefficient is represented according to the byte storage order as follows: “00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,01,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,”; (2) If the remainder is 2, then the compensation value within 256 seconds is the count value of 2 clock cycles. Therefore, a duration of 256 seconds corresponds to 256 positions, with 2 1s and 254 0s. To ensure the 1s are relatively evenly distributed across the 256 positions, a 1 is placed in the 128th (middle) position and a 1 is placed in the 256th (last) position. The compensation coefficient is represented according to the storage order of the bytes as follows: “00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,01,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,01,”; (3) If the remainder is 3, then the compensation value within 256 seconds is the count value of 3 clock cycles. Therefore, a duration of 256 seconds corresponds to 256 positions, with 3 1s and 253 0s. To ensure the 1s are relatively evenly distributed among the 0s, a 1 is placed at position 79, a 1 at position 159, and a 1 at position 256. The compensation coefficient is represented by the byte-corresponding storage order as follows: 00,00,00,00,00,00,00,00,00,01,00,00,00,00,00,00,00,00,00,01,00,00,00,00,00,00,00,00,00,00,00,00,01,”; By uniformly distributing the dynamic compensation coefficient positions as described above, the time deviation of the output second pulse DPPS within the set duration period can be effectively reduced, and other remainder compensation values can be calculated in the same way.
[0053] Example 4: The method for obtaining the reverse compensation coefficient of the temperature-controlled crystal oscillator decaying over time is to use the difference calculation module inside the FPGA to calculate the time difference between the second pulse PPS output by the satellite timing module and the uncompensated disciplined second pulse DPPS in real time according to the time sequence, and store the increment of the time difference before and after into the reverse compensation coefficient ROM in the time sequence.
[0054] In application, the timekeeping system reads the reverse compensation coefficients in chronological order and adds them to the second counter during compensation calculation, thereby realizing reverse compensation of the time decay characteristics of the constant temperature crystal oscillator and achieving high-precision time output over a long period of time.
[0055] Example 5 Figure 4 The figure shows the comparison results before and after compensation of the dynamic compensation method of the isothermal crystal oscillator timekeeping system of the present invention. The figure shows the test results of a precision isothermal crystal oscillator with a temperature coefficient of ±5ppb under normal temperature for 24 hours. The red curve is the time decay characteristic of the isothermal crystal oscillator over 24 hours, with a maximum deviation of 25us. The black curve is the output time deviation of the second pulse DPPS after compensation and discipline, with a maximum deviation of less than 2us over 24 hours. The crystal oscillator frequency is 10MHz, the steady-state working time is about 100s, the set duration of the cumulative count is set to 256s, the count clock frequency after frequency multiplication is 100MHz, and the time from power-on to output PPS of the satellite time synchronization module is less than 32s. Therefore, the total discipline time of the precision isothermal crystal oscillator is less than 7 minutes (100s+256s+32s=388s), which can meet the application requirements of rapid discipline, high precision, and long-term timekeeping.
[0056] The present invention has the following advantages: by using dynamic compensation and reverse compensation with time decay characteristics, the time deviation of the output disciplined second pulse DPPS is reduced, achieving high-precision timekeeping for a long time, reducing the training time of the isothermal crystal oscillator, and meeting the application requirements of the timekeeping system for rapid discipline and high-precision timekeeping for a long time.
[0057] Dynamic compensation can only guarantee the initial counting accuracy, while reverse compensation can compensate for the attenuation characteristics of the temperature-controlled crystal oscillator, thus ensuring long-term timekeeping. As time changes, the output clock of the temperature-controlled crystal oscillator will exhibit attenuation characteristics on a daily, monthly, and yearly basis. The reverse compensation time is usually 24H~48H. When the system is powered on again, the timekeeping system will re-train and dynamically compensate for a short period of time, thus ensuring that the timekeeping system will not have a large accuracy deviation due to long-term disuse.
[0058] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the present invention. Although detailed descriptions have been provided with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments, and they should all be covered within the protection scope of the claims.
Claims
1. A dynamic compensation system for a temperature-controlled crystal oscillator timekeeping system, comprising a hardware module; The hardware module includes an FPGA, a satellite timing module, and a temperature-controlled crystal oscillator. The FPGA internally includes a clock management module, a main control module, an interpolation calculation module, and a message parsing module; The main control module includes a delay module, a set duration counting module, a division operation module, and a timekeeping module; The timekeeping module includes a second counter, a DPPS generator, a compensation module, a dynamic compensation coefficient ROM, and a reverse compensation coefficient ROM. The satellite timing module has time message and PPS output functions. The temperature-controlled crystal oscillator is used to provide a highly stable clock signal. The satellite timing module transmits the time message to the message parsing module, transmits the PPS output of the satellite timing module to the main control module, and transmits the highly stable clock signal of the temperature-controlled crystal oscillator to the clock management module. The clock management module multiplies the clock signal and then transmits it to the main control module. The main control module obtains the reverse compensation coefficient through the difference calculation module and stores it in the reverse compensation coefficient ROM. The dynamic compensation coefficient is designed according to the set duration and stored in the dynamic compensation coefficient ROM. The satellite time synchronization module transmits the second pulse (PPS) signal to the delay module. After the delay module finishes counting, the signal is transmitted to the timekeeping module through the set duration counting module and then through the division operation module. The timekeeping module retrieves the dynamic compensation coefficient and the reverse compensation coefficient through the compensation module to compensate the DPPS generated by the DPPS generator and obtain the compensated DPPS.
2. A dynamic compensation method for a temperature-controlled crystal oscillator timekeeping system, characterized in that: The dynamic compensation system for a timekeeping system of a constant-temperature crystal oscillator as described in claim 1 is implemented by the following steps; Step 1: Test the time decay characteristics of the thermostatic crystal oscillator after power-on and store the test data in the reverse compensation coefficient ROM. This test data can reflect the decay characteristics of the thermostatic crystal oscillator as time changes. Step 2: The FPGA uses the clock management module to multiply the clock output of the thermostatic crystal oscillator to generate a high-frequency system operating clock signal, thereby improving the time resolution. Step 3: The satellite timing module outputs a second pulse (PPS) and a message with time information for time synchronization. Step 4: The FPGA uses the pulse-per-second (PPS) to perform delay counting, waiting for the thermostatic crystal oscillator to enter a stable working state; Step 5: After the delay ends, the high-frequency system operating clock is incremented within the set duration. Step 6: After the set duration ends, the accumulated count value is divided by the division operation module. The divisor is the set duration, the quotient is the output count reference value of the disciplined second pulse DPPS, and the remainder is the total time deviation value within the set duration. The division operation module transmits the calculation result signal to the timekeeping module. Step 7: The tamed second pulse DPPS compensates for the time deviation value according to the set duration. Based on the periodic dynamic deviation compensation, the compensation module queries the data of the inverse compensation coefficient ROM of the isothermal crystal oscillator attenuation characteristic according to the time change to perform inverse compensation, thereby ensuring the timekeeping accuracy over a long period of time. Step 8: After the timekeeping system outputs the disciplined second pulse DPPS, it enters the timekeeping phase. The satellite time synchronization module will not affect the operation of the timekeeping system after losing lock. The timekeeping system will automatically update the time information according to the disciplined second pulse DPPS and output the time information in the set format through the serial port.
3. The dynamic compensation method for a time-keeping system of a thermostatic crystal oscillator according to claim 2, characterized in that: The constant temperature crystal oscillator dynamic compensation coefficient is generated according to the set duration and stored in the dynamic compensation coefficient ROM. The timekeeping system calls the compensation coefficient in a cycle of seconds according to the set duration to perform dynamic compensation. The compensation coefficient is evenly distributed within the set duration period to avoid the accumulation of time deviation.
4. A dynamic compensation method for a time-keeping system of a thermostatic crystal oscillator according to claim 2, characterized in that: The method for obtaining the reverse compensation coefficient of the temperature-controlled crystal oscillator decaying over time is to calculate the time difference between the second pulse PPS output by the satellite timing module and the uncompensated disciplined second pulse DPPS in real time by the difference calculation module inside the FPGA in chronological order, and store the increment of the time difference before and after in chronological order into the reverse compensation coefficient ROM.
5. A dynamic compensation method for a time-keeping system of a thermostatic crystal oscillator according to claim 2, characterized in that: The delay counting duration depends on the steady-state operating characteristics of the isothermal crystal oscillator.
6. A dynamic compensation method for a time-keeping system of a thermostatic crystal oscillator according to claim 2, characterized in that: Step one also includes testing the temperature-controlled crystal oscillator to enter a stable working state.
7. A dynamic compensation method for a timekeeping system of a thermostatic crystal oscillator according to any one of claims 2-6, characterized in that: Set the duration to an integer power of 2.
8. A dynamic compensation method for a timekeeping system of a thermostatic crystal oscillator according to any one of claims 2-6, characterized in that: The duration is set to 256 seconds.
9. A dynamic compensation method for a timekeeping system of a thermostatic crystal oscillator according to any one of claims 2-6, characterized in that: The position of the evenly distributed dynamic compensation coefficient ROM is found by querying the remainder. The DPPS periodically outputs a second pulse according to the output count reference value. At the same time, the dynamic deviation coefficient is set by second within the set time period for compensation. If it is 0, it remains unchanged. If it is 1, an additional count pulse is added, thereby reducing the dynamic deviation of the DPPS every second.