Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor structure comprises a first stacked structure and a second stacked structure which are arranged in a stacked mode, and the first stacked structure comprises a first stacked structure and a plurality of supporting parts. The second stacked structure comprises a second stacked structure and a plurality of channel structures, the channel structures penetrate through the second stacked structure in the stacking direction, and one end of one channel structure is connected with one end of one supporting part. The second laminated structure comprises a first sub-laminated structure, a second sub-laminated structure and a first common-pole layer, and the first common-pole layer is arranged between the first sub-laminated structure and the second sub-laminated structure. The first connecting parts are arranged on the sides, away from the second stacking structures, of the first stacking structures, and one first connecting part penetrates through one supporting part in the stacking direction and extends into one channel structure. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor structure, a preparation method thereof, a storage system and an electronic device. BACKGROUND

[0002] As the feature size of memory storage units approaches the lower limit, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to improve storage density by arranging memory units three-dimensionally above a substrate. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, a storage system and an electronic device.

[0005] Embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, the present disclosure provides a semiconductor structure. The semiconductor structure comprises a stack structure, a plurality of first connection portions and a first bit line. The stack structure comprises a first stack structure and a second stack structure stacked in a stacking direction, the first stack structure comprises a first layer structure and a plurality of support portions. The support portions penetrate the first layer structure in the stacking direction, the first layer structure comprises two first dielectric layers and a support layer, and the support layer is arranged between the two first dielectric layers. The second stack structure comprises a second layer structure and a plurality of channel structures, the channel structures penetrate the second layer structure in the stacking direction, and one end of one channel structure is connected to one end of one support portion. The second layer structure comprises a first sub-layer structure, a second sub-layer structure and a first common electrode layer, the first sub-layer structure is arranged on one side of the first layer structure, the second sub-layer structure is arranged on a side of the first sub-layer structure away from the first layer structure, and the first common electrode layer is arranged between the first sub-layer structure and the second sub-layer structure. The first connection portions are arranged on a side of the first stack structure away from the second stack structure, and one first connection portion penetrates one support portion in the stacking direction and extends into one channel structure. The first bit line is arranged on a side of the first connection portions away from the first stack structure, the first bit line extends in a first direction, and the first bit line is connected to a column of first connection portions, wherein the first direction is perpendicular to the stacking direction.

[0007] In some embodiments, the channel structure includes a functional layer, a channel layer, and a support pillar. The functional layer and the channel layer encircle the support pillar, and the channel layer is between the functional layer and the support pillar. The first common electrode layer is connected to the functional layer, the channel layer, and the support pillar. The first connecting portion has an end connected to the functional layer, the channel layer, and the support pillar.

[0008] In some embodiments, the semiconductor structure further includes a plurality of second connecting portions and a second bit line. The second connecting portions are disposed on a side of the second stack structure away from the first stack structure, extend along the stacking direction, and have an end connected to the other end of a channel structure. The second bit line is disposed on a side of the second connecting portions away from the second stack structure, extends along the first direction, and is connected to a column of the second connecting portions.

[0009] In some embodiments, the channel structure includes a first channel structure, a second channel structure, and a third connecting portion. The first channel structure is disposed in the first sub-stack structure and extends through the first sub-stack structure along the stacking direction, has an end connected to the first connecting portion, and has the functional layer and the channel layer of the other end connected to the first common electrode layer. The second channel structure is disposed in the second sub-stack structure and extends through the second sub-stack structure along the stacking direction, has an end connected to the second connecting portion, and has the functional layer and the channel layer of the other end connected to the first common electrode layer. The third connecting portion is disposed in the first common electrode layer and extends through the first common electrode layer along the stacking direction, has an end connected to the support pillar of the first channel structure, and has the other end connected to the support pillar of the second channel structure.

[0010] In some embodiments, the first channel structure includes a first sub-channel structure and a second sub-channel structure, the second sub-channel structure is closer to the first common electrode layer than the first sub-channel structure, and a boundary of the support pillar of the second sub-channel structure close to the one end of the third connecting portion coincides with a boundary of the one end of the third connecting portion. The second channel structure includes a third sub-channel structure and a fourth sub-channel structure, the third sub-channel structure is closer to the first common electrode layer than the fourth sub-channel structure, and a boundary of the support pillar of the third sub-channel structure close to the one end of the third connecting portion coincides with a boundary of the other end of the third connecting portion.

[0011] In some embodiments, a boundary of the first sub-channel structure close to the one end of the second sub-channel structure is located outside a boundary of the second sub-channel structure close to the one end of the first sub-channel structure. A boundary of the third sub-channel structure close to the one end of the fourth sub-channel structure is located outside a boundary of the fourth sub-channel structure close to the one end of the third sub-channel structure.

[0012] In some embodiments, the first sub-stack structure includes a plurality of first gate layers and a plurality of second dielectric layers alternately stacked, and the second sub-stack structure includes a plurality of second gate layers and a plurality of third dielectric layers alternately stacked. The stack structure further includes: a third stack structure. The third stack structure includes a third sub-stack structure, a fourth sub-stack structure, a second common layer, and a connection structure. The third sub-stack structure is disposed on one side of the first stack structure along a second direction and is contiguous to the first stack structure and the first sub-stack structure. The fourth sub-stack structure is disposed on one side of the third sub-stack structure in a stacking direction and is contiguous to the second sub-stack structure. The second common layer is disposed between the third sub-stack structure and the fourth sub-stack structure and is contiguous to the first common layer. The connection structure penetrates the third sub-stack structure, the second common layer, and the fourth sub-stack structure along the stacking direction, and the connection structure connects one first gate layer and one second gate layer. The second direction is perpendicular to the stacking direction and the first direction.

[0013] In some embodiments, the connection structure includes: a connection column, a first connection layer, and a second connection layer. The connection column penetrates the third sub-stack structure, the second common layer, and the fourth sub-stack structure along the stacking direction. The first connection layer is disposed in the third sub-stack structure, the first connection layer extends along a direction perpendicular to the stacking direction, and the first connection layer is connected to one first gate layer. The second connection layer is disposed in the fourth sub-stack structure, the second connection layer extends along a direction perpendicular to the stacking direction, and the second connection layer is connected to one second gate layer.

[0014] In some embodiments, the semiconductor structure includes a first region and a second region, the first region is contiguous to the second region, the first stack structure and the second stack structure are located in the first region, and the third stack structure is located in the second region. The second region is located on one side of the first region in the second direction. Alternatively, the first region includes a first sub-region and a second sub-region, the first sub-region and the second sub-region are arranged along the second direction, and the second region is located between the first sub-region and the second sub-region.

[0015] In some embodiments, the semiconductor structure further includes: a gate trench. The gate trench extends along the second direction and penetrates the stack structure along the stacking direction, and the gate trench is connected to the first common layer. The second direction is perpendicular to the stacking direction and the first direction.

[0016] In some embodiments, the semiconductor structure further includes: an interconnection layer. The interconnection layer is disposed on one side of the second bit line away from the second stack structure, and the interconnection layer includes a circuit layer and a plurality of interconnection structures. The circuit layer is located between the interconnection structures and the second bit line. The interconnection structures include a first interconnection structure, a second interconnection structure, and a third interconnection structure. The first interconnection structure is connected to the second bit line through the circuit layer, the second interconnection structure is connected to the gate trench through the circuit layer, and the third interconnection structure is connected to the connection structure through the circuit layer.

[0017] In some embodiments, the semiconductor structure further includes: a transistor structure layer. The transistor structure layer is disposed at a side of the interconnection layer away from the second bit line, and the transistor structure layer includes a first transistor and a second transistor. A first electrode of the first transistor is connected to the second bit line via the interconnection layer, and a second electrode of the first transistor is connected to the gate isolation groove via the interconnection layer. A control electrode of the second transistor is connected to the connection structure via the interconnection layer.

[0018] In another aspect, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, the method comprising: forming a stack structure, the stack structure including a first stack structure and a second stack structure stacked together. The first stack structure includes a first laminated structure and a plurality of support portions, the support portions penetrating the first laminated structure along a stacking direction. The first laminated structure includes two first dielectric layers and a support layer, the support layer being disposed between the two first dielectric layers. The second stack structure includes a second laminated structure and a plurality of channel structures, the channel structures penetrating the second laminated structure along the stacking direction, and one end of one channel structure being connected to one end of one support portion. The second laminated structure includes a first sub-laminated structure, a second sub-laminated structure, and a first common electrode layer. The first sub-laminated structure is disposed at a side of the first laminated structure, the second sub-laminated structure is disposed at a side of the first sub-laminated structure away from the first laminated structure, and the first common electrode layer is disposed between the first sub-laminated structure and the second sub-laminated structure. A plurality of first connection portions are formed at a side of the first stack structure away from the second stack structure. One first connection portion penetrates one support portion along the stacking direction and extends into one channel structure. A first bit line is formed at a side of the first connection portion away from the first stack structure. The first bit line extends along a first direction, and the first bit line is connected to a column of the first connection portions. The first direction is perpendicular to the stacking direction.

[0019] In some embodiments, the forming the stack structure includes: forming a first initial stack structure, the first initial stack structure including a first initial layer stack structure and a plurality of support portions, the first initial layer stack structure including two first dielectric layers and a first sacrificial layer, the first sacrificial layer being disposed between the two first dielectric layers, the support portions penetrating the first initial layer stack structure along a stacking direction; forming a second initial stack structure on a side of the first initial stack structure, the second initial stack structure including a second initial layer stack structure and a plurality of first sacrificial columns, the second initial layer stack structure including a plurality of second dielectric layers and a plurality of second sacrificial layers alternately stacked, the first sacrificial columns penetrating the second initial layer stack structure along the stacking direction, and one end of one first sacrificial column being connected to one support portion; forming a third initial stack structure on a side of the second initial stack structure distal to the first initial stack structure, the third initial stack structure including a third sacrificial layer and a third initial layer stack structure stacked, and a plurality of second sacrificial columns, the third sacrificial layer being closer to the second initial stack structure than the third initial layer stack structure, the third initial layer stack structure including a plurality of third dielectric layers and a plurality of fourth sacrificial layers alternately stacked, the second sacrificial columns penetrating the third initial layer stack structure and the third sacrificial layer along the stacking direction, and one end of one second sacrificial column being connected to the other end of one first sacrificial column; removing the first sacrificial columns and the second sacrificial columns and forming channel structures; and replacing the first sacrificial layer with a support layer, the second sacrificial layer with a first gate layer, the third sacrificial layer with a first common layer, and the fourth sacrificial layer with a second gate layer to form the stack structure.

[0020] In some embodiments, before the replacing the first sacrificial layer with a support layer, the second sacrificial layer with a first gate layer, the third sacrificial layer with a first common layer, and the fourth sacrificial layer with a second gate layer, the method further includes forming a gate slit. The gate slit extends along a second direction, and the gate slit penetrates the stack structure along the stacking direction, wherein the second direction is perpendicular to the stacking direction and the first direction. The replacing the first sacrificial layer with a support layer, the second sacrificial layer with a first gate layer, the third sacrificial layer with a first common layer, and the fourth sacrificial layer with a second gate layer includes: removing the third sacrificial layer via the gate slit to form a first gap layer. The first common layer is formed in the first gap layer. The first sacrificial layer, the second sacrificial layer, and the fourth sacrificial layer are removed via the gate slit to form a second gap layer, a third gap layer, and a fourth gap layer. The support layer is formed in the second gap layer, the first gate layer is formed in the third gap layer, and the second gate layer is formed in the fourth gap layer.

[0021] In some embodiments, before the forming the first common layer in the first gap layer, the method further includes removing part of the channel structures via the first gap layer to form third connecting portions.

[0022] In some embodiments, the forming the stack structure comprises: forming a first initial stack structure, the first initial stack structure comprising a first initial layer stack structure and a plurality of support portions, the first initial layer stack structure comprising two first dielectric layers and a first sacrificial layer, the first sacrificial layer being disposed between the two first dielectric layers, the support portions penetrating the first initial layer stack structure along a stacking direction; forming a fourth initial stack structure on a side of the first initial stack structure, the fourth initial stack structure comprising a fourth initial layer stack structure and a plurality of third sacrificial columns, wherein the fourth initial layer stack structure comprises a plurality of fourth dielectric layers and a plurality of fifth sacrificial layers alternately stacked, the third sacrificial columns penetrating the fourth initial layer stack structure along the stacking direction, and one end of one third sacrificial column being connected to one support portion; forming a fifth initial stack structure on a side of the fourth initial stack structure distal to the first initial stack structure, the fifth initial stack structure comprising a fifth initial layer stack structure, a sixth sacrificial layer, a sixth initial layer stack structure, and a plurality of fourth sacrificial columns, wherein the fifth initial layer stack structure comprises a plurality of fifth dielectric layers and a plurality of seventh sacrificial layers alternately stacked, the sixth initial layer stack structure comprises a plurality of sixth dielectric layers and a plurality of eighth sacrificial layers alternately stacked, the fourth sacrificial columns penetrating the fifth initial layer stack structure, the sixth sacrificial layer, and the sixth initial layer stack structure along the stacking direction, and one end of one fourth sacrificial column being connected to the other end of one third sacrificial column; forming a sixth initial stack structure on a side of the fifth initial stack structure distal to the fourth initial stack structure, the sixth initial stack structure comprising a seventh initial layer stack structure and a plurality of fifth sacrificial columns, wherein the seventh initial layer stack structure comprises a plurality of seventh dielectric layers and a plurality of ninth sacrificial layers alternately stacked, the fifth sacrificial columns penetrating the seventh initial layer stack structure along the stacking direction, and one end of one fifth sacrificial column being connected to the other end of one fourth sacrificial column; removing the third sacrificial columns, the fourth sacrificial columns, and the fifth sacrificial columns, and forming a channel structure; replacing the first sacrificial layer with a support layer, replacing the fifth sacrificial layers and the seventh sacrificial layers with a first gate layer, replacing the sixth sacrificial layer with a first common layer, and replacing the eighth sacrificial layers and the ninth sacrificial layers with a second gate layer, to form the stack structure.

[0023] In some embodiments, before replacing the first sacrificial layer with the support layer, replacing the fifth sacrificial layer and the seventh sacrificial layer with the first gate layer, replacing the sixth sacrificial layer with the first common layer, and replacing the eighth sacrificial layer and the ninth sacrificial layer with the second gate layer, the method further comprises: forming a gate slit. The gate slit extends along a second direction, and the gate slit penetrates the stack structure along a stacking direction, wherein the second direction is perpendicular to the stacking direction and the first direction. Replacing the first sacrificial layer with the support layer, replacing the fifth sacrificial layer and the seventh sacrificial layer with the first gate layer, replacing the sixth sacrificial layer with the first common layer, and replacing the eighth sacrificial layer and the ninth sacrificial layer with the second gate layer comprises: removing the sixth sacrificial layer via the gate slit to form a fifth gap layer. The first common layer is formed in the fifth gap layer. The first sacrificial layer, the fifth sacrificial layer, the seventh sacrificial layer, the eighth sacrificial layer, and the ninth sacrificial layer are removed via the gate slit to form a sixth gap layer, a seventh gap layer, an eighth gap layer, a ninth gap layer, and a tenth gap layer. The support layer is formed in the sixth gap layer, the first gate layer is formed in the seventh gap layer and the eighth gap layer, and the second gate layer is formed in the ninth gap layer and the tenth gap layer.

[0024] In some embodiments, before forming the first common layer in the fifth gap layer, the method further comprises: removing part of the channel structure via the fifth gap layer to form a third connecting part.

[0025] In some embodiments, forming the plurality of first connecting parts on a side of the first stack structure away from the second stack structure comprises: forming a plurality of grooves, one groove penetrating one support part along the stacking direction and extending into one channel structure. The grooves expose the functional layer, the channel layer of the channel structure, and the support part. The first connecting parts are formed in the grooves.

[0026] In some embodiments, the method further comprises: forming a gate slot in the gate slit, the gate slot being connected to the first common layer.

[0027] In some embodiments, forming the first bit line on a side of the first connecting part away from the first stack structure comprises: forming a strip-shaped slot, the strip-shaped slot extending along the first direction and exposing a column of the first connecting parts. The first bit line is formed in the strip-shaped slot.

[0028] In another aspect, embodiments of the present disclosure provide a storage system, comprising: the semiconductor structure as described above and a controller. The controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0029] In another aspect, embodiments of the present disclosure provide an electronic device, comprising a mainboard and the storage system as described above disposed on the mainboard. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0031] Figure 1 The structural block diagram of an electronic device provided by some embodiments of the present disclosure is shown in FIG. 1.

[0032] Figure 2 The structural block diagram of a memory provided by some embodiments of the present disclosure is shown in FIG. 2.

[0033] Figure 3 The perspective structural schematic diagram of a memory provided by some embodiments of the present disclosure is shown in FIG. 3.

[0034] Figure 4 The structural schematic diagram of a memory provided by some embodiments of the present disclosure is shown in FIG. 4.

[0035] Figure 5 The structural schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 5.

[0036] Figure 6 The structural schematic diagram of another semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 6.

[0037] Figure 7 The structural schematic diagram of another semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 7.

[0038] Figure 8 The top view of a semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 8.

[0039] Figure 9 The top view of another semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 9. Figure 8 The splicing diagram of the cross sections of two positions AA' and BB' is shown in FIG. 10.

[0040] Figure 10 The top view of another semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 11.

[0041] Figure 11 The structural schematic diagram of another semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 12.

[0042] Figure 12 The flowchart of a preparation method of a semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 13.

[0043] Figure 13A flow chart of a preparation method of a stack structure provided for some embodiments of the present disclosure;

[0044] Figure 14 A structure diagram of a first initial stack structure corresponding to the preparation method of Figure 13 ;

[0045] Figure 15 A structure diagram of another first initial stack structure corresponding to the preparation method of Figure 13 ;

[0046] Figure 16 A structure diagram of a semiconductor structure corresponding to the preparation method of Figure 13 ;

[0047] Figure 17 A structure diagram of another semiconductor structure corresponding to the preparation method of Figure 13 ;

[0048] Figure 18 A structure diagram of yet another semiconductor structure corresponding to the preparation method of Figure 13 ;

[0049] Figure 19 A structure diagram of a semiconductor structure corresponding to a preparation procedure provided for some embodiments of the present disclosure;

[0050] Figure 20 A flow chart of a preparation method of a sacrificial layer replacement provided for some embodiments of the present disclosure;

[0051] Figure 21 A structure diagram of a semiconductor structure corresponding to the preparation method of Figure 20 ;

[0052] Figure 22 A structure diagram of a semiconductor structure corresponding to a preparation procedure provided for some embodiments of the present disclosure;

[0053] Figure 23 A flow chart of a preparation method of a first stack structure provided for some embodiments of the present disclosure;

[0054] Figure 24 A structure diagram of a semiconductor structure corresponding to the preparation method of Figure 23 ;

[0055] Figure 25 A structure diagram of another semiconductor structure corresponding to the preparation method of Figure 23 ;

[0056] Figure 26 A structure diagram of yet another semiconductor structure corresponding to the preparation method of Figure 23A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure;

[0057] Figure 27 A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure;

[0058] Figure 28 A flow chart of a preparation method of a first connection part provided by some embodiments of the present disclosure;

[0059] Figure 29 A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure; Figure 28

[0060] A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure; Figure 30

[0061] A flow chart of a preparation method of a first connection part provided by some embodiments of the present disclosure; Figure 31

[0062] A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure; Figure 32 Figure 31 A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure;

[0063] Figure 33 Figure 31 A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure;

[0064] Figure 34 A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure;

[0065] Figure 35 A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure;

[0066] Figure 36 A flow chart of a preparation process of a first bit line provided by some embodiments of the present disclosure;

[0067] Figure 37 A structure diagram of a semiconductor structure corresponding to the preparation method of the first stack structure. DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present disclosure. ​​

[0069] Unless the context clearly requires otherwise, throughout the description and the claims, the word "comprise," and variations such as "comprises" or "comprising," will be understood to mean the same as the word "include," and variations such as "includes" or "including." In describing some embodiments, the words "couple" and "connect" and variations thereof, are used. For example, the term "connected" can be used to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" can be used to indicate that two or more components are in either direct physical or electrical contact with each other, or that two or more components are not in direct contact with each other, but yet still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited in terms of the particular combinations of the hardware and software components, as such can depend on the specific implementation and requirements.

[0070] In the following description, the terms "first," "second," etc., are used only to describe various tenninates and do not imply a relative importance or a specific order of precedence. Thus, a feature defined with a "first" and a "second" can include one or more of either feature. In the description of embodiments of the disclosure, the meaning of "a," "an," and "the" includes two or more unless otherwise indicated.

[0071] In describing some embodiments, the expressions "coupled" and "connected" and variations thereof, can be used. For example, the term "connected" can be used to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" can be used to indicate that two or more components are in either direct physical or electrical contact with each other, or that two or more components are not in direct contact with each other, but yet still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited in terms of the particular combinations of the hardware and software components, as such can depend on the specific implementation and requirements.

[0072] Exemplary embodiments are described herein with reference to the drawings, which are in schematic form. In the drawings, the thickness of layers and regions can be exaggerated for clarity. Accordingly, variations to the shapes of the regions illustrated in the figures can occur. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0073] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0074] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0075] Figure 1 This is a structural block diagram of an electronic device 9000 provided in some embodiments of this disclosure. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0076] like Figure 1 As shown, the electronic device 9000 may include a storage system 910 and a host 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0077] The host 920 can include a processor of the electronic device 9000, for example, a central processing unit (CPU) or a system-on-chip (SoC) such as an application processor (AP). The host 920 can be configured to transmit or receive data to or from the memory.

[0078] In some embodiments, the storage system 910 can have one or more memories 911 and a controller 912. For example, the controller 912 can be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment, such as an SSD or eMMC used for data storage of mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Alternatively, in some examples, the controller 912 is coupled to the memory 911 and the host 920 and is configured to control data in the memory 911 while being able to communicate with an external device, such as a host.

[0079] The number of memories 911 in the storage system 910 can be one or more, Figure 1The diagram illustrates three memories 911 as an example. Controller 912 manages the data stored in each memory 911 and communicates with host 920. Controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. Controller 912 can also be configured to manage various functions related to data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, controller 912 is also configured to determine the maximum memory capacity usable by the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., host 920) according to specific communication protocols. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0080] Figure 2 This is a structural block diagram of a memory 911 provided in some embodiments of this disclosure. For example... Figure 2 As shown, memory 911 includes memory cell array 913 and peripheral circuitry 914 for controlling memory cell array 913. Peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0081] Exemplarily, the peripheral circuit 914 can use a complementary metal-oxide-semiconductor (CMOS) technology, for example, it can be implemented by using a logic process (e.g., a technology node of 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.).

[0082] The memory cell array 913 and the peripheral circuit 914 can be arranged side by side in the same plane, for example, on the same wafer, that is, the memory cell array 913 and the peripheral circuit 914 can be located in the same semiconductor structure. The memory cell array 913 and the peripheral circuit 914 can also be formed on different wafers and bonded together in a face-to-face manner. Figure 2 As shown, when the memory cell array 913 and the peripheral circuit 914 are formed on different wafers and bonded together in a face-to-face manner, the memory 911 can include a first semiconductor structure 901 and a second semiconductor structure 902, and a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902.

[0083] The first semiconductor structure 901 can include the memory cell array 913, and the second semiconductor structure 902 can include the peripheral circuit 914. A large number of interconnections (e.g., bonding contacts) are formed through the bonding interface 903, and direct short-distance (e.g., micron level) electrical connections can be made between the first semiconductor structure 901 and the second semiconductor structure 902, instead of long-distance (e.g., millimeter or centimeter level) chip-to-chip data buses on a circuit board (e.g., a printed circuit board (PCB)), thereby eliminating chip interface delays and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array in the first semiconductor structure 901 and the peripheral circuit in the second semiconductor structure 902 can be performed through the interconnections (e.g., bonding contacts) passing through the bonding interface 903. By vertically integrating the first semiconductor structure 901 and the second semiconductor structure 902, the chip size can be reduced, and the storage density of the memory 911 can be increased.

[0084] Figure 3 A perspective structural schematic diagram of a memory 911 provided by some embodiments of the present disclosure.

[0085] As Figure 3As shown, the memory 911 can include a stack structure 100, a source layer SL coupled with the stack structure 100, and a peripheral device coupled with the stack structure 100. The peripheral device can be disposed on a side of the stack structure 100 distal from the source layer SL.

[0086] The source layer SL can include a semiconductor material, such as monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL can be partially or entirely doped. Illustratively, the source layer SL can include a doped region doped with a p-type dopant. The source layer SL can also include an undoped region.

[0087] The stack structure 100 can include an array of strings of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings). The source layer SL can be coupled with source ends of the plurality of memory strings. As shown, each memory string can include a channel structure 122 and a plurality of gate lines G disposed around the channel structure 122. Figure 3

[0088] In some examples, along the stacking direction Z, a lowermost gate line (e.g., a gate line of the plurality of gate lines G closest to the source layer SL) can be configured as a source select gate SGS, an uppermost gate line (e.g., a gate line of the plurality of gate lines G farthest from the source layer SL) can be configured as a drain select gate SGD, and gate lines in between can be configured as a plurality of word lines WL, such as word line WL0, word line WL1, word line WL2, word line WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of individual memory cells (e.g., transistors T) in the memory strings can be accomplished.

[0089] Illustratively, by disposing gate line contacts G-CNT, an outlead of the gate lines G can be achieved, and in turn, writing of voltages on the gate lines G through the gate line contacts G-CNT can be achieved, to thereby achieve control of the memory strings within the stack structure 100. However, as the height of the stack structure 100 in the stacking direction Z increases, the distance between the memory strings and the source layer SL also gradually increases, thereby causing an increase in signal transmission loss of the memory strings, a decrease in current values within the memory strings, and even an impact on the electrical performance of the memory 911.

[0090] Figure 4 A structural schematic diagram of a memory 911 provided by some embodiments of the present disclosure.

[0091] ​In an embodiment, by arranging the source layer SL inside the stack structure 100, the stack structure 100 is divided into two sub-stack structures along the stacking direction Z by the source layer SL, and the source layer SL is used as the common source of the memory strings in the two sub-stack structures, thereby reducing the distance between the memory strings in the single-side sub-stack structure and the source layer SL, and further reducing the signal transmission loss of the memory strings in the single-side sub-stack structure.

[0092] In addition, by increasing the height of the single-side sub-stack structure along the stacking direction Z, the height of the overall stack structure 100 can be increased, thereby increasing the storage capacity of the memory 911 while ensuring the electrical performance of the memory 911.

[0093] However, the device structure of the memory 911 described above requires the first bit line 200 and the second bit line 300 to be respectively prepared on both sides of the stack structure 100 along the stacking direction Z. In the process of preparing the first bit line 200, the stack structure 100 lacks a support structure due to the removal of the substrate, so that the memory strings inside the stack structure 100 are prone to tilting or bending under the influence of process stress in the process of preparing the first bit line 200, thereby affecting the electrical performance of the memory 911.

[0094] Figure 5 A structural schematic diagram of a semiconductor structure 1000 provided by some embodiments of the present disclosure is shown in FIG. 1.

[0095] As shown in FIG. 1, the semiconductor structure 1000 includes a substrate 1000a, a stack structure 100, a first bit line 200, a second bit line 300, a memory 911, and a source layer SL. Figure 5As shown, in some embodiments, the semiconductor structure 1000 includes: a stack structure 100, a plurality of first connecting parts 500, and a first bit line 200. The stack structure 100 includes a first stack structure 110 and a second stack structure 120 which are stacked. The first stack structure 110 includes a first laminated structure 111 and a plurality of support parts 112 which penetrate through the first laminated structure 111 along a stacking direction Z, and the first laminated structure 111 includes two first dielectric layers 1111 and a support layer 1112 which is arranged between the two first dielectric layers 1111. The second stack structure 120 includes a second laminated structure 121 and a plurality of channel structures 122 which penetrate through the second laminated structure 121 along the stacking direction Z, and one end of one channel structure 122 is connected with one end of one support part 112. The second laminated structure 121 includes a first sub-laminated structure 123, a second sub-laminated structure 124, and a first common electrode layer 125, the first sub-laminated structure 123 is arranged at one side of the first laminated structure 111, the second sub-laminated structure 124 is arranged at one side of the first sub-laminated structure 123 away from the first laminated structure 111, and the first common electrode layer 125 is arranged between the first sub-laminated structure 123 and the second sub-laminated structure 124. The first connecting part 500 is arranged at one side of the first stack structure 110 away from the second stack structure 120, and one first connecting part 500 penetrates through one support part 112 along the stacking direction Z and extends into one channel structure 122. The first bit line 200 is arranged at one side of the first connecting part 500 away from the first stack structure 110, the first bit line 200 extends along a first direction Y, and the first bit line 200 is connected with a column of first connecting parts 500, wherein the first direction Y is perpendicular to the stacking direction Z.

[0096] wherein, Figure 5 are for illustrative purposes only and can not necessarily reflect actual device structures (e.g., interconnects).

[0097] In this embodiment, by arranging the first stack structure 110 at one side of the second stack structure 120, the support layer 1112 of the first laminated structure 111 can be used to provide support force for the second laminated structure 121 and the channel structures 122 inside it, so as to avoid the problem of bending or tilting of the channel structures 122 caused by stress during the preparation of the first bit line 200, thereby ensuring that the subsequently prepared first bit line 200 can be accurately aligned and connected with the channel structures 122, so as to improve the electrical connection effect of the semiconductor structure 1000, and further improve the electrical performance of the semiconductor structure 1000.

[0098] In addition, the first stack structure 111 is provided with a plurality of support portions 112. In this embodiment, the support portions 112 are used to form the channel structures 122, so that the depths of the channel structures 122 on the side close to the first bit line 200 are substantially the same. Therefore, before the first bit line 200 is formed, the process of polishing the back surface of the channel structures 122 with different depths can be omitted, so as to simplify the manufacturing process of the semiconductor structure 1000.

[0099] In addition, the first connection portion 500 can improve the electrical connection effect between the channel structure 122 and the first bit line 200, and further improve the electrical performance of the semiconductor structure.

[0100] In a possible implementation, the material of the first dielectric layer 1111 can include an insulating material. For example, the insulating material can include but is not limited to one or more of an oxide material (for example, silicon oxide), a nitride material (for example, silicon nitride), and an oxynitride material (for example, silicon oxynitride). The support portion 112 can include a semiconductor material. For example, the semiconductor material can be monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or another suitable semiconductor material. The support layer 1112 and the first connection portion 500 can include a conductive material. For example, the conductive material can include but is not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. In this embodiment, the material of the support layer 1112 is W, so as to improve the hardness of the support layer 1112 and improve the support performance of the support layer 1112.

[0101] For example, the thickness (i.e., the size along the stacking direction Z) of the support layer 1112 can be 40 nm to 300 nm, for example, 40 nm, 50 nm, 60 nm, 80 nm, 125 nm, 150 nm, 180 nm, 200 nm, 240 nm, 250 nm, or 300 nm.

[0102] Please continue to refer to Figure 5 In some embodiments, the channel structure 122 includes a functional layer 1221, a channel layer 1222, and a support column 1223. The functional layer 1221 and the channel layer 1222 surround the support column 1223, and the channel layer 1222 is located between the functional layer 1221 and the support column 1223. The first common electrode layer 125 is connected to the functional layer 1221, the channel layer 1222, and the support column 1223 of the channel structure 122. The end of the first connection portion 500 extending into the channel structure 122 is connected to the functional layer 1221, the channel layer 1222, and the support column 1223.

[0103] In the embodiment, the first common electrode layer 125 is connected with the channel layer 1222 of the channel structure 122, and can provide an electrical signal for the channel structure 122 in the first sub-laminate structure 123 and the second sub-laminate structure 124 on both sides of the first common electrode layer 125. In this way, the distance between the channel structure 122 in the first sub-laminate structure 123 and the second sub-laminate structure 124 and the first common electrode layer 125 is shortened, so as to reduce the loss of the channel structure 122 in signal transmission, and further improve the electrical performance of the whole semiconductor structure 1000.

[0104] In addition, by connecting one end of the first connecting part 500 with the functional layer 1221, the channel layer 1222 and the support column 1223, the electrical connection between the first connecting part 500 and the channel structure 122 can be realized, and further the electrical connection between the channel structure 122 and the first bit line 200 via the first connecting part 500 can be realized, so as to realize the control of the first bit line 200 on the data reading, writing or erasing operation of the channel structure 122 in the first sub-laminate structure 123.

[0105] In some examples, the functional layer 1221 can include a tunneling layer 1224, a charge trapping layer 1225 and a charge blocking layer 1226, wherein the charge trapping layer 1225 is arranged between the tunneling layer 1224 and the charge blocking layer 1226, and the charge blocking layer 1226 is farther away from the channel layer 1222 than the tunneling layer 1224.

[0106] Figure 6 Another structural schematic diagram of a semiconductor structure 1000 provided by some embodiments of the present disclosure is shown.

[0107] As shown in Figure 6 In some embodiments, the semiconductor structure 1000 further includes a plurality of second connecting parts 400 and a second bit line 300. The second connecting part 400 is arranged on the side of the second stack structure 120 away from the first stack structure 110, and the second connecting part 400 extends along the stacking direction Z, and one end of one second connecting part 400 is connected with the other end of one channel structure 122. The second bit line 300 is arranged on the side of the second connecting part 400 away from the second stack structure 120, and the second bit line 300 extends along the first direction Y, and the second bit line 300 is connected with a column of second connecting parts 400.

[0108] In the embodiment, the second bit line 300 is arranged on the side of the second stack structure 120 away from the first stack structure 110, so that the semiconductor structure 1000 is provided with bit lines on both sides in the stacking direction Z, and the corresponding channel structures 122 in the first sub-stack structure 123 and the second sub-stack structure 124 can be controlled by the bit lines (the first bit line 200 and the second bit line 300) on both sides, respectively. As a feasible implementation, the first bit line 200 can control the part of the channel structure 122 located in the first sub-stack structure 123, and the second bit line 300 can control the part of the channel structure 122 located in the second sub-stack structure 124.

[0109] In this way, the segmented control of one channel structure 122 can be realized, so as to shorten the distance between a single bit line (the first bit line 200 or the second bit line 300) and the part of the channel structure 122 controlled thereby, and further shorten the circuit length and reduce the circuit loss, so as to improve the current value in the channel structure 122, and further improve the electrical performance of the semiconductor structure 1000.

[0110] In addition, since the control of the channel structure 122 by the single-side bit line is limited by the height of the channel structure 122, in the embodiment, the first bit line 200 and the second bit line 300 are arranged on both sides of the semiconductor structure 1000, respectively, and the height of the channel structure 122 corresponding to each of the two bit lines can be increased, so as to increase the height of the entire channel structure 122, and further improve the storage capacity of the semiconductor structure 1000.

[0111] In the embodiment, the plurality of channel structures 122 can be arranged in multiple rows and multiple columns, the number of the first bit line 200 and the second bit line 300 can be one or more, and the plurality of first bit lines 200 and the second bit lines 300 can be arranged at intervals along the second direction X. One first bit line 200 and the second bit line 300 correspond to one column of channel structures 122, so as to realize the control of the data reading, writing or erasing operation of the channel structure 122. The second direction X is perpendicular to the stacking direction Z and the first direction Y.

[0112] In addition, the plurality of second connecting portions 400 can realize the via hole contact between the channel structure 122 and the second bit line 300. In this way, the electrical connection between the channel structure 122 and the second bit line 300 can be realized, and the precision of the butt joint between the channel structure 122 and the second bit line 300 can be improved, so as to improve the electrical effect of the connection between the channel structure 122 and the second bit line 300.

[0113] The second connection portion 400 can include a conductive material, for example, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The material of the second connection portion 400 can be the same as or different from the material of the first connection portion 500.

[0114] In some examples, the support portion 112, the first connection portion 500, and the second connection portion 400 can each include a through silicon contact (TSC), a through silicon via, or the like. In addition, the support portion 112, the first connection portion 500, and the second connection portion 400 can each have a columnar shape, for example, a circular columnar shape, a prismatic columnar shape, or the like. Correspondingly, the support portion 112, the first connection portion 500, and the second connection portion 400 can each have a circular, elliptical, rectangular, or the like cross-sectional shape in the first direction Z.

[0115] Please continue to refer to Figure 6 In some embodiments, the channel structure 122 includes a first channel structure 126, a second channel structure 127, and a third connection portion 128. The first channel structure 126 is disposed in the first sub-laminate structure 123 and extends through the first sub-laminate structure 123 along the stacking direction Z. One end of the first channel structure 126 is connected to the first connection portion 500, and the functional layer and the channel layer of the other end of the first channel structure 126 are both connected to the first common electrode layer 125. The second channel structure 127 is disposed in the second sub-laminate structure 124 and extends through the second sub-laminate structure 124 along the stacking direction Z. One end of the second channel structure 127 is connected to the second connection portion 400, and the functional layer and the channel layer of the other end of the second channel structure 127 are both connected to the first common electrode layer 125. The third connection portion 128 is disposed in the first common electrode layer 125 and extends through the first common electrode layer 125 along the stacking direction Z. One end of the third connection portion 128 is connected to the support column of the first channel structure 126, and the other end of the third connection portion 128 is connected to the support column of the second channel structure 127.

[0116] In some examples, the preparation of the channel structure 122 in the second laminate structure 121 can include a preparation process of etching a through hole in advance and then sequentially forming the functional layer 1221, the channel layer 1222, and the support column 1223 in the through hole. However, as the height of the second laminate structure 121 gradually increases, the etching process of the through hole also has higher requirements and challenges. Based on this, the present embodiment can use a multiple stacking technology to etch a through hole with a large height, so as to obtain a channel structure 122 with a large height, thereby improving the storage capacity of the semiconductor structure 1000. The specific preparation process of the multiple stacking technology will be introduced in the preparation method of the semiconductor structure 1000 later, and will not be described here.

[0117] In this embodiment, based on the preparation process of the above-mentioned multi-stacking technology, the number of the stack structures included in the second stack structure 120 can be 2, 3, 4, or any other number that meets the requirements of this embodiment. In the following, this embodiment takes the number of the stack structures as an example to introduce the semiconductor structure 1000, which is 2 (i.e., the first sub-stack structure 123 and the second sub-stack structure 124). Among them, for example, the first common electrode layer 125 in this embodiment can be located between two adjacent stack structures.

[0118] In combination with the existence of the first bit line 200 and the second bit line 300, part of the channel structures 122 (the first channel structure 126) in the first sub-stack structure 123 can be controlled by the first bit line 200 to realize the reading, writing or erasing of data, and part of the channel structures 122 (the second channel structure 127) in the second sub-stack structure 124 can be controlled by the second bit line 300 to realize the reading, writing or erasing of data.

[0119] Among them, as a feasible implementation manner, the first common electrode layer 125 can serve as the source layer of the first channel structure 126 and the second channel structure 127, thereby providing electrical signals for the operation of the channel layer 1222 of the first channel structure 126 in the first sub-stack structure 123 and the second channel structure 127 in the second sub-stack structure 124.

[0120] In the foregoing embodiments, the semiconductor structure 1000 is introduced by taking the example that the first common electrode layer 125 is located between two adjacent stack structures. In the following, the semiconductor structure 1000 is introduced by taking the example that the first common electrode layer 125 is located inside one stack structure (for example, arranged between two dielectric layers of one stack structure).

[0121] Among them, for example, the number of the stack structures in this embodiment is 3, and the first common electrode layer 125 is arranged in the target stack structure 130 located in the middle position among the three stack structures.

[0122] Figure 7 Another structure schematic diagram of the semiconductor structure 1000 provided by some embodiments of the present disclosure is provided.

[0123] As Figure 7As shown, in some embodiments, the first channel structure 126 includes a first sub-channel structure 1261 and a second sub-channel structure 1262, the second sub-channel structure 1262 is closer to the first common electrode layer 125 than the first sub-channel structure 1261, and the boundary of the support column of the second sub-channel structure 1262 close to one end of the third connecting part 128 coincides with the boundary of one end of the third connecting part 128. The second channel structure 127 includes a third sub-channel structure 1271 and a fourth sub-channel structure 1272, the third sub-channel structure 1271 is closer to the first common electrode layer 125 than the fourth sub-channel structure 1272, and the boundary of the support column of the third sub-channel structure 1271 close to one end of the third connecting part 128 coincides with the boundary of the other end of the third connecting part 128.

[0124] Since the first common electrode layer 125 is arranged in the target stack structure 130, the first common electrode layer 125 penetrates the functional layers of the channel structure 122 arranged in the target stack structure 130 and is connected with the channel layer, so as to separate the functional layers of the channel structure 122 in the target stack structure 130 by separating the channel structure 122 in the target stack structure 130 into the second sub-channel structure 1262, the third connecting part 128 and the third sub-channel structure 1271.

[0125] Among them, as a feasible implementation manner, the support columns of the second sub-channel structure 1262, the third connecting part 128 and the third sub-channel structure 1271 can be prepared by the same preparation process, so that, in structure, the two ends of the support column of the third connecting part 128 respectively coincide with the boundaries of the support columns of the second sub-channel structure 1262 and the third sub-channel structure 1271 and are an integral structure without obvious boundary.

[0126] In addition, before the channel structure 122 is prepared, a channel hole penetrating the stack structure needs to be prepared on each layer of the stack structure in advance, so as to provide space for the preparation of the channel structure 122. However, since the channel hole is mostly prepared by etching and other process flows, with the increase of the etching depth of the stack structure in the stacking direction Z, the width of the prepared channel hole will gradually decrease with the increase of the depth, and then lead to that, in the channel structure prepared based on the channel hole, the boundary of the second sub-channel structure 1262 close to one end of the third sub-channel structure 1271 is located inside the boundary of the third sub-channel structure 1271 close to one end of the second sub-channel structure 1262.

[0127] In addition, in the stacking direction Z, the channel structures 122 arranged in the two layer structures on both sides of the target layer structure 130 are respectively the first sub-channel structure 1261 and the fourth sub-channel structure 1272, so that the first sub-channel structure 1261 and the second sub-channel structure 1262 (i.e., the first channel structure 126) can be controlled by the first bit line 200 to read, write or erase data, and the third sub-channel structure 1271 and the fourth sub-channel structure 1272 (i.e., the second channel structure 127) can be controlled by the second bit line 300 to read, write or erase data.

[0128] In the embodiment, the first common electrode layer 125 is arranged in the target layer structure 130, so that the distances from the sub-channel structures on both sides of the first common electrode layer 125 to the first common electrode layer 125 are shortened, the signal loss in the sub-channel structures is reduced, the electrical connection effect between the sub-channel structures on both sides and the first common electrode layer 125 is improved, and the electrical performance of the semiconductor structure 1000 is improved.

[0129] In other examples, the first common electrode layer 125 can also be arranged in any one of the layer structures on both sides in the 3-layer stacked structure, and the embodiment of the present disclosure does not limit this.

[0130] In other examples, the number of layer structures on both sides of the target layer structure 130 in the stacking direction Z can be one or more, and the embodiment of the present disclosure does not limit this.

[0131] Please continue to refer to Figure 7 In some embodiments, the boundary of the first sub-channel structure 1261 at the end close to the second sub-channel structure 1262 is located outside the boundary of the second sub-channel structure 1262 at the end close to the first sub-channel structure 1261. The boundary of the third sub-channel structure 1271 at the end close to the fourth sub-channel structure 1272 is located outside the boundary of the fourth sub-channel structure 1272 at the end close to the third sub-channel structure 1271.

[0132] In the embodiment, based on the preparation process of the aforementioned multiple stacking technology, before the channel structure 122 is prepared, a channel hole penetrating through the layer structure needs to be prepared on each layer structure, thereby providing space for the preparation of the channel structure 122. However, since the channel hole is mostly prepared by etching and other process flows, as the etching depth of the layer structure in the stacking direction Z increases, the width of the prepared channel hole will gradually decrease with the increase of the depth, thereby causing the aperture at the end of the first sub-channel structure 1261 close to the second sub-channel structure 1262 to be smaller than the aperture at the end of the second sub-channel structure 1262 close to the first sub-channel structure 1261 in the channel structure prepared based on the channel hole.

[0133] Similarly, the aperture of the third sub-channel structure 1271 near one end of the fourth sub-channel structure 1272 is smaller than the aperture of the fourth sub-channel structure 1272 near one end of the third sub-channel structure 1271.

[0134] In this way, the accuracy of alignment between the channel holes of two adjacent stacked structures in the multi-stacking technology can be improved, so that the electrical connection effect between the channel structures 122 in the two adjacent stacked structures can be improved when the channel structures 122 are prepared based on the channel holes.

[0135] Figure 8 A top view of a semiconductor structure 1000 provided by some embodiments of the present disclosure, Figure 9 A top view of a semiconductor structure 1000 provided by some embodiments of the present disclosure, Figure 8 A splicing view of the cross sections at two positions AA' and BB'.

[0136] As shown in FIG. 1, in some embodiments, the first sub-stacked structure 123 includes a plurality of first gate layers 1231 and a plurality of second dielectric layers 1232 which are alternately stacked, and the second sub-stacked structure 124 includes a plurality of second gate layers 1241 and a plurality of third dielectric layers 1242 which are alternately stacked. Figure 8 In some embodiments, the first sub-stacked structure 123 includes a plurality of first gate layers 1231 and a plurality of second dielectric layers 1232 which are alternately stacked, and the second sub-stacked structure 124 includes a plurality of second gate layers 1241 and a plurality of third dielectric layers 1242 which are alternately stacked. Figure 9 As shown in FIG. 1, in some embodiments, the first sub-stacked structure 123 includes a plurality of first gate layers 1231 and a plurality of second dielectric layers 1232 which are alternately stacked, and the second sub-stacked structure 124 includes a plurality of second gate layers 1241 and a plurality of third dielectric layers 1242 which are alternately stacked.

[0137] In some embodiments, the first sub-stacked structure 123 includes a plurality of first gate layers 1231 and a plurality of second dielectric layers 1232 which are alternately stacked, and the second sub-stacked structure 124 includes a plurality of second gate layers 1241 and a plurality of third dielectric layers 1242 which are alternately stacked.

[0138] Please continue to refer to Figure 3In the background of users pursuing large-capacity and small-volume storage devices, in order to improve the capacity of the semiconductor structure 1000, the number of stacked layers of the gate line G is increasing. However, one gate line G is connected with one gate line contact G-CNT. With the increase of the number of layers of the gate line G, the number of gate line contacts G-CNT coupled with the gate line G also increases, and the area occupied by the gate line contact G-CNT increases, thereby causing the size of the semiconductor structure 1000 in the second direction X to increase, which is not conducive to improving the storage density of the semiconductor structure 1000 and is not conducive to the development of the semiconductor structure 1000 to a smaller volume.

[0139] In addition, the gate line G is coupled with the string driving device through the gate line contact G-CNT. However, one gate line contact G-CNT is connected with one string driving device, and with the increase of the number of gate line contacts G-CNT, the number of string driving devices also increases, and the area occupied by the string driving device also increases, which is not conducive to the development of the semiconductor structure 1000 to a smaller volume.

[0140] In this embodiment, by arranging the connection structure 144 (i.e. the gate line contact G-CNT) in the third stacked structure 140, the first gate layer 1231 in the first sub-stack structure 123 and the second gate layer 1241 in the second sub-stack structure 124 can be led out, so as to realize the reading, writing or erasing of data by the channel structure 122 in subsequent control.

[0141] In this way, one connection structure 144 can be used to lead out one first gate layer 1231 and one second gate layer 1241, thereby reducing the number of connection structures 144 required for leading out the first gate layer 1231 and the second gate layer 1241 respectively. Especially in the case where the number of first gate layers 1231 and second gate layers 1241 is multiple, in this way, the number of connection structures 144 can be greatly reduced, thereby reducing the area occupied by the connection structure 144 to the semiconductor structure 1000, and further improving the storage density of the semiconductor structure 1000, which is conducive to the development of the semiconductor structure 1000 to a smaller volume.

[0142] In some examples, the material of the second dielectric layer 1232 and the third dielectric layer 1242 can each include an insulating material, illustratively including one or more of an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), an oxynitride material (e.g., silicon oxynitride), etc. The insulating material of the second dielectric layer 1232 and the third dielectric layer 1242 can be the same or different. The material of the first gate layer 1231 and the second gate layer 1241 can each include a conductive material, illustratively including W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The material of the first gate layer 1231 and the second gate layer 1241 can be the same or different.

[0143] In the present embodiment, the insulating material of the second dielectric layer 1232 and the third dielectric layer 1242 can each be silicon oxide, and the material of the first gate layer 1231 and the second gate layer 1241 can each be tungsten (W). The second dielectric layer 1232, the third dielectric layer 1242, the first gate layer 1231, and the second gate layer 1241 can each be formed using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0144] Illustratively, the thickness (i.e., the dimension along the stacking direction Z) of the first gate layer 1231 and the second gate layer 1241 can be between 10 nm and 50 nm, such as 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. Similarly, the thickness (i.e., the dimension along the stacking direction Z) of the second dielectric layer 1232 and the third dielectric layer 1242 can be between 10 nm and 50 nm, such as 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. The first gate layer 1231 and the second gate layer 1241 can be gate lines G (see Figure 3 ) surrounding the memory string, and can extend laterally (i.e., along the second direction Y) as word lines WL (see Figure 3 ).

[0145] Please continue to refer to Figure 9In some embodiments, the connection structure 144 includes a connection post 1441, a first connection layer 1442, and a second connection layer 1443. The connection post 1441 penetrates the third sub-laminate structure 141, the second common electrode layer 143, and the fourth sub-laminate structure 142 along the stacking direction Z. The first connection layer 1442 is disposed in the third sub-laminate structure 141, extends along a direction perpendicular to the stacking direction Z, and is connected to a first gate layer 1231. The second connection layer 1443 is disposed in the fourth sub-laminate structure 142, extends along a direction perpendicular to the stacking direction Z, and is connected to a second gate layer 1241.

[0146] In this embodiment, by disposing the first connection layer 1442 and the second connection layer 1443, the first gate layer 1231 and the second gate layer 1241 can be led out, and then the first connection layer 1442 and the second connection layer 1443 can be led out through the connection post 1441. That is, the first gate layer 1231 and the second gate layer 1241 can be led out through the connection post 1441.

[0147] In this way, the number of connection structures 144 required for the first gate layer 1231 and the second gate layer 1241 to be led out, respectively, can be reduced, and the area of the semiconductor structure 1000 occupied by the connection structure 144 can be reduced, thereby improving the storage density of the semiconductor structure 1000 and facilitating the development of the semiconductor structure 1000 to a smaller volume.

[0148] For example, the constituent materials of the connection post 1441, the first connection layer 1442, and the second connection layer 1443 can all include conductive materials, which include but are not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or other suitable conductive materials.

[0149] Figure 10 Another top view of a semiconductor structure 1000 is provided for some embodiments of the present disclosure.

[0150] As Figure 8 and Figure 10As shown, in some embodiments, the semiconductor structure 1000 includes a first region 600 and a second region 700. The first region 600 is adjacent to the second region 700, the first stack structure and the second stack structure are both located in the first region 600, and the third stack structure 140 is located in the second region 700. In this case, the second region 700 is located on one side of the first region 600 in the second direction X. Alternatively, the first region 600 includes a first sub-region 610 and a second sub-region 620, the first sub-region 610 and the second sub-region 620 are arranged along the second direction X, and the second region 700 is located between the first sub-region 610 and the second sub-region 620.

[0151] Through the above arrangement, the connection structure 144 located in the second region 700 can be connected with one first gate layer 1231 and one second gate layer 1241 in the first region 600 (the first sub-region 610 and the second sub-region 620). In this way, one first gate layer 1231 and one second gate layer 1241 can share one connection structure 144, so as to reduce the number of connection structures 144 and the area occupied by the plurality of connection structures 144 in the second region 700, thereby improving the storage density of the semiconductor structure 1000.

[0152] Please continue to refer to Figure 9 In some embodiments, the semiconductor structure 1000 further includes a gate trench 150. The gate trench 150 extends along the second direction X and penetrates the stack structure 100 along the stacking direction Z, and the gate trench 150 is connected with the first common electrode layer 125. In this case, the second direction X is perpendicular to the stacking direction Z and the first direction X.

[0153] In this embodiment, by arranging the gate trench 150 to be connected with the first common electrode layer 125, the gate trench 150 can be used to lead out the first common electrode layer 125, and thus the gate trench 150 can be used to apply an electrical signal to the first common electrode layer 125.

[0154] Figure 11 Another structure schematic diagram of a semiconductor structure 1000 provided by some embodiments of the present disclosure is provided.

[0155] As Figure 11As shown, in some embodiments, the semiconductor structure further includes: an interconnection layer 160. The interconnection layer 160 is disposed on a side of the second bit line 300 away from the second stack structure 120, and the interconnection layer 160 includes a circuit layer 161 and a plurality of interconnection structures 162, the circuit layer 161 is located between the interconnection structures 162 and the second bit line 300. The interconnection structures 162 include a first interconnection structure 1621, a second interconnection structure 1622, and a third interconnection structure 1623. The first interconnection structure 1621 is connected to the second bit line 300 through the circuit layer 161, the second interconnection structure 1622 is connected to the gate isolation groove 150 through the circuit layer 161, and the third interconnection structure 1623 is connected to the connection structure 144 through the circuit layer 161.

[0156] In this embodiment, by providing the interconnection layer 160, the entire stack structure 100 can be led out, thereby realizing signal transmission between the storage array in the stack structure 100 and other device structures, so as to realize the control of the storage array in the stack structure 100 by the other device structures. The connection can include electrical connection or physical connection.

[0157] For example, the circuit layer 161 can include at least one circuit structure, so as to connect the storage array to other device structures (such as transistor structures) through the internal circuit structure (such as interconnection lines) and the interconnection structures 162. In addition, the circuit layer 161 can also include an interlayer dielectric for isolating the circuit structure. The interlayer dielectric can be made of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant dielectric, or any combination thereof. The first interconnection structure 1621, the second interconnection structure 1622, and the third interconnection structure 1623 can all include a conductive material, for example, the conductive material includes but is not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The conductive materials used by the first interconnection structure 1621, the second interconnection structure 1622, and the third interconnection structure 1623 can be the same or different, and the embodiments of the present disclosure do not make specific limitations thereon.

[0158] Please continue to refer to Figure 11 The semiconductor structure 1000 further includes: a transistor structure layer 170. The transistor structure layer 170 is disposed on a side of the interconnection layer 160 away from the second bit line 300. The transistor structure layer 170 includes a first transistor 171 and a second transistor 172, a first electrode of the first transistor 171 is connected to the second bit line 300 through the interconnection layer 160, a second electrode of the first transistor 171 is connected to the gate isolation groove 150 through the interconnection layer 160, and a control electrode of the second transistor 172 is connected to the connection structure 144 through the interconnection layer 160.

[0159] In this embodiment, the transistor structure layer 170 can include a plurality of transistors T, the coupling of the transistor structure layer 170 with the storage array and the coupling of the plurality of transistors T in the transistor structure layer 170 with the channel structure 122 in the storage array can be achieved through the interconnection layer 160, so as to achieve the transmission of electrical signals between the transistors T and the channel structure 122, and further achieve the writing, reading and erasing of data by the storage array.

[0160] Based on the semiconductor structure 1000 provided in some embodiments above, the disclosure further provides a preparation method of the semiconductor structure 1000, which is used to prepare the semiconductor structure 1000 described above.

[0161] Figure 12 A flowchart of the preparation method of the semiconductor structure 1000 provided in some embodiments of the disclosure is shown.

[0162] As shown in Figure 12 The semiconductor structure 1000 preparation method includes the following steps S1-S3.

[0163] S1, forming a stacked structure. The stacked structure includes a first stacked structure and a second stacked structure which are stacked. The first stacked structure includes a first laminated structure and a plurality of support portions. The support portions penetrate through the first laminated structure along the stacking direction, and the first laminated structure includes two first dielectric layers and a support layer, and the support layer is arranged between the two first dielectric layers. The second stacked structure includes a second laminated structure and a plurality of channel structures, the channel structures penetrate through the second laminated structure along the stacking direction, and one end of one channel structure is connected to one end of one support portion. The second laminated structure includes a first sub-laminated structure, a second sub-laminated structure and a first common electrode layer, the first sub-laminated structure is arranged on one side of the first laminated structure, the second sub-laminated structure is arranged on the side of the first sub-laminated structure away from the first laminated structure, and the first common electrode layer is arranged between the first sub-laminated structure and the second sub-laminated structure.

[0164] Please continue to refer to Figure 5 In this embodiment, by forming the first stacked structure 110 on one side of the second stacked structure 120, the support force provided by the support layer 1112 in the first laminated structure 111 for the second laminated structure 121 and the channel structure 122 inside it can be achieved, so as to avoid the problem of bending or tilting of the channel structure 122 caused by stress due to the preparation process in the process of preparing the first bit line 200, thereby improving the accuracy of the alignment and connection of the first bit line 200 and the channel structure 122, and further improving the electrical connection effect of the semiconductor structure 1000.

[0165] In addition, the first stack structure 111 is provided with a plurality of support portions 112. In this embodiment, the support portions 112 are used to form the channel structures 122, so that the depths of the channel structures 122 near the first bit line 200 are substantially the same. Therefore, before the first bit line 200 is formed, the channel structures 122 with different depths do not need to be polished from the back, so that the manufacturing process of the semiconductor structure 1000 is simplified.

[0166] S2, a plurality of first connecting portions are formed on the side of the first stack structure away from the second stack structure, one first connecting portion penetrates one support portion in the stacking direction and extends into one channel structure.

[0167] Please continue to refer to Figure 5 In this step S2, the first connecting portions 500 are formed, so that the via contact between the channel structures 122 and the first bit line 200 formed later is achieved. Therefore, the alignment accuracy between the channel structures 122 and the first bit line 200 is improved, so that the electrical connection effect between the channel structures 122 and the first bit line 200 is improved, and the electrical performance of the semiconductor structure 1000 is improved.

[0168] In addition, the first connecting portions 500 directly extend into one channel structure 122, so that the channel structure 122 and the first bit line 200 formed later are connected, and the process of removing the bottom of the channel structure 122 is omitted. Therefore, the manufacturing process of the semiconductor structure 1000 is simplified, and the manufacturing cost is reduced.

[0169] S3, a first bit line is formed on the side of the first connecting portion away from the first stack structure, the first bit line extends in a first direction, and the first bit line is connected with a column of first connecting portions, wherein the first direction is perpendicular to the stacking direction.

[0170] In this step S3, the first bit line 200 is formed, so that the corresponding channel structures 122 in the first sub-stack structure 123 can be controlled, and the reading, writing or erasing of data by the corresponding channel structures in the first sub-stack structure 123 is achieved.

[0171] In this way, the first common electrode layer 125 can be used to provide electrical signals for the channel structures 122 in the first sub-stack structure 123 and the second sub-stack structure 124, respectively. Therefore, the distance between the channel structures 122 in the first sub-stack structure 123 and the second sub-stack structure 124 and the first common electrode layer 125 is shortened, so that the signal transmission loss of the channel structures 122 is reduced, and the electrical performance of the second stack structure 120 is improved.

[0172] In addition, the first common electrode layer 125 is formed between the first sub-stack structure 123 and the second sub-stack structure 124, and the height of the second stack structure 120 can be increased by increasing the height of the first sub-stack structure 123 and the second sub-stack structure 124 on both sides, thereby increasing the storage capacity of the semiconductor structure 1000.

[0173] Figure 13 A flow chart of a preparation method of a stack structure 100 provided for some embodiments of the present disclosure, Figure 14 A structure diagram of a first initial stack structure 800 corresponding to the preparation method of Figure 13 A structure diagram of another first initial stack structure 800 corresponding to the preparation method of Figure 15 A structure diagram of another first initial stack structure 800 corresponding to the preparation method of Figure 13 A structure diagram of another first initial stack structure 800 corresponding to the preparation method of

[0174] As shown in Figure 13 The step S1 further includes the following steps S11-S15.

[0175] S11, forming a first initial stack structure. The first initial stack structure includes a first initial stack structure and a plurality of support portions, the first initial stack structure includes two first dielectric layers and a first sacrificial layer, the first sacrificial layer is arranged between the two first dielectric layers, and the support portions penetrate the first initial stack structure in the stacking direction.

[0176] For example, as shown in Figure 14 The two first dielectric layers 1111 and the first sacrificial layer 1113 can be formed on the substrate 870 by using a CVD, PVD, ALD or any combination of thin film deposition processes to obtain the first initial stack structure 810. The first sacrificial layer 1113 is arranged between the two first dielectric layers 1111.

[0177] In some examples, the first dielectric layer 1111 and the first sacrificial layer 1113 can both use insulating materials, such as silicon oxide, silicon nitride, and a combination of one or more of high dielectric constant insulating materials, or other suitable materials. In some examples, the materials of the first dielectric layer 1111 and the first sacrificial layer 1113 are different. For example, in the present embodiment, the material of the first dielectric layer 1111 is silicon oxide, and the material of the first sacrificial layer 1113 is silicon nitride.

[0178] Please continue to refer to Figure 14 A photoresist is applied to one side surface of the prepared first initial stack structure 810 to form a photoresist pattern, and then an etching pattern is formed on the first initial stack structure 810 using the photoresist pattern, and the first initial stack structure 810 is etched through the etching pattern to obtain a hole 820 penetrating the first initial stack structure 810.

[0179] As shown in FIG. 8A, a semiconductor material can be deposited in the hole 820 by using a CVD, PVD, ALD or any combination thereof thin film deposition process to form the support portion 112, and to complete the preparation of the first initial stack structure 800. Exemplarily, the semiconductor material can be monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other suitable semiconductor material.

[0180] As shown in FIG. 8A, a semiconductor material can be deposited in the hole 820 by using a CVD, PVD, ALD or any combination thereof thin film deposition process to form the support portion 112, and to complete the preparation of the first initial stack structure 800. Exemplarily, the semiconductor material can be monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other suitable semiconductor material. Figure 15

[0181] S12, forming a second initial stack structure on one side of the first initial stack structure. The second initial stack structure includes a second initial layer stack and a plurality of first sacrificial columns. The second initial layer stack includes a plurality of second dielectric layers and a plurality of second sacrificial layers which are alternately stacked. The first sacrificial columns pass through the second initial layer stack along the stacking direction, and one end of one first sacrificial column is connected to one support portion.

[0182] Figure 16 As shown in FIG. 9A, a semiconductor structure 1000 corresponding to the preparation method of the semiconductor structure 900. Figure 13 As shown in FIG. 8A, a semiconductor material can be deposited in the hole 820 by using a CVD, PVD, ALD or any combination thereof thin film deposition process to form the support portion 112, and to complete the preparation of the first initial stack structure 800. Exemplarily, the semiconductor material can be monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other suitable semiconductor material.

[0183] Figure 16 As shown in FIG. 8A, a semiconductor material can be deposited in the hole 820 by using a CVD, PVD, ALD or any combination thereof thin film deposition process to form the support portion 112, and to complete the preparation of the first initial stack structure 800. Exemplarily, the semiconductor material can be monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other suitable semiconductor material.

[0184] As shown in FIG. 8A, a semiconductor material can be deposited in the hole 820 by using a CVD, PVD, ALD or any combination thereof thin film deposition process to form the support portion 112, and to complete the preparation of the first initial stack structure 800. Exemplarily, the semiconductor material can be monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other suitable semiconductor material.

[0185] As shown in FIG. 8A, a semiconductor material can be deposited in the hole 820 by using a CVD, PVD, ALD or any combination thereof thin film deposition process to form the support portion 112, and to complete the preparation of the first initial stack structure 800. Exemplarily, the semiconductor material can be monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other suitable semiconductor material. ​​

[0186] The insulating material can be deposited in the via hole by a CVD, PVD, ALD or any combination thereof thin film deposition process to form the first sacrificial post 842 and complete the preparation of the second initial stack structure 840. Exemplarily, the insulating material is, for example, one or more of a combination of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable material.

[0187] Exemplarily, in the embodiment, the material of the second dielectric layer 1232 is silicon oxide, and the material of the second sacrificial layer 1233 is silicon nitride. In the case where the materials of the first dielectric layer 1111 and the second dielectric layer 1232 are the same, the two are structurally integrated and there is no obvious boundary between them.

[0188] In other examples, the materials of the second dielectric layer 1232 and the second sacrificial layer 1233 can also be other suitable materials.

[0189] S13, a third initial stack structure is formed on the side of the second initial stack structure away from the first initial stack structure. The third initial stack structure includes a third sacrificial layer and a third initial layer structure stacked, and a plurality of second sacrificial posts, the third sacrificial layer is closer to the second initial stack structure than the third initial layer structure. The third initial layer structure includes a plurality of third dielectric layers and a plurality of fourth sacrificial layers alternately stacked. The second sacrificial post penetrates the third initial layer structure and the third sacrificial layer in the stacking direction, and one end of one second sacrificial post is connected to the other end of one first sacrificial post.

[0190] Figure 17 For the preparation method of Figure 13 , another structure schematic diagram of a semiconductor structure 1000 corresponding to the preparation method of

[0191] As Figure 17 shown, in this step S13, a third sacrificial layer 851 can be formed on the side of the second initial stack structure 840 away from the first initial layer structure 810 by a CVD, PVD, ALD or any combination thereof thin film deposition process.

[0192] A plurality of third dielectric layers 1242 and a plurality of fourth sacrificial layers 1243 are alternately stacked on the side of the third sacrificial layer 851 away from the second initial stack structure 840 to form a third initial layer structure 852.

[0193] A photoresist is applied to one side surface of the prepared third initial stack structure 852 to form a photoresist pattern, and then an etching pattern is formed on the third initial stack structure 852 by using the photoresist pattern, and the third initial stack structure 852 and the third sacrificial layer 851 are etched by using the etching pattern, so as to obtain a through hole penetrating through the third initial stack structure 852 and the third sacrificial layer 851. The through hole exposes the first sacrificial pillar 842 in the second initial stack structure 840.

[0194] For example, the photoresist can be applied by using a static spin coating or a dynamic spray coating or other suitable method. Alternatively, the third initial stack structure 852 and the third sacrificial layer 851 can be etched by using a dry etching method.

[0195] The insulating material can be deposited in the through hole by using a CVD, PVD, ALD or any combination thereof, so as to form the second sacrificial pillar 853 and complete the preparation of the third initial stack structure 850. For example, the insulating material can be one or more of silicon oxide, silicon nitride and high dielectric constant insulating material, or other suitable material.

[0196] The material of the second sacrificial pillar 853 can be the same as or different from the material of the first sacrificial pillar 842, and the embodiments of the present disclosure do not make any limitation in this regard. When the material of the second sacrificial pillar 853 is the same as the material of the first sacrificial pillar 842, there is no obvious boundary between the two.

[0197] S14, removing the first and second sacrificial pillars and forming a channel structure.

[0198] Figure 18 For the preparation method of Figure 13 , another structure schematic diagram of a semiconductor structure 1000 is shown.

[0199] As shown in Figure 17 and Figure 18 , in this step S14, the first and second sacrificial pillars 842 and 853 can be removed by using a wet etching process, so as to obtain a through hole.

[0200] The functional layer 1221, the channel layer 1222 and the support pillar 1223 are sequentially prepared in the through hole, so as to form a channel structure 122.

[0201] In some other examples, other etching processes can also be used to remove the first and second sacrificial pillars 842 and 853, and the embodiments of the present disclosure do not make any specific limitation in this regard.

[0202] S15, replacing the first sacrificial layer with a support layer, replacing the second sacrificial layer with a first gate layer, replacing the third sacrificial layer with a first common electrode layer, and replacing the fourth sacrificial layer with a second gate layer to form a stack structure.

[0203] In some examples, the removing of the first sacrificial layer 1113, the second sacrificial layer 1233, the third sacrificial layer 851 and the fourth sacrificial layer 1243 can be implemented by using a wet etching process, and the support layer 1112, the first common electrode layer 125, the first gate layer 1231 and the second gate layer 1241 can be respectively formed in the corresponding gap layers after the first sacrificial layer 1113, the second sacrificial layer 1233, the third sacrificial layer 851 and the fourth sacrificial layer 1243 are removed, so as to complete the preparation of the first stack structure 111 and the second stack structure 121, and obtain the stack structure 100 as shown in FIG. 1. Figure 5

[0204] In the embodiment, the stack structure 100 is prepared by using the multi-stack technology, which can reduce the difficulty of the preparation process caused by the height of the stack structure, thereby improving the efficiency and the preparation precision of the stack structure 100, and further improving the electrical performance and the reliability of the semiconductor structure 1000.

[0205] In addition, the first common electrode layer 125 in the second stack structure 120 can be used as the source layer of the channel structure 122 in the first sub-stack structure 123 and the second sub-stack structure 124 on both sides of the first common electrode layer 125, so as to shorten the distance from the corresponding channel structure 122 in the first sub-stack structure 123 and the second sub-stack structure 124 to the first common electrode layer 125, thereby reducing the loss of the corresponding channel structure 122 in the first sub-stack structure 123 and the second sub-stack structure 124 in the signal transmission.

[0206] In this way, the height of the second stack structure 120 can be increased by increasing the height of the first sub-stack structure 123 and the second sub-stack structure 124 on both sides, so as to increase the storage capacity of the second stack structure 120 while ensuring good electrical performance of the second stack structure 120.

[0207] In the above embodiment, the number of the stack structure of the second stack structure 120 is taken as 2 for introducing the preparation process of the stack structure 100, and in other embodiments, the number of the stack structure can also be 3, 4, 5 or any other value. In addition, in the above embodiment, the first common electrode layer 125 is formed between the first sub-stack structure 123 and the second sub-stack structure 124 for introduction, and in other embodiments, the first common electrode layer 125 can also be formed in the inside of any one of the stack structures, which is not limited in the embodiments of the present disclosure.

[0208] ​In some examples, before step S15, the method for preparing the semiconductor structure further comprises the following step S150:

[0209] S150, forming a gate slit. The gate slit extends along a second direction, and the gate slit penetrates the stack structure along a stacking direction, wherein the second direction is perpendicular to the stacking direction and the first direction.

[0210] Referring to Figures 16-18 , as a feasible implementation manner, the preparation of the sacrificial trench 760 of the gate slit can be realized in the preparation process of the through hole of the channel structure 122 and the sacrificial column. The material of the sacrificial trench 760 includes an insulating material, for example, a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0211] In some examples, the material of the sacrificial trench 760 can be the same as or different from the material of the first sacrificial column 842 and the material of the second sacrificial column 853.

[0212] Figure 19 A structure schematic diagram of a semiconductor structure 1000 corresponding to the preparation process is provided for some embodiments of the present disclosure.

[0213] As Figure 19 shown, the removal of the sacrificial trench 760 can be realized by using a wet etching process, so as to obtain a gate slit 860 penetrating the stack structure. The gate slit 860 extends along the second direction X, and the sidewall of the gate slit 860 exposes the first sacrificial layer 1113, the second sacrificial layer 1233, the third sacrificial layer 851, and the fourth sacrificial layer 1243.

[0214] Figure 20 A preparation method flowchart of a sacrificial layer replacement is provided for some embodiments of the present disclosure, Figure 21 A structure schematic diagram of a semiconductor structure 1000 corresponding to the preparation method of Figure 20 .

[0215] As Figure 20 shown, in some examples, the above step S15 further comprises the following steps S151-S154:

[0216] S151, removing the third sacrificial layer through the gate slit to form a first gap layer.

[0217] As Figure 19 and Figure 21As shown, since the material of the third sacrificial layer 851 is different from the material of the first sacrificial layer 1113, the second sacrificial layer 1233 and the fourth sacrificial layer 1243, the removing process of the third sacrificial layer 851 can be performed separately from the removing process of the first sacrificial layer 1113, the second sacrificial layer 1233 and the fourth sacrificial layer 1243.

[0218] As a feasible implementation, a wet etching process can be adopted to remove the third sacrificial layer 851 via the gate slit 860, and correspondingly form the first gap layer 861.

[0219] S152, forming a first common electrode layer in the first gap layer.

[0220] A CVD, PVD, ALD or any combination thereof thin film deposition process can be adopted to deposit a semiconductor material in the first gap layer 861, so as to form the first common electrode layer 125. The semiconductor material can include monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor material, II-VI compound semiconductor material and other suitable materials.

[0221] S153, removing the first sacrificial layer, the second sacrificial layer and the fourth sacrificial layer via the gate slit to form a second gap layer, a third gap layer and a fourth gap layer.

[0222] Please continue to refer to Figure 19 and Figure 21 As a feasible implementation, a wet etching process can be adopted to remove the first sacrificial layer 1113, the second sacrificial layer 1233 and the fourth sacrificial layer 1243 via the gate slit 860, and correspondingly form the second gap layer 862, the third gap layer 863 and the fourth gap layer 864.

[0223] S154, forming a support layer in the second gap layer, forming a first gate layer in the third gap layer, and forming a second gate layer in the fourth gap layer.

[0224] For example, a CVD, PVD, ALD or any combination thereof thin film deposition process can be adopted to deposit a conductive material in the second gap layer 862, the third gap layer 863 and the fourth gap layer 864, so as to form the support layer 1112, the first gate layer 1231 and the second gate layer 1241 as shown in Figure 5 The conductive material includes but is not limited to W, Co, Cu, Al, doped silicon, silicide or any combination thereof.

[0225] In addition, in this embodiment, the conductive material of the support layer 1112, the first gate layer 1231 and the second gate layer 1241 can all be tungsten, and the surface of the tungsten is provided with a layer of titanium nitride, so as to prevent the diffusion of the metal material, and the titanium nitride has good adhesion, which is conducive to improving the stability of the structure.

[0226] In this embodiment, the replacement of the plurality of sacrificial layers can be realized in the same preparation process via the gate slit. In this way, the preparation process of the semiconductor structure 1000 can be simplified, the preparation process difficulty is reduced, and the preparation efficiency of the semiconductor structure 1000 is improved, thereby reducing the preparation cost.

[0227] In some embodiments, before the above step S152, the preparation process of the semiconductor structure 1000 further includes:

[0228] The part of the channel structure 122 is removed via the first gap layer 861 to form a third connecting part 128.

[0229] Figure 22 A structure schematic diagram of a semiconductor structure 1000 corresponding to a preparation process is provided for some embodiments of the present disclosure.

[0230] As Figure 22 shown, for example, a wet etching process can be used to remove the functional layer 1221 of the channel structure 122 via the first gap layer 861 to form an eleventh gap layer 869, wherein the eleventh gap layer 869 exposes the channel layer 1222 of the channel structure 122.

[0231] In this way, when the first common electrode layer 125 is formed in the subsequent preparation process, the connection of the first common electrode layer 125 and the channel layer 1222 can be realized, and then the transmission of ions in the first common electrode layer 125 can be realized through the channel layer 1222.

[0232] In this way, when the first common electrode layer 125 is formed in the subsequent preparation process, the connection of the first common electrode layer 125 and the channel layer 1222 can be realized, and then the transmission of ions in the first common electrode layer 125 can be realized through the channel layer 1222.

[0233] The preparation process of the stack structure 100 is introduced by taking the number of the layer structure as 2 and the first common electrode layer 125 formed between the first sub-layer structure 123 and the second sub-layer structure 124 as an example. In the following, the preparation process of the stack structure 100 is introduced by taking the number of the layer structure as 3 and the first common electrode layer 125 formed in the middle layer structure as an example.

[0234] Figure 23This is a flowchart illustrating a method for preparing another first stacked structure 100 according to some embodiments of the present disclosure. Figure 24 To and Figure 23 A schematic diagram of a semiconductor structure 1000 corresponding to the preparation method is shown. Figure 25 To and Figure 23 A schematic diagram of another semiconductor structure 1000 corresponding to the preparation method is shown. Figure 26 To and Figure 23 The schematic diagram of another semiconductor structure 1000 corresponding to the preparation method.

[0235] like Figure 23 As shown, in some embodiments, another method for preparing the first stacked structure 100 includes the following steps S16 to S21.

[0236] S16. A first initial stacked structure is formed. The first initial stacked structure includes a first initial layered structure and a plurality of support portions. The first initial layered structure includes two first dielectric layers and a first sacrificial layer. The first sacrificial layer is disposed between the two first dielectric layers. The support portions penetrate the first initial layered structure along the stacking direction.

[0237] Please continue reading Figure 14 Two first dielectric layers 1111 and a first sacrificial layer 1113 can be formed on the substrate 870 using CVD, PVD, ALD, or any combination thereof to obtain the first initial stacked structure 810. The first sacrificial layer 1113 is disposed between the two first dielectric layers 1111.

[0238] In some examples, both the first dielectric layer 1111 and the first sacrificial layer 1113 can be made of insulating materials, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, or other suitable materials. The materials of the first dielectric layer 1111 and the first sacrificial layer 1113 are different. For example, in this embodiment, the material of the first dielectric layer 1111 is silicon oxide, and the material of the first sacrificial layer 1113 is silicon nitride.

[0239] Photoresist is applied to one side of the prepared first initial stacked structure 810 to form a photoresist pattern. Then, an etching pattern is formed on the first initial stacked structure 810 using the photoresist pattern. The first initial stacked structure 810 is etched using the etching pattern to obtain a hole 820 penetrating the first initial stacked structure 810.

[0240] For example, photoresist can be applied using suitable methods such as static spin coating or dynamic spray coating. Alternatively, dry etching can be used to etch the first initial stacked structure 810.

[0241] Please continue to refer to Figure 15 A semiconductor material can be deposited in the hole 820 by a CVD, PVD, ALD or any combination thereof thin film deposition process to form the support portion 112, and complete the preparation of the first initial stack structure 800. Exemplarily, the semiconductor material can include single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material and other suitable materials.

[0242] S17, forming a fourth initial stack structure on one side of the first initial stack structure, the fourth initial stack structure comprising a fourth initial layer structure and a plurality of third sacrificial columns. The fourth initial layer structure comprises a plurality of fourth dielectric layers and a plurality of fifth sacrificial layers alternately stacked, the third sacrificial columns penetrate the fourth initial layer structure along the stacking direction, and one end of one third sacrificial column is connected with one support portion.

[0243] As shown in Figure 24 A plurality of fourth dielectric layers 994 and a plurality of fifth sacrificial layers 995 can be alternately stacked on the side of the first initial stack structure 800 away from the substrate 870 by a CVD, PVD, ALD or any combination thereof thin film deposition process to form a fourth initial layer structure 996.

[0244] A photoresist is applied on the side surface of the prepared fourth initial layer structure 996 to form a photoresist pattern, and then an etching pattern is formed on the fourth initial layer structure 996 using the photoresist pattern, and the fourth initial layer structure 996 is etched through the etching pattern to obtain a through hole penetrating the fourth initial layer structure 996. The one end of the support portion 112 is exposed.

[0245] Exemplarily, the photoresist can be applied by static spin coating or dynamic spray coating or other suitable methods. Alternatively, the fourth initial layer structure 996 can be etched by dry etching.

[0246] An insulating material can be deposited in the through hole by a CVD, PVD, ALD or any combination thereof thin film deposition process to form the third sacrificial column 997, and complete the preparation of the fourth initial stack structure 998. Exemplarily, the insulating material can be, for example, one or a combination of silicon oxide, silicon nitride and high dielectric constant insulating material, or other suitable materials.

[0247] Exemplarily, in the present embodiment, the material of the fourth dielectric layer 994 is silicon oxide, and the material of the fifth sacrificial layer 995 is silicon nitride. When the materials of the first dielectric layer 1111 and the fourth dielectric layer 994 are the same, the two are structurally integrated and there is no obvious boundary between them.

[0248] S18, a fifth initial stack structure is formed on a side of the fourth initial stack structure away from the first initial stack structure, the fifth initial stack structure comprising a fifth initial layer structure, a sixth sacrificial layer, a sixth initial layer structure, and a plurality of fourth sacrificial columns. The fifth initial layer structure comprises a plurality of fifth dielectric layers and a plurality of seventh sacrificial layers alternately stacked, and the sixth initial layer structure comprises a plurality of sixth dielectric layers and a plurality of eighth sacrificial layers alternately stacked. The fourth sacrificial columns pass through the fifth initial layer structure, the sixth sacrificial layer, and the sixth initial layer structure along the stacking direction, and one end of one fourth sacrificial column is connected to the other end of one third sacrificial column.

[0249] Please continue to refer to Figure 24 In some examples, a plurality of fifth dielectric layers 811 and a plurality of seventh sacrificial layers 812 can be formed alternately stacked on a side of the fourth initial stack structure 998 away from the first initial stack structure 800 by using a CVD, PVD, ALD or any combination thereof thin film deposition process, thereby forming the fifth initial layer structure 855.

[0250] The sixth sacrificial layer 856 is formed on a side of the fifth initial layer structure 855 away from the fourth initial stack structure 998.

[0251] A plurality of sixth dielectric layers 831 and a plurality of eighth sacrificial layers 832 are formed alternately stacked on a side of the sixth sacrificial layer 856 away from the fifth initial layer structure 855, thereby forming the sixth initial layer structure 880.

[0252] A photoresist is applied on a side surface of the prepared sixth initial layer structure 880, a photoresist pattern is formed, and then an etching pattern is formed on the sixth initial layer structure 880 by using the photoresist pattern, and the sixth initial layer structure 880, the sixth sacrificial layer 856, and the fifth initial layer structure 855 are etched through the etching pattern, thereby obtaining a via hole passing through the sixth initial layer structure 880, the sixth sacrificial layer 856, and the fifth initial layer structure 855. The via hole exposes the third sacrificial column 997 in the fourth initial stack structure 998.

[0253] For example, the photoresist can be applied by using a static spin coating or a dynamic spray coating or other suitable method. Alternatively, the sixth initial layer structure 880, the sixth sacrificial layer 856, and the fifth initial layer structure 855 can be etched by using a dry etching method.

[0254] An insulating material can be deposited in the via hole by using a CVD, PVD, ALD or any combination thereof thin film deposition process, thereby forming the fourth sacrificial column 833 and completing the preparation of the fifth initial stack structure 890. For example, the insulating material can be one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable material.

[0255] In this embodiment, the material of the fourth sacrificial column 833 and the material of the third sacrificial column 997 can be the same; in other embodiments, the materials of the fourth sacrificial column 833 and the materials of the third sacrificial column 997 can also be different.

[0256] S19. A sixth initial stacking structure is formed on the side of the fifth initial stacking structure away from the fourth initial stacking structure. The sixth initial stacking structure includes a seventh initial stacking structure and multiple fifth sacrificial pillars. The seventh initial stacking structure includes multiple alternately stacked seventh dielectric layers and multiple ninth sacrificial layers. The fifth sacrificial pillars penetrate the seventh initial stacking structure along the stacking direction, and one end of one fifth sacrificial pillar is connected to the other end of one fourth sacrificial pillar.

[0257] like Figure 25 As shown, in some examples, a plurality of seventh dielectric layers 882 and a plurality of ninth sacrificial layers 883 may be alternately stacked on the side of the fifth initial stack structure 890 away from the fourth initial stack structure 998 to form a seventh initial stack structure 881.

[0258] Photoresist is applied to one side of the prepared seventh initial stacked structure 881 to form a photoresist pattern. An etching pattern is then formed on the seventh initial stacked structure 881 using the photoresist pattern, and the seventh initial stacked structure 881 is etched using the etching pattern to obtain a through-hole penetrating the seventh initial stacked structure 881. The through-hole exposes the fourth sacrificial pillar 833 within the fifth initial stacked structure 890.

[0259] For example, photoresist can be applied using suitable methods such as static spin coating or dynamic spray coating. Alternatively, dry etching can be used to etch the seventh initial stacked structure 881.

[0260] Insulating material can be deposited within the via using CVD, PVD, ALD, or any combination thereof thin film deposition processes to form the fifth sacrificial pillar 884 and complete the fabrication of the sixth initial stack structure 885. Exemplarily, the insulating material may be one or more combinations of silicon oxide, silicon nitride, and high-dielectric-constant insulating materials, or other suitable materials.

[0261] In this embodiment, the material of the fifth sacrificial column 884 is the same as that of the fourth sacrificial column 833.

[0262] In some other embodiments, the materials of the fifth sacrificial pillar 884 and the fourth sacrificial pillar 833 may also be different.

[0263] S20, remove the third, fourth and fifth sacrificial columns, and form a channel structure.

[0264] As shown in FIG. 11, the third, fourth and fifth sacrificial columns 997, 833 and 884 can be removed by a wet etching process, for example, to form a via hole. Figure 25 and Figure 26 As shown in FIG. 11, the third, fourth and fifth sacrificial columns 997, 833 and 884 can be removed by a wet etching process, for example, to form a via hole. The functional layer 1221, channel layer 1222 and support column 1223 can be sequentially prepared in the via hole to form a channel structure 122.

[0265] In other examples, other etching processes can be used to remove the third, fourth and fifth sacrificial columns 997, 833 and 884, which are not limited in the embodiments of the present disclosure.

[0266] S21, replace the first sacrificial layer with a support layer, replace the fifth and seventh sacrificial layers with a first gate layer, replace the sixth sacrificial layer with a first common layer, and replace the eighth and ninth sacrificial layers with a second gate layer to form a stacked structure.

[0267] As shown in FIG. 11, the third, fourth and fifth sacrificial columns 997, 833 and 884 can be removed by a wet etching process, for example, to form a via hole. The functional layer 1221, channel layer 1222 and support column 1223 can be sequentially prepared in the via hole to form a channel structure 122.

[0268] The preparation of the stacked structure 100 in the embodiments is achieved by using the multi-stacking technology, which can reduce the difficulty of the etching process caused by the height of the stacked structure, thereby improving the efficiency and accuracy of the preparation of the stacked structure 100, and further improving the electrical performance and reliability of the semiconductor structure 1000.

[0269] In addition, the first common layer 125 in the second stacked structure 120 can serve as the source layer of the channel structure 122 in the first and second sub-stacked structures 123 and 124 on both sides of the first common layer 125, thereby shortening the distance from the corresponding channel structure 122 in the first and second sub-stacked structures 123 and 124 to the first common layer 125, and reducing the signal transmission loss of the corresponding channel structure 122 in the first and second sub-stacked structures 123 and 124.

[0270] In this way, the height of the second stack structure 120 can be increased by increasing the height of the first and second sub-stack structures 123 and 124, thereby increasing the storage capacity of the second stack structure 120 while ensuring good electrical performance of the second stack structure 120.

[0271] In some embodiments, before step S21, the method for manufacturing the semiconductor structure 1000 further includes the following step S210:

[0272] S210, forming a gate slit, the gate slit extending along a second direction, and the gate slit penetrating the stack structure along a stacking direction, wherein the second direction is perpendicular to the stacking direction and the first direction.

[0273] Referring to Figures 24-26 As a feasible implementation manner, the gate slit can be prepared in the process of preparing the through hole of the channel structure 122 and the sacrificial column. The material of the sacrificial groove 760 includes an insulating material, for example, silicon oxide, silicon nitride, and a combination of one or more of high dielectric constant insulating materials, or other suitable materials.

[0274] Figure 27 Another structure diagram of a semiconductor structure 1000 corresponding to the manufacturing process is provided for some embodiments of the present disclosure.

[0275] As Figure 27 shown, the sacrificial groove 760 can be removed by using a wet etching process to obtain a gate slit 860 penetrating the stack structure. The gate slit 860 extends along the second direction X, and the sidewall of the gate slit exposes the first sacrificial layer 1113, the fifth sacrificial layer 995, the sixth sacrificial layer 856, the seventh sacrificial layer 812, the eighth sacrificial layer 832, and the ninth sacrificial layer 883.

[0276] Figure 28 Another flowchart of a method for manufacturing a first stack structure 100 is provided for some embodiments of the present disclosure, Figure 29 A structure diagram of a semiconductor structure 1000 corresponding to the manufacturing method in Figure 28 is provided.

[0277] As Figure 28 shown, the above step S21 further includes the following sub-steps S211-S214:

[0278] S211, removing the sixth sacrificial layer through the gate slit to form a fifth gap layer.

[0279] As Figure 27 and Figure 29As shown, since the sixth sacrificial layer 856 is made of a material different from the first sacrificial layer 1113, the fifth sacrificial layer 995, the seventh sacrificial layer 812, the eighth sacrificial layer 832 and the ninth sacrificial layer 883, the removing process of the sixth sacrificial layer 856 can be performed separately from the removing process of the first sacrificial layer 1113, the fifth sacrificial layer 995, the seventh sacrificial layer 812, the eighth sacrificial layer 832 and the ninth sacrificial layer 883.

[0280] As a possible implementation, a wet etching process can be employed to remove the sixth sacrificial layer 856 via the gate slit 860, and to form the fifth gap layer 886 correspondingly.

[0281] S212, forming a first common electrode layer in the fifth gap layer.

[0282] A thin film deposition process such as CVD, PVD, ALD or any combination thereof can be employed to deposit a semiconductor material in the fifth gap layer 886, to form the first common electrode layer 125. The semiconductor material can include monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor material, II-VI compound semiconductor material and other suitable materials.

[0283] S213, removing the first sacrificial layer, the fifth sacrificial layer, the seventh sacrificial layer, the eighth sacrificial layer and the ninth sacrificial layer via the gate slit, to form a sixth gap layer, a seventh gap layer, an eighth gap layer, a ninth gap layer and a tenth gap layer.

[0284] Please refer to Figure 27 and Figure 29 As a possible implementation, a wet etching process can be employed to remove the first sacrificial layer 1113, the fifth sacrificial layer 995, the seventh sacrificial layer 812, the eighth sacrificial layer 832 and the ninth sacrificial layer 883 via the gate slit, and to form the sixth gap layer 887, the seventh gap layer 888, the eighth gap layer 889, the ninth gap layer 865 and the tenth gap layer 866 correspondingly.

[0285] S214, forming a support layer in the sixth gap layer, forming a first gate layer in the seventh gap layer and the eighth gap layer, and forming a second gate layer in the ninth gap layer and the tenth gap layer.

[0286] As an example, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be employed to deposit a conductive material in the sixth gap layer 887, the seventh gap layer 888, the eighth gap layer 889, the ninth gap layer 865 and the tenth gap layer 866, to form the support layer 1112, the first gate layer 1231 and the second gate layer 1241 as shown in Figure 5 The conductive material includes but is not limited to W, Co, Cu, Al, doped silicon, silicide or any combination thereof.

[0287] In some embodiments, the conductive material of the support layer 1112, the first gate layer 1231 and the second gate layer 1241 can be tungsten, and a surface of the tungsten is provided with a layer of titanium nitride to prevent diffusion of the metal material, and the titanium nitride has good adhesion to improve the stability of the structure.

[0288] In some embodiments, the replacement of the plurality of sacrificial layers can be realized in the same process step via the gate slit. In this way, the preparation process of the semiconductor structure 1000 can be simplified, the preparation process difficulty can be reduced, and the preparation efficiency of the semiconductor structure 1000 can be improved, thereby reducing the preparation cost.

[0289] In some embodiments, before the step S212, the preparation process of the semiconductor structure 1000 further includes:

[0290] The part of the channel structure 122 is removed via the fifth gap layer 886 to form a third connecting part 128.

[0291] Figure 30 Another structure diagram of a semiconductor structure 1000 corresponding to a preparation process is provided for some embodiments of the present disclosure.

[0292] As shown in Figure 30 , for example, a wet etching process can be used to remove the functional layer 1221 of the channel structure 122 via the fifth gap layer 886 to form a twelfth gap layer 770, wherein the twelfth gap layer 770 exposes the channel layer 1222 of the channel structure 122.

[0293] In this way, when the first common electrode layer 125 is formed in the subsequent preparation process, the connection between the first common electrode layer 125 and the channel layer 1222 can be realized, and the transmission of ions in the first common electrode layer 125 can be realized through the channel layer 1222.

[0294] Figure 31 A preparation method flow chart of a first connecting part 500 is provided for some embodiments of the present disclosure, Figure 32 A structure diagram of a semiconductor structure 1000 corresponding to the preparation method of Figure 31 , is provided, Figure 33 Another structure diagram of a semiconductor structure 1000 corresponding to the preparation method of Figure 31 is provided.

[0295] As shown in Figure 31 , the step S2 includes the following sub-steps S201-S202.

[0296] S201, a plurality of grooves are formed, one groove penetrates one support portion in the stacking direction and extends into one channel structure. Among them, the groove exposes the functional layer, the channel layer and the support portion of the channel structure.

[0297] As shown in Figure 32 , for example, before step S201, chemical mechanical polishing (CMP) can be used to remove the substrate to expose the support portion 112.

[0298] As shown in Figure 33 , for example, in this step S201, CVD, PVD, ALD or any combination of thin film deposition processes can be used to deposit insulating material on the side of the first stack structure 110 away from the second stack structure 120 to form a first insulating layer.

[0299] A photoresist is applied to the side surface of the prepared first insulating layer to form a photoresist pattern, and then an etching pattern is formed on the first insulating layer using the photoresist pattern, and the first insulating layer and the support portion are etched through the etching pattern, so as to obtain a groove 992 penetrating the first insulating layer, the support portion and extending into the channel structure 122. Among them, the groove 992 exposes the functional layer 1221, the channel layer 1222 and the support column 1223 of the channel structure 122.

[0300] Among them, for example, the material of the first insulating layer can be the same as the material of the first dielectric layer, so in terms of structure, the two are integrated structures and there is no obvious boundary between them.

[0301] S202, forming a first connecting portion in the groove.

[0302] For example, in this step S202, CVD, PVD, ALD or any combination of thin film deposition processes can be used to deposit conductive material in the groove 992 to form a first connecting portion 500 as shown in Figure 5 .

[0303] In this embodiment, by forming the first connecting portion 500, the via contact between the channel structure 122 and the first bit line 200 prepared later can be realized, and the first connecting portion 500 can provide the accuracy of alignment between the channel structure 122 and the first bit line 200, thereby improving the electrical connection effect between the channel structure 122 and the first bit line 200, and further improving the electrical performance of the semiconductor structure 1000.

[0304] Figure 34 Another structure diagram of a semiconductor structure 1000 corresponding to the preparation process is provided for some embodiments of the present disclosure, Figure 35This is a schematic diagram of another semiconductor structure 1000 corresponding to a fabrication process provided in some embodiments of this disclosure.

[0305] In some embodiments, the method for fabricating the semiconductor structure 1000 further includes the following step S4.

[0306] S4. A gate spacer is formed in the gate slit, and the gate spacer is connected to the first common layer.

[0307] In step S4, by forming a gate spacer in the gate slit, the first common layer can be led out using the gate spacer.

[0308] For example, such as Figure 34 As shown, when filling the first common-electrode layer in step S212, the filled semiconductor material will cover the sidewall of the gate slit. To avoid affecting the subsequent sacrificial layer replacement process, a dry or wet etching process can be used to remove the semiconductor material on the sidewall of the gate slit. In the actual fabrication process, during the removal of the semiconductor material on the sidewall of the gate slit, a portion of the first common-electrode layer will be removed simultaneously, thereby forming the first via 988.

[0309] Furthermore, during the replacement of multiple sacrificial layers in step S214, some metal material (e.g., tungsten) will cover the sidewalls of the gate slit. To avoid affecting the subsequent fabrication of the gate spacer, a dry or wet etching process can be used to remove the metal material on the sidewalls of the gate slit. In the actual fabrication process, during the removal of the gate material on the sidewalls of the gate slit, a portion of the gate layer and support layer will also be removed, thereby forming the second via 989.

[0310] The depth of the second through hole 989 in the first direction Y is greater than the depth of the first through hole 988 in the first direction Y.

[0311] This configuration allows the thickness of the second insulating layer at the corresponding position of the first common layer to be thinner than its thickness at the corresponding positions of the gate layer and the support layer during the subsequent process of depositing insulating material via the gate slit to form the second insulating layer. For example, the second insulating layer can provide insulation between the gate spacer structure and the multiple gate layers and the support layer during the subsequent process of fabricating the gate spacer.

[0312] like Figure 35As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench.

[0313] As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench.

[0314] As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench. Figure 9 As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench.

[0315] Figure 36 As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench. Figure 37 As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench.

[0316] As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench. Figure 36 As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench.

[0317] S31, a strip-shaped groove is formed, the strip-shaped groove extends along the first direction and exposes a row of first connection parts.

[0318] As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench.

[0319] As shown, in some examples, an etching process can be employed in a subsequent preparation process to remove part of the second insulating layer, thereby forming a third via hole 780, wherein the third via hole 780 can expose at least part of the first common electrode layer, and thus when a gate trench is subsequently prepared based on the third via hole 780, the connection between the first common electrode layer and the gate trench can be achieved, and the first common electrode layer can be led out through the gate trench.

[0320] S32, forming a first bit line in the strip groove.

[0321] For example, a CVD, PVD, ALD or any combination thereof thin film deposition process can be used to deposit a conductive material in the strip groove to form the first bit line and obtain a semiconductor structure as shown in Figure 11 For example, the conductive material includes but is not limited to W, Co, Cu, Al, doped silicon, silicide or any combination thereof.

[0322] In this way, the control of data reading, writing or erasing operation on the channel structure in the first sub-stack structure by using the first bit line can be realized.

[0323] In other examples, as shown in Figure 37 Before step S31, a fourth connecting part 900 can be prepared in advance on the side of the first connecting part 500 away from the first stack structure 110, so as to improve the connecting precision between the first connecting part 500 and the subsequently prepared bit line 200, and further improve the electrical connection effect of the semiconductor structure.

[0324] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which shall be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A stacking structure, the stacking structure comprising a first stacking structure and a second stacking structure stacked together; The first stacked structure includes a first stacked structure and a plurality of support portions; the support portions penetrate the first stacked structure along the stacking direction, the first stacked structure includes two first dielectric layers and a support layer, and the support layer is disposed between the two first dielectric layers; The second stacked structure includes a second stacked structure and a plurality of channel structures. The channel structures penetrate the second stacked structure along the stacking direction, and one end of one channel structure is connected to one end of one of the support portions. The second stacked structure includes a first sub-stacked structure, a second sub-stacked structure, and a first common electrode layer. The first sub-stacked structure is disposed on one side of the first stacked structure, the second sub-stacked structure is disposed on the side of the first sub-stacked structure away from the first stacked structure, and the first common electrode layer is disposed between the first sub-stacked structure and the second sub-stacked structure. Multiple first connecting portions are provided on the side of the first stacking structure away from the second stacking structure, and one first connecting portion penetrates one of the support portions along the stacking direction and extends into one of the channel structures; The first bit line is disposed on the side of the first connection portion away from the first stacking structure. The first bit line extends along a first direction and is connected to a column of the first connection portions, wherein the first direction is perpendicular to the stacking direction.

2. The semiconductor structure according to claim 1, characterized in that, The channel structure includes a functional layer, a channel layer, and a support column. The functional layer and the channel layer surround the support column, and the channel layer is located between the functional layer and the support column. The first common electrode layer is connected to the functional layer, the channel layer, and the support column of the channel structure; One end of the first connecting portion extending into the channel structure is connected to the functional layer, the channel layer, and the support column.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: Multiple second connecting portions are disposed on the side of the second stacking structure away from the first stacking structure, the second connecting portions extend along the stacking direction, and one end of one second connecting portion is connected to the other end of one of the channel structures; The second bit line is disposed on the side of the second connection portion away from the second stacking structure, the second bit line extends along the first direction, and the second bit line is connected to a column of the second connection portions.

4. The semiconductor structure according to claim 3, characterized in that, The channel structure includes: A first channel structure is disposed on the first sub-layer structure and penetrates the first sub-layer structure along the stacking direction. One end of the first channel structure is connected to the first connecting portion, and the functional layer and channel layer at the other end of the first channel structure are both connected to the first common electrode layer. The second channel structure is disposed on the second sub-layer structure and penetrates the second sub-layer structure along the stacking direction. One end of the second channel structure is connected to the second connecting part, and the functional layer and channel layer at the other end of the second channel structure are both connected to the first common electrode layer. The third connection portion is disposed on the first common electrode layer and penetrates the first common electrode layer along the stacking direction. One end of the third connection portion is connected to the support column of the first channel structure, and the other end of the third connection portion is connected to the support column of the second channel structure.

5. The semiconductor structure according to claim 4, characterized in that, The first channel structure includes a first sub-channel structure and a second sub-channel structure. The second sub-channel structure is closer to the first common layer than the first sub-channel structure. The boundary of the support column at one end of the second sub-channel structure near the third connection portion coincides with the boundary at one end of the third connection portion. The second channel structure includes a third sub-channel structure and a fourth sub-channel structure. The third sub-channel structure is closer to the first common electrode layer than the fourth sub-channel structure. The boundary of the support column at one end of the third sub-channel structure near the third connection portion coincides with the boundary at the other end of the third connection portion.

6. The semiconductor structure according to claim 5, characterized in that, The boundary of the first sub-channel structure near the end of the second sub-channel structure is located outside the boundary of the second sub-channel structure near the end of the first sub-channel structure. The boundary of the third sub-channel structure near the end of the fourth sub-channel structure is located outside the boundary of the fourth sub-channel structure near the end of the third sub-channel structure.

7. The semiconductor structure according to claim 1, characterized in that, The first sub-stack structure includes a plurality of alternating first gate layers and a plurality of second dielectric layers, and the second sub-stack structure includes a plurality of alternating second gate layers and a plurality of third dielectric layers. The stacking structure further includes: a third stacking structure; The third stacked structure includes a third sub-stacked structure, a fourth sub-stacked structure, a second common electrode layer, and a connection structure. The third sub-stacked structure is disposed on one side of the first stacked structure along a second direction and is adjacent to both the first stacked structure and the first sub-stacked structure. The fourth sub-stacked structure is stacked on one side of the third sub-stacked structure and is adjacent to the second sub-stacked structure. The second common electrode layer is disposed between the third sub-stacked structure and the fourth sub-stacked structure and is adjacent to the first common electrode layer. The connection structure penetrates the third sub-stacked structure, the second common electrode layer, and the fourth sub-stacked structure along the stacking direction, and the connection structure connects one first gate layer and one second gate layer. The second direction is perpendicular to both the stacking direction and the first direction.

8. The semiconductor structure according to claim 7, characterized in that, The connection structure includes: A connecting post, which penetrates the third sub-layer structure, the second common electrode layer and the fourth sub-layer structure along the stacking direction; A first connection layer is disposed within the third sub-stack structure, the first connection layer extends in a direction perpendicular to the stacking direction, and the first connection layer is connected to a first gate layer; A second connection layer is disposed within the fourth sub-stack structure. The second connection layer extends in a direction perpendicular to the stacking direction and is connected to a second gate layer.

9. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure includes a first region and a second region, the first region being adjacent to the second region, the first stacked structure and the second stacked structure being located in the first region, and the third stacked structure being located in the second region; The second region is located on one side of the first region in the second direction; Alternatively, the first region may include a first sub-region and a second sub-region, the first sub-region and the second sub-region being arranged along the second direction, and the second region being located between the first sub-region and the second sub-region.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A gate spacer extends along a second direction and penetrates the stacked structure along the stacking direction, and the gate spacer is connected to the first common layer; wherein the second direction is perpendicular to both the stacking direction and the first direction.

11. The semiconductor structure according to any one of claims 1-10, characterized in that, The semiconductor structure also includes: An interconnect layer is disposed on the side of the second bit line away from the second stacked structure. The interconnect layer includes a circuit layer and a plurality of interconnect structures, with the circuit layer located between the interconnect structures and the second bit line. The interconnect structure includes a first interconnect structure, a second interconnect structure, and a third interconnect structure. The first interconnect structure is connected to the second bit line through the circuit layer, the second interconnect structure is connected to the gate spacer through the circuit layer, and the third interconnect structure is connected to the connection structure through the circuit layer.

12. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure also includes: A transistor structure layer is disposed on the side of the interconnect layer away from the second bit line. The transistor structure layer includes a first transistor and a second transistor. The first electrode of the first transistor is connected to the second bit line via the interconnect layer. The second electrode of the first transistor is connected to the gate spacer via the interconnect layer. The control electrode of the second transistor is connected to the interconnect structure via the interconnect layer.

13. A method for fabricating a semiconductor structure, characterized in that, include: A stacked structure is formed, the stacked structure including a first stacked structure and a second stacked structure arranged in a stacked manner; The first stacked structure includes a first stacked structure and a plurality of support portions; the support portions penetrate the first stacked structure along the stacking direction, the first stacked structure includes two first dielectric layers and a support layer, the support layer being disposed between the two first dielectric layers; the second stacked structure includes a second stacked structure and a plurality of channel structures, the channel structures penetrating the second stacked structure along the stacking direction, and one end of one channel structure being connected to one end of one support portion; the second stacked structure includes a first sub-stacked structure, a second sub-stacked structure, and a first common electrode layer, the first sub-stacked structure being disposed on one side of the first stacked structure, the second sub-stacked structure being disposed on the side of the first sub-stacked structure away from the first stacked structure, and the first common electrode layer being disposed between the first sub-stacked structure and the second sub-stacked structure; A plurality of first connecting portions are formed on the side of the first stacked structure away from the second stacked structure, and one of the first connecting portions penetrates one of the support portions along the stacking direction and extends into one of the channel structures; A first bit line is formed on the side of the first connection portion away from the first stacking structure. The first bit line extends along a first direction and is connected to a column of the first connection portions, wherein the first direction is perpendicular to the stacking direction.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The formation of the stacked structure includes: A first initial stacking structure is formed, the first initial stacking structure includes a first initial layer structure and a plurality of support portions, the first initial layer structure includes two first dielectric layers and a first sacrificial layer, the first sacrificial layer is disposed between the two first dielectric layers, and the support portions penetrate the first initial layer structure along the stacking direction; A second initial stack structure is formed by stacking on one side of the first initial stack structure. The second initial stack structure includes a second initial stack structure and a plurality of first sacrificial pillars. The second initial stack structure includes a plurality of alternately stacked second dielectric layers and a plurality of second sacrificial layers. The first sacrificial pillars penetrate the second initial stack structure along the stacking direction, and one end of one of the first sacrificial pillars is connected to one of the support portions. A third initial stacking structure is formed on the side of the second initial stacking structure away from the first initial stacking structure. The third initial stacking structure includes a third sacrificial layer and a third initial stacking structure stacked together, as well as a plurality of second sacrificial pillars. The third sacrificial layer is closer to the second initial stacking structure than the third initial stacking structure. The third initial stacking structure includes a plurality of alternately stacked third dielectric layers and a plurality of fourth sacrificial layers. The second sacrificial pillars penetrate the third initial stacking structure and the third sacrificial layer along the stacking direction, and one end of one second sacrificial pillar is connected to the other end of one first sacrificial pillar. Remove the first sacrificial post and the second sacrificial post to form the channel structure; The first sacrificial layer is replaced with a support layer, the second sacrificial layer is replaced with a first gate layer, the third sacrificial layer is replaced with a first common layer, and the fourth sacrificial layer is replaced with a second gate layer to form the stacked structure.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, Before replacing the first sacrificial layer with a support layer, the second sacrificial layer with a first gate layer, the third sacrificial layer with a first common layer, and the fourth sacrificial layer with a second gate layer, the fabrication method further includes: A gate slit is formed, the gate slit extending along a second direction and penetrating the stacked structure along the stacking direction, wherein the second direction is perpendicular to both the stacking direction and the first direction; The step of replacing the first sacrificial layer with a support layer, replacing the second sacrificial layer with a first gate layer, replacing the third sacrificial layer with a first common layer, and replacing the fourth sacrificial layer with a second gate layer includes: The third sacrificial layer is removed via the gate slit to form a first gap layer; The first common electrode layer is formed within the first gap layer; The first sacrificial layer, the second sacrificial layer, and the fourth sacrificial layer are removed via the gate slit to form a second gap layer, a third gap layer, and a fourth gap layer; The support layer is formed in the second gap layer, the first gate layer is formed in the third gap layer, and the second gate layer is formed in the fourth gap layer.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, Before forming the first common electrode layer within the first gap layer, the preparation method further includes: A portion of the channel structure is removed via the first gap layer to form a third connection.

17. The method for preparing a semiconductor structure according to claim 13, characterized in that, The formation of the stacked structure includes: A first initial stacking structure is formed, the first initial stacking structure includes a first initial layer structure and a plurality of support portions, the first initial layer structure includes two first dielectric layers and a first sacrificial layer, the first sacrificial layer is disposed between the two first dielectric layers, and the support portions penetrate the first initial layer structure along the stacking direction; A fourth initial stacking structure is formed on one side of the first initial stacking structure. The fourth initial stacking structure includes a fourth initial stacked structure and a plurality of third sacrificial pillars. The fourth initial stacked structure includes a plurality of alternately stacked fourth dielectric layers and a plurality of fifth sacrificial layers. The third sacrificial pillars penetrate the fourth initial stacked structure along the stacking direction, and one end of one of the third sacrificial pillars is connected to one of the support portions. A fifth initial stacking structure is formed on the side of the fourth initial stacking structure away from the first initial stacking structure. The fifth initial stacking structure includes a fifth initial layer, a sixth sacrificial layer, a sixth initial layer, and a plurality of fourth sacrificial pillars. The fifth initial layer includes a plurality of alternately stacked fifth dielectric layers and a plurality of seventh sacrificial layers. The sixth initial layer includes a plurality of alternately stacked sixth dielectric layers and a plurality of eighth sacrificial layers. The fourth sacrificial pillars penetrate the fifth initial layer, the sixth sacrificial layer, and the sixth initial stacking structure along the stacking direction, and one end of one fourth sacrificial pillar is connected to the other end of one third sacrificial pillar. A sixth initial stacking structure is formed on the side of the fifth initial stacking structure away from the fourth initial stacking structure. The sixth initial stacking structure includes a seventh initial stacking structure and a plurality of fifth sacrificial pillars. The seventh initial stacking structure includes a plurality of alternately stacked seventh dielectric layers and a plurality of ninth sacrificial layers. The fifth sacrificial pillars penetrate the seventh initial stacking structure along the stacking direction, and one end of one fifth sacrificial pillar is connected to the other end of one fourth sacrificial pillar. Remove the third, fourth, and fifth sacrificial pillars to form the channel structure; The first sacrificial layer is replaced with a support layer, the fifth and seventh sacrificial layers are replaced with a first gate layer, the sixth sacrificial layer is replaced with the first common layer, and the eighth and ninth sacrificial layers are replaced with a second gate layer to form the stacked structure.

18. The method for preparing a semiconductor structure according to claim 17, characterized in that, Before replacing the first sacrificial layer with a support layer, replacing the fifth and seventh sacrificial layers with a first gate layer, replacing the sixth sacrificial layer with the first common layer, and replacing the eighth and ninth sacrificial layers with a second gate layer, the fabrication method further includes: A gate slit is formed, the gate slit extending along a second direction and penetrating the stacked structure along the stacking direction, wherein the second direction is perpendicular to both the stacking direction and the first direction; The step of replacing the first sacrificial layer with a support layer, replacing the fifth and seventh sacrificial layers with a first gate layer, replacing the sixth sacrificial layer with the first common layer, and replacing the eighth and ninth sacrificial layers with a second gate layer includes: The sixth sacrificial layer is removed via the gate slit to form the fifth gap layer; The first common electrode layer is formed within the fifth gap layer; The first sacrificial layer, the fifth sacrificial layer, the seventh sacrificial layer, the eighth sacrificial layer, and the ninth sacrificial layer are removed via the gate slit to form a sixth gap layer, a seventh gap layer, an eighth gap layer, a ninth gap layer, and a tenth gap layer; The support layer is formed in the sixth gap layer, the first gate layer is formed in the seventh and eighth gap layers, and the second gate layer is formed in the ninth and tenth gap layers.

19. The method for preparing a semiconductor structure according to claim 18, characterized in that, Before forming the first common electrode layer within the fifth gap layer, the preparation method further includes: A portion of the channel structure is removed via the fifth gap layer to form the third connection.

20. The method for fabricating a semiconductor structure according to claim 15 or 18, characterized in that, The preparation method further includes: A gate spacer is formed within the gate slit, and the gate spacer is connected to the first common layer.

21. The method for preparing a semiconductor structure according to claim 13, characterized in that, The first connection portion is formed on the side of the first stacked structure away from the second stacked structure, including: Multiple grooves are formed, one of which penetrates one of the support portions along the stacking direction and extends into one of the channel structures; wherein the groove exposes the functional layer, the channel layer, and the support portion of the channel structure; The first connecting portion is formed within the groove.

22. The method for preparing a semiconductor structure according to claim 13, characterized in that, The step of forming a first line on the side of the first connection portion away from the first stacked structure includes: A strip-shaped groove is formed, which extends along the first direction and exposes a row of the first connecting portions; The first bit line is formed within the strip groove.

23. A storage system, characterized in that, include: The semiconductor structure as described in any one of claims 1-12; A controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

24. An electronic device, characterized in that, Includes a motherboard and a storage system as described in claim 23, which is disposed on the motherboard.

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