Semiconductor structure and preparation method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method of the semiconductor structure, a memory and a storage system.The semiconductor structure comprises a first laminated structure and a channel structure, the first laminated structure comprises a first gate layer and a first selection gate, and the first gate layer is located on one side of the first selection gate in the first direction; the channel structure penetrates through the first laminated structure along the first direction; wherein the side wall of the channel structure comprises a first side wall, a second side wall and a connecting surface connected with the first side wall and the second side wall, the first side wall extends in the first selection gate, and the second side wall extends in the first gate layer; the connecting face intersects with the first side wall and the second side wall.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for fabricating semiconductor structures, memories, and memory systems. Background Technology

[0002] Memory is one of the most important components in electronic systems. Flash memory is an important type of memory. Flash memory (also known as flash storage) is characterized by its ability to retain stored information for extended periods without power, and it boasts advantages such as high integration density, fast access speed, and ease of erasing and rewriting, making it the mainstream non-volatile memory. Based on its structure, flash memory is divided into NOR flash memory and NAND flash memory. Compared to NOR flash memory, NAND flash memory offers higher cell density, achieving higher storage density, and also provides faster write and erase speeds. With significant advancements in semiconductor manufacturing processes, three-dimensional (3D) flash memory, such as 3D NAND flash memory, has emerged to pursue lower production costs per unit of storage cell. Summary of the Invention

[0003] This application provides semiconductor structures, methods for fabricating semiconductor structures, memories, and storage systems that can at least partially solve the problems described above or other problems in the art.

[0004] This application provides a semiconductor structure, including a first stacked structure and a channel structure. The first stacked structure includes a first gate layer and a first select gate. The first gate layer is located on one side of the first select gate along a first direction, and the channel structure penetrates the first stacked structure along the first direction. The sidewall of the channel structure includes a first sidewall, a second sidewall, and a connection surface connecting the first sidewall and the second sidewall. The first sidewall extends in the first select gate, and the second sidewall extends in the first gate layer. The connection surface intersects with the first sidewall and the second sidewall, respectively.

[0005] In some embodiments, the channel structure includes a first channel extension and a first channel connection. The first channel extension extends in the first select gate along a first direction and has a first sidewall. The first channel connection is located in a portion of the first gate layer and connected to the first channel extension. The first channel connection has a second sidewall and a connection surface. The dimension of the first channel extension is smaller than the dimension of the end of the first channel connection facing the first channel extension along a direction intersecting the first direction.

[0006] In some embodiments, along the direction intersecting the first direction, the dimension of the end of the first channel extension toward the first channel connector is smaller than the dimension of the end of the first channel connector toward the first channel extension.

[0007] In some embodiments, along a direction intersecting the first direction, the dimension of the end of the first channel extension away from the first channel connector is less than or equal to the dimension of the end of the first channel extension toward the first channel connector.

[0008] In some embodiments, the dimension of the end of the first channel extension away from the first channel connector along the direction intersecting the first direction is 70 nm to 200 nm.

[0009] In some embodiments, the semiconductor structure further includes a first isolation structure that extends through the first select gate along a first direction and is spaced apart from the first gate layer.

[0010] In some embodiments, the first isolation structure extends along a second direction, and the first isolation structure divides the first selection gate into a first sub-selection gate and a second sub-selection gate, which are respectively connected to different channel structures; wherein the second direction intersects the first direction.

[0011] In some embodiments, along a direction intersecting the first direction, the dimension of the end of the first isolation structure away from the first gate layer is greater than the dimension of the end of the first isolation structure facing the first gate layer.

[0012] In some implementations, the first selection gate has multiple layers.

[0013] In some embodiments, the semiconductor structure further includes a semiconductor layer and a second stacked structure, wherein the semiconductor layer is located on one side of the first stacked structure along a first direction, the second stacked structure is located on the side of the semiconductor layer opposite to the first stacked structure, and includes a second gate layer; wherein the first gate layer is located between the first select gate and the semiconductor layer; wherein the channel structure further extends through the second stacked structure and the semiconductor layer along the first direction, and the channel layer and the semiconductor layer in the channel structure are connected.

[0014] In some embodiments, the second stacked structure further includes a second selection gate located on the side of the second gate layer away from the semiconductor layer; wherein the semiconductor structure further includes a second isolation structure that extends through the second selection gate along a first direction and is spaced apart from the second gate layer; wherein, along a direction intersecting the first direction, the dimension of the end of the second isolation structure away from the second gate layer is larger than the dimension of the end of the second isolation structure facing the second gate layer.

[0015] In some embodiments, the second isolation structure extends along a second direction and divides the second selection gate into a third sub-selection gate and a fourth sub-selection gate, which are respectively connected to different channel structures; wherein the second direction intersects the first direction.

[0016] In some embodiments, the channel structure further includes a second channel extension and a third channel extension, the second channel extension extending in the semiconductor layer and a portion of the first gate layer along a first direction, and the third channel extension extending in the second stacked structure along the first direction; wherein, along a direction intersecting the first direction, the dimension of the end of the second channel extension toward the first channel connection is smaller than the dimension of the end of the first channel connection toward the second channel extension, and the dimension of the end of the second channel extension away from the first channel connection is larger than the dimension of the end of the third channel extension toward the side of the second channel extension.

[0017] In some embodiments, the channel structure further includes a second channel extension that extends along a first direction in the semiconductor layer and a portion of the first gate layer; wherein a portion of the first channel connection extends along the first direction into the second channel extension.

[0018] In some embodiments, the channel structure further includes a second channel extension and a third channel extension, the second channel extension extending along a first direction in the semiconductor layer and a portion of the first gate layer, and the third channel extension extending along the first direction in the second stacked structure; wherein the first channel extension, the first channel connection, the second channel extension, and the third channel extension together include a functional layer and a channel layer; or, the first channel extension and the first channel connection together include an isolation layer and a conductive layer, the isolation layer being located on the sidewall of the conductive layer; the second channel extension and the third channel extension together include a functional layer and a channel layer extending along the first direction, and the conductive layer and the channel layer are connected.

[0019] In some embodiments, the material of the conductive layer includes any one of polysilicon, doped polysilicon, metallic materials, or metal silicides.

[0020] In some embodiments, the semiconductor structure further includes an insulating protective layer located on one side of the first stacked structure in a direction opposite to the first direction; wherein the first channel extension penetrates the insulating protective layer.

[0021] In some implementations, potentials with different timings are applied to the first select gate and the first gate layer.

[0022] In some implementations, potentials with different timings are applied on the second select gate and the second gate layer.

[0023] Another embodiment of the present invention provides a method for fabricating a semiconductor structure, comprising: forming a first stacked structure; forming a channel structure; wherein the first stacked structure includes a first gate layer and a first select gate, the first gate layer being located on one side of the first select gate along a first direction; the channel structure penetrating the first stacked structure along the first direction; wherein the sidewalls of the channel structure include a first sidewall, a second sidewall, and a connection surface connecting the first sidewall and the second sidewall, the first sidewall extending in the first select gate, the second sidewall extending in the first gate layer; and the connection surface intersecting the first sidewall and the second sidewall respectively.

[0024] In some embodiments, forming a channel structure includes: forming a first channel extension and a first channel connection, the first channel extension extending in a first select gate along a first direction, the first channel extension having a first sidewall, the first channel connection being located in a portion of the first gate layer and connected to the first channel extension, the first channel connection having a second sidewall and a connection surface; wherein, along a direction intersecting the first direction, the size of the first channel extension is smaller than the size of the end of the first channel connection toward the first channel extension.

[0025] In some embodiments, forming the first stacked structure includes: forming a first initial sub-stacked structure, the first initial sub-stacked structure including a first sacrificial dielectric layer; forming a second initial sub-stacked structure on one side of the first initial sub-stacked structure along a first direction, the second initial sub-stacked structure including a second sacrificial dielectric layer; replacing at least a portion of the first sacrificial dielectric layer with a first select gate; and replacing at least a portion of the second sacrificial dielectric layer with a first gate layer.

[0026] In some embodiments, forming the first channel extension includes: forming a first sacrificial channel extension in a first initial sub-stack structure; and replacing the first sacrificial channel extension with the first channel extension; wherein forming the first channel connection includes: forming a first sacrificial channel connection in a portion of a second initial sub-stack structure; and replacing the first sacrificial channel connection with the first channel connection.

[0027] In some embodiments, forming a first sacrificial channel extension in a first initial sub-stack structure includes: forming a first extension opening in the first initial sub-stack structure; and forming a first sacrificial channel extension in the first extension opening.

[0028] In some embodiments, forming a first sacrificial channel connection in a portion of the second initial sub-stack structure includes: forming a first contact opening in the portion of the second initial sub-stack structure, the first contact opening exposing a first sacrificial channel extension; the size of the first contact opening being larger than the size of the first sacrificial channel extension along a direction intersecting a first direction; and forming the first sacrificial channel connection in the first contact opening.

[0029] In some implementations, the material of the first sacrificial channel extension is different from the material of the second initial sub-stack structure.

[0030] In some embodiments, replacing the first sacrificial channel extension with the first channel extension includes: replacing the first sacrificial channel extension with the first channel extension on one side of the first laminated structure in the direction opposite to the first direction; wherein, replacing the first sacrificial channel connection with the first channel connection includes: replacing the first sacrificial channel connection with the first channel connection on one side of the first laminated structure in the direction opposite to the first direction.

[0031] In some embodiments, replacing the first sacrificial channel extension with the first channel extension includes: replacing the first sacrificial channel extension with the first channel extension on the side of the second initial sub-stack structure opposite to the first initial sub-stack structure; wherein, replacing the first sacrificial channel connection with the first channel connection includes: replacing the first sacrificial channel connection with the first channel connection on the side of the second initial sub-stack structure opposite to the first initial sub-stack structure.

[0032] In some embodiments, forming the first channel extension includes forming the first channel extension in the first initial sub-stack structure before forming the second initial sub-stack structure; wherein forming the first channel connection includes forming the first channel connection in a portion of the second initial sub-stack structure.

[0033] In some embodiments, forming the first channel extension and the first channel connection includes forming an isolation layer and a conductive layer, wherein the isolation layer is located on the sidewall of the conductive layer; or, forming the first channel extension and the first channel connection includes forming a first functional portion and a first channel portion extending along a first direction.

[0034] In some embodiments, the fabrication method further includes: forming a semiconductor layer; forming a second stacked structure; wherein the semiconductor layer is located on one side of the first stacked structure along a first direction, the second stacked structure is located on the side of the semiconductor layer opposite to the first stacked structure, and the second stacked structure includes a second gate layer; wherein the first gate layer is located between a first select gate and the semiconductor layer; wherein the channel structure further extends through the second stacked structure and the semiconductor layer along the first direction, and the channel layer and the semiconductor layer in the channel structure are connected.

[0035] In some embodiments, forming the first stacked structure and the second stacked structure includes: forming the first stacked structure and the second stacked structure on one side of a temporary substrate; wherein the fabrication method further includes: after forming the first stacked structure and the second stacked structure, removing the temporary substrate; and after removing the temporary substrate, forming a first isolation structure in a first select gate, the first isolation structure being spaced apart from the first gate layer.

[0036] In some embodiments, the fabrication method further includes: after removing the temporary substrate, forming an insulating protective layer on the side of the first stacked structure opposite to the direction opposite to the first direction; wherein the first channel extension penetrates the insulating protective layer.

[0037] In some implementations, an insulating protective layer is formed during the formation of the first isolation structure.

[0038] This application also provides a memory, including a memory cell array, the memory cell array including a semiconductor structure as mentioned in any of the embodiments above; and peripheral circuitry coupled to the memory cell array.

[0039] In another aspect, this application provides a storage system, including a controller and a memory as mentioned in any of the embodiments above, wherein the controller is coupled to the memory and is used to control the memory to store data. Attached Figure Description

[0040] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0041] Figure 1 A semiconductor structure Figure 2

[0042] Figure 2 The structure of a semiconductor structure according to an exemplary embodiment of this application. Figure 2

[0043] Figure 3 for Figure 2 Enlarged view of part of the channel structure within the dashed box W Figure 2

[0044] Figure 4 The structure of a semiconductor structure according to yet another embodiment of this application Figure 2

[0045] Figure 5 for Figure 2 Enlarged view of part of the channel structure in the dashed box K Figure 2

[0046] Figure 6 The structure of a semiconductor structure according to yet another embodiment of this application Figure 2

[0047] Figure 7 for Figure 6 Enlarged view of part of the channel structure in the dashed box W1 Figure 2

[0048] Figure 8 The structure of a semiconductor structure according to yet another embodiment of this application Figure 2

[0049] Figure 9 for Figure 8 Enlarged view of part of the channel structure in the dashed box K1 Figure 2

[0050] Figure 10 The process flow of a semiconductor structure fabrication method according to an embodiment of this application Figure 2

[0051] Figures 11 to 26 The structure of the semiconductor structure fabrication process according to an embodiment of this application. Figure 2

[0052] Figures 27 to 30 The structure of the semiconductor structure fabrication process according to another embodiment of this application Figure 2

[0053] Figures 31 to 36 The structure of the semiconductor structure fabrication process according to another embodiment of this application Figure 2

[0054] Figures 37 to 43 The structure of the semiconductor structure fabrication process according to another embodiment of this application Figure 2

[0055] Figure 44 This is a schematic diagram of the structure of a memory according to an exemplary embodiment of this application. Figure 2 as well as

[0056] Figure 45 This is a schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0057] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0059] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0060] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0061] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0062] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0063] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0064] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0065] This application provides a semiconductor structure in some embodiments. Figure 2 The structure of semiconductor structure 100000 according to an exemplary embodiment of this application. Figure 2 Figure 3 for Figure 2 Enlarged view of part of the channel structure within the dashed box W Figure 2 Figure 4The structure of semiconductor structure 100000 according to another embodiment of this application. Figure 2 Figure 5 for Figure 2 Enlarged view of part of the channel structure in the dashed box K Figure 2 Figure 6 The structure of semiconductor structure 100000 according to another embodiment of this application. Figure 2 Figure 7 for Figure 6 Enlarged view of part of the channel structure in the dashed box W1 Figure 2 Figure 8 The structure of semiconductor structure 100000 according to another embodiment of this application. Figure 2 Figure 9 for Figure 8 Enlarged view of part of the channel structure in the dashed box K1.

[0066] refer to Figure 2 , Figure 4 , Figure 6 and Figure 8 The semiconductor structure 100000 includes a first stacked structure 100 and a channel structure 500. The first stacked structure 100 includes a first gate layer 103 and a first select gate 102, with the first gate layer 103 located on one side of the first select gate 102 along a first direction Z. The channel structure 500 extends through the first stacked structure 100 along the first direction Z.

[0067] refer to Figure 3 , Figure 5 , Figure 7 and Figure 9 The channel structure 500 has sidewalls including a first sidewall D1, a second sidewall D2, and a connecting surface D3 connecting the first sidewall D1 and the second sidewall D2. The first sidewall D1 extends in the first select gate 102, and the second sidewall D2 extends in the first gate layer 103. The connecting surface D3 intersects with the first sidewall D1 and the second sidewall D2, respectively.

[0068] In some implementations, reference Figure 2 , Figure 4 , Figure 6 and Figure 8 The channel structure 500 includes a first channel extension 502 and a first channel connection 501. The first channel extension 502 extends in the first select gate 102 along a first direction Z and has a first sidewall D1. The first channel connection 501 is located in a portion of the first gate layer 103 and is connected to the first channel extension 502. The first channel connection 501 has a second sidewall D2 and a connection surface D3. Along a direction intersecting the first direction Z, the size of the first channel extension 502 is smaller than the size of the end of the first channel connection 501 facing the first channel extension 502.

[0069] For example, the dimension of the first channel extension 502 along the second direction Y is smaller than the dimension of the first channel connector 501 toward the end of the first channel extension 502 along the second direction Y. The dimension of the first channel extension 502 along the third direction X is smaller than the dimension of the first channel connector 501 toward the end of the first channel extension 502 along the third direction X.

[0070] In at least one embodiment of this application, the size of the first channel extension 502 is smaller than the size of the end of the first channel connection 501 facing the first channel extension 502 along the direction intersecting the first direction Z. The first channel extension 502 is smaller along the direction intersecting the first direction Z. Therefore, the first channel extension 502 can serve as an alignment mark when performing process operations on the side of the first channel extension 502 away from the first channel connection 501.

[0071] Semiconductor structure 100000 can be a memory cell array, or it can be a part of a memory cell array.

[0072] In some embodiments, along a direction intersecting the first direction Z, the dimension of the end of the first channel extension 502 toward the first channel connection 501 is smaller than the dimension of the end of the first channel connection 501 toward the first channel extension 502. For example, the dimension of the end of the first channel extension 502 toward the first channel connection 501 along the second direction Y is smaller than the dimension of the end of the first channel connection 501 toward the first channel extension 502 along the second direction Y, and the dimension of the end of the first channel extension 502 toward the first channel connection 501 along the third direction X is smaller than the dimension of the end of the first channel connection 501 toward the first channel extension 502 along the third direction X.

[0073] In some embodiments, along the direction intersecting the first direction Z, the dimension of the end of the first channel extension 502 away from the first channel connector 501 is less than or equal to the dimension of the end of the first channel extension 502 facing the first channel connector 501. When the dimension of the end of the first channel extension 502 away from the first channel connector 501 along the direction intersecting the first direction Z is less than the dimension of the end of the first channel extension 502 facing the first channel connector 501 along the direction intersecting the first direction Z, the dimension of the end of the first channel extension 502 away from the first channel connector 501 along the direction intersecting the first direction Z is even smaller. The end of the first channel extension 502 away from the first channel connector 501 serves as an alignment mark during process operations on the side of the first channel extension 502 away from the first channel connector 501. The smaller dimension of the alignment mark along the direction intersecting the first direction Z facilitates process alignment.

[0074] For example, the dimension of the first channel extension 502 away from the end of the first channel connection 501 along the second direction Y is less than or equal to the dimension of the first channel extension 502 toward the end of the first channel connection 501 along the second direction Y, and the dimension of the first channel extension 502 away from the end of the first channel connection 501 along the third direction X is less than or equal to the dimension of the first channel extension 502 toward the end of the first channel connection 501 along the third direction X.

[0075] In some embodiments, the dimension of the end of the first channel extension 502 away from the first channel connector 501 along the direction intersecting the first direction Z is 70 nm to 200 nm. For example, the dimension of the end of the first channel extension 502 away from the first channel connector 501 along the second direction Y is 70 nm to 200 nm, and the dimension of the end of the first channel extension 502 away from the first channel connector 501 along the third direction X is 70 nm to 200 nm.

[0076] In some embodiments, the first selection gate 102 has multiple layers. The first channel extension 502 extends through multiple layers of the first selection gate 102, and the dimension of the first channel extension 502 increases along the first direction Z. When the dimension of the end of the first channel extension 502 away from the first channel connection 501 in the direction intersecting the first direction Z is smaller than the dimension of the end of the first channel extension 502 towards the first channel connection 501 in the direction intersecting the first direction Z, and the dimension of the end of the first channel extension 502 towards the first channel connection 501 in the direction intersecting the first direction Z is within a certain range, the larger the dimension of the first channel extension 502 along the first direction Z, the smaller the dimension of the end of the first channel extension 502 away from the first channel connection 501 in the direction intersecting the first direction Z. The smaller the dimension of the alignment mark of the end of the first channel extension 502 away from the first channel connection 501 in the direction intersecting the first direction Z, the better for process alignment.

[0077] In some implementations, reference Figure 2 , Figure 4 , Figure 6 and Figure 8 The semiconductor structure 100000 further includes a semiconductor layer 300 and a second stacked structure 200. The semiconductor layer 300 is located on one side of the first stacked structure 100 along the first direction Z, and the second stacked structure 200 is located on the side of the semiconductor layer 300 opposite to the first stacked structure 100. The second stacked structure 200 includes a second gate layer 203. The first gate layer 103 is located between the first select gate 102 and the semiconductor layer 300. The channel structure 500 also extends along the first direction Z through the second stacked structure 200 and the semiconductor layer 300, and the channel layer in the channel structure 500 is connected to the semiconductor layer 300.

[0078] In some implementations, reference Figure 2 , Figure 4 , Figure 6 and Figure 8 The first stacked structure 100 includes a first gate layer 103 and a first select gate 102, with the first gate layer 103 located on one side of the first select gate 102 along a first direction Z. The second stacked structure 200 includes a second select gate 202 and a second gate layer 203, with the second select gate 202 located on the side of the second gate layer 203 opposite to the semiconductor layer 300.

[0079] Potentials with different timings are applied to the first selection gate 102 and the first gate layer 103. Potentials with different timings are also applied to the second selection gate 202 and the second gate layer 203.

[0080] In some embodiments, the material of the first gate layer 103 includes any one of a metal gate material and a polysilicon gate material. For example, the material of the first gate layer 103 can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, and silicides. Exemplarily, the material of the first gate layer 103 is a combination of titanium nitride and tungsten.

[0081] In some embodiments, the material of the first selection gate 102 includes any one of a metal gate material and a polycrystalline silicon gate material. For example, the material of the first selection gate 102 can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, and silicides. For instance, the material of the first selection gate 102 is a combination of titanium nitride and tungsten.

[0082] In some embodiments, the material of the second selection gate 202 includes any one of a metal gate material and a polycrystalline silicon gate material. For example, the material of the second selection gate 202 can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, and silicides. For instance, the material of the second selection gate 202 is a combination of titanium nitride and tungsten.

[0083] In some embodiments, the material of the second gate layer 203 includes any one of a metal gate material and a polysilicon gate material. For example, the material of the second gate layer 203 can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, and silicides. Exemplarily, the material of the second gate layer 203 is a combination of titanium nitride and tungsten.

[0084] In some implementations, reference Figure 2 , Figure 4 , Figure 6 and Figure 8 The first stacked structure 100 further includes a first insulating layer 101, which is located between adjacent first gate layers 103, between the first gate layer 103 and the first select gate 102, between the first gate layer 103 and the semiconductor layer 300, and between adjacent first select gates 102.

[0085] In some embodiments, the material of the first insulating layer 101 includes, but is not limited to, insulating dielectric materials such as silicon oxide.

[0086] In some implementations, reference Figure 2 , Figure 4 , Figure 6 and Figure 8 The second stacked structure 200 further includes a second insulating layer 201, which is located between adjacent second gate layers 203, between the second gate layers 203 and the second selection gate 202, between the second gate layers 203 and the semiconductor layer 300, and between adjacent second selection gates 202.

[0087] In some embodiments, the material of the second insulating layer 201 includes, but is not limited to, insulating dielectric materials such as silicon oxide.

[0088] In some embodiments, the first stacked structure 100 further includes a third select gate (not shown), located between the first gate layer 103 and the semiconductor layer 300. The second stacked structure 200 further includes a fourth select gate (not shown), located between the second gate layer 203 and the semiconductor layer 300. The third select gate has one or more layers. The fourth select gate has one or more layers.

[0089] In some embodiments, the first insulating layer 101 is also located between the first gate layer 103 and the third select gate, between adjacent third select gates, and between the third select gate and the semiconductor layer 300. The second insulating layer 201 is also located between the fourth select gate and the second gate layer 203, between adjacent fourth select gates, and between the fourth select gate and the semiconductor layer 300.

[0090] In some embodiments, the material of the third selection gate includes any one of a metal gate material and a polycrystalline silicon gate material. For example, the material of the third selection gate can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, and silicides. Exemplarily, the material of the third selection gate is a combination of titanium nitride and tungsten. The material of the fourth selection gate includes any one of a metal gate material and a polycrystalline silicon gate material. For example, the material of the fourth selection gate can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride, doped crystalline silicon, and silicides. Exemplarily, the material of the fourth selection gate is a combination of titanium nitride and tungsten.

[0091] Furthermore, the number of layers of the first insulating layer 101, the second insulating layer 201, the first gate layer 103, the second gate layer 203, the first selection gate 102, and the second selection gate 202 are not limited to the following: Figure 2 , Figure 4 , Figure 6 and Figure 8 The number of layers shown can be set separately as needed. The number of layers in the first stacked structure 100 and the number of layers in the second stacked structure 200 are not limited to... Figure 2 , Figure 4 , Figure 6 and Figure 8 The number of layers shown can be set separately as needed.

[0092] In some embodiments, the multilayer first gate layer 103 includes a first gate layer to a Wth gate layer arranged along a first direction Z. The spacing between the first gate layer to the Wth gate layer and the semiconductor layer 300 decreases along the first direction Z. The multilayer second gate layer 203 includes a first gate layer to a Wth gate layer arranged along the first direction Z, where W is an integer greater than or equal to 2. The spacing between the first gate layer to the Wth gate layer and the semiconductor layer 300 increases along the first direction Z. The Vth gate layer and the Vth second gate layer are connected; exemplarily, the Vth gate layer and the Vth second gate layer are connected to the same contact structure (not shown), where V is an integer greater than or equal to 1 and less than or equal to W.

[0093] In some implementations, reference Figure 2 , Figure 4 , Figure 6 and Figure 8The channel structure 500 further includes a second channel extension 503 and a third channel extension 504. The second channel extension 503 extends along a first direction Z in the semiconductor layer 300 and a portion of the first gate layer 103, and the third channel extension 504 extends along the first direction Z in the second stacked structure 200. The second channel extension 503 may also extend along the first direction Z in a portion of the second gate layer 203 and a portion of the second insulating layer 201. The second channel extension 503 is located between the third channel extension 504 and the first channel connection portion 501, and the second channel extension 503 is connected to both the third channel extension 504 and the first channel connection portion 501.

[0094] The channel structure 500 extends along the first direction Z through the second stacked structure 200, the semiconductor layer 300, and the first stacked structure 100. The portions of the channel structure 500 in the first stacked structure 100 and the portions in the second stacked structure 200 share a common source, reducing the equivalent channel length and lowering the limitation imposed by the channel saturation current limit on the number of layers in the semiconductor structure 100,000. The first stacked structure 100 and the second stacked structure 200 are arranged along the first direction Z, causing the size of the semiconductor structure 100,000 to decrease along the direction intersecting the first direction Z.

[0095] In some embodiments, along the direction intersecting the first direction Z, the dimension of the end of the second channel extension 503 facing the first channel connection 501 is smaller than the dimension of the end of the first channel connection 501 facing the second channel extension 503, and the dimension of the end of the second channel extension 503 away from the first channel connection 501 is larger than the dimension of the end of the third channel extension 504 facing one side of the second channel extension 503. For example, the dimension of the end of the second channel extension 503 facing the first channel connection 501 along the second direction Y is smaller than the dimension of the end of the first channel connection 501 facing the second channel extension 503 along the second direction Y, and the dimension of the end of the second channel extension 503 facing the first channel connection 501 along the third direction X is smaller than the dimension of the end of the first channel connection 501 facing the second channel extension 503 along the third direction X. For example, the dimension of the end of the second channel extension 503 away from the first channel connection 501 along the second direction Y is greater than the dimension of the end of the third channel extension 504 facing the second channel extension 503 along the second direction Y, and the dimension of the end of the second channel extension 503 away from the first channel connection 501 along the third direction X is greater than the dimension of the end of the third channel extension 504 facing the second channel extension 503 along the third direction X.

[0096] In other embodiments, along a direction intersecting the first direction Z, the dimension of the end of the second channel extension toward the first channel connector is greater than or equal to the dimension of the end of the first channel connector toward the second channel extension, and the dimension of the end of the second channel extension away from the first channel connector is less than or equal to the dimension of the end of the third channel extension toward the side of the second channel extension.

[0097] In some implementations, the second direction Y intersects the first direction Z, the third direction X intersects the first direction Z, and the second direction Y intersects the third direction X. For example, the second direction Y is perpendicular to the first direction Z, the third direction X is perpendicular to the first direction Z, and the second direction Y is perpendicular to the third direction X.

[0098] In some implementations, reference Figure 2 and Figure 3 The channel structure 500 includes a channel layer 512, a functional layer 511, and a filling dielectric layer 513. The channel layer 512, functional layer 511, and filling dielectric layer 513 extend along a first direction Z. A first channel extension 502, a first channel connection 501, a second channel extension 503, and a third channel extension 504 together include the functional layer 511, the channel layer 512, and the filling dielectric layer 513. The functional layer 511 exposes the channel layer 512 within the semiconductor layer 300, thus establishing contact between the semiconductor layer 300 and the channel layer 512.

[0099] In some embodiments, the functional layer 511 includes a barrier layer, a charge trapping layer, and a tunneling layer, all of which extend along a first direction Z. The charge trapping layer is located between the barrier layer and the tunneling layer, and the tunneling layer is located between the charge trapping layer and the channel layer 512.

[0100] In some embodiments, the barrier layer is made of silicon oxide, the charge trapping layer is made of silicon nitride, and the tunneling layer is made of silicon oxide. The channel layer 512 is made of, for example, polysilicon or doped polysilicon. The filling dielectric layer is made of, but is not limited to, insulating dielectric materials such as silicon oxide.

[0101] In some implementations, reference Figure 6 and Figure 7The channel structure 500 includes a channel layer, a functional layer, and a filling dielectric layer, which extend along a first direction Z. A first channel extension 502, a first channel connection 501, a second channel extension 503, and a third channel extension 504 together include the functional layer, the channel layer, and the filling dielectric layer. The functional layer exposes the channel layer in the semiconductor layer 300, thus contacting the semiconductor layer 300 and the channel layer. The channel layer includes a connected first channel portion 552 and a second channel portion 562, which extend along the first direction Z, with the second channel portion 562 located on one side of the first channel portion 552 along the first direction Z. The functional layer includes a first functional portion 551 and a second functional portion 561, which extend along the first direction Z, with the second functional portion 561 located on one side of the first functional portion 551 along the first direction Z. The filling dielectric layer includes a first filling dielectric portion 553 and a second filling dielectric portion 563, which extend along a first direction Z. The second filling dielectric portion 563 is located on one side of the first filling dielectric portion 553 along the first direction Z. The first channel extension portion 502 and the first channel connection portion 501 together include a first functional portion 551, a first channel portion 552, and a first filling dielectric portion 553. The second channel extension portion 503 and the third channel extension portion 504 together include a second functional portion 561, a second channel portion 562, and a second filling dielectric portion 563. The second functional portion 561 exposes the second channel portion 562 in the semiconductor layer 300, and the semiconductor layer 300 and the second channel portion 562 are in contact.

[0102] In some embodiments, the first functional part 551 includes a first blocking part, a first charge capturing part, and a first tunneling part, all of which extend along a first direction Z. The first charge capturing part is located between the first blocking part and the first tunneling part, and the first tunneling part is located between the first charge capturing part and the first channel part 552. The second functional part 561 includes a second blocking part, a second charge capturing part, and a second tunneling part, all of which extend along the first direction Z. The second charge capturing part is located between the second blocking part and the second tunneling part, and the second tunneling part is located between the second charge capturing part and the second channel part 562.

[0103] In some embodiments, the materials of the first and second blocking portions include silicon oxide, the materials of the first and second charge trapping portions include silicon nitride, and the materials of the first and second tunneling portions include silicon oxide. The materials of the first channel portion 552 and the second channel portion 562 are, for example, polycrystalline silicon or doped polycrystalline silicon. The materials of the first filling dielectric portion 553 and the second filling dielectric portion 563 include, but are not limited to, insulating dielectric materials such as silicon oxide.

[0104] In some implementations, reference Figure 4 , Figure 5 , Figure 8 and Figure 9 The channel structure 500 includes a channel layer 522, a functional layer 521, a filling dielectric layer 523, an isolation layer 541, and a conductive layer 542, all of which extend along a first direction Z. The first channel extension 502 and the first channel connection 501 together include the isolation layer 541 and the conductive layer 542, with the isolation layer 541 located on the sidewall of the conductive layer 542. The second channel extension 503 and the third channel extension 504 together include the functional layer 521, the channel layer 522, and the filling dielectric layer 523. The conductive layer 542 is connected to the channel layer 522. The functional layer 521 exposes the channel layer 522 within the semiconductor layer 300, thus allowing the semiconductor layer 300 to contact the channel layer 522.

[0105] In some embodiments, the material of the conductive layer 542 includes any one of polycrystalline silicon, doped polycrystalline silicon, metallic materials, or metal silicides.

[0106] In some embodiments, the material of the insulating layer 541 includes an insulating dielectric material, such as silicon oxide or silicon nitride.

[0107] In some embodiments, the channel layer 522 is made of, for example, polysilicon or doped polysilicon. The filling dielectric layer 523 is made of an insulating dielectric material, such as silicon oxide or silicon nitride.

[0108] In some embodiments, the material of the conductive layer 542 is different from the material of the channel layer 522. In other embodiments, the material of the conductive layer 542 is the same as the material of the channel layer 522.

[0109] In some embodiments, functional layer 521 includes a barrier layer, a charge trapping layer, and a tunneling layer, all of which extend along a first direction Z. The charge trapping layer is located between the barrier layer and the tunneling layer, and the tunneling layer is located between the charge trapping layer and the channel layer 522. The materials of the barrier layer, the charge trapping layer, and the tunneling layer are as described in the foregoing embodiments.

[0110] In some implementations, in conjunction with reference Figure 6 , Figure 7 ,refer to Figure 8 and Figure 9 A portion of the first channel connecting portion 501 extends along the first direction Z into the second channel extension portion 503. (See reference) Figure 6 and Figure 7A portion of the first filling medium portion 553 and a portion of the first channel portion 552 extend along the first direction Z into the second filling medium portion 563. (See reference) Figure 8 and Figure 9 A portion of the conductive layer 542 extends in the first direction Z into the filling dielectric layer 523.

[0111] Figure 1 A semiconductor structure is illustrated, comprising a first stacked structure 10, a semiconductor layer 30, a second stacked structure 20, and a channel structure 40. The second stacked structure 20 is located on the side of the semiconductor layer 30 facing away from the first stacked structure 10 along a first direction Z. The first stacked structure 10 includes a first gate layer 12, a first select gate 11, and a second select gate 14. The first gate layer 12 is located between the second select gate 14 and the first select gate 11, and the second select gate 14 is located between the first gate layer 12 and the semiconductor layer 30. The second stacked structure 20 includes a second gate layer 22, a third select gate 21, and a fourth select gate 24. The second gate layer 22 is located between the third select gate 21 and the fourth select gate 24, and the fourth select gate 24 is located between the second gate layer 22 and the semiconductor layer 30. The channel structure 40 penetrates the first stacked structure 10, the second stacked structure 20, and the semiconductor layer 30 along the first direction Z. The channel structure 40 includes a first portion located in the first stacked structure 10, a second portion located in the second stacked structure 20, and a third portion located in the semiconductor layer 30. The dimension of the first portion in a direction perpendicular to the first direction Z varies linearly along the first direction Z, and the dimension of the end of the first portion away from the second portion in a direction perpendicular to the first direction Z needs to be reduced relative to the requirements of alignment marks.

[0112] However, in this embodiment, the size of the first channel extension 502 is smaller than the size of the end of the first channel connection 501 facing the first channel extension 502 along the direction intersecting with the first direction Z. Therefore, the first channel extension 502 can serve as an alignment mark when performing process operations on the side of the first channel extension 502 away from the first channel connection 501.

[0113] In some implementations, reference Figure 2 , Figure 4 , Figure 6 and Figure 8 The semiconductor structure 100000 also includes a first isolation structure 600, which extends through the first select gate 102 along a first direction Z and is spaced apart from the first gate layer 103. The first isolation structure 600 extends along a second direction Y, dividing the first select gate 102 into a first sub-select gate and a second sub-select gate. The first sub-select gate and the second sub-select gate are respectively connected to different channel structures 500. The first sub-select gate and the second select gate are respectively connected to different first channel extensions 502.

[0114] In some embodiments, along a direction intersecting the first direction Z, the dimension of the end of the first isolation structure 600 opposite to the first gate layer 103 is larger than the dimension of the end of the first isolation structure 600 toward the first gate layer 103. For example, the dimension of the end of the first isolation structure 600 opposite to the first gate layer 103 along a third direction X is larger than the dimension of the end of the first isolation structure 600 toward the first gate layer 103 in the third direction X. In other embodiments, the dimension of the end of the first isolation structure opposite to the first gate layer 103 along a third direction X is less than or equal to the dimension of the end of the first isolation structure toward the first gate layer 103 in the third direction X.

[0115] In some embodiments, the material of the first isolation structure 600 includes, but is not limited to, insulating dielectric materials such as silicon oxide.

[0116] In some embodiments, the semiconductor structure 100000 further includes a second isolation structure 700, which extends through the second select gate 202 along a first direction Z and is spaced from the second gate layer 203. Along a direction intersecting the first direction Z, the dimension of the end of the second isolation structure 700 opposite to the second gate layer 203 is larger than the dimension of the end of the second isolation structure 700 toward the second gate layer 203. For example, the dimension of the end of the second isolation structure 700 opposite to the second gate layer 203 along a third direction X is larger than the dimension of the end of the second isolation structure 700 toward the second gate layer 203 along a third direction X.

[0117] In other embodiments, the dimension of the end of the second isolation structure away from the second gate layer 203 along the third direction X is less than or equal to the dimension of the end of the second isolation structure facing the second gate layer 203 along the third direction X.

[0118] In some embodiments, the second isolation structure 700 extends along the second direction Y, dividing the second selection gate 202 into a third sub-selection gate and a fourth sub-selection gate, which are respectively connected to different channel structures 500. The third sub-selection gate and the fourth sub-selection gate are respectively connected to different third channel extensions 504.

[0119] In some embodiments, the material of the second isolation structure 700 includes, but is not limited to, insulating dielectric materials such as silicon oxide.

[0120] In some embodiments, the semiconductor structure 100000 further includes an insulating protective layer C located on one side of the first stacked structure 100 in a direction opposite to the first direction Z. Exemplarily, the insulating protective layer C is located on the side of the first stacked structure 100 opposite to the second stacked structure 200. The material of the insulating protective layer C includes, but is not limited to, insulating dielectric materials such as silicon oxide.

[0121] In some embodiments, the insulating protective layer C is made of the same material as the first insulating structure 600. In other embodiments, the insulating protective layer C is made of a different material than the first insulating structure 600.

[0122] In some embodiments, the material of the insulating protective layer C and the first isolation structure 600 are integrally formed.

[0123] In some embodiments, the first channel extension 502 penetrates the insulating protective layer C.

[0124] In some embodiments, the semiconductor structure 100000 further includes a first bit line (not shown) and a second bit line (not shown). The first bit line is located on the side of the first stacked structure 100 opposite to the second stacked structure 200 and is connected to the first channel extension 502. The second bit line is located on the side of the second stacked structure 200 opposite to the first stacked structure 100 and is connected to the third channel extension 504.

[0125] In some implementations, the first bit line and the second bit line, which are connected to the same channel structure 500, are isolated. The first bit line and the second bit line are controlled independently.

[0126] In some embodiments, the semiconductor structure 100000 also includes bit line interconnects (not shown). The first bit line and the second bit line, which are connected to the same channel structure 500, are connected via the bit line interconnects.

[0127] It should be noted that in other implementations, bit line connection lines may not be required.

[0128] Another embodiment of this application provides a method for fabricating a semiconductor structure, see reference. Figure 10 ,include:

[0129] Step S1: Form the first stacked structure;

[0130] Step S2: Form the channel structure.

[0131] The first stacked structure includes a first gate layer and a first select gate, with the first gate layer located on one side of the first select gate along a first direction; a channel structure extends through the first stacked structure along the first direction. The sidewalls of the channel structure include a first sidewall, a second sidewall, and a connecting surface connecting the first sidewall and the second sidewall, with the first sidewall extending in the first select gate and the second sidewall extending in the first gate layer; the connecting surface intersects with the first sidewall and the second sidewall, respectively.

[0132] In some embodiments, forming a channel structure includes: forming a first channel extension and a first channel connection, the first channel extension extending in a first select gate along a first direction, the first channel extension having a first sidewall, the first channel connection being located in a portion of the first gate layer and connected to the first channel extension, the first channel connection having a second sidewall and a connection surface; wherein, along a direction intersecting the first direction, the size of the first channel extension is smaller than the size of the end of the first channel connection toward the first channel extension.

[0133] In some embodiments, the method for fabricating a semiconductor structure further includes: forming a semiconductor layer; forming a second stacked structure; wherein the semiconductor layer is located on one side of the first stacked structure along a first direction, the second stacked structure is located on the side of the semiconductor layer away from the first stacked structure, and the second stacked structure includes a second gate layer; wherein the first gate layer is located between a first select gate and the semiconductor layer; wherein the channel structure further extends through the second stacked structure and the semiconductor layer along the first direction, and the channel layer and the semiconductor layer in the channel structure are connected.

[0134] In some embodiments, forming the first stacked structure includes: forming a first initial sub-stacked structure, the first initial sub-stacked structure including a first sacrificial dielectric layer; forming a second initial sub-stacked structure on one side of the first initial sub-stacked structure along a first direction, the second initial sub-stacked structure including a second sacrificial dielectric layer; replacing at least a portion of the first sacrificial dielectric layer with a first select gate; and replacing at least a portion of the second sacrificial dielectric layer with a first gate layer.

[0135] In some embodiments, forming the first channel extension includes: forming a first sacrificial channel extension in a first initial sub-stack structure; and replacing the first sacrificial channel extension with the first channel extension. Forming the first channel connection includes: forming a first sacrificial channel connection in a portion of a second initial sub-stack structure; and replacing the first sacrificial channel connection with the first channel connection.

[0136] In some embodiments, forming a first sacrificial channel extension in a first initial sub-stack structure includes: forming a first extension opening in the first initial sub-stack structure; and forming a first sacrificial channel extension in the first extension opening.

[0137] In some embodiments, forming a first sacrificial channel connection in a portion of the second initial sub-stack structure includes: forming a first contact opening in the portion of the second initial sub-stack structure, the first contact opening exposing a first sacrificial channel extension; the size of the first contact opening being larger than the size of the first sacrificial channel extension along a direction intersecting a first direction; and forming the first sacrificial channel connection in the first contact opening.

[0138] In some embodiments, forming the first channel extension and the first channel connection includes forming a first functional portion and a first channel portion extending along a first direction.

[0139] Figures 11 to 26 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this application.

[0140] refer to Figure 11 A first initial sub-stack structure 1000 is formed, which includes a first sacrificial dielectric layer 1002 and a first insulating layer 101 that are alternately spaced along the first direction Z.

[0141] In one embodiment, a first initial sub-stack structure 1000 is formed on one side of a temporary substrate C1 along the first direction Z.

[0142] In one embodiment, forming a temporary substrate C1 includes forming a first sacrificial semiconductor layer, a substrate isolation layer, and a second sacrificial semiconductor layer, wherein the substrate isolation layer is located between the second sacrificial semiconductor layer and the first sacrificial semiconductor layer. The materials of the second sacrificial semiconductor layer and the first sacrificial semiconductor layer may be semiconductor materials such as polycrystalline silicon, and the material of the substrate isolation layer may be an insulating dielectric material such as silicon oxide.

[0143] It should be noted that the method for forming the temporary substrate C1 is not limited to the method described above, and the temporary substrate C1 can also be other suitable structures.

[0144] In one embodiment, the process for forming the first sacrificial dielectric layer 1002 is a deposition process, including chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof as a thin film deposition process. The process for forming the first insulating layer 101 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof as a thin film deposition process.

[0145] In one embodiment, the material of the first sacrificial dielectric layer 1002 is different from the material of the first insulating layer 101. During the subsequent removal of at least a portion of the first sacrificial dielectric layer 1002, the first sacrificial dielectric layer 1002 has a higher etching selectivity relative to the first insulating layer 101.

[0146] In some embodiments, the material of the first sacrificial dielectric layer 1002 includes an insulating dielectric material. The material of the first insulating layer 101 includes an insulating dielectric material. For example, the material of the first sacrificial dielectric layer 1002 may be silicon nitride, amorphous carbon, or polycrystalline silicon, and the material of the first insulating layer 101 may include silicon oxide.

[0147] In some implementations, reference Figure 11The method for fabricating the semiconductor structure further includes forming a first extension port 1003 in the first initial sub-stack structure 1000.

[0148] In some embodiments, the first extension port 1003 may also extend into the temporary substrate C1.

[0149] In some embodiments, the process for forming the first extension opening 1003 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0150] In some embodiments, along the direction intersecting the first direction Z, the dimension of the end of the first extension 1003 facing the temporary substrate C1 along the first direction Z is less than or equal to the dimension of the end of the first extension 1003 away from the temporary substrate C1 along the first direction Z. For example, along the second direction Y, the dimension of the end of the first extension 1003 facing the temporary substrate C1 along the first direction Z is less than or equal to the dimension of the end of the first extension 1003 away from the temporary substrate C1 along the first direction Z. Along a third direction X, the dimension of the end of the first extension 1003 facing the temporary substrate C1 along the first direction Z is less than or equal to the dimension of the end of the first extension 1003 away from the temporary substrate C1 along the first direction Z.

[0151] In other embodiments, the dimensions of the end of the first extension 1003 facing the temporary substrate C1 along the first direction Z and the dimensions of the end of the first extension 1003 away from the temporary substrate C1 along the first direction Z are not limited.

[0152] refer to Figure 12 The first sacrificial channel extension 1004 is formed in the first extension port 1003.

[0153] In some embodiments, the material of the first sacrificial channel extension 1004 is different from the material of the first insulating layer 101, and the material of the first sacrificial channel extension 1004 is different from the material of the first sacrificial dielectric layer 1002. For example, the material of the first sacrificial channel extension 1004 includes amorphous carbon or polycrystalline silicon.

[0154] In some embodiments, the process of forming the first sacrificial channel extension 1004 in the first extension port 1003 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0155] refer to Figure 13 A first stack portion 2000-1 of a second initial sub-stack structure is formed on one side of the first initial sub-stack structure 1000 along the first direction Z. The first stack portion 2000-1 includes a second sacrificial dielectric layer 2002 and a first insulating layer 101 alternately stacked along the first direction Z.

[0156] In one embodiment, the process for forming the second sacrificial dielectric layer 2002 is a deposition process, including chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof as a thin film deposition process. The process for forming the first insulating layer 101 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof as a thin film deposition process.

[0157] In one embodiment, the material of the second sacrificial dielectric layer 2002 is different from the material of the first insulating layer 101. During the subsequent removal of at least a portion of the second sacrificial dielectric layer 2002, the second sacrificial dielectric layer 2002 has a higher etching selectivity relative to the first insulating layer 101.

[0158] In some embodiments, the material of the second sacrificial dielectric layer 2002 includes an insulating dielectric material. The material of the first insulating layer 101 includes an insulating dielectric material. For example, the material of the second sacrificial dielectric layer 2002 may be silicon nitride, amorphous carbon, or polycrystalline silicon, and the material of the first insulating layer 101 may include silicon oxide.

[0159] In some implementations, reference Figure 13 The method for fabricating a semiconductor structure further includes: forming a first contact 2003 in a portion of the second initial sub-stack structure, wherein the first contact 2003 exposes a first sacrificial channel extension 1004, for example, the first contact 2003 is formed in a first stack portion 2000-1.

[0160] In some embodiments, the process of forming the first contact 2003 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0161] In some embodiments, the size of the first contact opening 2003 is larger than the size of the first sacrificial channel extension 1004 along the direction intersecting the first direction Z. For example, the size of the first contact opening 2003 along the second direction Y is larger than the size of the first sacrificial channel extension 1004 along the second direction Y, and the size of the first contact opening 2003 along the third direction X is larger than the size of the first sacrificial channel extension 1004 along the third direction X.

[0162] In some embodiments, the material of the first sacrificial channel extension 1004 is different from the material of the second initial sub-stack structure 2000, so that the first sacrificial channel extension 1004 can be used as an etch stop layer during the formation of the first contact 2003.

[0163] refer to Figure 14 A first sacrificial channel connection portion 2004 is formed in the first contact port 2003.

[0164] In some embodiments, the process of forming the first sacrificial channel connection 2004 in the first contact 2003 includes a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0165] The materials of the first sacrificial channel connector 2004 and the second sacrificial dielectric layer 2002 are different, and the materials of the first sacrificial channel connector 2004 and the first insulating layer 101 are different. For example, the material of the first sacrificial channel connector 2004 includes amorphous carbon or polycrystalline silicon.

[0166] In some embodiments, the material of the first sacrificial channel connector 2004 is the same as the material of the first sacrificial channel extension 1004, or the material of the first sacrificial channel connector 2004 is different from the material of the first sacrificial channel extension 1004.

[0167] refer to Figure 15 The second stack portion 2000-2 of the second initial sub-stack structure 2000 is formed. The second stack portion 2000-2 includes a second sacrificial dielectric layer 2002 and a first insulating layer 101 that are alternately stacked along the first direction Z.

[0168] The second initial sub-stack structure 2000 includes a second stacked portion 2000-2 and a first stacked portion 2000-1. The second stacked portion 2000-2 is located on the side of the first stacked portion 2000-1 that is opposite to the first initial sub-stack structure 1000 along the first direction Z.

[0169] In some embodiments, the process for forming the second stack portion 2000-2 includes a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0170] The description of the second sacrificial dielectric layer 2002 and the first insulating layer 101 refers to the foregoing embodiment.

[0171] After the first sacrificial channel connection portion 2004 is formed, a second stack portion 2000-2 is formed, which covers the first sacrificial channel connection portion 2004.

[0172] The second initial sub-stack structure 2000 and the first initial sub-stack structure 1000 constitute the first initial stacked structure.

[0173] In some implementations, reference Figure 15A first sacrificial layer 3000 is formed on the side of the second initial sub-stack structure 2000 that is away from the first initial sub-stack structure 1000; a third initial sub-stack structure 4000-1 is formed on the side of the first sacrificial layer 3000 that is away from the second initial sub-stack structure 2000.

[0174] In some embodiments, the process for forming the first sacrificial layer 3000 includes a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0175] In some implementations, reference Figure 15 The third initial sub-layer structure 4000-1 includes a second insulating layer 201 and a third sacrificial dielectric layer 4001 that are alternately spaced along the first direction Z.

[0176] In some embodiments, the process for forming the second insulating layer 201 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the third sacrificial dielectric layer 4001 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0177] In some embodiments, the material of the third sacrificial dielectric layer 4001 is different from the material of the second insulating layer 201. During the subsequent removal of at least a portion of the third sacrificial dielectric layer 4001, the third sacrificial dielectric layer 4001 has a higher etching selectivity relative to the second insulating layer 201.

[0178] In some embodiments, the material of the third sacrificial dielectric layer 4001 includes an insulating dielectric material. The material of the second insulating layer 201 includes an insulating dielectric material. For example, the material of the third sacrificial dielectric layer 4001 may be silicon nitride, amorphous carbon, or polycrystalline silicon, and the material of the second insulating layer 201 may include silicon oxide.

[0179] In some implementations, reference Figure 15 The method for fabricating a semiconductor structure further includes: forming a second sacrificial channel extension 4004 extending along a first direction Z in a third initial sub-stack structure 4000-1, a first sacrificial layer 3000, and a second stacked portion 2000-2, wherein the second sacrificial channel extension 4004 is connected to a first sacrificial channel connection portion 2004.

[0180] In some embodiments, forming the second sacrificial channel extension 4004 includes: forming a second extension opening extending in a first direction Z in a third initial sub-stack structure 4000-1, a first sacrificial layer 3000, and a second stack portion 2000-2; and forming the second sacrificial channel extension 4004 in the second extension opening.

[0181] In some embodiments, the process for forming the second extension is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0182] In some embodiments, the process of forming the second sacrificial channel extension 4004 in the second extension port includes a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0183] In some embodiments, the material of the second sacrificial channel extension 4004 is different from that of the first sacrificial channel connector 2004, and the first sacrificial channel connector 2004 serves as an etching stop layer during the subsequent removal of the second sacrificial channel extension 4004.

[0184] In some embodiments, the material of the second sacrificial channel extension 4004 is the same as that of the first sacrificial channel connector 2004, and the etching endpoint is controlled by controlling the etching time during the subsequent removal of the second sacrificial channel extension 4004.

[0185] In some embodiments, the material of the second sacrificial channel extension 4004 includes amorphous carbon or polycrystalline silicon.

[0186] refer to Figure 16 A fourth initial sub-stack structure 4000-2 is formed on the side of the third initial sub-stack structure 4000-1 that is away from the first sacrificial layer 3000.

[0187] The fourth initial sub-stack structure 4000-2 includes a second insulating layer 201 and a third sacrificial dielectric layer 4001 that are alternately spaced along the first direction Z. The description of the second insulating layer 201 and the third sacrificial dielectric layer 4001 refers to the foregoing embodiment.

[0188] The third initial sub-stack structure 4000-1 and the fourth initial sub-stack structure 4000-2 constitute the second initial stack structure 4000.

[0189] In some embodiments, the process for forming the fourth initial sub-layer structure 4000-2 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0190] In some embodiments, the method for fabricating the semiconductor structure further includes forming a third sacrificial channel extension 4005 extending along a first direction Z in a second initial stacked structure 4000. For example, the third sacrificial channel extension 4005 extending along the first direction Z is formed in a fourth initial sub-stacked structure 4000-2.

[0191] The third sacrificial trench extension 4005 is located on the side of the second sacrificial trench extension 4004 that is away from the first sacrificial trench connection 2004. The third sacrificial trench extension 4005 is connected to the second sacrificial trench extension 4004.

[0192] In some embodiments, forming the third sacrificial channel extension 4005 includes: forming a third extension opening along the first direction Z in the fourth initial sub-stack structure 4000-2; and forming the third sacrificial channel extension 4005 in the third extension opening.

[0193] In some embodiments, the process for forming the third extension is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0194] In some embodiments, the process of forming the third sacrificial channel extension 4005 in the third extension port includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0195] In some embodiments, the material of the third sacrificial channel extension 4005 is different from the material of the second insulating layer 201, and the material of the third sacrificial channel extension 4005 is different from the material of the third sacrificial dielectric layer 4001.

[0196] In some embodiments, the material of the third sacrificial channel extension 4005 is the same as the material of the second sacrificial channel extension 4004.

[0197] In some embodiments, the material of the third sacrificial channel extension 4005 is different from the material of the second sacrificial channel extension 4004.

[0198] In some embodiments, the material of the third sacrificial channel extension 4005 includes amorphous carbon or polycrystalline silicon.

[0199] refer to Figure 17 Remove the third sacrificial channel extension 4005 and the second sacrificial channel extension 4004; after removing the third sacrificial channel extension 4005 and the second sacrificial channel extension 4004, form a second channel extension 503 in the second extension opening and form a third channel extension 504 in the third extension opening. The second channel extension 503 and the third channel extension 504 together include a second functional part 561, a second channel part 562 and a second filling medium part 563.

[0200] The second functional part 561 extends to the sidewalls of the second extension port and the third extension port, the second filling medium part 563 fills the second extension port and the third extension port, and the second channel part 562 is located between the second functional part 561 and the second filling medium part 563.

[0201] In some embodiments, the process for forming the second functional portion 561 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the second channel portion 562 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the second filling medium portion 563 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0202] refer to Figure 18 At least a portion of the first sacrificial dielectric layer 1002 is replaced with the first select gate 102, at least a portion of the second sacrificial dielectric layer 2002 is replaced with the first gate layer 103, and at least a portion of the third sacrificial dielectric layer 4001 is replaced with the second gate layer 203 and the second select gate 202.

[0203] In some embodiments, the fabrication of the semiconductor structure further includes forming a third isolation trench that penetrates the second initial stacked structure 4000, the first sacrificial layer 3000, and the first initial stacked structure. The third isolation trench is spaced apart from the third channel extension 504.

[0204] In some embodiments, the process for forming the third isolation trench is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0205] In some embodiments, at least a portion of the first sacrificial dielectric layer 1002 is replaced with the first select gate 102 via a third isolation trench, at least a portion of the second sacrificial dielectric layer 2002 is replaced with the first gate layer 103 via a third isolation trench, and at least a portion of the third sacrificial dielectric layer 4001 is replaced with the second gate layer 203 and the second select gate 202 via a third isolation trench.

[0206] The description of the first selection gate 102, the first gate layer 103, the second gate layer 203, and the second selection gate 202 refers to the description of the foregoing embodiments.

[0207] In other embodiments, at least a portion of the first sacrificial dielectric layer 1002 may be replaced with the first select gate 102, and at least a portion of the second sacrificial dielectric layer may be replaced with the first gate layer 103 and the third select gate; at least a portion of the third sacrificial dielectric layer 4001 may be replaced with the second gate layer 203, the second select gate 202, and the fourth select gate. The description of the first select gate 102, the first gate layer 103, the second gate layer 203, the second select gate 202, the third select gate, and the fourth select gate refers to the description of the foregoing embodiments.

[0208] refer to Figure 19 The first sacrificial layer 3000 is replaced with a semiconductor layer 300, and the semiconductor layer 300 and the second channel portion 562 are connected.

[0209] In some embodiments, the first sacrificial layer 3000 is replaced with a semiconductor layer 300, and the semiconductor layer 300 and the second channel portion 562 are connected. This includes: removing the first sacrificial layer 3000 to form a first opening; removing the portion of the second functional portion 561 exposed by the first opening through the first opening; and then forming the semiconductor layer 300 in the first opening, and connecting the semiconductor layer 300 and the second channel portion 562. After performing this step, the description of the second functional portion 561, the second channel portion 562, and the second filling dielectric portion 563 refers to the description of the foregoing embodiments.

[0210] In some embodiments, the process for removing the first sacrificial layer 3000 is an etching process, which includes one or a combination of dry etching and wet etching. The process for removing the portion of the second functional part 561 exposed by the first opening is an etching process, which includes one or a combination of dry etching and wet etching. The process for forming the semiconductor layer 300 in the first opening includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0211] In some embodiments, after forming the first select gate 102, the first gate layer 103, the second gate layer 203, and the second select gate 202, the first sacrificial layer 3000 is replaced with the semiconductor layer 300. In other embodiments, after replacing the first sacrificial layer 3000 with the semiconductor layer 300, the first select gate 102, the first gate layer 103, the second gate layer 203, and the second select gate 202 are formed.

[0212] In some embodiments, the method for fabricating the semiconductor structure further includes forming a third isolation structure in a third isolation trench, the third isolation structure penetrating the second stacked structure 200, the semiconductor layer 300, and the first stacked structure 100. The material of the third isolation structure includes, for example, an insulating dielectric material such as silicon oxide.

[0213] In some embodiments, the process for forming the third isolation structure in the third isolation tank includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0214] refer to Figure 20 A second isolation structure 700 is formed in the second selection gate 202. The second isolation structure 700 extends through the second selection gate 202 along the first direction Z and is spaced apart from the second gate layer 203.

[0215] In some embodiments, forming the second isolation structure 700 includes: forming a second isolation trench (not shown) that extends through the second select gate 202 along a first direction Z and is spaced from the second gate layer 203; and forming the second isolation structure 700 in the second isolation trench.

[0216] In some embodiments, the process for forming the second isolation trench is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the second isolation structure in the second isolation trench includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0217] The second isolation structure 700 extends along the second direction Y, dividing the second selection gate 202 into a third sub-selection gate and a fourth sub-selection gate. The third and fourth sub-selection gates are respectively connected to different channel structures 500, and the second direction Y intersects the first direction Z. The dimensional description of the second isolation structure 700 refers to the description of the aforementioned embodiment.

[0218] In some implementations, a second isolation structure 700 is formed after the third isolation structure is formed.

[0219] refer to Figure 21 The temporary substrate C1 is planarized until the first sacrificial trench extension 1004 is exposed.

[0220] In some embodiments, the process of planarizing the temporary substrate C1 until the first sacrificial channel extension 1004 is exposed includes a chemical mechanical polishing process.

[0221] Reference Figure 22 and Figure 23 The first sacrificial channel extension 1004 is replaced with the first channel extension 502, and the first sacrificial channel connecting part 2004 is replaced with the first channel connecting part 501.

[0222] In some embodiments, replacing the first sacrificial channel extension 1004 with the first channel extension 502 includes replacing the first sacrificial channel extension 1004 with the first channel extension 502 on the side of the first laminated structure 100 opposite to the first direction Z. For example, replacing the first sacrificial channel extension 1004 with the first channel extension 502 on the side of the first laminated structure 100 opposite to the second laminated structure 200.

[0223] In some embodiments, replacing the first sacrificial channel connection 2004 with the first channel connection 501 includes replacing the first sacrificial channel connection 2004 with the first channel connection 501 on the side of the first laminated structure 100 opposite to the first direction Z. For example, replacing the first sacrificial channel connection 2004 with the first channel connection 501 on the side of the first laminated structure 100 opposite to the second laminated structure 200.

[0224] refer to Figure 22Remove the first sacrificial channel extension 1004 and the first sacrificial channel connecting portion 2004.

[0225] In some embodiments, the process of removing the first sacrificial channel extension 1004 and the first sacrificial channel connection 2004 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0226] Remove the first sacrificial channel extension 1004 and the first sacrificial channel connection 2004 to expose the first extension port 1003 and the first contact port 2003.

[0227] In some embodiments, after removing the first sacrificial channel extension 1004 and the first sacrificial channel connector 2004, the portion of the second functional portion 561 located between the first contact port 2003 and the second filling medium portion 563, and the portion of the second channel portion 562 located between the first contact port 2003 and the second filling medium portion 563 are etched away. To ensure complete removal of the portions of the second functional portion 561 and the second channel portion 562 located between the first contact port 2003 and the second filling medium portion 563, over-etching is performed. During over-etching, a recess T is formed in the second filling medium portion 563.

[0228] refer to Figure 23 A first channel extension 502 is formed in the first extension opening 1003, and a first channel connection 501 is formed in the first contact opening 2003.

[0229] For example, a first channel connection portion 501 is formed in the first contact port 2003 and the recess T, a portion of the first channel connection portion 501 extends along the first direction Z into the second filling medium portion 563, and a portion of the first channel connection portion 501 is embedded in the second filling medium portion 563.

[0230] In some embodiments, forming a first channel extension 502 in the first extension opening 1003 and a first channel connection 501 in the first contact opening 2003 and the recess T includes: forming a first functional portion 551 on the sidewall of the first extension opening 1003 and the sidewall of the first contact opening 2003, the first functional portion 551 exposing a second channel portion 562 and the inner wall of the recess T; forming a first channel portion 552 on the sidewall of the first functional portion 551 and the sidewall of the recess T, the first channel portion 552 and the second channel portion 562 being connected; and after forming the first channel portion 552, forming a first filling medium portion 553 in the first extension opening 1003, the first contact opening 2003 and the recess T.

[0231] In some embodiments, forming a first functional portion 551 on the sidewall of the first extension port 1003 and the sidewall of the first contact port 2003 includes: forming a first initial functional portion on the sidewall of the first extension port 1003, the inner wall of the first contact port 2003, and the inner wall of the recess T; removing the portion of the first initial functional portion located on the inner wall of the recess T and the portion of the first initial functional portion located on the inner wall of the first contact port 2003 opposite to the first extension port 1003, and the remaining first initial functional portion forming the first functional portion 551.

[0232] In some embodiments, the process for forming the first initial functional portion includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0233] In some embodiments, the portion of the first initial functional part located on the inner wall of the recess T and the portion of the first initial functional part located on the side of the first contact port 2003 opposite to the first extension port 1003 are removed by an etching process, which includes one or a combination of dry etching and wet etching processes.

[0234] In some embodiments, the process of forming the first channel portion 552 on the sidewall of the first functional portion 551 and the sidewall of the recess T includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process of forming the first filling medium portion 553 in the first extension port 1003, the first contact port 2003, and the recess T includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0235] Figure 24 for Figure 23 Enlarged view of the dashed box W. The first channel extension 502, the first channel connection 501, the second channel extension 503, and the third channel extension 504 together include a functional layer, a channel layer, and a filling dielectric layer. The first channel extension 502 and the first channel connection 501 together include a first functional portion 551, a first channel portion 552, and a first filling dielectric portion 553. The second channel extension 503 and the third channel extension 504 together include a second functional portion 561, a second channel portion 562, and a second filling dielectric portion 563. The second functional portion 561 exposes the second channel portion 562 in the semiconductor layer 300, and the semiconductor layer 300 and the second channel portion 562 are in contact.

[0236] The descriptions of the first functional part 551, the first channel part 552 and the first filling medium part 553, the second functional part 561, the second channel part 562 and the second filling medium part 563 are the same as those of the foregoing embodiments and will not be described in detail again.

[0237] refer to Figure 25 , Figure 25 In order to be in Figure 23 A schematic diagram based on the previous diagram, with the temporary substrate C1 removed.

[0238] In some embodiments, the etching process for removing the temporary substrate C1 includes one or a combination of dry etching and wet etching processes.

[0239] refer to Figure 26 After removing the temporary substrate C1, a first isolation structure 600 is formed in the first select gate 102, and the first isolation structure 600 is spaced apart from the first gate layer 103. After removing the temporary substrate C1, an insulating protective layer C is formed on the side of the first stacked structure 100 away from the direction opposite to the first direction Z, and the first channel extension 502 penetrates the insulating protective layer C.

[0240] In some embodiments, the insulating protective layer C is formed during the formation of the first isolation structure 600, simplifying the process. The material of the first isolation structure 600 is the same as the material of the insulating protective layer C.

[0241] In some embodiments, after the first isolation structure 600 is formed, an insulating protective layer C is formed. The material of the first isolation structure 600 and the material of the insulating protective layer C may be the same or different.

[0242] In some embodiments, forming a first isolation structure 600 in the first selection gate 102 includes: forming a first isolation groove in the first selection gate 102; and forming a first isolation structure 600 in the first isolation groove.

[0243] In some embodiments, the process for forming the first isolation trench is an etching process, which includes one or a combination of dry etching and wet etching processes. The process for forming the first isolation structure 600 in the first isolation trench includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0244] A first isolation structure 600 extends through the first select gate 102 along a first direction Z and is spaced apart from the first gate layer 103. The first isolation structure 600 extends along a second direction Y, dividing the first select gate 102 into a first sub-select gate and a second sub-select gate. The first sub-select gate and the second sub-select gate are respectively connected to different channel structures 500. The first sub-select gate and the second select gate are respectively connected to different first channel extensions 502.

[0245] In some embodiments, along a direction intersecting the first direction Z, the dimension of the end of the first isolation structure 600 away from the first gate layer 103 is larger than the dimension of the end of the first isolation structure 600 toward the first gate layer 103. For example, the dimension of the end of the first isolation structure 600 away from the first gate layer 103 along a third direction X is larger than the dimension of the end of the first isolation structure 600 toward the first gate layer 103 in the third direction X.

[0246] In other embodiments, the dimension of the end of the first isolation structure away from the first gate layer 103 along a third direction X is less than or equal to the dimension of the end of the first isolation structure toward the first gate layer 103 along a third direction X.

[0247] Further description of the first isolation structure 600 is given in reference to the description of the aforementioned embodiments.

[0248] Another embodiment of the present invention provides a method for fabricating a semiconductor structure. The difference between this embodiment and the previous embodiment is that replacing the first sacrificial channel extension with the first channel extension includes: replacing the first sacrificial channel extension with the first channel extension on the side of the second initial sub-stack structure opposite to the first initial sub-stack structure; wherein, replacing the first sacrificial channel connection with the first channel connection includes: replacing the first sacrificial channel connection with the first channel connection on the side of the second initial sub-stack structure opposite to the first initial sub-stack structure.

[0249] The following reference Figures 27 to 30 A detailed introduction will be provided.

[0250] refer to Figure 27 , Figure 27 In order to be in Figure 16 Based on the schematic diagram, on the side of the second initial sub-stack structure 2000 opposite to the first initial sub-stack structure 1000, the first sacrificial channel extension 1004 is replaced with the first channel extension 502; on the side of the second initial sub-stack structure 2000 opposite to the first initial sub-stack structure 1000, the first sacrificial channel connection 2004 is replaced with the first channel connection 501; the second sacrificial channel extension 4004 is replaced with the second channel extension 503; and the third sacrificial channel extension 4005 is replaced with the third channel extension 504.

[0251] In some embodiments, forming the first channel extension 502, the first channel connecting portion 501, the second channel extension 503, and the third channel extension 504 includes: removing the first sacrificial channel extension 1004, the first sacrificial channel connecting portion 2004, the second sacrificial channel extension 4004, and the third sacrificial channel extension 4005 to expose the first extension opening, the first contact opening, the second extension opening, and the third extension opening; and forming a channel structure 500 in the first extension opening, the first contact opening, the second extension opening, and the third extension opening. Specifically, removing the first sacrificial channel extension 1004 exposes the first extension opening; removing the first sacrificial channel connecting portion 2004 exposes the first contact opening; removing the second sacrificial channel extension 4004 exposes the second extension opening; and removing the third sacrificial channel extension 4005 exposes the third extension opening. The channel structure 500 formed in the first extension port, the first contact port, the second extension port, and the third extension port includes: a first channel extension portion 502 formed in the first extension port, a first sacrificial channel connection portion 2004 formed in the first contact port, a second channel extension portion 503 formed in the second extension port, and a third channel extension portion 504 formed in the third extension port.

[0252] In some embodiments, the first channel extension 502, the first channel connection 501, the second channel extension 503, and the third channel extension 504 together include a functional layer 511, a channel layer 512, and a filling dielectric layer 513. The functional layer 511 exposes the channel layer 512 in the semiconductor layer 300, such that the semiconductor layer 300 and the channel layer 512 are in contact.

[0253] In some embodiments, forming a channel structure 500 in the first extension port, the first contact port, the second extension port, and the third extension port includes forming a functional layer 511, a channel layer 512, and a filling medium layer 513 sequentially in the first extension port, the first contact port, the second extension port, and the third extension port.

[0254] In some embodiments, the process for forming the functional layer 511 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the channel layer 512 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the filling dielectric layer 513 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0255] refer to Figure 28 At least a portion of the first sacrificial dielectric layer 1002 is replaced with the first select gate 102, at least a portion of the second sacrificial dielectric layer 2002 is replaced with the first gate layer 103, and at least a portion of the third sacrificial dielectric layer 4001 is replaced with the second gate layer 203 and the second select gate 202.

[0256] The description of the first selection gate 102, the first gate layer 103, the second gate layer 203, and the second selection gate 202 refers to the description of the foregoing embodiments.

[0257] In some embodiments, the semiconductor structure is further fabricated by forming a third isolation trench that penetrates the second initial stacked structure 4000, the first sacrificial layer 3000, and the first initial stacked structure. The third isolation trench is spaced apart from the second sacrificial channel extension 4004.

[0258] In some embodiments, the process for forming the third isolation trench is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0259] In some embodiments, at least a portion of the first sacrificial dielectric layer 1002 is replaced with the first select gate 102 via a third isolation trench, at least a portion of the second sacrificial dielectric layer 2002 is replaced with the first gate layer 103 via a third isolation trench, and at least a portion of the third sacrificial dielectric layer 4001 is replaced with the second gate layer 203 and the second select gate 202 via a third isolation trench.

[0260] In other embodiments, at least a portion of the first sacrificial dielectric layer 1002 may be replaced with the first select gate 102, and at least a portion of the second sacrificial dielectric layer 2002 may be replaced with the first gate layer 103 and the third select gate; at least a portion of the third sacrificial dielectric layer 4001 may be replaced with the second gate layer 203, the second select gate 202, and the fourth select gate. The description of the first select gate 102, the first gate layer 103, the second gate layer 203, the second select gate 202, the third select gate, and the fourth select gate refers to the description of the foregoing embodiments.

[0261] Continue to refer to Figure 28 The first sacrificial layer 3000 is replaced with a semiconductor layer 300, and the semiconductor layer 300 and the channel layer 512 are connected.

[0262] In some embodiments, the first sacrificial layer 3000 is replaced with a semiconductor layer 300, which is connected to the channel layer 512. This includes: removing the first sacrificial layer 3000 to form a first opening; removing the portion of the functional layer 511 exposed by the first opening through the first opening; and then forming the semiconductor layer 300 in the first opening, which is connected to the channel layer 512. After performing this step, the description of the functional layer 511, the channel layer 512, and the filling dielectric layer 513 refers to the description of the foregoing embodiments.

[0263] In some embodiments, the process for removing the first sacrificial layer 3000 is an etching process, which includes one or a combination of dry etching and wet etching. The process for removing the portion of the functional layer 511 exposed by the first opening is an etching process, which includes one or a combination of dry etching and wet etching. The process for forming the semiconductor layer 300 in the first opening includes a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0264] In some embodiments, the order of the steps of forming the first select gate 102, the first gate layer 103, the second gate layer 203 and the second select gate 202, and the step of replacing the first sacrificial layer 3000 with the semiconductor layer 300 is as described in the foregoing embodiments.

[0265] refer to Figure 29 A second isolation structure 700 is formed in the second selection gate 202. The second isolation structure 700 extends through the second selection gate 202 along the first direction Z and is spaced apart from the second gate layer 203.

[0266] The description of forming the second isolation structure 700 in the second selection gate 202 refers to the description of the aforementioned embodiment.

[0267] refer to Figure 30 Remove the temporary substrate C1; after removing the temporary substrate C1, form a first isolation structure 600 in the first select gate 102, the first isolation structure 600 being spaced apart from the first gate layer 103; after removing the temporary substrate C1, form an insulating protective layer C on the side of the first stacked structure 100 away from the direction opposite to the first direction Z, the first channel extension 502 penetrating the insulating protective layer C.

[0268] The steps of removing the temporary substrate C1, forming the first isolation structure 600, and forming the insulating protective layer C are described in the foregoing embodiments.

[0269] The preparation method of the semiconductor structure in this embodiment is the same as that in the previous embodiments, and will not be described in detail again.

[0270] Another embodiment of the present invention provides a method for fabricating a semiconductor structure. The difference between this embodiment and the semiconductor structure fabrication method of the aforementioned embodiments is that: before forming the second initial sub-stack structure, a first channel extension is formed in the first initial sub-stack structure; wherein, forming the first channel connection includes: forming the first channel connection in a portion of the second initial sub-stack structure.

[0271] In some embodiments, forming the first channel extension and the first channel connection includes forming an isolation layer and a conductive layer, wherein the isolation layer is located on the sidewall of the conductive layer.

[0272] The following reference Figures 31 to 36 This section provides a detailed introduction to the fabrication methods of semiconductor structures.

[0273] refer to Figure 31 A first channel extension 502 is formed in the first initial sub-stack structure 1000; after forming the first channel extension 502 in the first initial sub-stack structure 1000, a first stack portion 2000-1 of the second initial sub-stack structure is formed; a first channel connection portion 501 is formed in the first stack portion 2000-1. The first channel connection portion 501 and the first channel extension 502 together include an insulating layer 541 and a conductive layer 542.

[0274] In some embodiments, forming a first channel extension 502 in the first initial sub-stack structure 1000 includes: forming a first extension opening in the first initial sub-stack structure 1000; and forming the first channel extension 502 in the first extension opening.

[0275] In some embodiments, forming a first channel connection portion 501 in the first stack portion 2000-1 includes: forming a first contact port in the first stack portion 2000-1; and forming the first channel connection portion 501 in the first contact port.

[0276] In some embodiments, forming a first channel extension 502 in the first extension opening includes: forming a first isolation portion on the sidewall of the first extension opening; forming a first conductive portion in the first extension opening, wherein the first isolation portion is located between the first conductive portion and the first selection gate 102.

[0277] In some embodiments, the process of forming the first insulating portion on the sidewall of the first extension includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process of forming the first conductive portion in the first extension includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0278] In some embodiments, forming a first channel connection portion 501 in the first contact port includes: forming a second isolation portion on the sidewall of the first contact port; forming a second conductive portion in the first contact port, wherein the second isolation portion is located between the second conductive portion and the first gate layer 103.

[0279] In some embodiments, the process of forming the second insulating portion on the sidewall of the first contact includes a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process of forming the second conductive portion in the first contact includes a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0280] The isolation layer 541 includes a first isolation portion and a second isolation portion. The conductive layer 542 includes a first conductive portion and a second conductive portion.

[0281] The description of the isolation layer 541 and the conductive layer 542 is the same as that of the aforementioned embodiments.

[0282] refer to Figure 32 This forms a second stack portion 2000-2 of the second initial sub-stack structure 2000. The second stack portion 2000-2 includes a second sacrificial dielectric layer 2002 and a first insulating layer 101 alternately stacked along the first direction Z. The second stack portion 2000-2 is located on the side of the first channel connection portion 501 opposite to the first channel extension portion 502.

[0283] The description of forming the second stack portion 2000-2 refers to the description of the aforementioned embodiment.

[0284] Continue to refer to Figure 32 A first sacrificial layer 3000 is formed on the side of the second initial sub-stack structure 2000 opposite to the first initial sub-stack structure 1000; a third initial sub-stack structure 4000-1 is formed on the side of the first sacrificial layer 3000 opposite to the second initial sub-stack structure 2000. The third initial sub-stack structure 4000-1 includes a second insulating layer and a third sacrificial dielectric layer that are alternately spaced along a first direction Z; a second sacrificial channel extension 4004 extending along the first direction Z is formed in the third initial sub-stack structure 4000-1, the first sacrificial layer 3000, and the second stack portion 2000-2, and the second sacrificial channel extension 4004 is connected to the first sacrificial channel connection portion 2004.

[0285] The steps for forming the first sacrificial layer 3000, the steps for forming the third initial sub-stack structure 4000-1, and the steps for forming the second sacrificial channel extension 4004 are described in the foregoing embodiment.

[0286] Continue to refer to Figure 32A fourth initial sub-layer structure 4000-2 is formed on the side of the third initial sub-layer structure 4000-1 opposite to the first sacrificial layer 3000. The fourth initial sub-layer structure 4000-2 includes a second insulating layer and a third sacrificial dielectric layer that are alternately spaced along the first direction Z. The third initial sub-layer structure 4000-1 and the fourth initial sub-layer structure 4000-2 constitute the second initial sub-layer structure 4000.

[0287] The steps for forming the fourth initial sub-layer structure 4000-2 are described in the foregoing embodiment.

[0288] Continue to refer to Figure 32 A third sacrificial channel extension 4005 extending along the first direction Z is formed in the second initial stacked structure 4000. For example, the third sacrificial channel extension 4005 extending along the first direction Z is formed in the fourth initial sub-stacked structure 4000-2.

[0289] The steps for forming the third sacrificial channel extension 4005 are described in the foregoing embodiment.

[0290] refer to Figure 33 Remove the third sacrificial channel extension 4005 and the second sacrificial channel extension 4004; after removing the third sacrificial channel extension 4005 and the second sacrificial channel extension 4004, form a second channel extension 503 in the second extension opening and form a third channel extension 504 in the third extension opening. The second channel extension 503 and the third channel extension 504 together include a functional layer 521, a channel layer 522 and a filling medium layer 523.

[0291] refer to Figure 34 At least a portion of the first sacrificial dielectric layer 1002 is replaced with the first select gate 102, at least a portion of the second sacrificial dielectric layer 2002 is replaced with the first gate layer 103, and at least a portion of the third sacrificial dielectric layer 4001 is replaced with the second gate layer 203 and the second select gate 202.

[0292] In some embodiments, the fabrication of the semiconductor structure further includes forming a third isolation trench that penetrates the second initial stacked structure 4000, the first sacrificial layer 3000, and the first initial stacked structure. The third isolation trench is spaced apart from the third channel extension 504.

[0293] In some embodiments, the process for forming the third isolation trench is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0294] In some embodiments, at least a portion of the first sacrificial dielectric layer 1002 is replaced with the first select gate 102 via a third isolation trench, at least a portion of the second sacrificial dielectric layer 2002 is replaced with the first gate layer 103 via a third isolation trench, and at least a portion of the third sacrificial dielectric layer 4001 is replaced with the second gate layer 203 and the second select gate 202 via a third isolation trench.

[0295] In other embodiments, at least a portion of the first sacrificial dielectric layer 1002 may be replaced with the first select gate 102, and at least a portion of the second sacrificial dielectric layer may be replaced with the first gate layer 103 and the third select gate; at least a portion of the third sacrificial dielectric layer 4001 may be replaced with the second gate layer 203, the second select gate 202, and the fourth select gate. The description of the first select gate 102, the first gate layer 103, the second gate layer 203, the second select gate 202, the third select gate, and the fourth select gate refers to the description of the foregoing embodiments.

[0296] refer to Figure 34 The first sacrificial layer 3000 is replaced with a semiconductor layer 300, and the semiconductor layer 300 and the channel layer 522 are connected.

[0297] In some embodiments, the first sacrificial layer 3000 is replaced with a semiconductor layer 300, which is connected to the channel layer 522. This includes: removing the first sacrificial layer 3000 to form a first opening; removing the portion of the functional layer 521 exposed by the first opening through the first opening; and then forming the semiconductor layer 300 in the first opening, which is connected to the channel layer 522. After performing this step, the description of the functional layer 521, the channel layer 522, and the filling dielectric layer 523 refers to the description of the foregoing embodiments.

[0298] In some embodiments, the method for fabricating the semiconductor structure further includes forming a third isolation structure in a third isolation trench, the third isolation structure penetrating the second stacked structure 200, the semiconductor layer 300, and the first stacked structure 100. The material of the third isolation structure includes, for example, an insulating dielectric material such as silicon oxide.

[0299] refer to Figure 35 A second isolation structure 700 is formed in the second selection gate 202. The second isolation structure 700 extends through the second selection gate 202 along the first direction Z and is spaced apart from the second gate layer 203.

[0300] The steps for forming the second isolation structure 700 are described in the foregoing embodiment.

[0301] refer to Figure 36Remove the temporary substrate C1; after removing the temporary substrate C1, form a first isolation structure 600 in the first select gate 102, the first isolation structure 600 being spaced apart from the first gate layer 103; after removing the temporary substrate C1, form an insulating protective layer C on the side of the first stacked structure 100 away from the direction opposite to the first direction Z, the first channel extension 502 penetrating the insulating protective layer C.

[0302] The steps of removing the temporary substrate C1, forming the first isolation structure 600, and forming the insulating protective layer C are described in the foregoing embodiments.

[0303] Another embodiment of the present invention provides a method for fabricating a semiconductor structure. The difference between this embodiment and the semiconductor structure fabrication method of the preceding embodiments is that: a first sacrificial channel extension is replaced with a first channel extension on one side of the first stacked structure along the direction opposite to the first direction; replacing the first sacrificial channel connection with a first channel connection includes: replacing the first sacrificial channel connection with a first channel connection on one side of the first stacked structure along the direction opposite to the first direction. Forming the first channel connection includes: forming an isolation layer and a conductive layer, wherein the isolation layer is located on the sidewall of the conductive layer.

[0304] The following is combined with Figures 37 to 43 This section provides a detailed introduction to the fabrication methods of semiconductor structures.

[0305] refer to Figure 37 , Figure 37 In order to be in Figure 16 Based on the schematic diagram, the third sacrificial channel extension 4005 and the second sacrificial channel extension 4004 are removed; after removing the third sacrificial channel extension 4005 and the second sacrificial channel extension 4004, a second channel extension 503 is formed in the second extension opening, and a third channel extension 504 is formed in the third extension opening. The second channel extension 503 and the third channel extension 504 together include a functional layer 521, a channel layer 522, and a filling medium layer 523.

[0306] The functional layer 521 extends to the sidewalls of the second and third extension ports, the filling medium layer 523 fills the second and third extension ports, and the channel layer 522 is located between the functional layer 521 and the filling medium layer 523.

[0307] In some embodiments, the process for forming the functional layer 521 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the channel layer 522 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the filling dielectric layer 523 includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0308] refer to Figure 38 At least a portion of the first sacrificial dielectric layer 1002 is replaced with the first select gate 102, at least a portion of the second sacrificial dielectric layer 2002 is replaced with the first gate layer 103, and at least a portion of the third sacrificial dielectric layer 4001 is replaced with the second gate layer 203 and the second select gate 202.

[0309] In some embodiments, the fabrication of the semiconductor structure further includes forming a third isolation trench that penetrates the second initial stacked structure 4000, the first sacrificial layer 3000, and the first initial stacked structure. The third isolation trench is spaced apart from the third channel extension 504.

[0310] In some embodiments, the process for forming the third isolation trench is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0311] In some embodiments, at least a portion of the first sacrificial dielectric layer 1002 is replaced with the first select gate 102 via a third isolation trench, at least a portion of the second sacrificial dielectric layer 2002 is replaced with the first gate layer 103 via a third isolation trench, and at least a portion of the third sacrificial dielectric layer 4001 is replaced with the second gate layer 203 and the second select gate 202 via a third isolation trench.

[0312] The description of the first selection gate 102, the first gate layer 103, the second gate layer 203, and the second selection gate 202 refers to the description of the foregoing embodiments.

[0313] In other embodiments, at least a portion of the first sacrificial dielectric layer 1002 may be replaced with the first select gate 102, and at least a portion of the second sacrificial dielectric layer may be replaced with the first gate layer 103 and the third select gate; at least a portion of the third sacrificial dielectric layer 4001 may be replaced with the second gate layer 203, the second select gate 202, and the fourth select gate. The description of the first select gate 102, the first gate layer 103, the second gate layer 203, the second select gate 202, the third select gate, and the fourth select gate refers to the description of the foregoing embodiments.

[0314] refer to Figure 38 The first sacrificial layer 3000 is replaced with a semiconductor layer 300, and the semiconductor layer 300 and the channel layer 522 are connected.

[0315] In some embodiments, the method for fabricating the semiconductor structure further includes forming a third isolation structure in a third isolation trench, the third isolation structure penetrating the second stacked structure 200, the semiconductor layer 300, and the first stacked structure 100. The material of the third isolation structure includes, for example, an insulating dielectric material such as silicon oxide.

[0316] refer to Figure 39A second isolation structure 700 is formed in the second selection gate 202. The second isolation structure 700 extends through the second selection gate 202 along the first direction Z and is spaced apart from the second gate layer 203.

[0317] The steps for forming the second isolation structure 700 are described in the foregoing embodiments.

[0318] refer to Figure 40 The temporary substrate C1 is planarized until the first sacrificial trench extension 1004 is exposed.

[0319] The steps of planarizing the temporary substrate C1 until the first sacrificial trench extension 1004 is exposed are described in the foregoing embodiment.

[0320] Reference Figure 41 and Figure 42 The first sacrificial channel extension 1004 is replaced with the first channel extension 502, and the first sacrificial channel connecting part 2004 is replaced with the first channel connecting part 501.

[0321] In some embodiments, replacing the first sacrificial channel extension 1004 with the first channel extension 502 includes replacing the first sacrificial channel extension 1004 with the first channel extension 502 on the side of the first laminated structure 100 opposite to the first direction Z. For example, replacing the first sacrificial channel extension 1004 with the first channel extension 502 on the side of the first laminated structure 100 opposite to the second laminated structure 200.

[0322] In some embodiments, replacing the first sacrificial channel connection 2004 with the first channel connection 501 includes replacing the first sacrificial channel connection 2004 with the first channel connection 501 on the side of the first laminated structure 100 opposite to the first direction Z. For example, replacing the first sacrificial channel connection 2004 with the first channel connection 501 on the side of the first laminated structure 100 opposite to the second laminated structure 200.

[0323] refer to Figure 41 Remove the first sacrificial channel extension 1004 and the first sacrificial channel connecting portion 2004.

[0324] In some embodiments, the process of removing the first sacrificial channel extension 1004 and the first sacrificial channel connection 2004 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0325] Remove the first sacrificial channel extension 1004 and the first sacrificial channel connection 2004 to expose the first extension port 1003 and the first contact port 2003.

[0326] In some embodiments, after removing the first sacrificial channel extension 1004 and the first sacrificial channel connector 2004, the portion of the functional layer 521 located between the first contact 2003 and the filling dielectric layer 523, and the portion of the channel layer 522 located between the first contact 2003 and the filling dielectric layer 523 are etched away. To ensure complete removal of the portions of the functional layer 521 and the channel layer 522 located between the first contact 2003 and the filling dielectric layer 523, over-etching is performed, during which a recess T is formed in the filling dielectric layer 523.

[0327] refer to Figure 42 A first channel extension 502 is formed in the first extension opening 1003, and a first channel connection 501 is formed in the first contact opening 2003.

[0328] For example, a first channel connection portion 501 is formed in the first contact port 2003 and the recess T, a portion of the first channel connection portion 501 extends along the first direction Z into the filling medium layer 523, and a portion of the first channel connection portion 501 is embedded in the filling medium layer 523.

[0329] In some embodiments, a first channel extension 502 is formed in the first extension opening 1003, and a first channel connection 501 is formed in the first contact opening 2003 and the recess T, including: forming an isolation layer 541 on the sidewall of the first extension opening 1003 and the sidewall of the first contact opening 2003, the isolation layer 541 exposing the channel layer 522 and the inner wall of the recess T; forming a conductive layer 542 on the sidewall of the isolation layer 541 and the sidewall of the recess T, the conductive layer 542 and the channel layer 522 being connected.

[0330] In some embodiments, forming an isolation layer 541 on the sidewall of the first extension port 1003 and the sidewall of the first contact port 2003 includes: forming an initial isolation layer on the sidewall of the first extension port 1003, the inner wall of the first contact port 2003, and the inner wall of the recess T; removing the portion of the initial isolation layer located on the inner wall of the recess T and the portion of the initial isolation layer located on the inner wall of the first contact port 2003 opposite to the first extension port 1003, with the remaining initial isolation layer forming the isolation layer 541.

[0331] In some implementations, the process for forming the initial isolation layer includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0332] In some embodiments, the portion of the initial isolation layer located on the inner wall of the recess T, and the portion of the initial isolation layer located on the inner wall of the first contact port 2003 opposite to the first extension port 1003, are removed by an etching process, which includes one or a combination of dry etching and wet etching processes.

[0333] In some embodiments, the process of forming the conductive layer 542 on the sidewalls of the isolation layer 541 and the sidewalls of the recess T includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0334] Figure 43 for Figure 42 Enlarged view of the dashed box K1. The first channel extension 502 and the first channel connection 501 together include an isolation layer 541 and a conductive layer 542. The second channel extension 503 and the third channel extension 504 together include a functional layer 521, a channel layer 522 and a filling dielectric layer 523. The functional layer 521 exposes the channel layer 522 in the semiconductor layer 300. The semiconductor layer 300 and the channel layer 522 are in contact.

[0335] The descriptions of the functional layer 521, channel layer 522, filling dielectric layer 523, isolation layer 541, and conductive layer 542 are the same as those in the foregoing embodiments and will not be repeated in detail.

[0336] refer to Figure 42 Remove the temporary substrate C1; after removing the temporary substrate C1, form a first isolation structure 600 in the first select gate 102, the first isolation structure 600 being spaced apart from the first gate layer 103; after removing the temporary substrate C1, form an insulating protective layer C on the side of the first stacked structure 100 away from the direction opposite to the first direction Z, the first channel extension 502 penetrating the insulating protective layer C.

[0337] The steps of removing the temporary substrate C1, forming the first isolation structure 600, and forming the insulating protective layer C are described in the foregoing embodiments.

[0338] Another embodiment of this application also provides a memory, referenced... Figure 44 It includes a memory cell array F1 and a peripheral circuit F2. The memory cell array F1 includes the semiconductor structure provided in the above embodiments of this application, and the peripheral circuit F2 is coupled to the memory cell array F1.

[0339] The memory can be 3D NAND flash memory. The memory cell array F1 can be a 3D NAND flash memory cell array.

[0340] The semiconductor structure may be the same as the semiconductor structure described in any of the embodiments above, and will not be described again in the embodiments of this application.

[0341] In some implementations, the peripheral circuitry F2 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array F1. For example, the peripheral circuitry F2 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0342] Another embodiment of this application also provides a storage system 30000, see reference. Figure 45 The storage system 30000 includes a controller 32200 and a memory 32100 provided in the above embodiments of this application. The controller 32200 is coupled to the memory 32100 and is used to control the memory 32100 to store data.

[0343] The storage system 30000 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage device located therein). Figure 45 As shown, the storage system 30000 also includes a host 31000. The host 31000 may be a processor of an electronic device, such as a central processing unit (CPU), or it may be a system-on-chip (SoC), such as an application processor (AP). The host 31000 may be configured to send or receive data to and from the memory 32100.

[0344] According to some embodiments, controller 32200 is coupled to memory 32100 and host 31000, and is configured to control memory 32100. Controller 32200 can manage data stored in memory 32100 and communicate with host 31000. In some embodiments, controller 32200 is designed to operate in a low duty cycle environment, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 32200 is designed to operate in a high duty cycle environment, such as SSDs or embedded multi-media cards (eMMC) used as data storage devices in mobile devices such as smartphones, tablets, laptops, etc. Controller 32200 can be configured to control operations of memory 32100, such as read, erase, and program operations. The controller 32200 can also be configured to manage various functions related to data stored in or to be stored in the memory 32100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 32200 is further configured to process error correction codes (ECCs) related to data read from or written to the memory 32100. The controller 32200 can also perform any other appropriate functions, such as formatting the memory 32100. The controller 32200 can communicate with external devices (e.g., the host 31000) according to a specific communication protocol.For example, the controller 32200 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0345] Although exemplary fabrication methods and structures of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. Furthermore, the materials of the exemplified layers are merely exemplary.

[0346] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, comprising: The first stacked structure includes a first gate layer and a first select gate, wherein the first gate layer is located on one side of the first select gate along a first direction; as well as A channel structure that penetrates the first stacked structure along the first direction; The channel structure includes a first sidewall, a second sidewall, and a connecting surface connecting the first sidewall and the second sidewall. The first sidewall extends in the first select gate, and the second sidewall extends in the first gate layer. The connecting surface intersects the first sidewall and the second sidewall, respectively.

2. The semiconductor structure according to claim 1, wherein, The channel structure includes: A first channel extension extends in the first selection gate along the first direction, the first channel extension having the first sidewall; and A first channel connection portion is located in a portion of the first gate layer and connected to the first channel extension portion, the first channel connection portion having a second sidewall and the connection surface; Wherein, along the direction intersecting the first direction, the size of the first channel extension is smaller than the size of the end of the first channel connection toward the first channel extension.

3. The semiconductor structure according to claim 2, wherein, Along the direction intersecting the first direction, the dimension of the end of the first channel extension toward the first channel connection is smaller than the dimension of the end of the first channel connection toward the first channel extension.

4. The semiconductor structure according to claim 3, wherein, Along the direction intersecting the first direction, the dimension of the end of the first channel extension away from the first channel connection is less than or equal to the dimension of the end of the first channel extension toward the first channel connection.

5. The semiconductor structure according to claim 2, wherein, Along the direction intersecting the first direction, the dimension of the end of the first channel extension away from the first channel connection portion is 70nm to 200nm.

6. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: A first isolation structure extends through the first select gate along the first direction and is spaced apart from the first gate layer.

7. The semiconductor structure according to claim 6, wherein, The first isolation structure extends along the second direction and divides the first selection gate into a first sub-selection gate and a second sub-selection gate, the first sub-selection gate and the second sub-selection gate being respectively connected to different channel structures; The second direction intersects with the first direction.

8. The semiconductor structure according to claim 6, wherein, Along the direction intersecting the first direction, the dimension of the end of the first isolation structure away from the first gate layer is greater than the dimension of the end of the first isolation structure facing the first gate layer.

9. The semiconductor structure according to claim 1, wherein, The first selection gate has multiple layers.

10. The semiconductor structure according to claim 2, wherein, The semiconductor structure also includes: A semiconductor layer is located on one side of the first stacked structure along the first direction; and The second stacked structure is located on the side of the semiconductor layer opposite to the first stacked structure, and includes a second gate layer; Wherein, the first gate layer is located between the first selection gate and the semiconductor layer; The channel structure also extends through the second stacked structure and the semiconductor layer along the first direction, and the channel layer and the semiconductor layer in the channel structure are connected.

11. The semiconductor structure according to claim 10, wherein, The second stacked structure further includes: The second selection gate is located on the side of the second gate layer opposite to the semiconductor layer; The semiconductor structure further includes: The second isolation structure extends through the second selection gate along the first direction and is spaced apart from the second gate layer; Wherein, along the direction intersecting the first direction, the dimension of the end of the second isolation structure away from the second gate layer is greater than the dimension of the end of the second isolation structure facing the second gate layer.

12. The semiconductor structure according to claim 11, wherein, The second isolation structure extends along the second direction and divides the second selection gate into a third sub-selection gate and a fourth sub-selection gate, the third sub-selection gate and the fourth sub-selection gate being respectively connected to different channel structures; The second direction intersects with the first direction.

13. The semiconductor structure according to claim 10, wherein, The channel structure also includes: A second channel extension extends along the first direction in the semiconductor layer and a portion of the first gate layer; and The third channel extension extends in the second stacked structure along the first direction; Wherein, along the direction intersecting with the first direction, the dimension of the end of the second channel extension toward the first channel connection is smaller than the dimension of the end of the first channel connection toward the second channel extension, and the dimension of the end of the second channel extension away from the first channel connection is larger than the dimension of the end of the third channel extension toward the side of the second channel extension.

14. The semiconductor structure according to claim 10, wherein, The channel structure also includes: The second channel extension extends along the first direction in the semiconductor layer and a portion of the first gate layer; A portion of the first channel connection extends into the second channel extension along the first direction.

15. The semiconductor structure according to claim 10, wherein, The channel structure further includes: a second channel extension extending in the semiconductor layer and a portion of the first gate layer along the first direction; and a third channel extension extending in the second stacked structure along the first direction. The first channel extension, the first channel connection, the second channel extension, and the third channel extension together include a functional layer and a channel layer. Alternatively, the first channel extension and the first channel connection together include an isolation layer and a conductive layer, the isolation layer being located on the sidewall of the conductive layer; the second channel extension and the third channel extension together include a functional layer and a channel layer extending along the first direction, the conductive layer and the channel layer being connected.

16. The semiconductor structure according to claim 15, wherein, The material of the conductive layer includes any one of polycrystalline silicon, doped polycrystalline silicon, metallic materials, or metal silicides.

17. The semiconductor structure according to any one of claims 2 to 5 and claims 10 to 16, wherein, The semiconductor structure also includes: An insulating protective layer is located on one side of the first laminated structure in a direction opposite to the first direction; The first channel extension penetrates the insulating protective layer.

18. The semiconductor structure according to claim 1, wherein, The first selection gate and the first gate layer are used to apply potentials at different timings.

19. The semiconductor structure according to claim 11, wherein, The second selection gate and the second gate layer are used to apply potentials with different timings.

20. A method for fabricating a semiconductor structure, comprising: Forming the first layered structure; Forming a channel structure; The first stacked structure includes a first gate layer and a first select gate, wherein the first gate layer is located on one side of the first select gate along a first direction; the channel structure extends through the first stacked structure along the first direction. The channel structure includes a first sidewall, a second sidewall, and a connecting surface connecting the first sidewall and the second sidewall. The first sidewall extends in the first select gate, and the second sidewall extends in the first gate layer. The connecting surface intersects the first sidewall and the second sidewall, respectively.

21. The preparation method according to claim 20, wherein, The formation of the channel structure includes: A first channel extension and a first channel connection are formed. The first channel extension extends in the first select gate along the first direction and has the first sidewall. The first channel connection is located in a portion of the first gate layer and connected to the first channel extension. The first channel connection has the second sidewall and the connection surface. Wherein, along the direction intersecting the first direction, the size of the first channel extension is smaller than the size of the end of the first channel connection toward the first channel extension.

22. The preparation method according to claim 21, wherein, The formation of the first stacked structure includes: A first initial sub-stack structure is formed, the first initial sub-stack structure including a first sacrificial dielectric layer; A second initial sub-stack structure is formed on one side of the first initial sub-stack structure along the first direction, the second initial sub-stack structure including a second sacrificial dielectric layer; At least a portion of the first sacrificial dielectric layer is replaced with the first select gate; and at least a portion of the second sacrificial dielectric layer is replaced with the first gate layer.

23. The preparation method according to claim 22, wherein, The first channel extension includes: A first sacrificial channel extension is formed in the first initial sub-stack structure; and Replace the first sacrificial channel extension with the first channel extension; The first channel connection portion includes: A first sacrificial channel connection is formed in a portion of the second initial sub-stack structure; and Replace the first sacrificial channel connector with the first channel connector.

24. The preparation method according to claim 23, wherein, Forming the first sacrificial channel extension in the first initial sub-stack structure includes: A first extension opening is formed in the first initial sub-stacked structure; and The first sacrificial channel extension is formed in the first extension opening.

25. The preparation method according to claim 23, wherein, The formation of the first sacrificial channel connection in a portion of the second initial sub-stack structure includes: A first contact opening is formed in a portion of the second initial sub-stack structure, the first contact opening exposing the first sacrificial channel extension; the size of the first contact opening is larger than the size of the first sacrificial channel extension in a direction intersecting the first direction; and a first sacrificial channel connection is formed in the first contact opening.

26. The preparation method according to claim 23, 24 or 25, wherein, The material of the first sacrificial channel extension is different from the material of the second initial sub-layer structure.

27. The preparation method according to claim 23, wherein, Replacing the first sacrificial channel extension with the first channel extension includes: The first sacrificial channel extension is replaced with the first channel extension on one side of the first stacked structure in the opposite direction to the first direction. The replacement of the first sacrificial channel connection portion with the first channel connection portion includes: replacing the first sacrificial channel connection portion with the first channel connection portion on one side of the first laminated structure in the direction opposite to the first direction.

28. The preparation method according to claim 23, wherein, Replacing the first sacrificial channel extension with the first channel extension includes: On the side of the second initial sub-stack structure that is away from the first initial sub-stack structure, the first sacrificial channel extension is replaced with the first channel extension; The replacement of the first sacrificial channel connection with the first channel connection includes: replacing the first sacrificial channel connection with the first channel connection on the side of the second initial sub-stack structure that is away from the first initial sub-stack structure.

29. The preparation method according to claim 22, wherein, The first channel extension includes: Before forming the second initial sub-stack structure, the first channel extension is formed in the first initial sub-stack structure; The formation of the first channel connection portion includes: forming the first channel connection portion in a portion of the second initial sub-stack structure.

30. The preparation method according to claim 21, wherein, Forming the first channel extension and the first channel connection includes: forming an isolation layer and a conductive layer, wherein the isolation layer is located on the sidewall of the conductive layer; Alternatively, forming the first channel extension and the first channel connection includes forming a first functional portion and a first channel portion extending along the first direction.

31. The preparation method according to claim 21, wherein, The preparation method further includes: Forming a semiconductor layer; Forming a second layered structure; Wherein, the semiconductor layer is located on one side of the first stacked structure along the first direction, the second stacked structure is located on the side of the semiconductor layer opposite to the first stacked structure, and the second stacked structure includes a second gate layer; Wherein, the first gate layer is located between the first selection gate and the semiconductor layer; The channel structure also extends through the second stacked structure and the semiconductor layer along the first direction, and the channel layer and the semiconductor layer in the channel structure are connected.

32. The preparation method according to claim 31, wherein, The formation of the first stacked structure and the second stacked structure includes: The first stacked structure and the second stacked structure are formed on one side of a temporary substrate; The preparation method further includes: After forming the first and second stacked structures, the temporary substrate is removed; and After removing the temporary substrate, a first isolation structure is formed in the first select gate, the first isolation structure being spaced apart from the first gate layer.

33. The preparation method according to claim 32, wherein, The preparation method further includes: After removing the temporary substrate, an insulating protective layer is formed on the side of the first stacked structure opposite to the direction opposite to the first direction; The first channel extension penetrates the insulating protective layer.

34. The preparation method according to claim 33, wherein, The insulating protective layer is formed during the formation of the first isolation structure.

35. A memory comprising: A memory cell array, comprising the semiconductor structure as described in any one of claims 1 to 19; as well as The peripheral circuitry is coupled to the memory cell array.

36. A storage system, comprising: The memory as described in claim 35; as well as A controller, coupled to the memory, is used to control the memory to store data.

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