A trench silicon carbide MOSFET and its fabrication method, chip

Abstract

This application belongs to the field of power device technology and provides a trench silicon carbide MOSFET, its fabrication method, and a chip. By discretizing the P-type well region inside the device into a first P-type well region and a second P-type well region with different doping concentrations, the first P-type well region mainly acts as a breakdown junction in the device blocking state. The high doping of the first P-type well region can ensure that the breakdown voltage of the device meets the requirements. Moreover, the high doping of the first P-type well region can deplete the second current extension layer near the channel of the second P-type well region, preventing the second P-type well region from breaking down prematurely. Furthermore, by wrapping the bottom corner of the trench with the first P-type well region, the drain electric field line can be terminated in the device blocking state, realizing the transfer of the electric field peak in the gate oxide layer, improving the gate reliability of the device, and extending its service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a trench silicon carbide MOSFET and its fabrication method and chip. Background Technology

[0002] Due to their excellent material properties, including wide bandgap, high critical electric field, and good thermal conductivity, silicon carbide-based devices, such as the SiC Trench-Gate Metal Oxide Semiconductor Field Effect Transistor (SiC TG-MOSFET), have very high gate density without being limited by the parasitic JFET channels in planar SiC MOSFETs, thus reducing the contribution of channel resistance to the total on-resistance.

[0003] Compared to traditional planar MOSFETs, TG-MOSFETs can significantly reduce specific on-resistance by accommodating more channels within a given chip area and completely eliminating the JFET effect. However, during device operation, high electric field peaks tend to form in the gate oxide layer of the trench, especially at the bottom corner, affecting the reliability of long-term operation; the gate-drain capacitance is generally large, resulting in higher switching time and switching losses. To alleviate these problems, continuous optimization of the trench SiC MOSFET structure is necessary. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a trench silicon carbide MOSFET and its fabrication method and chip, aiming to reduce the gate oxide electric field strength and parasitic capacitance of the device without sacrificing the device's on-resistance, thereby optimizing the device's dynamic characteristics.

[0005] The first aspect of this application provides a trench silicon carbide MOSFET, which includes: a drain layer, a silicon carbide substrate, an N-type drift region, a first P-type well region, a second P-type well region, a first current spreading layer, a second current spreading layer, a gate oxide layer, an N-type heavily doped region, an insulating dielectric layer, a source layer, and a plurality of P-type heavily doped regions.

[0006] The drain layer, the silicon carbide substrate, and the N-type drift region are stacked in a first direction. The N-type drift region has a convex structure. The gate oxide layer is formed on the protrusion of the N-type drift region, and a gate layer is formed in the gate oxide layer.

[0007] The first P-type well region and the first current spreading layer are formed on the horizontal portion of the N-type drift region, and the first P-type well region surrounds the bottom corner of the gate oxide layer; the second current spreading layer is formed on the first P-type well region and the first current spreading layer, the second P-type well region is formed on the horizontal portion of the second current spreading layer, and the heavily doped N-type region is formed on the horizontal portion of the second P-type well region. The first P-type well region, the second current spreading layer, the second P-type well region, and the heavily doped N-type region are located on both sides of the gate oxide layer within a first predetermined cross section in the second direction.

[0008] Multiple P-type heavily doped regions are spaced apart on the second P-type well region in a third direction, and are located between the vertical portion of the second P-type well region and the second current spreading layer within a second predetermined cross section in the second direction; the first direction, the second direction, and the third direction are perpendicular to each other;

[0009] The source layer and the second current spread layer are connected by a Schottky contact, and the source layer is connected by an ohmic contact with the N-type heavily doped region, the P-type heavily doped region and the second P-type well region. The insulating dielectric layer is disposed between the source layer and the gate layer.

[0010] In some embodiments, the first P-type well region has an L-shaped structure, with the horizontal portion of the first P-type well region contacting the bottom of the gate oxide layer, and the vertical portion of the first P-type well region contacting the side of the gate oxide layer; or

[0011] The interface between the first P-type well region and the gate oxide layer is arc-shaped. One end of the interface between the first P-type well region and the gate oxide layer contacts the bottom of the gate oxide layer, and the other end of the interface between the first P-type well region and the gate oxide layer contacts the side of the gate oxide layer.

[0012] In some embodiments, the doping concentration of the first current spreading layer is greater than the doping concentration of the second current spreading layer;

[0013] The doping concentrations of the first current spreading layer and the second current spreading layer are greater than the doping concentration of the N-type drift region.

[0014] In some embodiments, the heavily doped P-type region extends into the vertical portion of the first P-type well region, and divides the second current extension layer into isolated horizontal and vertical portions within the second preset cross section; the second preset cross section is horizontally aligned with the third portion.

[0015] In some embodiments, the depth of the P-type heavily doped region in the first direction is greater than the depth of the second current spreading layer, and in the third direction it is located between the vertical portion of the N-type heavily doped region and the second current spreading layer.

[0016] In some embodiments, the contact interface between the P-type heavily doped region and the source layer within the second preset cross-section is smaller than the width of the P-type heavily doped region within the second preset cross-section, so that the N-type heavily doped region does not contact the source layer within the second preset cross-section.

[0017] In some embodiments, the spacing between adjacent heavily doped P-type regions is greater than the width of the heavily doped P-type regions in the second direction.

[0018] A second aspect of this application also provides a method for fabricating a trench silicon carbide MOSFET, the method comprising:

[0019] A silicon carbide substrate is provided, and an N-type drift region is formed on the front side of the silicon carbide substrate;

[0020] A first P-type well region and a first current spreading layer are formed in the peripheral region of the N-type drift region through multiple ion implantation processes, so that the N-type drift region has a convex structure.

[0021] A second current spreading layer is formed along the first direction on the first P-type well region, the first current spreading layer, and the N-type drift region, and a second P-type well region and an N-type heavily doped region are formed on the second current spreading layer through multiple ion implantation processes; the second current spreading layer and the second P-type well region are concave in shape within the cross-section of the second direction;

[0022] Multiple P-type impurities are injected into multiple preset regions spaced upwards from the third side to form multiple heavily doped P-type regions; wherein, the cross-section of the portion between adjacent preset regions in the second direction is defined as a first preset cross-section, and the cross-section of the portion within the preset regions in the second direction is defined as a second preset cross-section.

[0023] A gate trench is formed by etching a predetermined trench region, and a gate oxide layer and a gate layer are formed in the gate trench; wherein the gate layer is located in the groove of the gate oxide layer;

[0024] An insulating dielectric layer is deposited and etched so that the insulating dielectric layer covers the gate layer, and covers a portion of the heavily doped N-type region within the first preset cross section, and covers the entire region of the heavily doped N-type region within the second preset cross section.

[0025] A source layer and a drain layer are formed, wherein the source layer and the second current extension layer are connected by a Schottky contact, and the source layer and the N-type heavily doped region, the P-type heavily doped region and the second P-type well region are connected by an ohmic contact.

[0026] In some embodiments, etching a predetermined trench region to form a gate trench, and forming a gate oxide layer and a gate layer within the gate trench, includes:

[0027] Through multiple etching processes, the first P-type well region is made into an L-shaped structure, with the horizontal portion of the first P-type well region contacting the bottom of the gate oxide layer, and the vertical portion of the first P-type well region contacting the side of the gate oxide layer; or

[0028] Through multiple etching processes, the horizontal and vertical portions of the first P-type well region are made to be arc-shaped, the interface between the first P-type well region and the gate oxide layer is arc-shaped, one end of the interface between the first P-type well region and the gate oxide layer is in contact with the bottom of the gate oxide layer, and the other end of the interface between the first P-type well region and the gate oxide layer is in contact with the side of the gate oxide layer.

[0029] A third aspect of this application also provides a chip, including a trench silicon carbide MOSFET as described in any of the preceding embodiments; or, including a trench silicon carbide MOSFET prepared by the preparation method described in any of the preceding embodiments.

[0030] The beneficial effects of this application's embodiments are as follows: By discretizing the P-type well region inside the device into a first P-type well region and a second P-type well region with different doping concentrations, in the device blocking state, the first P-type well region mainly acts as a breakdown junction. The high doping of the first P-type well region can ensure that the breakdown voltage of the device meets the requirements. Moreover, the high doping of the first P-type well region can deplete the second current extension layer near the channel of the second P-type well region, preventing the second P-type well region from breaking down prematurely. Furthermore, by wrapping the bottom corner of the trench with the first P-type well region, the drain electric field line can be terminated in the device blocking state, realizing the transfer of the electric field peak in the gate oxide layer, improving the gate reliability of the device, and extending its service life. At the same time, it plays a certain shielding role for the drain voltage, reduces the parasitic capacitance at the bottom of the gate trench, optimizes the gate drain charge, and optimizes the dynamic characteristics of the device. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a horizontal cross-section of a trench silicon carbide MOSFET provided in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of cross-section A of the trench silicon carbide MOSFET provided in an embodiment of this application;

[0033] Figure 3 This is a schematic diagram of cross-section B of the trench silicon carbide MOSFET provided in the embodiments of this application;

[0034] Figure 4 This is a schematic flowchart of a method for fabricating a trench silicon carbide MOSFET provided in an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0036] Figure 6 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0037] Figure 7 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0038] Figure 8 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0039] Figure 9 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0040] Figure 10 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0041] Figure 11 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0042] Figure 12 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0043] Figure 13 This is a schematic diagram of one of the structural methods for fabricating a trench silicon carbide MOSFET provided in the embodiments of this application. Detailed Implementation

[0044] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0045] In current SiC MOSFET device development, trench structures are a highly promising design because they can optimize the device's conduction capability (specific on-resistance) by creating channels in crystal orientations with higher mobility, eliminating JFET region resistance, and increasing channel density through cell size compression. Most manufacturers are currently focusing their research on trench structures, which are considered the mainstream structure for future SiC MOSFET devices. Compared to traditional planar MOSFETs, TG-MOSFETs can significantly reduce specific on-resistance by accommodating more channels within a given chip area and completely eliminating the JFET effect. However, during device operation, high electric field peaks easily form in the gate oxide layer of the trench, especially at the bottom corner, affecting long-term reliability; the gate-drain capacitance is generally large, leading to higher switching time and switching losses. To alleviate these problems, continuous optimization of the trench SiC MOSFET structure is necessary.

[0046] To address the aforementioned technical problems, this application provides a trench silicon carbide MOSFET, see [link to relevant documentation]. Figure 1 , Figure 2 as well as Figure 3 As shown, the trench silicon carbide MOSFET in this embodiment includes: a drain layer 110, a silicon carbide substrate 210, an N-type drift region 220, a first P-type well region 310, a second P-type well region 320, a first current spreading layer 410, a second current spreading layer 420, a gate oxide layer 610, an N-type heavily doped region 510, an insulating dielectric layer 630, a source layer 120, and a plurality of P-type heavily doped regions 710; the drain layer 110, the silicon carbide substrate 210, and the N-type drift region 220 are stacked in a first direction, the N-type drift region 220 has a convex structure, the gate oxide layer 610 is formed on the protrusion of the N-type drift region 220, and a gate layer 6 is formed in the gate oxide layer 610. 20; A first P-type well region 310 and a first current spreading layer 410 are formed on the horizontal portion of the N-type drift region 220, and the first P-type well region 310 surrounds the bottom corner of the gate oxide layer 610; a second current spreading layer 420 is formed on the first P-type well region 310 and the first current spreading layer 410, the second P-type well region 320 is formed on the horizontal portion of the second current spreading layer 420, and an N-type heavily doped region 510 is formed on the horizontal portion of the second P-type well region 320. The first P-type well region 310, the second current spreading layer 420, the second P-type well region 320, and the N-type heavily doped region 510 are located on both sides of the gate oxide layer 610 within a first predetermined cross-section (cross-section A) in the second direction. Figure 1As shown, multiple P-type heavily doped regions 710 are spaced apart on the second P-type well region 320 in the third direction, and are located between the vertical portion of the second P-type well region 320 and the second current extension layer 420 in the second predetermined cross section (cross section B) in the second direction; the first direction, the second direction and the third direction are perpendicular to each other; the source layer 120 and the second current extension layer 420 are in Schottky contact, and the source layer 120 and the N-type heavily doped region 510, the P-type heavily doped region 710 and the second P-type well region 320 are in ohmic contact; the insulating dielectric layer 630 is disposed between the source layer 120 and the gate layer 620.

[0047] In this embodiment, by discretizing the P-type well region inside the device into a first P-type well region 310 and a second P-type well region 320 with different doping concentrations, the first P-type well region 310 mainly acts as a breakdown junction in the device blocking state. The high doping of the first P-type well region 310 can ensure that the breakdown voltage of the device meets the requirements. Moreover, the high doping of the first P-type well region 310 can deplete the second current extension layer 420 near the channel of the second P-type well region 320, preventing the second P-type well region 320 from breaking down prematurely. Furthermore, by wrapping the bottom corner of the trench with the first P-type well region 310, the drain electric field line can be terminated in the device blocking state to realize the transfer of the electric field peak in the gate oxide layer 610, thereby improving the gate reliability of the device and extending its service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

[0048] In some embodiments, the first P-type well region 310 is located at the bottom of the trench, and the shape of the first P-type well region 310 in section A is not limited to L-shape and arc shape, forming a structure that wraps the corner pole of the gate oxide layer 610 at the bottom of the trench.

[0049] In this embodiment, the first P-type well region 310 and the second P-type well region 320 have different doping concentrations. By forming the first P-type well region 310 and the second P-type well region 320 with different doping concentrations, the P-type well region is discretely divided into two parts. The first P-type well region 310 is located below the second P-type well region 320, and the first P-type well region 310 is located at the bottom of the trench. The active region of the device is... Figure 2The cross-section A shown presents a repeating arrangement of multiple cells. Since the doping concentration of the first P-type well region 310 is greater than that of the second P-type well region 320, the high doping of the first P-type well region 310 can deplete the second current extension layer 420 near the channel of the second P-type well region 320, preventing the second P-type well region 320 from breaking down prematurely. Furthermore, by wrapping the bottom corner of the trench with the first P-type well region 310, the drain electric field line can be terminated in the device blocking state, realizing the transfer of the electric field peak in the gate oxide layer 610, improving the gate reliability of the device, and extending its service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

[0050] In some embodiments, the first P-type well region 310 has an L-shaped structure, with the horizontal portion of the first P-type well region 310 contacting the bottom of the gate oxide layer 610 and the vertical portion of the first P-type well region 310 contacting the side portion of the gate oxide layer 610.

[0051] In this embodiment, the first P-type well region 310 is configured as an L-shaped structure, which can wrap the bottom of the gate oxide layer 610 and the side adjacent to its bottom, thereby wrapping the corner position of the gate oxide layer 610. By setting the doping concentration of the first P-type well region 310 to be greater than that of the second P-type well region 320, the high doping of the first P-type well region 310 can deplete the second current extension layer 420 near the channel of the second P-type well region 320, preventing the second P-type well region 320 from breaking down prematurely. Furthermore, by wrapping the corner of the bottom of the trench with the first P-type well region 310, the drain electric field line can be terminated in the device blocking state to realize the transfer of the electric field peak in the gate oxide layer 610, thereby improving the gate reliability of the device and extending its service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

[0052] In some embodiments, the area between the first P-type well region 310 and the second P-type well region 320 is the horizontal portion of the second current spreading layer 420.

[0053] In some embodiments, the thickness of the horizontal portion of the second current extension layer 420 is equal to or greater than 0.2 μm to ensure the formation of a low-resistance current path under low current, the spacing between the first P-type well region 310 and the second P-type well region 320 is not less than 0.2 μm, the spacing between the P-type well regions of adjacent cells is not less than 0.5 μm, and the peak doping concentration in the channel of the second P-type well region 320 is not higher than 4e17cm-3.

[0054] In some embodiments, the interface between the first P-type well region 310 and the gate oxide layer 610 is arc-shaped, with one end of the interface between the first P-type well region 310 and the gate oxide layer 610 contacting the bottom of the gate oxide layer 610, and the other end of the interface between the first P-type well region 310 and the gate oxide layer 610 contacting the side of the gate oxide layer 610.

[0055] In this embodiment, the first P-type well region 310 is configured as an arc-shaped structure, which can wrap around the bottom of the gate oxide layer 610 and the side adjacent to its bottom, thereby wrapping the corner position of the gate oxide layer 610. By setting the doping concentration of the first P-type well region 310 to be greater than that of the second P-type well region 320, the high doping of the first P-type well region 310 can deplete the second current extension layer 420 near the channel of the second P-type well region 320, preventing the second P-type well region 320 from breaking down prematurely. Furthermore, by wrapping the corner of the bottom of the trench with the first P-type well region 310, the drain electric field line can be terminated in the device blocking state to realize the transfer of the electric field peak in the gate oxide layer 610, thereby improving the gate reliability of the device and extending its service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

[0056] In some embodiments, the peak doping concentration of the first P-type well region 310 is not less than 1e18cm-3, which is beneficial for reducing short-circuit current and optimizing breakdown voltage.

[0057] In some embodiments, the doping concentration of the first current spreading layer 410 is greater than the doping concentration of the second current spreading layer 420; the doping concentration of the first current spreading layer 410 and the second current spreading layer 420 is greater than the doping concentration of the N-type drift region 220.

[0058] In this embodiment, both the first current spreading layer 410 and the second current spreading layer 420 are N-type doped, and the doping concentration of the first current spreading layer 410 and the second current spreading layer 420 is higher than that of the N-type drift region 220. This can provide a low-resistance transport path for electrons, thereby reducing the specific on-resistance of the device. At the same time, the interface between the second current spreading layer 420 and the source layer 120 is a Schottky contact, which can act as the body diode inside the device. Furthermore, the high doping concentration of the first current spreading layer 410 and the second current spreading layer 420 reduces the voltage drop of the body diode.

[0059] In this embodiment, when the trench silicon carbide MOSFET is turned on, at low voltage, the second P-type well region 320 has a low doping concentration, which can achieve a low channel resistance. Conductive electrons mainly flow through the channel in the low-resistance second P-type well region 320 → second current extension layer 420 → first current extension layer 410 → drain layer 110, without needing to pass through the highly doped region of the first P-type well region 310, thus reducing the device on-resistance within the rated current range. At high voltage, the regions of the first P-type well region 310 between adjacent cells and the heavily doped P-type region 710... The space charge region expansion pinches off the paths of the first current extension layer 410 and the second current extension layer 420. Conductive electrons pass through the channels of the second P-type well region 320 and the first P-type well region 310 at the same time. The opening of the conductive channel in the first P-type well region 310 can ensure that the device has a certain pulse voltage capability. At the same time, because the channel length of the first P-type well region 310 is large (the channel of the first P-type well region 310 includes vertical and horizontal parts) and the doping concentration is high, it has a high channel resistance, which can reduce the saturation current of the device under short-circuit conditions and avoid high instantaneous power burning out the device.

[0060] In some embodiments, both the first P-type well region 310 and the second P-type well region 320 have an L-shaped structure within cross-section A, and the doping concentration of the first P-type well region 310 is at least 10 times that of the second P-type well region 320. In this embodiment, by discretizing the P-type well regions of the device into two parts, the first P-type well region 310 plays a major role in blocking and short-circuit modes, optimizing device reliability and robustness; the second P-type well region 320 plays a major role in conducting mode and can be used to design the device's resistance and threshold voltage. Separate design reduces device complexity, facilitates improved overall device performance, and accelerates product development iteration. Furthermore, the grounding design of the two P-type well regions is more convenient, requiring no additional structure and reducing chip area cost.

[0061] In some embodiments, the P-type heavily doped region 710 extends into the vertical portion of the first P-type well region 310, and divides the second current extension layer 420 into isolated horizontal and vertical portions within a second preset cross section; the second preset cross section is horizontally disposed in the third direction.

[0062] In this embodiment, by setting spaced P-type heavily doped regions 710 and increasing the implantation junction depth of the P-type heavily doped regions 710, it is ensured that the P-type heavily doped regions 710 on cross-section B extend into the first P-type well region 310. This eliminates the need for increased area cost and additional grounding structures, enabling both discrete P-type well regions (first P-type well region 310 and second P-type well region 320) to be grounded. Simultaneously, because the P-type heavily doped regions 710 employ a discontinuous island-like design in the third direction, only the N-type heavily doped region 510 exists on cross-section A. This facilitates cell size compression and avoids blocking current paths on cross-section A, thus preventing the device from turning on normally.

[0063] In some embodiments, in order to ensure the grounding effect of the first P-type well region 310, the heavily doped P-type region 710 extends into the first P-type well region 310 by at least 0.2 μm in the first direction of the cross section B.

[0064] In some embodiments, the depth of the P-type heavily doped region 710 in the first direction is greater than the depth of the second current extension layer 420, and in the third direction it is located between the vertical portion of the N-type heavily doped region 510 and the second current extension layer 420.

[0065] In this embodiment, within section B, the cell width is increased by leaving a current path composed of a first current extension layer 410 and a second current extension layer 420 between the P-type well regions of adjacent cells. This is compensated for by the island-shaped design of the heavily doped P-type region 710 and the grounding design of the heavily doped P-type region 710. Furthermore, compared to traditional trench SiC MOSFET structures, this region incorporates a built-in Schottky diode, which reduces the body diode voltage drop of the MOSFET device and optimizes the reverse recovery characteristics of the body diode. This allows the trench silicon carbide MOSFET in this embodiment to be used in practical applications without requiring anti-parallel connection with an external diode, thus saving overall system area cost. In blocking mode, the space charge region of the P-type well region and the heavily doped P-type region 710 also protects the Schottky contact, preventing excessive leakage current.

[0066] In some embodiments, the contact interface between the P-type heavily doped region 710 and the source layer 120 within the second preset cross section is smaller than the width of the P-type heavily doped region 710 within the second preset cross section, so that the N-type heavily doped region 510 does not contact the source layer 120 within the second preset cross section.

[0067] In some embodiments, the spacing between adjacent heavily doped P-type regions 710 is greater than the width of the heavily doped P-type regions 710 in the second direction.

[0068] This application also provides a method for fabricating a trench silicon carbide MOSFET, see [link to relevant documentation]. Figure 4As shown, the preparation method in this embodiment includes steps S100 to S700.

[0069] In step S100, a silicon carbide substrate 210 is provided, and an N-type drift region 220 is formed on the front side of the silicon carbide substrate 210.

[0070] In this embodiment, combined with Figure 5 As shown, a silicon carbide epitaxial wafer that meets the requirements is provided, or an N-type drift region 220 is epitaxially formed on the front side of the corresponding silicon carbide substrate 210, such as... Figure 5 As shown, the structures of section A and section B are identical.

[0071] In step S200, a first P-type well region 310 and a first current extension layer 410 are formed in the peripheral region of the N-type drift region 220 through multiple ion implantation processes, so that the N-type drift region 220 has a convex structure.

[0072] In this embodiment, combined with Figure 6 As shown, the regions of the first current extension layer 410 and the first P-type well region 310 are defined by a preset mask. Under the cover of the mask, local P-type impurities (e.g., aluminum ions) and N-type impurities (e.g., nitrogen ions) are implanted in sequence to form the first P-type well region 310 and the first current extension layer 410, respectively.

[0073] In some embodiments, the N-type drift region 220 has a convex structure, and the first P-type well region 310 and the first current spreading layer 410 are both located on the horizontal portion of the N-type drift region 220. A first P-type well region 310 and a first current spreading layer 410 are respectively provided on both sides of the protrusion of the N-type drift region 220, and the first P-type well region 310 is in contact with the protrusion of the N-type drift region 220.

[0074] In some embodiments, the ion implantation depth of the first P-type well region 310 and the first current spreading layer 410 are the same, and the thickness of the first P-type well region 310 and the first current spreading layer 410 is the same.

[0075] In some embodiments, the peak doping concentration of the first P-type well region 310 is not less than 1e18cm-3, which is beneficial for reducing short-circuit current and optimizing breakdown voltage.

[0076] In step S300, a second current extension layer 420 is formed on the first P-type well region 310, the first current extension layer 410 and the N-type drift region 220 along the first direction, and a second P-type well region 320 and an N-type heavily doped region 510 are formed on the second current extension layer 420 by multiple ion implantation processes.

[0077] In this embodiment, combined with Figure 7 As shown, in Figure 6An epitaxial layer with the same doping type as the N-type drift region 220 is formed on the entire wafer. Then, a nitrogen ion implantation process is performed on the newly formed epitaxial layer to form a second current spreading layer 420 on the first P-type well region 310, the first current spreading layer 410, and the N-type drift region 220. Alternatively, a second current spreading layer 420 can be formed on the first P-type well region 310, the first current spreading layer 410, and the N-type drift region 220. Figure 6 A second current-extending layer 420 with a predetermined N-type doping concentration is directly grown on the entire wafer. Combined with... Figure 8 As shown, by sequentially implanting P-type impurities (e.g., aluminum ions) and N-type impurities (e.g., nitrogen ions) into a portion of the second current extension layer 420, a second P-type well region 320 and an N-type heavily doped region 510 can be formed, such that the second current extension layer 420 and the second P-type well region 320 have concave shapes in the cross-section of the second direction.

[0078] In some embodiments, the horizontal portion of the second current extension layer 420 is located between the first P-type well region 310 and the second P-type well region 320. To ensure the formation of a low-resistance current path under low current, the spacing between the first P-type well region 310 and the second P-type well region 320 is not less than 0.2 μm, the spacing between the P-type well regions of adjacent cells is not less than 0.5 μm, and the peak doping concentration in the channel of the second P-type well region 320 is not higher than 4e17 cm-3.

[0079] In step S400, P-type impurities are injected into multiple preset regions spaced upwards to form multiple heavily doped P-type regions 710.

[0080] In this embodiment, the cross-section of the portion between adjacent preset regions in the second direction is defined as the first preset cross-section, and the cross-section of the portion within the preset region in the second direction is defined as the second preset cross-section. Multiple preset regions spaced upwards are implanted with P-type impurities (e.g., aluminum ions) to form multiple heavily doped P-type regions 710, such as... Figure 9 Section A is shown in the figure.

[0081] In step S500, a gate trench is formed by etching a preset trench region, and a gate oxide layer 610 and a gate layer 620 are formed in the gate trench.

[0082] Combination Figure 10 As shown, etching is performed on a predetermined region in the heavily doped N-type region 510, with the etching depth reaching the first P-type well region 310 but not exceeding it, forming a gate trench. Combined with... Figure 11 As shown, a thermal oxidation process is performed to form a gate oxide layer 610 along the inner wall of the gate trench, and a polysilicon material is deposited to form a gate layer 620, which is located in the groove of the gate oxide layer 610.

[0083] In step S600, an insulating dielectric layer 630 is deposited and etched so that the insulating dielectric layer 630 covers the gate layer 620, covers a portion of the N-type heavily doped region 510 within a first preset cross section, and covers the entire region of the N-type heavily doped region 510 within a second preset cross section.

[0084] In this embodiment, Figure 11 The wafer surface shown is deposited with insulating dielectric material to form an insulating dielectric layer 630, such as Figure 12 As shown. Then, the insulating dielectric layer 630 is etched to create openings, forming an ohmic contact metal layer and a Schottky contact metal layer.

[0085] In step S700, a source layer 120 and a drain layer 110 are formed, as follows: Figure 13 As shown.

[0086] A thickened source layer 120 is formed on the front side of the wafer, and a drain layer 110 is formed on the back side of the silicon carbide substrate 210. The source layer 120 and the second current extension layer 420 are connected by a Schottky contact, and the source layer 120 is connected by an ohmic contact with the N-type heavily doped region 510, the P-type heavily doped region 710 and the second P-type well region 320.

[0087] In some embodiments, step S500 involves etching a preset trench region to form a gate trench, and forming a gate oxide layer 610 and a gate layer 620 within the gate trench. This includes: through multiple etching processes, making the first P-type well region 310 an L-shaped structure, with the horizontal portion of the first P-type well region 310 contacting the bottom of the gate oxide layer 610, and the vertical portion of the first P-type well region 310 contacting the side portion of the gate oxide layer 610.

[0088] In some embodiments, step S500 involves etching a preset trench region to form a gate trench, and forming a gate oxide layer 610 and a gate layer 620 within the gate trench. This includes: through multiple etching processes, making the horizontal and vertical portions of the first P-type well region 310 arc-shaped, the interface between the first P-type well region 310 and the gate oxide layer 610 arc-shaped, one end of the interface between the first P-type well region 310 and the gate oxide layer 610 contacting the bottom of the gate oxide layer 610, and the other end of the interface between the first P-type well region 310 and the gate oxide layer 610 contacting the side portion of the gate oxide layer 610.

[0089] In some embodiments, in order to avoid surface breakdown and improve the effect of ohmic contact, it is necessary to appropriately increase the doping concentration of the surface of the second P-type well region 320 so that it is significantly higher than the doping concentration of the channel region of the second P-type well region 320, which is beneficial to reduce the leakage current of the Schottky contact.

[0090] In some embodiments, in order to ensure the grounding effect of the first P-type well region 310, the heavily doped P-type region 710 extends into the first P-type well region 310 by at least 0.2 μm in the first direction of the cross section B.

[0091] This application also provides a chip including a trench silicon carbide MOSFET as described in any of the above embodiments.

[0092] In this embodiment, the chip includes a chip substrate, on which one or more trench silicon carbide MOSFETs are disposed. The trench silicon carbide MOSFETs can be disposed on the chip substrate as described in any of the above embodiments.

[0093] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the trench silicon carbide MOSFET.

[0094] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0095] In this embodiment, the P-type well region inside the device is discretized into a first P-type well region 310 and a second P-type well region 320 with different doping concentrations. In the device blocking state, the first P-type well region 310 mainly acts as a breakdown junction. The high doping of the first P-type well region 310 can ensure that the breakdown voltage of the device meets the requirements. Moreover, the high doping of the first P-type well region 310 can deplete the second current extension layer 420 near the channel of the second P-type well region 320, preventing the second P-type well region 320 from breaking down prematurely. Furthermore, by wrapping the bottom corner of the trench with the first P-type well region 310, the drain electric field line can be terminated in the device blocking state to realize the transfer of the electric field peak in the gate oxide layer 610, thereby improving the gate reliability of the device and extending its service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

[0096] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0097] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0098] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0099] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0100] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A trench silicon carbide MOSFET, characterized by, The trench silicon carbide MOSFET comprises a drain layer, a silicon carbide substrate, an N-type drift region, a first P-type well region, a second P-type well region, a first current spreading layer, a second current spreading layer, a gate oxide layer, an N-type heavily doped region, an insulating dielectric layer, a source layer, and a plurality of P-type heavily doped regions; The drain layer, the silicon carbide substrate, and the N-type drift region are stacked in a first direction, the N-type drift region is in a convex structure, the gate oxide layer is formed on a convex part of the N-type drift region, and a gate layer is formed in the gate oxide layer; The first P-type well region and the first current spreading layer are formed on a horizontal part of the N-type drift region, and the first P-type well region wraps the bottom corner of the gate oxide layer; the second current spreading layer is formed on the first P-type well region and the first current spreading layer, the second P-type well region is formed on a horizontal part of the second current spreading layer, the N-type heavily doped region is formed on a horizontal part of the second P-type well region, and the first P-type well region, the second current spreading layer, the second P-type well region, and the N-type heavily doped region are located on both sides of the gate oxide layer in a first preset cross section in a second direction; A plurality of the P-type heavily doped regions are spaced apart on the second P-type well region in a third direction and located between the second P-type well region and a vertical part of the second current spreading layer in a second preset cross section in the second direction; the first direction, the second direction, and the third direction are perpendicular to each other; the doping concentration of the first P-type well region is greater than the doping concentration of the second P-type well region; The source layer and the second current spreading layer are in Schottky contact, the source layer and the N-type heavily doped region, the P-type heavily doped region, and the second P-type well region are in Ohmic contact, and the insulating dielectric layer is arranged between the source layer and the gate layer.

2. The trench silicon carbide MOSFET of claim 1, wherein, The first P-type well region is in an L-shaped structure, a horizontal part of the first P-type well region is in contact with a bottom part of the gate oxide layer, and a vertical part of the first P-type well region is in contact with a side part of the gate oxide layer; Or An interface between the first P-type well region and the gate oxide layer is in an arc shape, one end of the interface between the first P-type well region and the gate oxide layer is in contact with the bottom part of the gate oxide layer, and the other end of the interface between the first P-type well region and the gate oxide layer is in contact with the side part of the gate oxide layer.

3. The trench silicon carbide MOSFET of Claim 1 wherein, The doping concentration of the first current spreading layer is greater than the doping concentration of the second current spreading layer; The doping concentration of the first current spreading layer and the second current spreading layer is greater than the doping concentration of the N-type drift region.

4. The trench silicon carbide MOSFET of Claim 1 wherein, The P-type heavily doped region extends to the vertical part of the first P-type well region and divides the second current spreading layer into an isolated horizontal part and a vertical part in the second preset cross section; the second preset cross section is arranged horizontally with respect to the third direction.

5. The trench silicon carbide MOSFET of Claim 1 wherein, The depth of the P-type heavily doped region in the first direction is greater than the depth of the second current spreading layer, and the P-type heavily doped region is located between the N-type heavily doped region and the vertical part of the second current spreading layer in the third direction.

6. The trench silicon carbide MOSFET of Claim 1 wherein, The contact interface between the P-type heavily doped region and the source layer in the second preset section is less than the width of the P-type heavily doped region in the second preset section, so that the N-type heavily doped region and the source layer are not in contact with each other in the second preset section.

7. The trench silicon carbide MOSFET of Claim 1 wherein, The distance between adjacent P-type heavily doped regions is greater than the width of the P-type heavily doped region in the second direction.

8. A method of fabricating a trench silicon carbide MOSFET, comprising: The preparation method comprises: providing a silicon carbide substrate, and forming an N-type drift region on a front surface of the silicon carbide substrate; forming a first P-type well region and a first current spreading layer on a peripheral region of the N-type drift region by a multiple ion implantation process, so that the N-type drift region is in a convex structure; forming a second current spreading layer on the first P-type well region, the first current spreading layer, and the N-type drift region in a first direction, and forming a second P-type well region and an N-type heavily doped region on the second current spreading layer by a multiple ion implantation process; the second current spreading layer and the second P-type well region are in a concave shape in a section in a second direction, and the doping concentration of the first P-type well region is greater than the doping concentration of the second P-type well region; forming a plurality of P-type heavily doped regions by implanting P-type impurities into a plurality of preset regions spaced in a third direction; wherein a part between adjacent preset regions in a section in the second direction is defined as a first preset section, and a part in the preset region in the section in the second direction is defined as a second preset section; etching a preset trench region to form a gate trench, and forming a gate oxide layer and a gate layer in the gate trench; wherein the gate layer is located in a groove of the gate oxide layer; depositing an insulating medium layer, and etching the insulating medium layer, so that the insulating medium layer covers the gate layer, and covers a part of the N-type heavily doped region in the first preset section, and covers the entire N-type heavily doped region in the second preset section; forming a source layer and a drain layer, wherein the source layer is in Schottky contact with the second current spreading layer, and the source layer is in Ohmic contact with the N-type heavily doped region, the P-type heavily doped region, and the second P-type well region.

9. The production method according to claim 8, characterized by, The etching a preset trench region to form a gate trench, and forming a gate oxide layer and a gate layer in the gate trench comprises: by a multiple etching process, the first P-type well region is in an L-shaped structure, a horizontal part of the first P-type well region is in contact with a bottom of the gate oxide layer, and a vertical part of the first P-type well region is in contact with a side of the gate oxide layer; or by a multiple etching process, an arc shape is formed between the horizontal part and the vertical part of the first P-type well region, an interface between the first P-type well region and the gate oxide layer is in an arc shape, one end of the interface between the first P-type well region and the gate oxide layer is in contact with the bottom of the gate oxide layer, and the other end of the interface between the first P-type well region and the gate oxide layer is in contact with the side of the gate oxide layer.

10. A chip, characterized by The trench silicon carbide MOSFET comprises any one of the trench silicon carbide MOSFETs according to claims 1-7; or, the trench silicon carbide MOSFET is prepared by the preparation method according to claim 8 or 9.

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