A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; forming an epitaxial layer on one side of the substrate; the epitaxial layer comprises an isolation region, a first conductive type column with a width of N1 and a second conductive type column with a width of P1; the first conductive type column and the second conductive type column are alternately arranged on the side of the isolation region away from the substrate; at least once, a first operation is performed, the first operation comprises the following steps: removing a part of the first conductive type column and the second conductive type column adjacent to the first conductive type column to form a first groove; forming a first conductive type column with a width of N2 in the first groove, wherein N2 is greater than N1; the second conductive type column with a width of P1 becomes a second conductive type column with a width of P2, wherein P2 is less than P1; with the increase of the number of the first operation, N2 gradually increases, and P2 gradually decreases. The application can improve the device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Super junction metal oxide semiconductor field effect transistor (MOSFET) is known as a milestone device in power semiconductor, and the super junction structure replaces the single-doped drift region with the "charge-balanced" P-type column and N-type column arranged alternately, which successfully breaks through the inherent "silicon limit" contradiction between the breakdown voltage (BV) and the on-resistance in the traditional power MOSFET.

[0003] At present, reducing the specific on-resistance of super junction MOSFET is the goal pursued by the industry, for N-channel MOSFET, the P-type column does not provide a conductive channel, and the narrower the P-type column is, the more conducive to reducing the specific on-resistance of the device. For P-channel MOSFET, the N-type column does not provide a conductive channel, and the narrower the N-type column is, the more conducive to reducing the specific on-resistance of the device. At present, the main method for preparing an extremely narrow P-type column or N-type column is a groove filling process, and the high aspect ratio groove puts forward an extreme requirement for the anisotropy of etching technology, and when epitaxial growth or dielectric filling is performed in the narrow groove, a blockage is easily formed at the entrance, thereby causing a hole or a gap at the bottom of the groove, and further affecting the performance of the super junction device. SUMMARY

[0004] The present application provides a semiconductor device and a preparation method thereof, to solve the problem that the preparation of an extremely narrow P-type column or N-type column affects the performance of the super junction device.

[0005] In a first aspect, the present application provides a preparation method of a semiconductor device, wherein the preparation method comprises:

[0006] providing a substrate; the substrate is set as a first conductive type;

[0007] forming an epitaxial layer on one side of the substrate; the epitaxial layer comprises an isolation region set as the first conductive type, a first conductive type column with a width of N1, and a second conductive type column with a width of P1; the isolation region is located on one side of the substrate, and the first conductive type column and the second conductive type column are arranged alternately on the side of the isolation region away from the substrate;

[0008] performing a first operation at least once, the first operation comprising:

[0009] simultaneously removing part of the first conductive type column and the second conductive type column adjacent to the first conductive type column to form a first groove;

[0010] forming a first conductive type pillar with a width of N2 in the first trench, wherein N2 is greater than N1; a second conductive type pillar with a width of P1 becomes a second conductive type pillar with a width of P2, wherein P2 is less than P1; N2 gradually increases and P2 gradually decreases with an increase in the number of the first operations.

[0011] Optionally, simultaneously removing a part of the first conductive type pillar and a part of the second conductive type pillar adjacent to the first conductive type pillar to form the first trench, and forming the first conductive type pillar with a width of N2 in the first trench, comprises:

[0012] removing one of every two adjacent first conductive type pillars by an etching process, and simultaneously removing a part of the second conductive type pillar adjacent to the first conductive type pillar when the first conductive type pillar is removed to form a part of the first trench;

[0013] forming the first conductive type pillar with a width of N2 in the part of the first trench;

[0014] removing the remaining first conductive type pillars by an etching process, and simultaneously removing a part of the second conductive type pillar adjacent to the remaining first conductive type pillars to form the remaining part of the first trench;

[0015] forming the first conductive type pillar with a width of N2 in the remaining part of the first trench.

[0016] Optionally, forming an epitaxial layer on one side of the substrate, comprises:

[0017] forming a first epitaxial layer of the first conductive type on one side of the substrate; the thickness of the first epitaxial layer is the same as the thickness of the epitaxial layer;

[0018] etching the first epitaxial layer to form a second trench with a width of P1; the vertical distance between adjacent second trenches is N1, and the etching depth of the second trench is less than the thickness of the first epitaxial layer;

[0019] forming a second conductive type pillar with a width of P1 in the second trench; the region of the first epitaxial layer on both sides of the second conductive type pillar and with the same thickness as the second conductive type pillar serves as a first conductive type pillar with a width of N1, and the region of the first epitaxial layer between the first conductive type pillar and the second conductive type pillar and the substrate serves as an isolation region.

[0020] Optionally, forming an epitaxial layer on one side of the substrate, comprises:

[0021] forming a second epitaxial layer of the first conductive type on one side of the substrate, and the thickness of the second epitaxial layer is less than the thickness of the epitaxial layer;

[0022] forming a first island region with a width of P1 in the second epitaxial layer by a lithography and doping process; the first island region is set to the second conductivity type, and a thickness of the first island region is less than a thickness of the second epitaxial layer;

[0023] performing the second operation at least once, the second operation comprising:

[0024] forming a third epitaxial layer of the first conductivity type on a side of the second epitaxial layer away from the substrate, and a thickness of the third epitaxial layer is less than the thickness of the epitaxial layer;

[0025] forming a second island region with a width of P1 in the third epitaxial layer by a lithography and doping process; the second island region is set to the second conductivity type, and the second island region is in contact with the first island region; a vertical projection of the second island region on the substrate coincides with a vertical projection of the first island region on the substrate;

[0026] after performing the second operation, further comprising:

[0027] performing annealing treatment on the first island region and the second island region, so that the first island region and the second island region are connected to form a second conductivity type column with a width of P1.

[0028] Optionally, forming a first conductivity type column with a width of N2 in the first trench comprises:

[0029] forming a first conductivity type semiconductor layer on a side of the first trench and the second conductivity type column away from the substrate;

[0030] removing the first conductivity type semiconductor layer on the side of the second conductivity type column away from the substrate by chemical mechanical polishing, and retaining the first conductivity type semiconductor layer in the first trench; the first conductivity type semiconductor layer in the first trench serves as the first conductivity type column with a width of N2.

[0031] Optionally, forming a second conductivity type column with a width of P1 in the second trench comprises:

[0032] forming a second conductivity type semiconductor layer on a side of the second trench and the first epitaxial layer away from the substrate;

[0033] removing the second conductivity type semiconductor layer on the side of the first conductivity type column away from the substrate by chemical mechanical polishing, and retaining the second conductivity type semiconductor layer in the second trench; the second conductivity type semiconductor layer in the second trench serves as the second conductivity type column with a width of P1.

[0034] Optionally, simultaneously removing the first conductivity type column and a partial region of the second conductivity type column adjacent to the first conductivity type column to form the first trench comprises:

[0035] etching to remove a part of the first conductive type column and the second conductive type column adjacent to the first conductive type column to form a first trench, a center of the first trench coincides with a center of the first conductive type column.

[0036] Optionally, before forming the epitaxial layer on one side of the substrate, further comprising:

[0037] forming a buffer layer of the first conductive type on one side of the substrate;

[0038] forming the epitaxial layer on one side of the substrate, comprising:

[0039] forming the epitaxial layer on one side of the buffer layer away from the substrate.

[0040] In a second aspect, the present application provides a semiconductor device, wherein the semiconductor device is made by the method for manufacturing a semiconductor device provided by any of the embodiments of the present application, and the semiconductor device comprises:

[0041] a substrate, the substrate is set to the first conductive type;

[0042] an epitaxial layer, the epitaxial layer is located on one side of the substrate; the epitaxial layer comprises an isolation region set to the first conductive type, a first conductive type column with a width of N2, and a second conductive type column with a width of P2; the isolation region is located on one side of the substrate, and the first conductive type column and the second conductive type column are arranged alternately on one side of the isolation region away from the substrate.

[0043] Optionally, the width P2 of the second conductive type column is less than or equal to half of the width N2 of the first conductive type column.

[0044] The doping concentration of the second conductive type column is greater than or equal to twice the doping concentration of the first conductive type column; the product of the width of the first conductive type column and the doping concentration of the first conductive type column is the same as the product of the width of the second conductive type column and the doping concentration of the second conductive type column.

[0045] The technical scheme of the embodiment of the present application can first form a second conductive type column with a wider width in the epitaxial layer, then etch the first conductive type column through an etching process, etch part of the region of the second conductive type column on both sides of the first conductive type column at the same time, remove the first conductive type column and part of the region of the second conductive type column on both sides of the first conductive type column, and thus form a first groove. Then, the first conductive type column with a width of N2 is epitaxially grown in the first groove. At this time, the width of the second conductive type column changes from P1 to P2, wherein P2 is less than P1. By performing the first operation once, the width of the second conductive type column can be effectively reduced. According to actual requirements, the number of times of the first operation can be greater than or equal to one. With the increase of the number of times of the first operation, N2 gradually increases and P2 gradually decreases, that is, with the increase of the number of times of the first operation, the width of the second conductive type column can be continuously reduced, and an extremely narrow second conductive type column is obtained, so that the specific on-resistance of the device is effectively reduced. In the process of preparing the extremely narrow second conductive type column, the traditional groove digging and filling process is not used, the difficulty of groove etching and groove filling is greatly reduced, and the problem that the hole or gap is formed at the bottom of the groove, thereby affecting the performance of the super-junction device, is effectively avoided.

[0046] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0048] Figure 1 is a flowchart of a preparation method of a semiconductor device provided by an embodiment of the present application;

[0049] Figures 2-5 is a structure schematic diagram corresponding to each step in the preparation method of a semiconductor device provided by an embodiment of the present application;

[0050] Figure 6 is a flowchart of another preparation method of a semiconductor device provided by an embodiment of the present application;

[0051] Figures 7-9 is a structure schematic diagram corresponding to part of the steps in another preparation method of a semiconductor device provided by an embodiment of the present application;

[0052] Figure 10 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application;

[0053] Figures 11-12 is a structural diagram corresponding to part of steps in the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0054] Figure 13 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application;

[0055] Figures 14-15 is a structural diagram corresponding to part of steps in the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0056] Figure 16 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application;

[0057] Figure 17 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0059] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] Figure 1 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application, Figures 2-5This is a schematic diagram of the structure corresponding to each step in a semiconductor device fabrication method provided by an embodiment of the present invention. The semiconductor device fabrication method provided by the embodiment of the present invention includes a method for fabricating a superjunction MOSFET, such as... Figure 1 As shown, the preparation method includes:

[0061] S100: Provides a substrate; the substrate is configured as a first conductivity type.

[0062] Specifically, such as Figure 2 As shown, a substrate 1 is first provided, which includes a highly doped substrate. A buffer layer 2 can also be formed on one side of the substrate 1 by an epitaxial process. The buffer layer 2 includes a lightly doped buffer layer, and the thickness of the buffer layer 2 can be in the range of 5um-10um. For an N-channel superjunction MOSFET, the substrate 1 includes an N-type substrate, and the buffer layer 2 includes an N-type buffer layer. For a P-channel superjunction MOSFET, the substrate 1 includes a P-type substrate, and the buffer layer 2 includes a P-type buffer layer.

[0063] S110: An epitaxial layer is formed on one side of the substrate; the epitaxial layer includes an isolation region configured as a first conductivity type, a first conductivity type pillar with a width of N1, and a second conductivity type pillar with a width of P1; the isolation region is located on one side of the substrate, and the first conductivity type pillar and the second conductivity type pillar are alternately arranged on the side of the isolation region away from the substrate.

[0064] Specifically, such as Figure 3 As shown, an epitaxial layer 3 can be formed on the side of the buffer layer 2 away from the substrate 1. The epitaxial layer 3 may include an isolation region 31, a first conductivity type pillar 32 with a width of N1, and a second conductivity type pillar 33 with a width of P1. The isolation region 31 is disposed on the side of the buffer layer 2 away from the substrate 1, and the first conductivity type pillar 32 and the second conductivity type pillar 33 are alternately arranged on the side of the isolation region 31 away from the substrate 1. For an N-channel superjunction MOSFET, the isolation region 31 includes an N-type isolation region, the first conductivity type pillar 32 includes an N-type pillar, and the second conductivity type pillar 33 includes a P-type pillar. For a P-channel superjunction MOSFET, the isolation region 31 includes a P-type isolation region, the first conductivity type pillar 32 includes a P-type pillar, and the second conductivity type pillar 33 includes an N-type pillar. That is, the second conductivity type pillar 33 does not provide a conductive path; the narrower the width of the second conductivity type pillar 33, the smaller the specific on-resistance of the device.

[0065] For example, a first epitaxial layer can be grown first on the side of the buffer layer 2 away from the substrate 1. For an N-channel superjunction MOSFET, the first epitaxial layer includes an N-type epitaxial layer; for a P-channel superjunction MOSFET, the first epitaxial layer includes a P-type epitaxial layer. Then, the first epitaxial layer can be etched to form trenches, the trenches being positioned corresponding to... Figure 3The position of the second conductive type column 33 is shown, at this time, the second conductive type column 33 is wider, so the width of the trench formed by etching the first epitaxial layer is wider, and the depth-width ratio is small, then the second conductive type semiconductor material is epitaxially grown in the trench, thereby forming the second conductive type column 33. The first epitaxial layer on both sides of the second conductive type column 33 serves as the first conductive type column 32, and the first epitaxial layer on the side close to the buffer layer 2 of the second conductive type column 33 serves as the isolation region 31, thereby forming the epitaxial layer 3.

[0066] S120: performing the first operation at least once, the first operation comprising: simultaneously removing a part of the first conductive type column and a part of the second conductive type column adjacent to the first conductive type column to form a first trench; forming a first conductive type column with a width of N2 in the first trench, wherein N2 is greater than N1; the second conductive type column with a width of P1 becomes a second conductive type column with a width of P2, wherein P2 is less than P1; as the number of times of the first operation increases, N2 gradually increases and P2 gradually decreases.

[0067] Specifically, then at least one first operation is performed, the first operation can be divided into two steps, as Figure 4 As shown, the first step of the first operation is to etch the first conductive type column, at the same time of etching the first conductive type column, a part of the second conductive type column 33 on both sides of the first conductive type column is also etched, and a part of the first conductive type column and a part of the second conductive type column on both sides of the first conductive type column are removed, thereby forming a first trench 34. As Figure 5 As shown, the second step of the first operation is to epitaxially grow a first conductive type column 32 with a width of N2 in the first trench, wherein N2 is greater than N1. At this time, the width of the second conductive type column 33 changes from P1 to P2, wherein P2 is less than P1. Exemplarily, the center line of the first trench 34 can coincide with the center line of the first conductive type column 32, and the second conductive type column 33 is etched on one side by 0.5 (N2-N1), the second conductive type column 33 is etched as a whole by (N2-N1), and the width P2 of the second conductive type column 33 after etching is P1-(N2-N1).

[0068] By performing the first operation once, the width of the second conductive type column 33 can be effectively reduced, according to actual requirements, the number of times of the first operation can be greater than or equal to one, as the number of times of the first operation increases, N2 gradually increases and P2 gradually decreases, that is, as the number of times of the first operation increases, the width of the second conductive type column 33 can be continuously reduced, and an extremely narrow second conductive type column 33 is obtained, thereby effectively reducing the specific on-resistance of the device.

[0069] Exemplarily, the embodiment of the present application can perform the first operation M times, where M is an integer greater than or equal to 1, at this time, the width of the first conductive type column 32 is changed from N1 to N2, the width of the second conductive type column 33 is changed from P1 to P2, the doping concentration of the first conductive type column 32 is Nn, the doping concentration of the second conductive type column 33 is Np, and the finally formed first conductive type column 32 and second conductive type column 33 satisfy: Nn M+1 , the width of the second conductive type column 33 is changed from P1 to P M+1 , the doping concentration of the first conductive type column 32 is Nn, the doping concentration of the second conductive type column 33 is Np, and the finally formed first conductive type column 32 and second conductive type column 33 satisfy: N M+1 Nn= P M+1 Np.

[0070] The technical scheme of the embodiment of the present application can first form a second conductive type column 33 with a wider width in the epitaxial layer 3, then etch the first conductive type column through an etching process, and at the same time of etching the first conductive type column, etch part of the region of the second conductive type column 33 on both sides of the first conductive type column, remove the first conductive type column and part of the region of the second conductive type column on both sides of the first conductive type column, thereby forming a first groove 34. Then, the first conductive type column 32 with a width of N2 is epitaxially grown in the first groove, where N2 is greater than N1. At this time, the width of the second conductive type column 33 is changed from P1 to P2, where P2 is less than P1. By performing the first operation once, the width of the second conductive type column 33 can be effectively reduced. According to actual requirements, the number of times of the first operation can be greater than or equal to one. With the increase of the number of times of the first operation, N2 gradually increases and P2 gradually decreases, that is, with the increase of the number of times of the first operation, the width of the second conductive type column 33 can be continuously reduced to obtain an extremely narrow second conductive type column 33, thereby effectively reducing the specific on-resistance of the device. In the process of preparing the extremely narrow second conductive type column 33, the technical scheme of the embodiment of the present application does not use the traditional groove digging and filling process, greatly reduces the difficulty of groove etching and groove filling, effectively avoids the problem that holes or gaps are formed at the bottom of the groove, thereby affecting the performance of the super-junction device.

[0071] Optionally, based on each of the above embodiments, Figure 6 is a flow chart of another preparation method of a semiconductor device provided by the embodiment of the present application, Figures 7-9 is a structure schematic diagram corresponding to part of steps in the preparation method of another semiconductor device provided by the embodiment of the present application, as shown in Figure 6 , the preparation method comprises:

[0072] S200: providing a substrate; the substrate is set to be of a first conductive type.

[0073] S210: Forming an epitaxial layer on one side of a substrate; the epitaxial layer comprises an isolation region configured as a first conductive type, a first conductive type column with a width of N1, and a second conductive type column with a width of P1; the isolation region is located on one side of the substrate, and the first conductive type column and the second conductive type column are alternately arranged on the side of the isolation region away from the substrate.

[0074] S220: Performing a first operation at least once, the first operation comprising: removing one of every two adjacent first conductive type columns by an etching process, and synchronously removing a partial region of the second conductive type column adjacent to the first conductive type column when the first conductive type column is removed, to form a partial first trench; forming a first conductive type column with a width of N2 in the partial first trench; removing the remaining first conductive type column by an etching process, and synchronously removing a partial region of the second conductive type column adjacent to the remaining first conductive type column, to form a remaining first trench; and forming a first conductive type column with a width of N2 in the remaining first trench.

[0075] Specifically, the first operation can be divided into four steps, as shown in Figure 6 The first step of the first operation can be etching one of every two adjacent first conductive type columns 32, and etching a partial region of the second conductive type column 33 adjacent to the first conductive type column 32 at the same time, so as to form a partial first trench 34. The width of the first trench 34 is N2, and at this time, each second conductive type column 33 is etched on one side only. For example, the center line of the first trench 34 can coincide with the center line of the first conductive type column 32, and the second conductive type column 33 is etched on one side by 0.5 (N2-N1), and the width P3 of the second conductive type column 33 after etching is P1-0.5 (N2-N1).

[0076] As shown in Figure 7 The second step of the first operation can be epitaxial growth of a first conductive type semiconductor material in the formed first trench 34, so as to form a first conductive type column 32 with a width of N2 in the first trench 34.

[0077] As shown in Figure 8 The third step of the first operation can be etching the remaining first conductive type column 32 with a width of N1, and synchronously etching a partial region of the second conductive type column 33 adjacent to the remaining first conductive type column 32, so as to form a remaining first trench 34. At this time, the other side of each second conductive type column 33 is also etched. For example, the center line of the first trench 34 can coincide with the center line of the first conductive type column 32, and the other side of the second conductive type column 33 is also etched by 0.5 (N2-N1), the width P2 of the second conductive type column 33 after etching is P1-(N2-N1).

[0078] As shown in Figure 9 , the fourth step of the first operation can be epitaxial growth of the first conductive type semiconductor material in the first trench 34 formed as shown in Figure 8 , so as to form the first conductive type column 32 with a width of N2 in the first trench 34.

[0079] The technical solution of the embodiment of the present application is that one of every two adjacent first conductive type columns 32 is etched first, and the second conductive type columns 33 on both sides are etched synchronously to form the first trench 34, and the first conductive type column 32 with a width of N2 is formed in the first trench 34, and then the remaining first conductive type columns 32 are etched, and the second conductive type columns 33 on both sides are etched synchronously. At this time, the first conductive type column 32 with a width of N2 formed in the last step can support the second conductive type column 33, so that when the remaining first conductive type columns 32 are etched and the second conductive type columns 33 on both sides are etched synchronously, the extremely narrow second conductive type column 33 does not collapse, thereby avoiding irreparable economic losses.

[0080] Optionally, on the basis of each of the above embodiments, Figure 10 is a flow chart of another method for manufacturing a semiconductor device provided by the embodiment of the present application, Figures 11-12 is a structure diagram corresponding to part of the steps in the method for manufacturing a semiconductor device provided by the embodiment of the present application, as shown in Figure 10 , the manufacturing method comprises:

[0081] S300: providing a substrate; the substrate is set to be of the first conductive type.

[0082] S310: forming a first epitaxial layer of the first conductive type on one side of the substrate; the thickness of the first epitaxial layer is the same as the thickness of the epitaxial layer.

[0083] Specifically, as shown in Figure 11 , after the substrate 1 and the buffer layer 2 are formed, the first epitaxial layer 4 can be formed on the side of the buffer layer 2 away from the substrate 1. For an N-channel super-junction MOSFET, the first epitaxial layer 4 comprises an N-type epitaxial layer, and for a P-channel super-junction MOSFET, the first epitaxial layer 4 comprises a P-type epitaxial layer. The thickness of the first epitaxial layer 4 is determined by the breakdown voltage of the device, and the thickness L of the first epitaxial layer 4 is BV / Ec+L', wherein BV is the breakdown voltage of the device, Ec is the critical breakdown electric field of the semiconductor material of the first epitaxial layer 4, and L' is a process allowance, which is generally 5um-20um.

[0084] S320: Etch the first epitaxial layer to form a second trench with a width of P1; the vertical spacing between adjacent second trenches is N1, and the etching depth of the second trench is less than the thickness of the first epitaxial layer.

[0085] Specifically, such as Figure 12 As shown, the first epitaxial layer 4 is etched to form a second trench 41 with a width of P1. The second trench 41 has a relatively wide width and a small aspect ratio. For example, the width P1 of the second trench 41 can be set to 5µm-10µm, and the vertical spacing N1 between adjacent second trenches can be set to 5µm-10µm. The etching depth of the second trench 41 is less than the thickness of the first epitaxial layer 4, and the vertical spacing between the bottom of the second trench 41 and the bottom surface of the first epitaxial layer 4 can be 2µm-5µm.

[0086] S330: A second conductive type pillar with a width of P1 is formed in the second trench; the regions of the first epitaxial layer located on both sides of the second conductive type pillar and having the same thickness as the second conductive type pillar are used as the first conductive type pillar with a width of N1; the regions of the first epitaxial layer located between the first conductive type pillar, the second conductive type pillar and the substrate are used as the isolation region.

[0087] Specifically, such as Figure 3 As shown, a second conductivity type semiconductor material is epitaxially grown inside and outside the second trench 41, thereby forming a second conductivity type pillar 33 with a width of P1 within the second trench 41. The regions of the first epitaxial layer 4 located on both sides of the second conductivity type pillar 33 and having the same thickness as the second conductivity type pillar 33 serve as first conductivity type pillars 32 with a width of N1. The region of the first epitaxial layer 4 located between the first conductivity type pillar 32, the second conductivity type pillar 33, and the buffer layer 2 serves as an isolation region 31, which prevents the second conductivity type pillar 33 from contacting the first conductivity type buffer layer 2.

[0088] S340: Perform a first operation at least once, the first operation including: simultaneously removing a portion of a first conductive type post and a portion of a second conductive type post adjacent to the first conductive type post to form a first trench; forming a first conductive type post with a width of N2 in the first trench, wherein N2 is greater than N1; the second conductive type post with a width of P1 becomes a second conductive type post with a width of P2, wherein P2 is less than P1; as the number of first operations increases, N2 gradually increases and P2 gradually decreases.

[0089] Optionally, based on the above embodiments, Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figures 14-15 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in this embodiment of the invention, as shown below. Figure 13 As shown, the preparation method includes:

[0090] S400: Provides a substrate; the substrate is set to the first conductivity type.

[0091] S410: A second epitaxial layer of a first conductivity type is formed on one side of the substrate, the thickness of the second epitaxial layer being less than the thickness of the epitaxial layer.

[0092] Specifically, such as Figure 14 As shown, after forming the substrate 1 and the buffer layer 2, a second epitaxial layer 5 can be epitaxially grown on the side of the buffer layer 2 away from the substrate 1. For an N-channel superjunction MOSFET, the second epitaxial layer 5 includes an N-type epitaxial layer; for a P-channel superjunction MOSFET, the second epitaxial layer 5 includes a P-type epitaxial layer. The thickness of the second epitaxial layer 5 can be less than the required final epitaxial layer thickness. For example, to achieve the required breakdown voltage of the device, the thickness of the epitaxial layer needs to be set to 50 μm. A second epitaxial layer 5 with a thickness of 5 μm can be formed first on the side of the buffer layer 2 away from the substrate 1.

[0093] S420: A first island region with a width of P1 is formed in the second epitaxial layer through photolithography and doping processes; the first island region is set to the second conductivity type, and the thickness of the first island region is less than the thickness of the second epitaxial layer.

[0094] Specifically, such as Figure 14 As shown, a portion of the second epitaxial layer 5 is doped. For example, a mask layer can be formed on the side of the second epitaxial layer 5 away from the substrate 1 first. A mask trench is then formed in the mask layer using photolithography. The mask trench exposes the portion of the second epitaxial layer 5 that needs to be doped. Then, a first island region 51 is formed in the second epitaxial layer 5 using doping processes such as ion implantation. The first island region 51 has a second conductivity type. For an N-channel superjunction MOSFET, the first island region 51 includes a P-type island region; for a P-channel superjunction MOSFET, the first island region 51 includes an N-type island region.

[0095] The thickness of the first island region 51 can be less than the thickness of the second epitaxial layer 5. For example, the vertical distance between the bottom surface of the first island region 51 and the bottom surface of the second epitaxial layer 5 can be 2um-5um.

[0096] S430: Perform a second operation at least once, the second operation including: forming a third epitaxial layer of a first conductivity type on the side of the second epitaxial layer away from the substrate, the thickness of the third epitaxial layer being less than the thickness of the epitaxial layer; forming a second island region of width P1 in the third epitaxial layer by photolithography and doping processes; setting the second island region to a second conductivity type, the second island region being in contact with the first island region; the vertical projection of the second island region onto the substrate coinciding with the vertical projection of the first island region onto the substrate.

[0097] Specifically, such as Figure 15As shown, the second operation is performed at least once, and the second operation can include: first epitaxially growing a third epitaxial layer 6 on the side of the second epitaxial layer 5 away from the substrate 1, for an N-channel super-junction MOSFET, the third epitaxial layer 6 includes an N-type epitaxial layer, and for a P-channel super-junction MOSFET, the third epitaxial layer 6 includes a P-type epitaxial layer. The thickness of the third epitaxial layer 6 can be less than the thickness of the final epitaxial layer required, and for example, the thickness of the third epitaxial layer 6 can also be 5 um. The doping concentration of the third epitaxial layer 6 can be the same as the doping concentration of the second epitaxial layer 5. Then, a second island region 61 can be formed in the third epitaxial layer 6 by using a photolithography and ion implantation process, and for example, a mask layer can be first formed on the side of the third epitaxial layer 6 away from the substrate 1, a mask trench can be formed in the mask layer by a photolithography process, and the mask trench can expose a part of the third epitaxial layer 6 that needs to be doped. Then, the second island region 61 can be formed in the third epitaxial layer 6 by a doping process such as ion implantation, and the second island region 61 is of a second conductivity type, for an N-channel super-junction MOSFET, the second island region 61 includes a P-type island region, and for a P-channel super-junction MOSFET, the second island region 61 includes an N-type island region.

[0098] The thickness of the second island region 61 can be the same as the thickness of the third epitaxial layer 6, and the second island region 61 is in contact with the first island region 51; the vertical projection of the second island region 61 on the substrate 1 coincides with the vertical projection of the first island region 51 on the substrate 1.

[0099] The technical solution of the embodiment of the present application can repeat the second operation multiple times, so that the thickness of the third epitaxial layer 6 formed multiple times and the thickness of the second epitaxial layer 5 satisfy the requirement of the breakdown voltage of the device. For example, in order to achieve the required breakdown voltage of the device, the thickness of the epitaxial layer needs to be set to 50 um, the thickness of the second epitaxial layer 5 is 5 um, and the thickness of each third epitaxial layer 6 is also 5 um, so that the second operation needs to be performed 9 times.

[0100] S440: annealing the first island region and the second island region to make the first island region and the second island region communicate to form a second conductivity type column with a width of P1.

[0101] Specifically, as shown in Figure 15 and Figure 3 the first island region 51 and all the second island regions 61 are subjected to high-temperature annealing to make the first island region 51 and all the second island regions 61 communicate to form a second conductivity type column 33 with a width of P1.

[0102] S450: performing the first operation at least once, the first operation comprising: simultaneously removing a partial region of the first conductive type pillar and the second conductive type pillar adjacent to the first conductive type pillar to form a first trench; forming a first conductive type pillar with a width of N2 in the first trench, wherein N2 is greater than N1; a second conductive type pillar with a width of P1 becomes a second conductive type pillar with a width of P2, wherein P2 is less than P1; N2 gradually increases and P2 gradually decreases as the number of times of performing the first operation increases.

[0103] Optionally, based on each of the above embodiments, Figure 16 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present application, as shown in the figure, the method comprises the following steps: Figure 16

[0104] S500: providing a substrate; the substrate is set to a first conductive type.

[0105] S510: forming an epitaxial layer on one side of the substrate; the epitaxial layer comprises an isolation region set to the first conductive type, a first conductive type pillar with a width of N1, and a second conductive type pillar with a width of P1; the isolation region is located on one side of the substrate, and the first conductive type pillar and the second conductive type pillar are arranged alternately on the side of the isolation region away from the substrate.

[0106] S520: performing the first operation at least once, the first operation comprising: simultaneously removing a partial region of the first conductive type pillar and the second conductive type pillar adjacent to the first conductive type pillar to form a first trench; forming a first conductive type semiconductor layer on the side of the first trench and the second conductive type pillar away from the substrate; removing the first conductive type semiconductor layer on the side of the second conductive type pillar away from the substrate by chemical mechanical polishing, and retaining the first conductive type semiconductor layer in the first trench; the first conductive type semiconductor layer in the first trench serves as a first conductive type pillar with a width of N2.

[0107] Specifically, as shown in Figure 4 and Figure 5 ​As shown, the first step of the first operation is to etch the first-conductivity-type pillars, etching the first-conductivity-type pillars and part of the second-conductivity-type pillars 33 on both sides of the first-conductivity-type pillars at the same time, removing the first-conductivity-type pillars and part of the second-conductivity-type pillars on both sides of the first-conductivity-type pillars, thereby forming first trenches 34. Then, first-conductivity-type semiconductor material is epitaxially grown on the side of the first trenches 34 and the second-conductivity-type pillars 33 away from the substrate 1, and then a chemical mechanical polishing process is used to remove the first-conductivity-type semiconductor material on the side of the second-conductivity-type pillars 33 away from the substrate 1, and to remove the first-conductivity-type semiconductor material outside the first trenches 34, leaving only the first-conductivity-type semiconductor material inside the first trenches 34. The first-conductivity-type semiconductor layer inside the first trenches 34 is the first-conductivity-type pillars 32 with a width of N2.

[0108] Optionally, on the basis of each of the above embodiments, Figure 17 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present application, as shown in Figure 17 The method comprises the following steps:

[0109] S600: providing a substrate; the substrate is of a first conductivity type.

[0110] S610: forming a first epitaxial layer of the first conductivity type on one side of the substrate; the thickness of the first epitaxial layer is the same as the thickness of the epitaxial layer.

[0111] S620: etching the first epitaxial layer to form second trenches with a width of P1; the vertical distance between adjacent second trenches is N1, and the etching depth of the second trenches is less than the thickness of the first epitaxial layer.

[0112] S630: forming a second-conductivity-type semiconductor layer on the side of the second trenches and the first epitaxial layer away from the substrate.

[0113] Specifically, as shown in Figure 12 and Figure 3 after the second trenches 41 are formed, second-conductivity-type semiconductor material is epitaxially grown on the side of the second trenches 41 and the first epitaxial layer 4 away from the substrate 1.

[0114] S640: removing the second-conductivity-type semiconductor layer on the side of the first epitaxial layer away from the substrate by chemical mechanical polishing, and retaining the second-conductivity-type semiconductor layer inside the second trenches; the second-conductivity-type semiconductor layer inside the second trenches is the second-conductivity-type pillars with a width of P1. The region of the first epitaxial layer on both sides of the second-conductivity-type pillars and with the same thickness as the second-conductivity-type pillars is the first-conductivity-type pillars with a width of N1, and the region of the first epitaxial layer between the first-conductivity-type pillars and the second-conductivity-type pillars and the substrate is the isolation region.

[0115] Specifically, as shown inFigure 12 and Figure 3 As shown, the second conductive type semiconductor material on the side of the first epitaxial layer 4 away from the substrate 1 is removed by chemical mechanical polishing process. At the same time, the second conductive type semiconductor material outside the second trench 41 is also removed, leaving only the second conductive type semiconductor material inside the second trench 41. The second conductive type semiconductor layer inside the second trench 41 serves as a second conductive type pillar 33 with a width of P1.

[0116] S650: Perform a first operation at least once, the first operation including: simultaneously removing a portion of a first conductive type post and a second conductive type post adjacent to the first conductive type post to form a first trench; forming a first conductive type post with a width of N2 in the first trench, wherein N2 is greater than N1; the second conductive type post with a width of P1 becomes a second conductive type post with a width of P2, wherein P2 is less than P1; as the number of first operations increases, N2 gradually increases and P2 gradually decreases.

[0117] Optionally, based on the above embodiments, such as Figure 4 , Figure 7 and Figure 9 As shown, when etching away a portion of the first conductive type pillar 32 and a portion of the second conductive type pillar 33 adjacent to the first conductive type pillar 32 to form the first trench 34, the center of the first trench 34 may coincide with the center of the first conductive type pillar 32.

[0118] Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. The semiconductor device provided in this embodiment is fabricated using the fabrication method of any of the semiconductor devices provided in the above embodiments of the present invention, such as... Figure 5 As shown, the semiconductor device includes: a substrate 1, which is configured with a first conductivity type; and an epitaxial layer 3, located on one side of the substrate 1. The epitaxial layer 3 includes an isolation region 31 configured with the first conductivity type, a first conductivity type pillar 32 with a width of N2, and a second conductivity type pillar 33 with a width of P2. The isolation region 31 is located on one side of the substrate 1, and the first conductivity type pillar 32 and the second conductivity type pillar 33 are alternately arranged on the side of the isolation region 31 away from the substrate 1.

[0119] Specifically, substrate 1 includes a highly doped substrate. A buffer layer 2 can also be formed on one side of substrate 1 using an epitaxial process. Buffer layer 2 includes a lightly doped buffer layer, and its thickness can range from 5µm to 10µm. For an N-channel superjunction MOSFET, substrate 1 includes an N-type substrate, and buffer layer 2 includes an N-type buffer layer. For a P-channel superjunction MOSFET, substrate 1 includes a P-type substrate, and buffer layer 2 includes a P-type buffer layer.

[0120] The epitaxial layer 3 can include an isolation region 31, first conductive type columns 32 with a width of N2, and second conductive type columns 33 with a width of P2. The isolation region 31 is arranged on a side of the buffer layer 2 away from the substrate 1. The first conductive type columns 32 and the second conductive type columns 33 are alternately arranged on a side of the isolation region 31 away from the substrate 1. For an N-channel super-junction MOSFET, the isolation region 31 includes an N-type isolation region, the first conductive type columns 32 include N-type columns, and the second conductive type columns 33 include P-type columns. For a P-channel super-junction MOSFET, the isolation region 31 includes a P-type isolation region, the first conductive type columns 32 include P-type columns, and the second conductive type columns 33 include N-type columns. That is, the second conductive type columns 33 do not provide a conductive channel. The narrower the width of the second conductive type columns 33, the smaller the on-resistance ratio of the device.

[0121] The width P2 of the second conductive type columns 33 can be less than or equal to half of the width N2 of the first conductive type columns 32. This makes the current path of the super-junction structure wider and the on-resistance ratio lower for the same area. The doping concentration of the second conductive type columns 33 can be greater than or equal to twice the doping concentration of the first conductive type columns 32. This makes the product of the width of the first conductive type columns 32 and the doping concentration of the first conductive type columns 32 the same as the product of the width of the second conductive type columns 33 and the doping concentration of the second conductive type columns 33. When the device is subjected to a reverse bias, the first conductive type columns 32 and the second conductive type columns 33 can be mutually depleted, so that the drift region can maintain a high blocking voltage.

[0122] The super-junction MOSFET semiconductor device provided by the embodiments of the present application can also include other conventional structures, such as a body region, an N+ active region, a P+ active region, a gate, a gate oxide layer, a source, an interlayer dielectric layer, a drain, and the like. The arrangement of the above-mentioned structures is consistent with that of a conventional super-junction MOSFET. The super-junction MOSFET semiconductor device provided by the embodiments of the present application can include a planar super-junction MOSFET and a trench super-junction MOSFET.

[0123] It should be understood that the various forms of flow shown above can be reordered, added to, or deleted from without departing from the scope of the present application. For example, the steps described in the present application can be executed in parallel, in sequence, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, and the present application is not limited herein.

[0124] The specific embodiments described above are not intended to limit the scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principles of the present application should be included in the scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: providing a substrate; the substrate is set to a first conductive type; forming an epitaxial layer on one side of the substrate; the epitaxial layer comprises an isolation region set to the first conductive type, a first conductive type column with a width of N1, and a second conductive type column with a width of P1; the isolation region is located on one side of the substrate, and the first conductive type column and the second conductive type column are arranged alternately on the side of the isolation region away from the substrate; performing a first operation at least once, the first operation comprising: simultaneously removing part of the first conductive type column and the second conductive type column adjacent to the first conductive type column to form a first trench; forming a first conductive type column with a width of N2 in the first trench, wherein N2 is greater than N1; the second conductive type column with a width of P1 becomes the second conductive type column with a width of P2, wherein P2 is less than P1; as the number of times of the first operation increases, N2 gradually increases and P2 gradually decreases; simultaneously removing part of the first conductive type column and the second conductive type column adjacent to the first conductive type column to form a first trench, comprising: etching to remove part of the first conductive type column and the second conductive type column adjacent to the first conductive type column to form a first trench, the center of the first trench coincides with the center of the first conductive type column.

2. The method of producing a semiconductor device according to claim 1, wherein simultaneously removing part of the first conductive type column and the second conductive type column adjacent to the first conductive type column to form a first trench, and forming a first conductive type column with a width of N2 in the first trench, comprising: removing one of every two adjacent first conductive type columns by etching process, and synchronously removing part of the second conductive type column adjacent to the first conductive type column when the first conductive type column is removed, to form part of the first trench; forming a first conductive type column with a width of N2 in part of the first trench; removing the remaining first conductive type column by etching process, and synchronously removing part of the second conductive type column adjacent to the remaining first conductive type column, to form the remaining part of the first trench; forming a first conductive type column with a width of N2 in the remaining part of the first trench.

3. The method of manufacturing a semiconductor device according to claim 1, wherein forming an epitaxial layer on one side of the substrate, comprising: forming a first epitaxial layer of a first conductive type on one side of the substrate; the thickness of the first epitaxial layer is the same as the thickness of the epitaxial layer; etching the first epitaxial layer to form a second trench with a width of P1; the vertical distance between adjacent second trenches is N1, and the etching depth of the second trench is less than the thickness of the first epitaxial layer; forming a second conductive type column with a width of P1 in the second trench; the region of the first epitaxial layer with the same thickness as the second conductive type column on both sides of the second conductive type column serves as the first conductive type column with a width of N1, and the region of the first epitaxial layer between the first conductive type column and the second conductive type column and the substrate serves as the isolation region.

4. The method of producing a semiconductor device according to Claim 1, wherein forming an epitaxial layer on one side of the substrate, comprising: forming a second epitaxial layer of a first conductivity type on one side of the substrate, the thickness of the second epitaxial layer being less than the thickness of the epitaxial layer; forming a first island region with a width of P1 in the second epitaxial layer by a lithography and doping process; the first island region is set to a second conductivity type, the thickness of the first island region being less than the thickness of the second epitaxial layer; performing a second operation at least once, the second operation comprising: forming a third epitaxial layer of a first conductivity type on one side of the substrate away from the second epitaxial layer, the thickness of the third epitaxial layer being less than the thickness of the epitaxial layer; forming a second island region with a width of P1 in the third epitaxial layer by a lithography and doping process; the second island region is set to a second conductivity type, the second island region being in contact with the first island region; the vertical projection of the second island region on the substrate coincides with the vertical projection of the first island region on the substrate; after performing the second operation, further comprising: annealing the first island region and the second island region to make the first island region and the second island region communicate to form a second conductivity type column with a width of P1.

5. The method of producing a semiconductor device according to Claim 1, wherein forming a first conductivity type column with a width of N2 in the first trench, comprising: forming a first conductivity type semiconductor layer on one side of the first trench and the second conductivity type column away from the substrate; removing the first conductivity type semiconductor layer on one side of the second conductivity type column away from the substrate by chemical mechanical polishing, leaving the first conductivity type semiconductor layer in the first trench; the first conductivity type semiconductor layer in the first trench serves as a first conductivity type column with a width of N2.

6. The method of producing a semiconductor device according to claim 3, wherein forming a second conductivity type column with a width of P1 in the second trench, comprising: forming a second conductivity type semiconductor layer on one side of the second trench and the first epitaxial layer away from the substrate; removing the second conductivity type semiconductor layer on one side of the first epitaxial layer away from the substrate by chemical mechanical polishing, leaving the second conductivity type semiconductor layer in the second trench; the second conductivity type semiconductor layer in the second trench serves as a second conductivity type column with a width of P1.

7. The method of producing a semiconductor device according to Claim 1, wherein before forming an epitaxial layer on one side of the substrate, further comprising: forming a buffer layer of a first conductivity type on one side of the substrate; forming an epitaxial layer on one side of the substrate, comprising: forming an epitaxial layer on one side of the buffer layer away from the substrate.

8. A semiconductor device, characterized by The semiconductor device is prepared by the method of any one of claims 1-7, the semiconductor device comprising: a substrate, the substrate being set to a first conductivity type; an epitaxial layer, the epitaxial layer being located on one side of the substrate; the epitaxial layer comprising an isolation region set to a first conductivity type, a first conductivity type column with a width of N2 and a second conductivity type column with a width of P2; the isolation region is located on one side of the substrate, and the first conductivity type column and the second conductivity type column are alternately arranged on one side of the isolation region away from the substrate.

9. The semiconductor device of claim 8, wherein, the width P2 of the second conductivity type column is less than or equal to half of the width N2 of the first conductivity type column; The doping concentration of the second conductive type pillar is greater than or equal to twice the doping concentration of the first conductive type pillar; and the product of the width of the first conductive type pillar and the doping concentration of the first conductive type pillar is the same as the product of the width of the second conductive type pillar and the doping concentration of the second conductive type pillar.

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