Solar cell, solar cell module and photovoltaic system

Abstract

The invention is applicable to the technical field of photovoltaic modules, and provides a solar cell, a solar cell module and a photovoltaic system.The solar cell comprises a silicon substrate, a plurality of grid lines are alternately arranged on the surface of the silicon substrate, the grid lines are connected with a welding strip through at least one row of welding media, and the welding media comprise a plurality of welding medium points in the first direction; the welding strip at least partially covers the welding medium points, the welding strip is further connected with the silicon substrate through a plurality of bonding pieces, at least one row of welding media is provided with a plurality of avoiding areas, the bonding pieces are at least partially located in the avoiding areas, and the avoiding areas are not internally provided with the welding media. By arranging the avoiding area, the bonding piece is prevented from flowing during extrusion and making contact with a welding medium point, then the bonding piece is prevented from polluting the welding medium point, meanwhile, stress distribution is optimized, and the welding quality is improved. The method has the advantages of preventing a bonding piece from polluting a welding medium point, improving the welding reliability, reducing pseudo soldering and cavity defects, optimizing stress distribution and prolonging the service life.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of photovoltaic modules, and particularly relates to a solar cell, a solar cell module and a photovoltaic system. BACKGROUND

[0002] With the development of the photovoltaic industry, the requirements for the power output and long-term reliability of modules are increasingly improved. In the manufacturing process of solar cells, a plurality of cell pieces are usually connected in series by using a welding strip to form a cell string, so as to realize electrical interconnection. In order to realize reliable connection of the welding strip and the main grid of the cell piece, a tin paste welding process is generally used, that is, tin paste points are pre-set on the main grid of the cell piece, after high-temperature reflow welding, the tin paste is melted to weld the welding strip and the cell piece together, to form a low-resistance ohmic contact, which is a guarantee of "electrical connection".

[0003] However, the welding points are fragile, and mechanical stress will be generated due to thermal expansion and contraction (day and night and seasonal temperature difference) and external vibration during long-term use of the module, which is easy to cause hidden cracks of the cell piece or fatigue fracture of the welding point. Therefore, the industry usually increases a dispensing process on the basis of welding, that is, a glue point (such as silicone glue) is dispensed beside the welding strip, and the elasticity of the glue is used to absorb and release mechanical stress to protect the cell piece and the welding point, which is a guarantee of "mechanical connection" and "service life".

[0004] In the prior art, the tin paste points and the glue points are usually arranged adjacent to each other. However, due to the limitation of space layout, the tin paste points are usually arranged densely, and even if the glue points are arranged in the gap beside the tin paste points, the liquid glue is easy to expand and flow under extrusion during the dispensing process (especially when the pressurized dispensing method is used). Once the expanded glue contacts or covers the adjacent tin paste points, the tin paste will be contaminated, especially in the subsequent welding link, the glue will hinder the volatilization and cleaning effect of the flux in the tin paste, which will cause poor wetting, virtual welding, void and other defects during welding, and seriously reduce the connection reliability and the power output of the module. SUMMARY

[0005] The solar cell provided by the present application aims to solve the technical problem that the existing solar cell is easy to cause the connection reliability to be reduced due to the contact between the glue under pressure and the tin paste during the welding process.

[0006] The present application is implemented as follows, a solar cell, comprising: a silicon substrate; a plurality of grid lines are alternately arranged on the surface of the silicon substrate, the grid lines are connected with a welding strip through at least one row of welding medium, the welding medium comprises a plurality of welding medium points along a first direction, and the welding strip at least partially covers the welding medium points; The solder strip is also connected to the silicon substrate by a plurality of adhesive members, the at least one row of soldering medium is provided with a plurality of avoidance areas, the adhesive members are at least partially located in the avoidance areas, and the avoidance areas are not provided with the soldering medium.

[0007] Further, the avoidance areas include a first avoidance area and a second avoidance area, and the first avoidance area and the second avoidance area are staggered in a second direction.

[0008] Further, along the first direction, the avoidance areas are located at opposite ends of the solder strip in the second direction, and the first avoidance area and the second avoidance area are spaced apart.

[0009] Further, the plurality of soldering medium points are arranged into a plurality of dot arrays, the dot arrays include a first dot array and a second dot array, the first dot array and the second dot array are respectively located at opposite edges of the solder strip in the second direction, and the first dot array and the second dot array are spaced apart. The first avoidance area is located at the other edge opposite to the first dot array, and the second avoidance area is located at the other edge opposite to the second dot array.

[0010] Further, at least one of the first avoidance area and the second avoidance area has a width of 0.5mm-3.5mm in the second direction.

[0011] Further, the first dot array contains the soldering medium points with a width of 0.3mm-4mm in the second direction. The second dot array contains the soldering medium points with a width of 0.3mm-4mm in the second direction.

[0012] Further, the plurality of soldering medium points are also arranged into a third dot array, and along the second direction, the distances from the two end points of the soldering medium points of the third dot array to the edges of the solder strip are the same.

[0013] Further, the distances from the soldering medium points of the third dot array to the two edges of the solder strip have an absolute value of 0mm-2mm.

[0014] Further, the solder strip covers at least part of the adhesive member.

[0015] Further, the ratio of the area of the part of the solder strip covering the adhesive member to the total area of the adhesive member is less than 0.6.

[0016] Further, the ratio of the area of the part of the solder strip covering all the adhesive members to the total area of all the adhesive members ranges from 10% to 60%.

[0017] Further, the gate lines include first gate lines and second gate lines, the soldering media include first soldering media and second soldering media, the adhesive members include first adhesive members and second adhesive members, and the solder strips include first solder strips and second solder strips; The surface of the silicon substrate is alternately provided with the first gate lines and the second gate lines, the first gate lines are connected with the first solder strips through the first soldering media, the first solder strips are connected with the silicon substrate through the first adhesive members, the second gate lines are connected with the second solder strips through the second soldering media, and the second solder strips are connected with the silicon substrate through the second adhesive members.

[0018] Further, the silicon substrate includes a first region and a second region, a first doped layer is arranged on the first region, and a second doped layer is arranged on the second region, the first doped layer and the second doped layer are different in polarity. The first gate lines are located on the first region, and the second gate lines are located on the second region.

[0019] Further, the first soldering media include the first dot matrix located at a first edge of the first solder strip, the second dot matrix located at a second edge of the first solder strip, the first dot matrix and the second dot matrix are arranged at intervals, the first avoiding region is located at the second edge of the first solder strip, and the second avoiding region is located at the first edge of the first solder strip.

[0020] Further, the second soldering media include the first dot matrix located at a second edge of the second solder strip, the second dot matrix located at a first edge of the second solder strip, the first dot matrix and the second dot matrix are arranged at intervals, the first avoiding region is located at the first edge of the second solder strip, and the second avoiding region is located at the second edge of the second solder strip.

[0021] Further, the silicon substrate is further provided with third solder strips and fourth solder strips, the first gate lines are connected with the third solder strips through the third soldering media, the third solder strips are connected with the silicon substrate through the third adhesive members, the second gate lines are connected with the fourth solder strips through the fourth soldering media, and the fourth solder strips are connected with the silicon substrate through the fourth adhesive members.

[0022] Further, the first soldering media and the first adhesive members, the fourth soldering media and the fourth adhesive members are arranged in the same manner on the silicon substrate, and the second soldering media and the second adhesive members, the third soldering media and the third adhesive members are arranged in the same manner on the silicon substrate.

[0023] Further, the distance between the bonding member and the edge of the solder ribbon is 0.5mm-2mm.

[0024] Further, the interval distance between the plurality of solder medium points along the first direction is 0.4mm-1.5mm.

[0025] Further, the bonding member is made of a material with adhesive property, which can be at least one of UV glue, double-sided tape, pressure-sensitive adhesive, and thermosetting adhesive.

[0026] A solar cell module comprising the solar cell of any one of the above, the solar cell module comprising a plurality of solar cells connected in series along the first direction, and the plurality of solar cells are connected by the solder ribbon.

[0027] A photovoltaic system comprising the solar cell module of the above.

[0028] The present application has the advantages that, since the surface of the silicon substrate is alternately provided with a plurality of grid lines, the grid lines are connected with the solder ribbon through at least one row of solder medium, the solder medium includes a plurality of solder medium points along the first direction, and the solder ribbon at least partially covers the solder medium points; the solder ribbon is further connected with the silicon substrate through a plurality of bonding members, at least one row of solder medium is provided with a plurality of avoiding areas, the bonding members are at least partially located in the avoiding areas, no solder medium is provided in the avoiding areas, the avoiding areas avoid the flow of the bonding members when being pressed and contact with the solder medium points, thereby preventing the bonding members from polluting the solder medium points, optimizing the stress distribution, avoiding the pollution of the bonding members to the solder medium points, improving the soldering reliability, reducing the false welding and hollow defects, optimizing the stress distribution, and prolonging the service life. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a plan view of the solar cell provided by the embodiment of the present application; Figure 2 is another plan view of the solar cell provided by the embodiment of the present application; Figure 3 is a perspective view of the solar cell module provided by the embodiment of the present application; Figure 4 is a partial plan view of the solar cell module provided by the embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0031] In the prior art, the tin paste dots and the glue dots are usually arranged adjacent to each other. However, due to the limitation of space layout, the tin paste dots are usually arranged densely, and even if the glue dots are arranged in the gap beside the tin paste dots, the liquid glue is prone to flow and expand during the glue dispensing process (especially when the pressurized glue dispensing method is used). Once the expanded glue contacts or covers the adjacent tin paste dot, the tin paste will be contaminated. Especially in the subsequent welding process, the glue will hinder the volatilization and cleaning effect of the flux in the tin paste, resulting in poor wetting, false welding, voids and other defects during welding, which seriously reduces the connection reliability and component power output. The silicon substrate has a plurality of grid lines arranged alternately on the surface, the grid lines are connected with the solder strip through at least one row of welding medium, the welding medium includes a plurality of welding medium points in the first direction, and the solder strip at least partially covers the welding medium points; the solder strip is also connected with the silicon substrate through a plurality of adhesive pieces, at least one row of welding medium is provided with a plurality of avoiding areas, the adhesive piece is at least partially located in the avoiding area, no welding medium is arranged in the avoiding area, the avoiding area is arranged to avoid the flow of the adhesive piece when it is extruded and contacts the welding medium point, thereby preventing the adhesive piece from contaminating the welding medium point, and optimizing the stress distribution, which has the advantages of avoiding the contamination of the adhesive piece to the welding medium point, improving the welding reliability, reducing false welding and void defects, optimizing the stress distribution, and prolonging the service life.

[0032] Embodiment one Please refer to Figure 1 The embodiment of the present application is implemented as follows: a solar cell 100 comprises: a silicon substrate 1001; The surface of the silicon substrate 1001 is provided with a plurality of grid lines (not shown in the figure) arranged alternately, the grid lines are connected with the solder strip 50 through at least one row of welding medium 10, the welding medium 10 includes a plurality of welding medium points 101 in the first direction A, and the solder strip 50 at least partially covers the welding medium points 101; The solder strip 50 is also connected with the silicon substrate 1001 through a plurality of adhesive pieces 60, at least one row of welding medium 10 is provided with a plurality of avoiding areas 601, the adhesive piece 60 is at least partially located in the avoiding area 601, and no welding medium 10 is arranged in the avoiding area 601.

[0033] In the embodiment, the avoiding area 601 refers to a blank area reserved when the welding medium points 101 are arranged, and the adhesive piece 60 is arranged in the blank area. When the solder strip 50 is connected with the silicon substrate 1001 through the adhesive piece 60, the adhesive piece 60 will deform and flow to the periphery under pressure. Since the adhesive piece 60 is arranged in the avoiding area 601, the adhesive piece 60 can avoid contacting the welding medium 10 when it deforms and flows to the periphery. The welding medium point 101 refers to a conductive material for realizing electrical connection between the solder strip 50 and the grid line, which can be formed by tin paste, silver paste or conductive glue, and is distributed discretely along a specific direction. It can be understood that, in the embodiment, the welding medium point 101 is tin paste, and in other embodiments, the welding medium point 101 can also be formed by materials other than tin paste, silver paste or conductive glue, which can be designed according to actual conditions, and is not limited herein. The adhesive member 60 is made of a material with adhesive property, which can be at least one of UV glue, double-sided adhesive, pressure-sensitive adhesive and heat-set adhesive. It should be noted that the main purpose of the adhesive member 60 is to connect the solder strip 50 and the silicon substrate 1001, and therefore, in other embodiments, the material of the adhesive member 60 can also be made of other materials with adhesive property, which can be considered according to actual conditions, and is not limited herein.

[0034] Further, the solar cell 100 can be a back contact cell, that is, the grid lines of the solar cell 100 are all located on the back surface of the solar cell 100, and the front surface is completely free of grid line shielding, so as to maximize the use of incident light and significantly improve the short-circuit current and conversion efficiency. The grid line can be a main grid line or a fine grid line, and the back contact cell can be a back contact cell with a main grid or a back contact cell without a main grid, which is not limited herein.

[0035] It should be noted that, in other embodiments, the solar cell 100 can also be other cells with grid lines, for example, in one embodiment, the solar cell 100 can be a TOPCon cell; in another embodiment, the solar cell 100 can be a HJT / HIT cell, which can be designed according to different conditions, and is not limited herein.

[0036] In the embodiment, the number of welding medium points 101 is 80, and the number of adhesive members 60 is 4. Along the first direction A, two ends of the solder strip 50 are respectively provided with two adhesive members 60, and the two adhesive members 60 are arranged at intervals. In another embodiment, the number of welding medium points 101 is 90, and the number of adhesive members 60 is 2. Along the first direction A, one end of the solder strip 50 is provided with one adhesive member 60. In another embodiment, the number of welding medium points 101 is 90, and the number of adhesive members 60 is 2. Along the first direction A, the two adhesive members 60 are located at the same end of the solder strip 50, and the two adhesive members 60 are arranged at intervals, that is, one end of the solder strip 50 is provided with two adhesive members 60, and the other end of the solder strip 50 is not provided with an adhesive member 60. In another embodiment, the number of soldering medium points 101 is 100, and the number of adhesive pieces 60 is 6, two adhesive pieces 60 are arranged at the two ends of the solder strip 50 along the first direction A, and two adhesive pieces 60 are arranged in the middle region of the solder strip 50. Specifically, the soldering medium points 101 form a linear array along the first direction A, and the solder strip 50 covers at least part of the soldering medium points 101 to form an electrical connection channel. An avoidance region 601 is arranged in the array of soldering medium 10, which does not arrange any soldering medium points 101, and the adhesive piece 60 is arranged in this region. When the solder strip 50 is pressure soldered, the soldering medium points 101 melt to form a solder joint, and the adhesive piece 60 does not contact the molten solder because it is located in the avoidance region 601. In the subsequent dispensing process, the adhesive is confined within the avoidance region 601, avoiding spreading to the soldering region.

[0037] Wherein, the first direction A refers to the extension direction of the solder strip 50. When the solar cell 100 is a back contact cell, since the back contact cell can be a cell with main grids or a cell without main grids, when the back contact cell is a cell with main grids, the surface of the silicon substrate 1001 is provided with first polarity fine grid lines and second polarity fine grid lines extending along the second direction B and alternately arranged in the first direction A, the first polarity fine grid lines are connected with the first polarity main grids located thereon, the first polarity main grids are connected with the solder strip 50 through the soldering medium points 101, the second polarity fine grid lines are connected with the second polarity main grids located thereon, and the second polarity main grids are connected with the solder strip 50 through the soldering medium points 101, the extension directions of the first polarity main grids and the second polarity main grids are consistent with the extension direction of the solder strip 50. When the back contact cell is a cell without main grids, the surface of the silicon substrate 1001 is provided with first polarity fine grid lines and second polarity fine grid lines extending along the second direction B and alternately arranged in the first direction A, and the first polarity fine grid lines and the second polarity fine grid lines are connected with the solder strip 50 through the soldering medium points 101. The first direction A and the second direction B intersect, specifically, the first direction A can be perpendicular to the second direction B, or they can intersect at a certain angle, which is not limited here.

[0038] Embodiment two Please refer to Figure 1 Further, the avoidance region 601 includes a first avoidance region 6011 and a second avoidance region 6012, and the first avoidance region 6011 and the second avoidance region 6012 are staggered in the second direction B.

[0039] In the embodiment, the number of the avoidance regions 601 is two, each of which includes a first avoidance region 6011 and a second avoidance region 6012, and the first avoidance region 6011 and the second avoidance region 6012 are staggered in the second direction B. In this way, the settable range of the adhesive 60 can be expanded. The second direction B refers to the vertical arrangement direction perpendicular to the extension direction of the solder strip 50, and can be achieved by adjusting the relative position relationship between the solder strip 50 and the silicon substrate 1001, and is used to define the staggered arrangement rule of the avoidance regions 601.

[0040] Specifically, the avoidance regions 601 arranged on the surface of the silicon substrate 1001 are divided into two groups, which are located on the two lateral edges of the solder strip 50, and the two groups are staggered when arranged in the lateral direction. When the solder strip 50 covers the solder medium points 101, the adhesive 60 is arranged in the blank position within the avoidance region 601. Because the first avoidance region 6011 and the second avoidance region 6012 are alternately distributed in the lateral direction, the adhesive 60 can be dispersedly arranged at different positions on both sides of the solder strip 50, so as to avoid that the adhesive 60 (glue) covers the adjacent solder medium points 101 due to lateral expansion during dispensing. At the same time, the staggered arrangement of the avoidance regions 601 increases the spacing between the adjacent adhesives 60, further reducing the risk of lateral flow of the glue to the solder medium points 101.

[0041] In this way, without reducing the number of the solder medium points 101, more flexible arrangement space is provided for the adhesive 60, so as to avoid the welding defects caused by the adhesive 60 (glue) covering the solder medium points 101, and the balance between the mechanical connection strength and the welding reliability is improved by the staggered avoidance regions 601.

[0042] Embodiment Three Please refer to Figure 1 Further, along the first direction A, the avoidance regions 601 are located at the opposite ends of the solder strip 50 in the second direction B, and the first avoidance region 6011 and the second avoidance region 6012 are arranged at intervals.

[0043] In the embodiment, the interval arrangement refers to that the first avoidance region 6011 and the second avoidance region 6012 are staggered in the second direction B, which can be achieved by the way of alternate arrangement, and is used to balance the stress distribution on both sides of the solder strip 50.

[0044] Specifically, the solder strip 50 is provided with an avoidance area 601 at each of the two edges along the second direction B, each avoidance area 601 including a first avoidance area 6011 and a second avoidance area 6012, the first avoidance area 6011 and the second avoidance area 6012 being spaced apart along the first direction A. The adhesive 60 is arranged within the first avoidance area 6011 and the second avoidance area 6012, so that a spatial isolation is formed between the adhesive 60 and the solder medium point 101. Since the avoidance area 601 is located at the two side edges of the solder strip 50 and is spaced apart, the adhesive flow generated by the adhesive 60 during dispensing is limited within the avoidance area 601, avoiding the spread of the adhesive to the area where the solder medium point 101 is located. At the same time, the spaced avoidance areas 601 make the distribution of the adhesive 60 on both sides of the solder strip 50 more uniform, thereby reducing local stress concentration when absorbing mechanical stress.

[0045] In this way, stable physical isolation can be ensured between the adhesive 60 and the solder medium point 101, preventing the adhesive 60 (e.g., glue) from contaminating the soldering area during dispensing and soldering, thereby improving soldering reliability and long-term operation stability of the assembly. At the same time, the spaced avoidance areas 601 optimize the distribution of mechanical support on both sides of the solder strip 50, reducing the risk of hidden cracks caused by stress concentration.

[0046] Embodiment Four Please refer to Figure 1 Furthermore, the plurality of solder medium points 101 are arranged into a plurality of dot arrays 102, the dot arrays 102 including a first dot array 1021 and a second dot array 1022, the first dot array 1021 and the second dot array 1022 being located at opposite two edges of the solder strip 50 along the second direction B, the first dot array 1021 and the second dot array 1022 being spaced apart. The first avoidance area 6011 is located at the other edge opposite the first dot array 1021, and the second avoidance area 6012 is located at the other edge opposite the second dot array 1022.

[0047] Specifically, the dot array 102 refers to a collection formed by a plurality of solder medium points 101 arranged according to a predetermined rule, which can be implemented by horizontal array or staggered array, and the distribution density and position of the solder medium 10 can be controlled by the arrangement of the dot array 102. The first dot array 1021 and the second dot array 1022 refer to the collection of solder medium points 101 located at the two side edges of the solder strip 50, which can be implemented by symmetric or asymmetric arrangement, and the avoidance space for the adhesive 60 can be reserved by spacing.

[0048] Further, the first dot array 1021 and the second dot array 1022 extend along the two side edges of the solder strip 50 respectively, and the first dot array 1021 and the second dot array 1022 are kept apart. Since the avoidance area 601 and the dot array 102 are located at different edges of the solder strip 50 respectively, even if the adhesive 60 expands during dispensing, the adjacent solder medium dots 101 will not be covered. For example, when the first dot array 1021 is located at the upper edge of the solder strip 50, the first avoidance area 6011 is located at the lower edge of the solder strip 50, and the adhesive 60 is only dispensed in the avoidance area 601 of the lower edge, and the solder medium dots 101 of the upper edge are not contaminated by the glue.

[0049] Embodiment Five Further, at least one of the first avoidance area 6011 and the second avoidance area 6012 has a width of 0.5mm-3.5mm in the second direction B.

[0050] In this embodiment, the first avoidance area 6011 and the second avoidance area 6012 have the same width of 2.8mm in the second direction B, but in other embodiments, the first avoidance area 6011 and the second avoidance area 6012 can have different widths in the second direction B. For example, the first avoidance area 6011 has a width of 2.5mm in the second direction B, and the second avoidance area 6012 has a width of 2.8mm in the second direction B, or the first avoidance area 6011 has a width of 2.3mm in the second direction B, and the second avoidance area 6012 has a width of 3.5mm in the second direction B. The specific width can be considered according to the actual situation, and is not limited herein.

[0051] Further, in other embodiments, the width of at least one of the first avoidance region 6011 and the second avoidance region 6012 along the second direction B can also be other ranges of values, for example, in one embodiment, the width of at least one of the first avoidance region 6011 and the second avoidance region 6012 along the second direction B is 1.0mm-4.5mm; for another example, in another embodiment, the width of at least one of the first avoidance region 6011 and the second avoidance region 6012 along the second direction B is 0.2mm-3mm; for yet another example, in yet another embodiment, the width of at least one of the first avoidance region 6011 and the second avoidance region 6012 along the second direction B is 1.0mm-3.2mm, and the specific value can be set according to actual conditions, which is not limited herein. By setting the width of at least one of the first avoidance region 6011 and the second avoidance region 6012 along the second direction B to a reasonable range, it can be ensured that even if the adhesive 60 expands during dispensing, it will not cover the adjacent solder medium points 101, avoiding that the first avoidance region 6011 and the second avoidance region 6012 are set too large to affect the connection reliability of the multiple solder medium points 101 on the opposite side of the solder strip 50 edge and the solder strip 50, and that the first avoidance region 6011 and the second avoidance region 6012 are set too small to cause the adhesive 60 to expand during dispensing, covering the adjacent solder medium points 101, polluting the soldering area, and reducing the soldering reliability and long-term operation stability of the assembly.

[0052] The width of at least one of the first avoidance region 6011 and the second avoidance region 6012 along the second direction B in the above embodiments refers to the vertical distance from the edge of the avoidance region close to the multiple solder medium points 101 on the opposite side to the edge of the solder strip 50 on the opposite side in the second direction B. When the opposite side contains multiple solder medium points 101, any one of the average, minimum, and maximum of the vertical distance from the edge of the avoidance region close to the multiple solder medium points 101 on the opposite side to the edge of the solder strip 50 on the opposite side can be selected as the width of the avoidance region along the second direction B, which is not limited herein.

[0053] Embodiment Six Further, the width of the solder medium points 101 contained in the first dot array 1021 along the second direction B is 0.3mm-4mm. The width of the solder medium points 101 contained in the second dot array 1022 along the second direction B is 0.3mm-4mm.

[0054] In the embodiment, the width of the soldering medium points 101 in the first dot array 1021 along the second direction B is consistent with the width of the soldering medium points 101 in the second dot array 1022 along the second direction B. In other embodiments, the width of the soldering medium points 101 in the first dot array 1021 along the second direction B can also be inconsistent with the width of the soldering medium points 101 in the second dot array 1022 along the second direction B, which is determined according to actual conditions.

[0055] Further, by adjusting the width of the soldering medium points 101 along the second direction B, a soldering area with a specific size can be formed at the edge of the solder strip 50, thereby reserving more space for the adhesive member 60, and the structure is simple and easy to implement.

[0056] Of course, in other embodiments, the width of the soldering medium points 101 in the first dot array 1021 along the second direction B can be 0.5mm-3.8mm; the width of the soldering medium points 101 in the second dot array 1022 along the second direction B is 0.2mm-3.5mm; or the width of the soldering medium points 101 in the first dot array 1021 along the second direction B can be 0.1mm-5mm; the width of the soldering medium points 101 in the second dot array 1022 along the second direction B is 0.1mm-5mm; or the width of the soldering medium points 101 in the first dot array 1021 along the second direction B can be 4mm-7mm; the width of the soldering medium points 101 in the second dot array 1022 along the second direction B is 4mm-7mm. That is, the width range of the soldering medium points 101 in the first dot array 1021 along the second direction B and the width range of the soldering medium points 101 in the second dot array 1022 along the second direction B can be other values, which are not limited herein. By adjusting the width range of the soldering medium points 101 along the second direction B, the connection reliability of the plurality of soldering medium points 101 and the solder strip 50 can be improved, so that even if the adhesive member 60 expands during the dispensing process, the adjacent soldering medium points 101 will not be covered, thereby avoiding contamination of the soldering area and improving the soldering reliability and long-term operation stability of the assembly.

[0057] In the above embodiments, the width of the soldering medium points 101 in the first dot array 1021 or the second dot array 1022 along the second direction B can be any one of the average width, the maximum width, or the minimum width of the plurality of soldering medium points 101 along the second direction B, which is not limited herein.

[0058] Embodiment Seven Please refer toFigure 1 and Figure 2 Further, the plurality of soldering medium points 101 are also arranged into a third point array 1023, along the second direction B, the distance from the two end points of the soldering medium points 101 of the third point array 1023 to the edges of the solder strip 50 is the same.

[0059] In the embodiment, the third point array 1023 refers to the set of soldering medium points 101 located in the middle region of the solder strip 50 and arranged complementarily with the first point array 1021 and the second point array 1022. The symmetrical arrangement of the third point array 1023 makes the stress on both sides of the solder strip 50 uniform, avoiding the offset of the glue due to unilateral stress concentration. Wherein, the same distance from the two end points to the edges of the solder strip 50 means that the distance between the upper and lower two side end points of the soldering medium points 101 relative to the edges of the solder strip 50 is equal, which can be achieved by adjusting the position of the point array 102 or using a positioning mold. Through the symmetry design, the difference in thermal expansion between the solder strip 50 and the silicon substrate 1001 can be balanced, and the transverse flow range of the glue when being squeezed can be reduced.

[0060] Specifically, the third point array 1023 is arranged in the middle region of the solder strip 50, and the soldering medium points 101 thereof are arranged symmetrically along the first direction A. When the solder strip 50 is covered on the soldering medium points 101, the symmetrical structure of the third point array 1023 makes the deformation of the solder strip 50 generated when being heated and expanded or mechanically vibrated be uniformly dispersed, thereby reducing the risk of expansion of the glue due to excessive local stress. At the same time, the third point array 1023 forms an interlaced complementary layout with the first and second point arrays 1022, which provides more stable avoidance space for the bonding member 60 on the basis of ensuring the strength of electrical connection.

[0061] It can be understood that in other embodiments, along the second direction B, the distance from the two end points of the soldering medium points 101 of the third point array 1023 to the edges of the solder strip 50 can also be different, for example, the distance from the two end points of the soldering medium points 101 of part of the third point array 1023 to the edges of the solder strip 50 is the same, the distance from the two end points of the soldering medium points 101 of the remaining part of the third point array 1023 to the edges of the solder strip 50 is different, that is, alternating distribution, or the distance from the two end points of all the soldering medium points 101 of the third point array 1023 to the edges of the solder strip 50 is different, which can be designed according to actual conditions, and is not limited herein.

[0062] Embodiment Eight Please refer to Figure 1 and Figure 2 Further, the absolute value of the distance from the soldering medium points 101 of the third point array 1023 to the two edges of the solder strip 50 is 0mm-2mm.

[0063] Specifically, the absolute value of the distance from the soldering medium point 101 of the third lattice 1023 to the two edges of the solder strip 50 refers to the distance from one end of the soldering medium point 101 to one of the edges. In the embodiment, the soldering medium point 101 is located between the solder strips 50, and the solder strip 50 can completely cover the soldering medium point 101 during the installation process of the solder strip 50. When the absolute value of the distance from the soldering medium point 101 of the third lattice 1023 to the two edges of the solder strip 50 is 0, one of the edges of the solder strip 50 coincides with one end of the soldering medium point 101, and the length from the other end of the soldering medium point 101 to the edge of the other solder strip 50 is 2 mm. In other embodiments, the soldering medium point 101 can be partially located outside the solder strip 50. In this way, during the installation process of the solder strip 50, only the part of the soldering medium point 101 located inside the solder strip 50 can be attached to the solder strip 50, and the part located outside the solder strip 50 cannot be attached to the solder strip 50.

[0064] Embodiment Nine Further, the solder strip 50 covers at least part of the area of the adhesive 60.

[0065] The solder strip 50 covers at least part of the area of the adhesive 60, which means that the solder strip 50 and the adhesive 60 form a spatial overlapping structure. Specifically, the solder strip 50 can have a width greater than the width of the adhesive 60 or the edges of the solder strip 50 can extend beyond the edges of the adhesive 60. In this way, the solder strip 50 forms a physical isolation layer by partially covering the adhesive 60, preventing the gel from spreading outward before solidification.

[0066] Specifically, the solder strip 50 is located above the soldering medium point 101 and the adhesive 60. When the solder strip 50 forms an ohmic contact with the soldering medium point 101 through the hot-pressing process, part of the solder strip 50 covers the surface of the adhesive 60 at the same time. Since the solder strip 50 only covers part of the area of the adhesive 60, the edge area of the adhesive 60 that is not covered can still form an effective bond with the silicon substrate 1001. In the subsequent dispensing process, the gel is applied to the gap area between the solder strip 50 and the silicon substrate 1001. At this time, the structure of the solder strip 50 covering part of the adhesive 60 can block the lateral flow of the gel to the area where the soldering medium point 101 is located.

[0067] Embodiment Ten Further, the ratio of the area of the part of the single adhesive 60 covered by the solder strip 50 to the total area of the single adhesive 60 is less than 0.6.

[0068] The area of the portion of the single adhesive 60 covered by the solder strip 50 refers to the overlapping area formed by the solder strip 50 on the surface of the adhesive 60, and can be achieved by adjusting the relative position of the solder strip 50 and the adhesive 60 or changing the shape of the adhesive 60. This feature is used to limit the degree of coverage of the adhesive 60 by the solder strip 50. The ratio of the total area of the single adhesive 60 to the area of the portion of the single adhesive 60 covered by the solder strip 50 is less than 0.6. It can be understood that in other embodiments, the ratio of the total area of the single adhesive 60 to the area of the portion of the single adhesive 60 covered by the solder strip 50 can also be less than 0.5, or the ratio of the total area of the single adhesive 60 to the area of the portion of the single adhesive 60 covered by the solder strip 50 is less than 0.4, or the ratio of the total area of the single adhesive 60 to the area of the portion of the single adhesive 60 covered by the solder strip 50 is less than 0.35, or the ratio of the total area of the single adhesive 60 to the area of the portion of the single adhesive 60 covered by the solder strip 50 is less than 0.7. The ratio of the total area of the single adhesive 60 to the area of the portion of the single adhesive 60 covered by the solder strip 50 can be designed according to actual conditions, and is not limited herein.

[0069] Embodiment eleven Further, the ratio of the total area of all adhesives 60 to the area of the portion of all adhesives 60 covered by the solder strip 50 ranges from 10% to 60%.

[0070] The area ratio of the solder strip 50 to the adhesive 60 refers to the percentage of the total area of the overlapping region of the solder strip 50 and the adhesive 60 to the total area of all adhesives 60. This can be achieved by adjusting the width of the solder strip 50, the size or layout of the adhesive 60. The ratio is limited to a range of 10% to 60%, for example, it can be 15%, 30% or 50%. The purpose of this is to balance the degree of coverage of the adhesive 60 by the solder strip 50: if the coverage area is too small, it may result in too much exposed area of the adhesive 60, affecting the mechanical stress absorption effect; if the coverage area is too large, it may hinder the elastic deformation space of the adhesive material when it is squeezed, reducing the stress buffering capacity.

[0071] Specifically, during the connection process of the solder strip 50 and the adhesive 60, when the solder strip 50 partially covers the adhesive 60, the uncovered area allows the adhesive 60 to deform when subjected to external force, thereby absorbing mechanical stress. By controlling the coverage area ratio to be within the range of 10% to 60%, for example, by staggering or spacing the adhesives 60, effective connection between the solder strip 50 and the adhesive 60 can be ensured, and at the same time, the diffusion of the adhesive to the soldering medium 10 area due to excessive pressure can be avoided. Within this range, the effective adhesive area and the elastic deformation space of the adhesive 60 are coordinated, maintaining the reliability of the mechanical connection and preventing the adhesive from contaminating the soldering medium 10.

[0072] It can be understood that in other embodiments, the ratio of the area of the portion of the solder strip 50 covering all the adhesive 60 to the total area of all the adhesive 60 can also range from 70% to 80%, or the ratio of the area of the portion of the solder strip 50 covering all the adhesive 60 to the total area of all the adhesive 60 can also range from 70% to 90%, or the ratio of the area of the portion of the solder strip 50 covering all the adhesive 60 to the total area of all the adhesive 60 can also range from 60% to 80%. The ratio of the area of the portion of the solder strip 50 covering all the adhesive 60 to the total area of all the adhesive 60 can be considered according to actual conditions, which is not limited herein.

[0073] Embodiment twelve Further, the gate lines include first gate lines and second gate lines, the soldering medium 10 includes first soldering medium 103 and second soldering medium 104, the adhesive 60 includes first adhesive 601 and second adhesive 602, and the solder strip 50 includes first solder strip 501 and second solder strip 502. The surface of the silicon substrate 1001 is alternately provided with first gate lines and second gate lines, the first gate lines are connected with the first solder strip 501 through the first soldering medium 103, the first solder strip 501 is connected with the silicon substrate 1001 through the first adhesive 601, the second gate lines are connected with the second solder strip 502 through the second soldering medium 104, and the second solder strip 502 is connected with the silicon substrate 1001 through the second adhesive 602.

[0074] In the embodiment, the first gate lines and the second gate lines alternately arranged on the surface of the silicon substrate 1001 are respectively connected with the independent first solder strip 501 and the second solder strip 502 through the corresponding first soldering medium 103 and the second soldering medium 104. The first solder strip 501 is fixed on the silicon substrate 1001 through the first adhesive 601, the second solder strip 502 is fixed on the silicon substrate 1001 through the second adhesive 602, and the soldering medium 10 and the adhesive 60 avoid each other in space. In this way, the connection areas of the first solder strip 501 and the second solder strip 502 are separated from each other, the soldering medium point 101 array and the adhesive 60 do not interfere with each other, and the contamination of the soldering interface by the flow of the adhesive is avoided.

[0075] Through the independent connection of different gate lines and corresponding solder strips 50, the interference problem caused by the superimposed arrangement of multiple groups of soldering medium 10 and adhesive 60 in the same area is avoided. After the soldering interface and the mechanical adhesive interface are separated, the flow range of the adhesive is limited in the independent area, the cleanliness of the soldering medium 10 is ensured, and the layout of the split solder strip 50 enhances the mechanical stress dispersion capability, thereby improving the connection reliability and the service life of the component.

[0076] Embodiment thirteen Further, the silicon substrate 1001 comprises a first region and a second region, the first region is provided with a first doped layer, and the second region is provided with a second doped layer, the first doped layer and the second doped layer are different in polarity; The first gate line is located in the first region, and the second gate line is located in the second region.

[0077] The first doped layer and the second doped layer are different in polarity, which means that P-type doped and N-type doped semiconductor layers are formed respectively, and the P-N junction is formed by the diffusion of phosphorus or boron to promote the separation of photo-generated carriers. The first gate line located in the first region means that the positive electrode collection gate line is arranged in the P-type doped region, and the second gate line located in the second region means that the negative electrode collection gate line is arranged in the N-type doped region, so as to ensure that the carrier transmission path matches the doped region. In some embodiments, the first gate line located in the first region can also mean that the negative electrode collection gate line is arranged in the N-type doped region, and the second gate line located in the second region can also mean that the positive electrode collection gate line is arranged in the P-type doped region.

[0078] In this embodiment, after the P-type doped first region and the N-type doped second region or the N-type doped second region and the P-type doped first region are divided on the surface of the silicon substrate 1001, the positive electrode collection gate line is arranged in the P-type region to collect hole carriers, and the negative electrode collection gate line is arranged in the N-type region to collect electrons. This layout mode forms a directional carrier transmission channel between the gate line and the corresponding doped region, avoiding the carrier recombination loss caused by the interlaced arrangement of the positive and negative electrode gate lines in the traditional design.

[0079] Embodiment fourteen Please refer to Figure 1 and Figure 2 Further, the first solder medium 103 comprises a first dot array 1021 located at the first edge 505 of the first solder strip 501, and a second dot array 1022 located at the second edge 506 of the first solder strip 501, the first dot array 1021 and the second dot array 1022 are arranged in a spaced manner, the first avoiding area 6011 is located at the second edge 506 of the first solder strip 501, and the second avoiding area 6012 is located at the first edge 505 of the first solder strip 501.

[0080] By setting the first dot matrix 1021 at the first edge 505 of the first solder strip 501 and the second dot matrix 1022 at the second edge 506, both of which are arranged at intervals along the length direction of the solder strip 50, two parallel arrays of solder medium dots 101 are formed. Meanwhile, no solder medium dots 101 are arranged in the first avoiding area 6011 at the second edge 506 of the solder strip 50 and the second avoiding area 6012 at the first edge 505, so that the adhesive 60 can be completely embedded in the avoiding area 601. Since the array of solder medium dots 101 and the avoiding area 601 are spatially isolated from each other, the adhesive only covers the avoiding area 601 during the dispensing process and does not invade the area where the solder medium dots 101 are located, thereby avoiding the soldering defects caused by adhesive pollution.

[0081] In the embodiment, the first dot matrix 1021 and the second dot matrix 1022 are both located at the two ends of the first solder strip 501 and are arranged close to the two end portions of the first solder strip 501, the second dot matrix 1022 is arranged at intervals from the first dot matrix 1021, and the third dot matrix 1023 is located between the second dot matrix 1022 and the end portion corresponding to the first dot matrix 1021 or the third dot matrix 1023 can also be arranged close to the edge of the solder strip 50 at the second dot matrix 1022 or the first dot matrix 1021, for example, the third dot matrix 1023 is parallel to the second dot matrix 1022 or the first dot matrix 1021 in the first direction A.

[0082] In other embodiments, the dot matrix can further include a fourth dot matrix and a fifth dot matrix, the fourth dot matrix and the fifth dot matrix are located at the middle of the first solder strip 501, the fourth dot matrix is located at the first edge 505 of the first solder strip 501, the fifth dot matrix is located at the second edge 506 of the first solder strip 501, the fourth dot matrix and the fifth dot matrix are arranged at intervals, the first avoiding area 6011 is located at the second edge 506 of the first solder strip 501, and the second avoiding area 6012 is located at the first edge 505 of the first solder strip 501; or the fourth dot matrix is located at the second edge 506 of the first solder strip 501, the fifth dot matrix is located at the first edge 505 of the first solder strip 501, the fourth dot matrix and the fifth dot matrix are arranged at intervals, the first avoiding area 6011 is located at the first edge 505 of the first solder strip 501, and the second avoiding area 6012 is located at the second edge 506 of the first solder strip 501.

[0083] The above is only an example to illustrate the types of solder medium dots 101, and in different embodiments, the solder medium dots 101 can also be arranged at other positions, which can be designed according to actual conditions and are not limited herein.

[0084] Embodiment Fifteen Please refer again to Figure 1 and Figure 2 ​​​​​​Further, the first dot array 1021 of the second soldering medium 104 is located at the second edge 506 of the second soldering ribbon 502, the second dot array 1022 of the second soldering medium 104 is located at the first edge 505 of the second soldering ribbon 502, the first dot array 1021 and the second dot array 1022 are arranged in an interval, the first avoiding area 6011 is located at the first edge 505 of the second soldering ribbon 502, and the second avoiding area 6012 is located at the second edge 506 of the second soldering ribbon 502.

[0085] By distributing the first dot array 1021 of the second soldering medium 104 along the second edge 506 of the second soldering ribbon 502 and distributing the second dot array 1022 along the first edge 505 of the second soldering ribbon 502, the two dot arrays 102 are arranged in an interval to form a discontinuous dot array 102 layout. The first avoiding area 6011 and the second avoiding area 6012 are arranged at the first edge 505 and the second edge 506 respectively, and the two avoiding areas 601 are arranged in an interval in the length direction of the soldering ribbon 50. The adhesive 60 is arranged in the avoiding area 601 to avoid overlapping with the soldering medium dot 101. In the soldering process, the second soldering ribbon 502 is electrically connected with the second grid line through the dot array 102 of the second soldering medium 104, and the adhesive 60 is located in the avoiding area 601 and does not contact the soldering medium dot 101, so as not to interfere with the soldering interface in the mechanical fixing.

[0086] In the embodiment, the first dot array 1021 and the second dot array 1022 are respectively located at the two ends of the second soldering ribbon 502 and are arranged close to the two end portions of the second soldering ribbon 502, the second dot array 1022 is arranged in an interval with the first dot array 1021, and the third dot array 1023 is located between the second dot array 1022 and the end portion corresponding to the first dot array 1021 or the third dot array 1023 can be arranged close to the soldering ribbon 50 edge of the second dot array 1022 or the first dot array 1021, for example, the third dot array 1023 is parallel to the second dot array 1022 or the first dot array 1021 in the first direction A.

[0087] In other embodiments, the dot array can further include a fourth dot array and a fifth dot array, the fourth dot array and the fifth dot array are located in the middle of the second soldering ribbon 502, the fourth dot array is located at the second edge 506 of the second soldering ribbon 502, the fifth dot array is located at the first edge 505 of the second soldering ribbon 502, the fourth dot array and the fifth dot array are arranged in an interval, the first avoiding area 6011 is located at the first edge 505 of the first soldering ribbon 501, and the second avoiding area 6012 is located at the second edge 506 of the first soldering ribbon 501; or the fourth dot array is located at the first edge 505 of the second soldering ribbon 502, the fifth dot array is located at the second edge 506 of the second soldering ribbon 502, the fourth dot array and the fifth dot array are arranged in an interval, the first avoiding area 6011 is located at the second edge 506 of the first soldering ribbon 501, and the second avoiding area 6012 is located at the first edge 505 of the first soldering ribbon 501.

[0088] The above is only an example to illustrate the types of soldering medium points 101. In different embodiments, the soldering medium points 101 can also be arranged at other positions, which can be designed according to actual conditions and are not limited herein.

[0089] Embodiment sixteen Please continue to refer to Figure 1 and Figure 2 Further, the third soldering band 503 and the fourth soldering band 504 are arranged on the silicon substrate 1001. The first gate line is connected with the third soldering band 503 through the third soldering medium 105, and the third soldering band 503 is connected with the silicon substrate 1001 through the third adhesive 603. The second gate line is connected with the fourth soldering band 504 through the fourth soldering medium 106, and the fourth soldering band 504 is connected with the silicon substrate 1001 through the fourth adhesive 604.

[0090] The first gate line is electrically connected with the third soldering band 503 through the third soldering medium 105, and the third soldering band 503 is fixed on the surface of the silicon substrate 1001 through the third adhesive 603. The second gate line is electrically connected with the fourth soldering band 504 through the fourth soldering medium 106, and the fourth soldering band 504 is fixed on the surface of the silicon substrate 1001 through the fourth adhesive 604. When a plurality of soldering bands 50 are arranged on the solar cell 100, for example, the third soldering band 503 and the fourth soldering band 504 are arranged, and the soldering area and the adhesive area are further separated in space through the above arrangement mode, so as to avoid the pollution of the soldering medium 10 by the flow of the adhesive. The third soldering medium 105 and the fourth soldering medium 106 are independently distributed below different soldering bands 50, and the adhesive 60 is arranged in the avoiding area 601 at the edge of the soldering band 50, so as to ensure that the soldering and the adhesive functions do not interfere with each other.

[0091] Embodiment seventeen Please continue to refer to Figure 1 and Figure 2 Further, the arrangement modes of the first soldering medium 103 and the first adhesive 601 and the fourth soldering medium 106 and the fourth adhesive 604 on the silicon substrate are the same, and the arrangement modes of the second soldering medium 104 and the second adhesive 602 and the third soldering medium 105 and the third adhesive 603 on the silicon substrate are the same.

[0092] In the embodiment, the same arrangement refers to the space distribution mode and relative position relationship of the soldering medium 10 and the corresponding adhesive 60 being consistent. This design can ensure that the synergistic effect of the soldering medium 10 and the adhesive 60 in different regions is consistent. The corresponding relationship between the soldering medium 10 and the adhesive 60 refers to that a specific soldering medium 10 group and a specific adhesive 60 group form a fixed combination. Specifically, the position offset of the soldering medium point 101 array and the adhesive 60 can be pre-set to realize this corresponding relationship, which can avoid interference between different soldering media 10 and adhesives 60.

[0093] Specifically, when the first soldering medium 103 is arranged on the surface of the silicon substrate, the corresponding first adhesive 601 is arranged at a fixed interval or offset, and the fourth soldering medium 106 and the fourth adhesive 604 are arranged according to the same arrangement rule. Similarly, the second soldering medium 104 and the second adhesive 602, and the third soldering medium 105 and the third adhesive 603 each form another group of symmetrical arrangement modes. This symmetrical layout makes the solder strip 50 form a repeated and predictable connection structure at the edge region of the silicon substrate, which not only ensures the effective isolation of the soldering medium point 101 and the adhesive 60, but also realizes the standardized configuration of different solder strip 50 connection modes.

[0094] In the embodiment, the polarity of the first solder strip 501 and the third solder strip 503 is the same, and the polarity of the second solder strip 502 and the fourth solder strip 504 is the same. Through the above staggered arrangement, when one of the solder strips is offset, the other solder strip with the same polarity can also contact the corresponding solder paste, thereby avoiding the situation that the solder strip is offset and does not contact the solder paste, and improving the working performance of the solar cell 100.

[0095] Of course, in other embodiments, the arrangement of the first soldering medium 103 and the first adhesive 601, the second soldering medium 104 and the second adhesive 602 on the silicon substrate can be the same, and the arrangement of the third soldering medium 105 and the third adhesive 603, the fourth soldering medium 106 and the fourth adhesive 604 on the silicon substrate can be the same; or The arrangement of the first soldering medium 103 and the first adhesive 601, the third soldering medium 105 and the third adhesive 603 on the silicon substrate can be the same, and the arrangement of the second soldering medium 104 and the second adhesive 602, the fourth soldering medium 106 and the fourth adhesive 604 on the silicon substrate can be the same. Specifically, it can be designed according to actual conditions, which is not limited here.

[0096] It needs to be understood that in other embodiments, the fifth solder strip 50, the sixth solder strip 50, etc. can also be arranged on the silicon substrate 1001, and the specific arrangement modes of the corresponding fifth soldering medium 10, the fifth adhesive 60, and the sixth soldering medium 10, the sixth adhesive 60 can be the same as the above, and will not be repeated here.

[0097] Embodiment eighteen Further, the distance between the adhesive 60 and at least one edge of the solder strip 50 is 0.5mm-2mm.

[0098] In the embodiment, the adhesive 60 is generally in the shape of a racetrack, and along the second direction B, it includes an upper edge and a lower edge, and the adhesive 60 is at least partially located outside the solder strip 50, so as to facilitate the bonding work of the adhesive 60 and easy molding, and the distance between the adhesive 60 and at least one edge of the solder strip 50 is the distance from the upper edge or the lower edge of the adhesive 60 located outside the solder strip 50 to the edge of the solder strip 50 close to it.

[0099] It can be understood that in other embodiments, the distance between the adhesive 60 and at least one edge of the solder strip 50 can also be other values, for example, in one example, the distance between the adhesive 60 and at least one edge of the solder strip 50 is 0.2mm-2.5mm; in another example, the distance between the adhesive 60 and at least one edge of the solder strip 50 is 0.1mm-1.5mm; in another example, the distance between the adhesive 60 and at least one edge of the solder strip 50 is 0.1mm-2.5mm, which can be considered according to actual conditions, and is not limited here. By reasonably setting the distance between the adhesive 60 and at least one edge of the solder strip 50, the bonding work of the adhesive 60 and the solder strip 50 is facilitated, easy to mold, and the firmness of the bonding can be ensured.

[0100] It needs to be noted that in other embodiments, the adhesive 60 can also be other shapes, such as circular, square, triangular, etc., which can be designed according to actual conditions, and is not limited here.

[0101] Embodiment nineteen Further, the interval distance of the plurality of soldering medium points 101 along the first direction A is 0.4mm-1.5mm.

[0102] Of course, in other embodiments, the interval distance of the plurality of solder medium points 101 along the first direction A can also be other values, for example, in one example, the interval distance of the plurality of solder medium points 101 along the first direction A is 0.2mm-1.6mm; for example, in another example, the interval distance of the plurality of solder medium points 101 along the first direction A is 0.3mm-2mm; for example, in another example, the interval distance of the plurality of solder medium points 101 along the first direction A is 0.5mm-1.5mm, which can be designed according to actual conditions, which is not limited here. By reasonably setting the interval distance of the plurality of solder medium points 101 along the first direction A, it can be avoided that the interval distance is too small to cause the plurality of solder medium points 101 to be bonded together, thereby affecting the welding performance, or the interval distance is too large, and the reliability of the plurality of solder medium points 101 connecting the grid line and the solder strip 50 is reduced.

[0103] Embodiment twenty Please refer to Figure 3 and Figure 4 A solar cell module 1000, comprising the solar cell 100 of any one of the above, the solar cell module 1000 comprises a plurality of solar cells 100 connected in series along the first direction A, and the plurality of solar cells 100 are connected by the solder strip 50.

[0104] In the present embodiment, the solar cell module 1000 further comprises an isolation strip 30 and a bus bar 40, the isolation strip 30 refers to a strip structure arranged at the top of the adjacent solar cell 100 stacking area, which can be made of flexible insulating materials such as rubber or polyurethane, the bus bar 40 is located on the side of the isolation strip 30 away from the solar cell 100, the bus bar 40 refers to a conductive component for collecting and transmitting the current generated by the solar cell 100, which can be made of copper-based materials or aluminum-based materials, the bus bar 40 is arranged outside the isolation strip 30, the solder strip 50 connects the adjacent two solar cells 100 and the bus bar 40, and the solder strip 50 includes a copper-based solder strip 50, an alloy-based solder strip 50 and a silver-based solder strip 50.

[0105] Embodiment twenty-one A photovoltaic system, comprising the solar cell module 1000 described above.

[0106] The beneficial effects achieved by the present application are that the surface of the silicon substrate 1001 is alternately provided with a plurality of gate lines, the gate lines are connected with the solder strip 50 through at least one row of welding medium 10, the welding medium 10 includes a plurality of welding medium points 101 along the first direction A, and the solder strip 50 at least partially covers the welding medium points 101; the solder strip 50 is also connected with the silicon substrate 1001 through a plurality of adhesive pieces 60, at least one row of welding medium 10 is provided with a plurality of avoidance areas 601, the adhesive pieces 60 are at least partially located in the avoidance areas 601, the avoidance areas 601 are not provided with the welding medium 10, the avoidance areas 601 are arranged to avoid the adhesive pieces 60 from flowing when being extruded and contacting the welding medium points 101, thereby preventing the adhesive pieces 60 from polluting the welding medium points 101, optimizing the stress distribution, and having the advantages of avoiding the adhesive pieces 60 from polluting the welding medium points 101, improving the welding reliability, reducing the false welding and cavity defects, optimizing the stress distribution, and prolonging the service life.

[0107] It can be understood that those skilled in the art can combine various embodiments in each of the above embodiments to obtain various embodiments of the technical solutions.

[0108] The above is only a preferred embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A solar cell, characterized in that, include: Silicon substrate; The surface of the silicon substrate is alternately provided with a plurality of gate lines, the gate lines are connected to the solder strip through at least one row of soldering medium, the soldering medium includes a plurality of soldering medium points along a first direction, and the solder strip at least partially covers the soldering medium points; The solder strip is also connected to the silicon substrate by a number of adhesives. A number of clearance areas are provided on the at least one row of soldering medium. The adhesives are at least partially located in the clearance areas, and no soldering medium is provided in the clearance areas.

2. The solar cell as described in claim 1, characterized in that, The avoidance area includes a first avoidance area and a second avoidance area, which are staggered in a second direction.

3. The solar cell as described in claim 2, characterized in that, Along the first direction, the avoidance area is located at the opposite ends of the welding strip in the second direction, and the first avoidance area and the second avoidance area are spaced apart.

4. The solar cell as described in claim 2, characterized in that, The plurality of welding medium points are arranged into a plurality of dot arrays, the dot arrays including a first dot array and a second dot array, the first dot array and the second dot array are respectively located at two opposite edges of the welding strip along the second direction, and the first dot array and the second dot array are spaced apart; The first avoidance area is located on the other edge opposite to the first dot matrix, and the second avoidance area is located on the other edge opposite to the second dot matrix.

5. The solar cell as described in claim 3, characterized in that, The width of at least one of the first avoidance area and the second avoidance area along the second direction is 0.5mm-3.5mm.

6. The solar cell as described in claim 4, characterized in that, The width of the welding medium dots included in the first dot matrix along the second direction is 0.3mm-4mm; The width of the welding medium dots included in the second dot matrix along the second direction is 0.3mm-4mm.

7. The solar cell as claimed in claim 4, characterized in that, The plurality of welding medium points are further arranged in a third dot matrix, and along the second direction, the two endpoints of the welding medium points in the third dot matrix are at the same distance from the edge of the weld strip.

8. The solar cell as claimed in claim 7, characterized in that, The absolute value of the distance from the welding medium point of the third dot matrix to the two edges of the welding strip is 0mm-2mm.

9. The solar cell according to claim 1, characterized in that, The solder strip covers at least a portion of the adhesive component.

10. The solar cell according to claim 9, characterized in that, The ratio of the area of ​​the portion of the solder strip covering a single adhesive element to the total area of ​​the single adhesive element is less than 0.

6.

11. The solar cell as claimed in claim 9, characterized in that, The ratio of the area of ​​the portion of the solder strip covering all the adhesive components to the total area of ​​all the adhesive components ranges from 10% to 60%.

12. The solar cell according to claim 4, characterized in that, The grid lines include a first grid line and a second grid line; the welding medium includes a first welding medium and a second welding medium; the adhesive includes a first adhesive and a second adhesive; and the welding strip includes a first welding strip and a second welding strip. The surface of the silicon substrate is alternately provided with the first gate line and the second gate line. The first gate line is connected to the first solder ribbon through the first welding medium. The first solder ribbon is connected to the silicon substrate through the first adhesive. The second gate line is connected to the second solder ribbon through the second welding medium. The second solder ribbon is connected to the silicon substrate through the second adhesive.

13. The solar cell according to claim 12, characterized in that, The silicon substrate includes a first region and a second region. A first doped layer is disposed on the first region, and a second doped layer is disposed on the second region. The first doped layer and the second doped layer have different polarities. The first gate line is located in the first region, and the second gate line is located in the second region.

14. The solar cell according to claim 12, characterized in that, The first welding medium includes a first dot matrix located at the first edge of the first weld strip, and a second dot matrix included in the first welding medium located at the second edge of the first weld strip. The first dot matrix and the second dot matrix are spaced apart. The first clearance area is located at the second edge of the first weld strip, and the second clearance area is located at the first edge of the first weld strip.

15. The solar cell as claimed in claim 14, characterized in that, The first dot matrix of the second welding medium is located at the second edge of the second welding strip, and the second dot matrix of the second welding medium is located at the first edge of the second welding strip. The first dot matrix and the second dot matrix are spaced apart. The first clearance area is located at the first edge of the second welding strip, and the second clearance area is located at the second edge of the second welding strip.

16. The solar cell as claimed in claim 15, characterized in that, The silicon substrate is further provided with a third solder strip and a fourth solder strip. The first gate line is connected to the third solder strip through the third soldering medium. The third solder strip is connected to the silicon substrate through the third adhesive. The second gate line is connected to the fourth solder strip through the fourth soldering medium. The fourth solder strip is connected to the silicon substrate through the fourth adhesive.

17. The solar cell as claimed in claim 16, characterized in that, The first welding medium and the first adhesive, the fourth welding medium and the fourth adhesive are arranged in the same way on the silicon substrate, and the second welding medium and the second adhesive, the third welding medium and the third adhesive are arranged in the same way on the silicon substrate.

18. The solar cell according to claim 1, characterized in that, The distance between the adhesive and at least one edge of the solder strip is 0.5mm-2mm.

19. The solar cell according to claim 1, characterized in that, The distance between the multiple welding medium points along the first direction is 0.4mm-1.5mm.

20. The solar cell according to claim 1, characterized in that, The adhesive is made of an adhesive material, which may be at least one of UV adhesive, double-sided adhesive, pressure-sensitive adhesive, and thermosetting adhesive.

21. A solar cell module, characterized in that, The solar cell module includes any one of the solar cells described in claims 1-20, wherein the solar cell module comprises a plurality of solar cells connected in series along the first direction, and the plurality of solar cells are connected by the solder strip.

22. A photovoltaic system, characterized in that, Includes the solar cell module as described in claim 21.

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