Metal semiconductor contact structure and preparation method thereof, solar cell and photovoltaic module

Abstract

The invention relates to a metal semiconductor contact structure and a preparation method thereof, a solar cell and a photovoltaic module. The metal semiconductor contact structure comprises a metal electrode and a semiconductor layer which are in contact with each other, the metal electrode comprises metal elements, and the semiconductor layer comprises semiconductor elements and doping elements used for doping the semiconductor layer; a conductive structure is arranged on a contact interface of the metal electrode and the semiconductor layer, and the conductive structure comprises a conductive aggregate which is close to the metal electrode and extends towards the direction of the semiconductor layer. A conductive network can be formed between the conductive aggregate and the metal particles wrapped in the glass phase, so that the contact resistance is remarkably reduced, and the electron transmission efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a metal-semiconductor contact structure, a preparation method thereof, a solar cell and a photovoltaic module. BACKGROUND

[0002] In a solar cell, the contact quality between a metal electrode and a semiconductor layer directly affects the performance of the solar cell. However, the conductive contact performance of the metal-semiconductor contact structure of the current solar cell is not ideal (for example, the contact resistance is high), which limits the further improvement of the electrical performance of the solar cell. SUMMARY

[0003] Therefore, it is necessary to provide a metal-semiconductor contact structure and a preparation method thereof, a solar cell and a photovoltaic module, which can improve the contact performance of the metal-semiconductor contact structure and optimize the electrical performance of the solar cell.

[0004] In a first aspect, the present application provides a metal-semiconductor contact structure, which comprises a metal electrode and a semiconductor layer in contact with each other, the metal electrode comprises a metal element, and the semiconductor layer comprises a semiconductor element and a doping element for doping the semiconductor layer.

[0005] The metal-semiconductor contact structure further comprises a conductive structure at the contact interface between the metal electrode and the semiconductor layer, the conductive structure comprises a conductive aggregate extending from the metal electrode towards the semiconductor layer.

[0006] In one embodiment, the conductive structure further comprises a first conductive crystal, the first conductive crystal is in contact with the metal electrode, and the first conductive crystal comprises a crystal formed by crystallization of the metal element; and the conductive aggregate extends from the first conductive crystal towards the semiconductor layer.

[0007] In one embodiment, the conductive aggregate comprises an aggregate of the first conductive crystal.

[0008] In one embodiment, the metal-semiconductor contact structure further comprises a second conductive crystal, the second conductive crystal is located on the surface of the semiconductor layer, and the first conductive crystal comprises a crystal formed by crystallization of the metal element.

[0009] In one embodiment, the metal electrode comprises a silver electrode, a copper electrode or a tin electrode; and / or,

[0010] The semiconductor element comprises a silicon element; and / or,

[0011] The semiconductor layer comprises a doped single crystal silicon layer, a doped polycrystalline silicon layer or an intrinsic silicon layer.

[0012] In one of the embodiments, the conductive aggregate comprises a crystalline main chain and a crystalline side chain extending from the crystalline main chain in a direction different from a growth direction of the crystalline main chain.

[0013] In one of the embodiments, the conductive aggregate has a maximum extension width of 5nm-200nm and a maximum extension length of 10nm-500nm.

[0014] In one of the embodiments, the metal-semiconductor contact structure has a first conductive region and a second conductive region, the second conductive region has a conductive structure, and the first conductive region has a glass phase and metal particles, the glass phase is formed by sintering of a glass frit, the glass frit is in contact with the semiconductor layer and ablates part of the passivation layer on the semiconductor layer; wherein the metal particles form a direct conductive contact with the semiconductor layer through the ablated part of the passivation layer; the metal particles and the conductive aggregate have the same kind of metal elements.

[0015] In one of the embodiments, the conductive aggregate is wrapped by the glass phase, and part of the conductive aggregate is in contact with part of the metal particles.

[0016] In a second aspect, the application further provides a method for preparing a metal-semiconductor contact structure, the metal-semiconductor contact structure is the metal-semiconductor contact structure described above, and the method comprises the following steps:

[0017] printing an electrode paste on the semiconductor layer; the electrode paste comprises a glass frit, metal particles and an organic carrier;

[0018] sintering the electrode paste at high temperature to form an electrode precursor on the semiconductor layer, the electrode precursor comprises a glass phase, and metal particles and conductive aggregates wrapped in the glass phase;

[0019] performing photo-injection on the electrode precursor to form a metal electrode, so that a metal-semiconductor contact structure is formed between the metal electrode and the semiconductor layer.

[0020] In one of the embodiments, the high-temperature sintering of the electrode paste comprises a first heating stage, a second heating stage and a cooling stage.

[0021] The peak temperature of the first heating stage is 300℃-400℃.

[0022] The peak temperature of the second heating stage is 750℃-850℃.

[0023] The cooling stage comprises gradient cooling.

[0024] In one of the embodiments, the first heating stage comprises the following process:

[0025] heating to a first preset temperature, the first preset temperature is 250℃-350℃;

[0026] After heating from the first preset temperature to the peak temperature of the first heating stage, the temperature is decreased to the first preset temperature again within a first preset time, wherein the first preset time is 5s-10s.

[0027] In one of the embodiments, the second heating stage includes the following processes:

[0028] Heating to a second preset temperature, wherein the second preset temperature is 700℃-800℃;

[0029] After heating from the second preset temperature to the peak temperature of the second heating stage, the temperature is decreased to the second preset temperature again within a second preset time, wherein the second preset time is 5s-10s.

[0030] In one of the embodiments, the gradient cooling includes the following processes: starting from the second preset temperature, the temperature is decreased within 3s-10s, and the temperature decreasing rate is 130℃ / s-160℃ / s; after decreasing to 300℃-400℃, the temperature is decreased slowly, and the decreasing rate of the slow temperature decrease is 50℃ / s-100℃ / s.

[0031] In one of the embodiments, the step of light injection includes:

[0032] Heating the electrode precursor once, and the peak temperature of the once heating is 180℃-620℃;

[0033] Heating the electrode precursor twice and performing light irradiation, and the peak temperature of the twice heating is 80℃-320℃, the energy density of the light irradiation is 12kW / m 2 ~120kW / m 2 , and the wavelength of the light irradiation is 500nm-1100nm of the continuous spectrum band.

[0034] In a third aspect, the application further provides a solar cell, which includes:

[0035] A metal-semiconductor contact structure, which includes a metal electrode and a semiconductor layer in contact with each other, the metal electrode has a metal element, and the semiconductor layer has a semiconductor element and a doping element for doping the semiconductor layer; the contact interface between the metal electrode and the semiconductor layer has a conductive structure, and the conductive structure includes a conductive aggregate extending towards the semiconductor layer close to the metal electrode;

[0036] A silicon substrate, and the light-receiving surface of the silicon substrate has a textured structure;

[0037] The metal-semiconductor contact structure is arranged on the light-receiving surface and / or the back surface of the silicon substrate, and the semiconductor layer is arranged close to the silicon substrate.

[0038] In one of the embodiments, the textured structure is a pyramid structure.

[0039] In one of the embodiments, the solar cell further comprises a passivation layer disposed on the surface of the semiconductor layer away from the silicon substrate, and the metal electrode penetrates the passivation layer to contact the semiconductor layer.

[0040] In one of the embodiments, the solar cell comprises:

[0041] On the light-receiving surface of the silicon substrate, a PN junction region, a first passivation layer and a first metal electrode are sequentially disposed in the direction away from the light-receiving surface, wherein the PN junction region is a first semiconductor layer;

[0042] On the back surface of the silicon substrate, a passivation contact structure, a second passivation layer and a second metal electrode are sequentially disposed in the direction away from the back surface, wherein the passivation contact structure comprises a tunneling passivation layer disposed close to the silicon substrate and a doped silicon layer disposed away from the silicon substrate, the doped silicon layer has the same conductivity type as the silicon substrate, and the doped silicon layer is a second semiconductor layer;

[0043] The first metal electrode penetrates part of the first passivation layer to contact the first semiconductor layer, so that the first metal electrode and the PN junction region form a metal-semiconductor contact structure, and / or the second metal electrode penetrates the second passivation layer to contact the doped silicon layer, so that the second metal electrode and the doped silicon layer form a metal-semiconductor contact structure.

[0044] In one of the embodiments, the first semiconductor layer is formed by thermal diffusion of a doping element to the silicon substrate, or the first semiconductor layer is a doped polysilicon layer or a doped amorphous silicon layer deposited on the light-receiving surface of the silicon substrate; and / or,

[0045] The first passivation layer is one or more of an aluminum oxide layer, a silicon oxide layer, a silicon oxynitride layer or a silicon nitride layer deposited on the PN junction region; and / or,

[0046] The tunneling passivation layer is at least one of a silicon oxide layer, an amorphous silicon layer, a polysilicon layer or a silicon carbide layer; and / or, the second passivation layer is one or more of a silicon oxide layer, a silicon oxynitride layer or a silicon nitride layer deposited on the second semiconductor layer.

[0047] In one of the embodiments, the solar cell comprises:

[0048] A tunneling passivation layer, a first semiconductor layer, a first passivation layer and a first metal electrode are sequentially disposed on an N-type conductive region of the back surface of the silicon substrate;

[0049] A tunneling passivation layer, a second semiconductor layer, a second passivation layer and a second metal electrode are sequentially disposed on a P-type conductive region of the back surface of the silicon substrate; one of the first semiconductor layer and the second semiconductor layer has an N-type doping element, and the other has a P-type doping element;

[0050] The first metal electrode penetrates the first passivation layer and contacts the first semiconductor layer, so that the first metal electrode and the first semiconductor layer form a metal-semiconductor contact structure, and / or the second metal electrode penetrates the second passivation layer and contacts the second semiconductor layer, so that the second metal electrode and the second semiconductor layer form a metal-semiconductor contact structure.

[0051] In a fourth aspect, the present application further provides a photovoltaic module comprising the solar cell described above.

[0052] The metal-semiconductor contact structure, the preparation method thereof, the solar cell and the photovoltaic module described above can enhance the electron transmission efficiency by having the conductive structure at the contact interface between the metal electrode and the semiconductor layer, wherein the conductive structure comprises a conductive aggregate close to the metal electrode and extending towards the semiconductor layer, and the conductive aggregate can form a conductive network with the metal particles wrapped in the glass phase, so that the contact resistance is significantly reduced and the electron transmission efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other related drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0054] Figure 1 FIG. 1 is a structural schematic diagram of a solar cell in an embodiment;

[0055] Figure 2 FIG. 2 is an enlarged schematic diagram of the structure at A in FIG. 1; Figure 1

[0056] Figure 3 FIG. 3 is a structural schematic diagram of a conductive aggregate in a metal-semiconductor contact structure in an embodiment;

[0057] Figure 4 FIG. 4 is a structural schematic diagram of a solar cell in another embodiment;

[0058] Figure 5 FIG. 5 is an SEM image of a contact interface of a metal-semiconductor contact structure in a solar cell in an embodiment.

[0059] Legend of the drawings:

[0060] ​100, silicon substrate; 200, semiconductor layer; 201, first semiconductor layer; 202, second semiconductor layer; 300, metal electrode; 301, first metal electrode; 302, second metal electrode; 400, passivation layer; 401, first passivation layer; 4011, aluminum oxide passivation layer; 4012, anti-reflection layer; 402, second passivation layer; 403, third passivation layer; 500, tunneling passivation layer;

[0061] 1, metal-semiconductor contact structure; 110, metal block; 12, conductive structure; 121, conductive aggregate; 122, first conductive crystalline body; 123, second conductive crystalline body; 1211, crystalline main chain; 1212, crystalline side chain; 13, contact interface; 14, glass phase; 15, metal particle; 1a, first conductive region; 1b, second conductive region 1b. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application, and are not intended to limit the present application.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0064] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, for example, a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0065] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other directions (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0066] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0067] Embodiments of the application are described herein with reference to the drawings, which show idealized embodiments (and intermediate structures) of the application as schematic cross-sections. Variations of the shapes of the regions shown are to be expected as a result, for example, of manufacturing processes and / or tolerances, and are to be considered within the scope of the embodiments of the present application. Thus, embodiments of the present application should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region that is shown as a rectangle will often have rounded or curved features at its edges rather than a binary change from implanted to non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Thus, the regions shown in the drawings are schematic in nature and their shapes are not intended to be limiting of the present application.

[0068] In the metallization process of crystalline silicon solar cells, the contact quality between metal electrodes and semiconductor layers directly affects the series resistance and fill factor. The traditional contact structure usually adopts silver paste containing glass frit to form by high-temperature sintering, and the key mechanism is that at the peak temperature (about 800℃), the glass frit melts and corrodes the passivation layer such as silicon nitride or aluminum oxide, so that the silver colloidal particles form ohmic contact with the silicon matrix. However, the existence of the glass phase formed by sintering of the glass frit promotes the penetration of the metal sintering through the passivation layer, while forming a disordered conductive zone at the Ag bulk-glass interface, resulting in an increase in contact resistance. For example, the TOPCon (Tunnel Oxide Passivated Contact) cell (i.e. passivated contact cell), the isolated grain structure formed after sintering of the existing silver paste is difficult to establish an effective conductive network.

[0069] Therefore, the current metal / semiconductor interface at least has the following problems: high contact resistance (passivation layer penetration and discrete metal particle contact) and passivation damage (composite loss caused by excessive corrosion of glass frit).

[0070] Based on the above-mentioned traditional technology, taking the silver electrode as an example of the metal electrode, the embodiments of the present application propose to construct the conductive sub-region of the silver-glass phase interface, and to solve the above-mentioned problems by regulating the crystal growth of the interface microstructure and the glass phase. It should be noted that the beneficial effects brought about by the embodiments of the present application or the technical problems solved are not limited to this one, but also other implicit or related problems, which can be referred to the description of the following embodiments.

[0071] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes can not be described again in some examples. The embodiments of the present application will be described below with reference to the drawings. Since the metal-semiconductor contact structure of the embodiments of the present application is applied to a solar cell (for example, applied to a TOPCon cell), the metal-semiconductor contact structure and its preparation method will be introduced when the solar cell of the embodiments of the present application is introduced below, and the metal-semiconductor contact structure and its preparation method will not be described again.

[0072] In one exemplary embodiment, the embodiments of the present application provide a solar cell with a metal-semiconductor contact structure. As shown in Figure 1 Figure 1 is a structural schematic diagram of a solar cell of an embodiment of the present application, which comprises:

[0073] a silicon substrate 100;

[0074] a semiconductor layer 200, a passivation layer 400 arranged on the surface of the silicon substrate 100 in sequence;

[0075] a metal electrode 300, the metal electrode 300 is in physical contact with the semiconductor layer 200 after penetrating the passivation layer 400.

[0076] It can be understood that the metal electrode 300 and the semiconductor layer 200 in physical contact form a metal-semiconductor contact structure 1. Wherein, the physical contact refers to the direct contact between the structure of the metal electrode and the structure of the semiconductor layer.

[0077] Wherein, the semiconductor layer 200 can be arranged on the light-receiving surface and / or the back surface of the silicon substrate 100, and optionally, the metal-semiconductor contact structure 1 can also be arranged on the light-receiving surface and / or the back surface of the silicon substrate 100. As shown in Figure 1 , the semiconductor layer 200 comprises a first semiconductor layer 201 arranged on the light-receiving surface of the silicon substrate 100 and a second semiconductor layer 202 arranged on the back surface of the silicon substrate 100; the passivation layer 400 comprises a first passivation layer 401 arranged on the side of the first semiconductor layer 201 away from the silicon substrate 100, and a second passivation layer 402 arranged on the side of the second semiconductor layer 202 away from the silicon substrate 100; the metal electrode 300 comprises a first metal electrode 301 in contact with the first semiconductor layer 201, and a second metal electrode 302 in contact with the second semiconductor layer 202. Wherein, the first semiconductor layer 201 and the first metal electrode 301 in contact form a metal-semiconductor contact structure 1 located on the light-receiving surface of the silicon substrate 100. The second semiconductor layer 202 and the second metal electrode 302 in contact form a metal-semiconductor contact structure 1 located on the back surface of the silicon substrate 100. ​

[0078] It should be noted that the metal electrode 300 can also include a metal block, the metal block has the same kind of metal element as the metal electrode 300, and in some embodiments, the metal block can be a conductive metal block. It can be understood that the metal block can refer to a large-area metal block left in the surface layer during the sintering process. Exemplarily, taking an electrode paste containing 80-90% of metal elements, 10-20% of glass body, and 5% of organic matter as an example, during the sintering process, the organic matter volatilizes, the glass body sinks and corrodes silicon nitride, and then only a large-area metal block is left in the surface layer; alternatively, the metal block can include but is not limited to a silver block, a copper block, a tin block, and the like.

[0079] The following further describes the metal semiconductor contact structure 1 of the embodiments of the present application by taking the metal semiconductor contact structure 1 located on the light-receiving surface of the silicon substrate 100 as an example. As shown in Figure 2 and Figure 3 shown, Figure 2 is Figure 1 an enlarged schematic view of the structure at A in FIG. 1, and is also a structural schematic view of the metal semiconductor contact structure 1 of the embodiments of the present application, Figure 3 is a structural schematic view of the conductive aggregate 121 in the metal semiconductor contact structure of the embodiments of the present application.

[0080] As shown in Figure 2 , the metal semiconductor contact structure 1 includes a first metal electrode and a first semiconductor layer 201 in contact with each other, the first metal electrode 301 has a metal element, and the first semiconductor layer 201 has a semiconductor element and a doping element for doping the semiconductor layer. The contact interface 13 between the first metal electrode 301 and the first semiconductor layer 201 has a conductive structure 12, and the conductive structure 12 includes a conductive aggregate 121 extending towards the first semiconductor layer 201 close to the first metal electrode 301. Among them, the conductive aggregate 121 can significantly improve the transmission efficiency of electrons.

[0081] Further, as shown in Figure 2As shown, the first metal electrode 301 may further include a metal block 110, which has the same type of metal element as the first metal electrode 301. In this embodiment, the conductive aggregate 121 can bridge the surface metal block 110 and the metal particles 15 encapsulated in the glass phase 14, forming a conductive path across the interface barrier between the metal block 110 and the glass phase, thereby establishing an effective conductive network (e.g., the conductive aggregate and the metal particles form a conductive network), improving the interface conductivity, reducing the contact resistivity, reducing the series resistance, and increasing the fill factor (FF), thus improving efficiency. The above-mentioned metal-semiconductor contact structure 1, by forming a conductive structure 12 at the interface where the first metal electrode 301 contacts the first semiconductor layer 201, improves the interface conductivity, reduces the contact resistance between the first metal electrode 301 and the first semiconductor layer 201, and improves the electron transport efficiency.

[0082] The first metal electrode 301 contains a metal element, meaning that the material corresponding to the metal element is the main component of the first metal electrode 301. For example, when the first metal electrode 301 is a silver electrode, the main component of the first metal electrode 301 is silver. Since the first metal electrode 301 is usually processed by screen printing of electrode paste, and the electrode paste includes glass frit and organic carrier in addition to metal powder, the final first metal electrode 301 may contain not only metal elements as the main component, but also other components that were not completely decomposed in the electrode paste.

[0083] Regarding the first semiconductor layer 201 having semiconductor elements and doping elements for doping the semiconductor layer, it can refer to the fact that the first semiconductor layer 201 has a material corresponding to the semiconductor element as its main component. For example, when the semiconductor element is silicon and the first semiconductor layer 201 is a PN junction region, the main component of the first semiconductor layer 201 is a silicon film layer corresponding to silicon. This PN junction region can be a diffused silicon layer formed by diffusing doping elements of a different type to the silicon substrate 100, or it can be a crystalline silicon layer doped with doping elements formed on the silicon substrate 100 through in-situ doping. The doping element can be, for example, phosphorus or boron, indicating that a certain concentration of doping elements can be added when the main component is silicon.

[0084] In some embodiments, such as Figure 2 As shown, the conductive structure 12 also includes a first conductive crystal 122, which is in contact with the first metal electrode 301. The first conductive crystal 122 includes a crystal formed by the crystallization of metal elements. The conductive aggregate 121 extends from the first conductive crystal 122 toward the first semiconductor layer 201.

[0085] In the first conductive crystal 122 contacts the first metal electrode 301, the first conductive crystal 122 can contact the metal block 110, and the conductive aggregate 121 can contact the metal block 110 through the first conductive crystal 122 and extend to the first semiconductor layer 201 through the glass phase 14, so that the conductive aggregate 121 can bridge the metal block 110 and the metal particles 15 wrapped in the glass phase 14, form a conductive path across the metal block 110 and the glass phase interface barrier, and thus improve the interface conductivity, reduce the contact resistance, reduce the series resistance, improve the fill factor, and significantly improve the transmission efficiency of the electrons.

[0086] In one embodiment, the conductive aggregate 121 includes an aggregate formed by the first conductive crystal 122. Specifically, the conductive aggregate 121 can be formed by the first conductive crystal 122.

[0087] In the above structure, the conductive structure 12 includes not only the first conductive crystal 122 contacting the metal block 110, but also the conductive aggregate 121 extending from the first conductive crystal 122 and growing into the first semiconductor layer 201. Since the first conductive crystal 122 includes a crystal formed by crystallization of a metal element, the conductive crystal 122 formed by crystallization of the metal element has the characteristics of higher purity, lower resistance, and better carrier transmission capability. Since the conductive aggregate 121 is formed by the first conductive crystal 122, the conductive aggregate can conduct with the metal particles 15 wrapped in the glass phase 14 to form a conductive network, so that the contact resistance is significantly reduced. The embodiments of the present application enhance the electron transmission efficiency and optimize the contact performance of the first metal electrode 301 and the first semiconductor layer 201 by the cooperation of the first conductive crystal 122 and the conductive aggregate 121, and thus improve the performance index of the solar cell.

[0088] In one possible implementation, as shown in FIG. 1, Figure 2 The metal-semiconductor contact structure 1 can further include a second conductive crystal 123 located on the surface of the first semiconductor layer 201. The second conductive crystal 123 includes a crystal formed by crystallization of a metal element. Since the second conductive crystal 123 is located on the surface of the first semiconductor layer 201, it cooperates with the metal particles 15 distributed in the glass phase 14 to form a carrier transport path of the photo-generated carriers at the contact interface 13 of the metal-semiconductor contact structure 1 through the conductive contact with the first semiconductor layer 201. The photo-generated carriers generated in the silicon substrate 100 can be transported through the second conductive crystal 123 in direct contact with the first semiconductor layer 201.

[0089] In one embodiment, the first metal electrode 301 comprises one or more of silver electrode, copper electrode or tin electrode. Optionally, the first semiconductor layer 201 comprises a doped silicon layer or an intrinsic silicon layer, wherein the doped silicon layer comprises one of a doped amorphous silicon layer, a doped polycrystalline silicon layer or a crystalline silicon layer doped by thermal diffusion, and the intrinsic silicon layer comprises an intrinsic amorphous silicon layer, a hydrogenated amorphous silicon layer or an intrinsic polycrystalline silicon layer. For example, in a passivated contact solar cell, the first semiconductor layer 201 can be a doped silicon layer, such as a doped amorphous silicon layer or a PN junction region (the PN junction region can be a diffusion silicon layer formed on the silicon substrate 100 by high temperature diffusion). Optionally, the semiconductor element in the first semiconductor layer 201 can be silicon element. For example, the silicon substrate 100 is an N-type silicon substrate 100, the first metal electrode 301 is a silver electrode, and the first semiconductor layer 201 is a PN junction region formed by boron diffusion to the N-type silicon substrate 100. The above metal-semiconductor contact structure 1 is a contact structure of silver electrode and PN junction. In the conductive structure 12 at the contact interface 13, the conductive structure 12 can comprise a conductive aggregate 121 and a first conductive crystalline 122, the conductive aggregate 121 is an aggregate formed by aggregation of the first conductive crystalline 122, and the first conductive crystalline 122 is a crystalline formed by crystallization of silver element, i.e. a crystalline form of silver element.

[0090] Further combining Figure 3 As shown, in the metal-semiconductor contact structure 1 of the embodiments of the present application, the conductive aggregate 121 comprises a crystalline main chain 1211 and a crystalline side chain 1212 extending from the crystalline main chain 1211 in a direction different from the growth direction of the crystalline main chain 1211. In the embodiments of the present application, the crystalline main chain 1211 and the side chain 1212 laterally grown from the crystalline main chain 1211 make the conductive aggregate 121 as a whole in a form of arborization structure. Compared with the conductive aggregate 121 (e.g. a rod-shaped conductive aggregate 121) grown in only a single direction, the arborization conductive aggregate 121 can provide more transport channels, and due to the more divergent structure form, the arborization conductive aggregate 121 is also beneficial to increase the contact probability of the conductive aggregate 121 with other conductive materials (e.g. metal particles 15) around, so as to establish an effective conductive network, and comprehensively improve the enhancement capability of the conductive aggregate 121 to the electron transport efficiency from multiple aspects, and significantly improve the electron transport efficiency. It can be understood that the first conductive crystalline can be a chain-shaped conductive crystalline formed by guiding the metal atoms to precipitate preferentially along the glass phase / metal interface.

[0091] In one embodiment, the maximum extension width of the conductive aggregate is 5 nm to 200 nm, and the maximum extension length of the conductive aggregate is 10 nm to 500 nm. In the embodiment, the maximum extension width of the conductive aggregate 121 can be 5 nm to 200 nm, and the maximum extension length of the conductive aggregate 121 can be 10 nm to 500 nm. The conductive aggregate 121 with the above size range can establish an effective conductive network, and the transmission capacity of the carrier particles can be improved by forming the high-purity metal single-element crystal aggregate.

[0092] For example, the maximum extension width of the conductive aggregate 121 is 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, or 200 nm. Alternatively, the maximum extension length of the conductive aggregate 121 is 10 nm, 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm.

[0093] Further, taking the silver electrode as an example, the conductive aggregate can be a nanoscale continuous crystal chain formed by partial metal atoms diffusing along the glass phase to the surface Ag block, and the maximum extension width of the nanoscale continuous crystal chain perpendicular to the Ag-Si contact interface can be 5 nm to 200 nm, and the maximum extension length can be 10 nm to 500 nm (the tangent direction of the growth point of the continuous crystal chain on the Ag block is the width extension direction, and the normal direction is the length extension direction). The conductive aggregate can bridge the surface Ag block and the micron-sized silver particles in the glass phase, and form a conductive path across the Ag block and the glass phase interface barrier.

[0094] In some embodiments, as Figure 2 and Figure 3As shown, the metal-semiconductor contact structure has a first conductive region 1a and a second conductive region 1b, the second conductive region 1b has a conductive structure 12, and the first conductive region 1a has a glass phase 14 and metal particles 15, the glass phase 14 is formed by sintering of a glass frit, the glass frit is in contact with the first semiconductor layer 201 and ablates part of the passivation layer on the first semiconductor layer 201; wherein the metal particles 15 form a direct conductive contact with the first semiconductor layer 201 through the ablated part of the passivation layer; the metal particles 15 and the conductive aggregate 121 have the same kind of metal elements. In the embodiment of the present application, the second conductive region 1b is introduced, and the conductive structure 12 of the second conductive region 1b includes a conductive aggregate 121 formed by aggregation of first conductive crystalline bodies 122, thereby significantly improving the transmission efficiency of electrons. Exemplarily, the conductive aggregate 121 can be in conduction with the metal particles 15 in the first conductive region 1a to form a conductive network, improve the interface conductive performance, reduce the contact resistivity, reduce the series resistance, improve the FF, and thus improve the efficiency.

[0095] In the first conductive region 1a, the glass phase 14 is in contact with the first semiconductor layer 201 but does not corrode the first semiconductor layer 201, which can be ensured by reducing the sintering temperature of the glass frit and the like to ensure that the glass phase 14 cannot reach a state of large-area corrosion or cannot corrode the first semiconductor layer 201. Through the first conductive region 1a, the combination of the glass phase 14 and the metal particles 15 can effectively ablate the passivation layer, reduce the interface resistance, and enhance the conductivity. The first conductive region 1a in the embodiment of the present application can effectively ablate part of the passivation layer between the metal block and the semiconductor layer, improve the interface conductive performance, and directly contact the metal block with the glass frit for conduction by means of the etching effect of the high-fluidity glass frit while maintaining the integrity of the passivation layer.

[0096] Compared with the first conductive region 1a, the conductive aggregate 121 and the first conductive crystal 122 of the second conductive region 1b have the same metal element as the metal particles 15 of the first conductive region 1a, but the metal particles 15 are simple substances formed by the metal element (for example, the metal particles 15 are micron-level silver particles when the metal element is silver), which have a lower resistivity and a good carrier transport capacity. However, compared with the metal particles 15 formed by the same metal element, the conductive aggregate 121 and the first conductive crystal 122 have a higher purity, a stronger carrier transport capacity, and a lower resistance because the conductive aggregate 121 and the first conductive crystal 122 are obtained by crystallization (for example, the first conductive crystal 122 is a silver crystal and the conductive aggregate 121 is a nanometer-level continuous crystal chain formed by directional diffusion of part of metal atoms along the glass phase to the surface Ag block when the metal element is silver). In addition, the metal particles 15 in the first conductive region 1a are dispersed in the glass phase 14 with a higher resistivity, while the second conductive crystal 123 capable of contacting the first semiconductor layer 201 is more dispersedly distributed on the first semiconductor layer 201, which can be seen from the schematic diagram of FIG. 2. This structural feature makes the resistivity of the second conductive crystal 123 lower, which is beneficial to further improve the transport capacity of the carriers. Figure 2

[0097] As can be seen from the above analysis, the first conductive region 1a can effectively ablate part of the passivation layer between the metal block 110 and the first semiconductor layer 201, and improve the interface conductive performance. With the etching effect of the high-flow glass frit, the metal block 110 is directly contacted with the glass phase to conduct electricity under the premise of maintaining the integrity of the passivation layer, thereby reducing the interface resistance and enhancing the conductivity. The conductive aggregate 121 formed by the aggregation of the first conductive crystal 122 in the second conductive region 1b is in conductive connection with the metal particles 15 distributed in the glass phase 14 to form a conductive network, and the contact resistance is significantly reduced. Among them, the second conductive region 1b can improve the interface conductive performance, reduce the contact resistivity, reduce the series resistance, and improve the FF, thereby significantly improving the electron transport efficiency. The embodiments of the present application can solve the problem of high contact resistance caused by the contact of the passivation layer penetration and the dispersed metal particles through the complementary cooperation of the first conductive region 1a and the second conductive region 1b, and can also cope with the passivation damage (composite loss caused by excessive corrosion of the glass phase). In the case of ensuring that the structure of the contact interface has a high integrity, the contact resistance is significantly reduced, and the electron transport efficiency is improved, thereby improving the contact performance of the metal-semiconductor contact structure 1, and finally reflecting on the improvement of the photoelectric conversion efficiency and other electrical performance indicators of the solar cell.

[0098] ​In one of the embodiments, the conductive aggregate 121 is wrapped by the glass phase 14, and part of the conductive aggregate 121 is in contact with part of the metal particles 15. In the embodiments of the present application, the contact interface 13 between the first metal electrode 301 and the first semiconductor layer 201 has a first conductive region 1a and a second conductive region 1b, the first conductive region 1a includes the glass phase 14 and the metal particles 15 wrapped in the glass phase 14, and the second conductive region 1b includes the conductive structure 12, wherein the conductive structure 12 includes the first conductive crystal 122 and the conductive aggregate 121 wrapped in the glass phase 14. The conductive aggregate 121 can form a conductive path across the cross-sectional barrier of the metal block 110 and the glass phase by being in contact with the metal particles 15 distributed in the glass phase material (the glass phase 14), and forms a conductive network with the metal particles 15 to enhance the efficiency of electron transmission.

[0099] The metal-semiconductor contact structure of the embodiments of the present application can significantly reduce the contact resistance. For example, for a TOPCon cell, the contact resistance of the metal-semiconductor contact structure of the embodiments of the present application is reduced from the conventional 5-7 mΩ·cm² (average 6.37 mΩ·cm²) to 4-6 mΩ·cm² (average 5.11 mΩ·cm²), with a reduction of 30%. The conductive aggregates formed by the aggregation of the conductive crystals and the metal particles in the glass frit form a conductive network to improve the interface conductivity, reduce the contact resistance, reduce the series resistance, improve the FF, and thus improve the efficiency. In addition, the combination of the glass frit and the metal particles can effectively ablate the passivation layer, reduce the interface resistance, and enhance the conductivity. The embodiments of the present application introduce the second conductive region and its structure, the conductive aggregate is formed by the aggregation of the conductive crystals, and the main chain and side chain structure is formed to significantly improve the transmission efficiency of electrons.

[0100] The preparation method of the metal-semiconductor contact structure 1 is further described below.

[0101] The preparation method of the metal-semiconductor contact structure 1 includes the following steps:

[0102] Printing an electrode paste on the first semiconductor layer 201; the electrode paste includes a glass frit, metal particles, and an organic carrier;

[0103] Sintering the electrode paste at high temperature to form an electrode precursor on the first semiconductor layer 201, the electrode precursor includes a glass phase 14, and metal particles 15 and conductive aggregates 121 wrapped in the glass phase 14;

[0104] Light injection is performed on the electrode precursor to form a first metal electrode 301, so as to form a metal-semiconductor contact structure 1 between the first metal electrode 301 and the first semiconductor layer 201.

[0105] In the application, the metal-semiconductor contact structure 1 is made by configuring the slurry formula and corresponding sintering curve (e.g. sintering-light injection curve); the electrode slurry can include glass frit, metal particles and organic carrier; for example, for silver electrode, the slurry formula can include but is not limited to: spherical Ag particles (D50=0.3-1.2μm, specific surface area 0.3~0.8m² / g) are selected, SPAN value ≤1.5, which can ensure high conductivity and printing suitability; the glass powder is PbO(40%)-B2O3(35%)-SiO2(15%)-TeO2(10%).

[0106] Further, the electrode slurry can be printed on the first semiconductor layer 201 to fix the electrode slurry on the first semiconductor layer 201, for example, the second electrode is printed on the second passivation layer corresponding to the n-type polysilicon region, and is dried in a drying furnace with a temperature of 100-300℃; and the p-type polysilicon region is printed on the first passivation layer. ++ The emitter prints the first electrode.

[0107] In the process of high-temperature sintering of the electrode slurry, the crystal growth and glass phase of the interface microstructure can be controlled, for example, the silver grains present fractal crystallization in the glass phase, thereby constructing the conductive partition (first conductive area 1a and second conductive area 1b) of the metal block-glass phase interface. In the embodiment of the application, the electrode precursor is formed on the first semiconductor layer 201 by high-temperature sintering of the electrode slurry, the electrode precursor includes glass phase 14, and metal particles 15 and conductive aggregates 121 wrapped in the glass phase 14. Finally, the first metal electrode 301 is formed by light injection on the electrode precursor, so that the metal-semiconductor contact structure 1 is formed between the first metal electrode 301 and the first semiconductor layer 201.

[0108] In one embodiment, the high-temperature sintering of the electrode slurry includes a first heating stage, a second heating stage and a cooling stage; the peak temperature of the first heating stage is 300℃~400℃; the peak temperature of the second heating stage is 750℃~850℃; and the cooling stage includes gradient cooling.

[0109] Specifically, the application regulates the crystal growth of the interface microstructure through a sintering curve including a heating stage and a cooling stage. Exemplarily, the first heating stage can be heating the solidified electrode, wherein the peak temperature of the first heating stage can be 300-400°C, and the softening temperature of the glass body in the electrode paste is about 300-400°C. Through the first heating stage, the electrode paste can be kept in a softened state for a long distance in the furnace body, so that the freshly printed electrode paste is uniformly distributed on the surface of the battery, and the metal particles and conductive crystals in the electrode paste are uniformly distributed in the paste. Optionally, the peak temperature of the first heating stage can be 300°C, 320°C, 340°C, 360°C, 380°C or 400°C.

[0110] The second heating stage can refer to heating the softened electrode, so that the crystal grains are gathered on the metal block, for example, the silver crystal grains are slowly gathered on the silver block. Optionally, the peak temperature of the second heating stage can be 750°C, 760°C, 780°C, 800°C, 810°C, 830°C or 850°C. The cooling stage can be gradient cooling to slowly grow the crystal grains on the metal block, for example, the silver crystal grains are slowly crystallized and grown on the silver block, thereby forming the conductive aggregate 121, so as to ensure that the prepared conductive structure 12 meets the scope of the application.

[0111] Further, in one of the embodiments, the first heating stage can include the following processes:

[0112] heating to a first preset temperature, the first preset temperature being 250-350°C;

[0113] after heating from the first preset temperature to the peak temperature of the first heating stage for a first preset time, cooling to the first preset temperature, wherein the first preset time is 5-10s.

[0114] Specifically, the first heating stage can include heating the solidified first electrode and the second electrode, wherein the peak temperature of the first heating stage is 300-400°C, the first preset temperature is 250-350°C, and the first preset time is 5-10s. The application embodiment ensures that the electrode paste is kept in a softened state for a long distance in the furnace body by heating from the first preset temperature to the peak temperature of the first heating stage for a first preset time and then cooling to the first preset temperature, so that the freshly printed electrode paste is uniformly distributed on the surface of the battery, and the metal particles and conductive crystals in the electrode paste are uniformly distributed in the paste. Optionally, the first preset temperature can be 250°C, 260°C, 280°C, 300°C, 310°C, 320°C, 330°C or 350°C. The first preset time can be 5s, 6s, 8s or 10s.

[0115] In some embodiments, the second heating stage includes the following processes:

[0116] heating to a second preset temperature, the second preset temperature being 700-800℃;

[0117] after heating from the second preset temperature to a peak temperature of the second heating stage within a second preset time, and then cooling to the second preset temperature, wherein the second preset time is 5-10s.

[0118] Specifically, the second heating stage can refer to heating the softened electrode. By heating to the second preset temperature, and then after heating from the second preset temperature to a peak temperature of the second heating stage within a second preset time, and then cooling to the second preset temperature, the crystal grains (e.g., conductive crystalline bodies) can be slowly gathered on the metal block, wherein the second preset temperature is 700-800℃, and the second preset time is 5-10s. Optionally, the second preset temperature can be 700℃, 710℃, 720℃, 730℃, 740℃, 750℃, 760℃, 770℃, 780℃ or 800℃, and the second preset time can be 5s, 6s, 7s, 8s, 9s or 10s.

[0119] In one possible implementation, the gradient cooling includes the following processes: starting from the second preset temperature, cooling for 3-10s, and the temperature drop rate is 130-160℃ / s; after being reduced to 300-400℃, slowly cooling at a rate of 50-100℃ / s.

[0120] Specifically, by the gradient cooling, the crystal grains can be slowly crystallized and grown on the metal block. Based on the second heating stage and the cooling stage in the embodiments of the present application, the conductive aggregates can be formed.

[0121] The gradient cooling includes starting from the second preset temperature, wherein the cooling time is 3-10s, and the temperature drop rate is 130-160℃ / s. Exemplarily, the cooling time can be 3s, 5s, 7s, 9s or 10s. Optionally, the temperature drop rate can be 130℃ / s, 140℃ / s, 150℃ / s or 160℃ / s. Further, the gradient cooling can further include slowly cooling at a rate of 50-100℃ / s after being reduced to 300-400℃. Optionally, the slowly cooling rate can be 50℃ / s, 60℃ / s, 70℃ / s, 80℃ / s, 90℃ / s or 100℃ / s.

[0122] In one exemplary embodiment, the step of injecting light includes:

[0123] heating the electrode precursor once, and the peak temperature of the once heating is 180-620℃;

[0124] The electrode precursor is subjected to secondary heating and illumination. The peak temperature of the secondary heating is 80℃~320℃, and the energy density of the illumination is 12kW / m³. 2 ~120kW / m 2 The wavelength of the light is a continuous spectral band of 500nm to 1100nm.

[0125] Specifically, after the electrode precursor is fabricated, it can be photoinjected. Through photoinjection and the heating operation of the photoinjection process, hydrogen atoms can diffuse from the passivation film to recombination centers with high defect state density, thereby improving the passivation effect at these recombination centers. This is beneficial for further improving the open-circuit voltage and fill factor of the solar cell with this metal-semiconductor contact structure, and thus improving the photoelectric conversion efficiency.

[0126] Furthermore, the light injection step may include: first heating the electrode precursor, with a peak temperature of 180℃~620℃; second heating the electrode precursor and then irradiating it, with a peak temperature of 80℃~320℃ and an energy density of 12kW / m². 2 ~120kW / m 2 The illumination wavelength is a continuous spectral band of 500nm to 1100nm. The light injection step controls the heating and illumination conditions within the above range, which can achieve a good passivation effect and avoid the glass material corroding the first semiconductor layer due to excessive heating temperature.

[0127] In summary, this application guides metal atoms to preferentially precipitate along the glass / metal interface by controlling the sintering light injection curve and the glass phase composition, thereby forming chain-like conductive crystals (conductive aggregates).

[0128] The other structural film layers of the solar cell in the embodiments of this application will be further described below.

[0129] See Figure 1 In the solar cell of this application embodiment, the silicon substrate 100 has an N-type conductivity type or a P-type conductivity type, for example, the silicon substrate 100 is an N-type silicon wafer. The light-receiving surface of the silicon substrate 100 has a textured structure, such as a pyramid-shaped textured structure. By setting the textured structure, it is beneficial to reduce the reflectivity of the surface of the silicon substrate 100 and increase the refraction and scattering of light inside the silicon substrate 100.

[0130] The first semiconductor layer 201 on the light-receiving surface of the silicon substrate 100 can be a diffusion layer formed by diffusing and incorporating N-type or P-type doping elements into the silicon substrate 100, or a doped polysilicon layer or a doped amorphous silicon layer formed on the light-receiving surface of the silicon substrate 100 by deposition. For example, the first semiconductor layer 201 of the silicon substrate can be a phosphorus diffusion layer or a boron diffusion layer, so that a PN junction is formed between the N-type silicon wafer and the first semiconductor layer 201, and when the silicon substrate 100 has a textured structure, the surface of the first semiconductor layer 201 also has the same textured structure.

[0131] For the first semiconductor layer 201 with a textured structure described above, the textured structure is a pyramid structure. Further, on the side of the first semiconductor layer 201 away from the silicon substrate 100, there is also a first passivation layer 401. The first passivation layer 401 includes one or a combination of an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As shown in the solar cell, Figure 1 As shown in the solar cell, the first passivation layer 401 includes an aluminum oxide passivation layer 4011 disposed close to the first semiconductor layer 201 and a reflection-reducing layer 4012 with a reflection-reducing function disposed away from the first semiconductor layer 201. The first metal electrode 301 penetrates the reflection-reducing layer 4012 and the aluminum oxide passivation layer 4011 in sequence and contacts the first semiconductor layer 201.

[0132] The above is an introduction to the structure of the film layers on the light-receiving surface of the solar cell. It can be understood that according to the structural characteristics of different types of solar cells, other film layers with other structural characteristics can also be provided on the light-receiving surface and the back surface of the solar cell. For example, when the film layer on the back surface has a second metal electrode 302 in contact with the first semiconductor layer 201, the metal-semiconductor contact structure 1 described above can also be used. In addition, the method of forming the structure film layer can also use the conventional method of the prior art. For example, the silicon substrate 100 with a textured structure is obtained by texturing, the first semiconductor layer 201 with a PN junction is obtained by thermal diffusion doping of the doping elements, the first passivation layer 401 is obtained by ALD or PECVD process, and so on. In addition, according to the formation of the plating layer, borosilicate glass layer or phosphosilicate glass layer in the process of forming each structure film layer, the conventional method of polishing, cleaning, etc. can be used, which is not limited in the present application.

[0133] Taking a TOPCon solar cell as an example, as shown in Figure 1 As shown in the solar cell, in the direction away from the silicon substrate 100, the back surface of the silicon substrate 100 is sequentially provided with a tunneling passivation layer 500, a second semiconductor layer 202, a second passivation layer 402, and a patterned second metal electrode 302, and the second metal electrode 302 penetrates the second passivation layer 402 and contacts the second semiconductor layer 202.

[0134] The material of the tunneling passivation layer 500 can include a plurality of dielectric materials, such as at least one of silicon oxide, amorphous silicon, polysilicon, silicon carbide. Specifically, the tunneling passivation layer 500 can be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation performance, can minimize the recombination loss of the semiconductor substrate surface minority carriers, and is a thin film with excellent durability to subsequent high-temperature processes. The tunneling passivation layer 500 acts as a potential barrier for electrons or holes, and can be combined with a polysilicon layer to prevent minority carriers from passing through. The tunneling passivation layer 500 can also have a pinhole channel effect, allowing free movement of carriers within the solar cell, and selective passage of majority carriers through heavy-doped polysilicon, which helps to reduce the recombination loss of minority carriers. The second semiconductor layer 202 is a phosphorus-doped polysilicon layer, and the second passivation layer 402 is a passivation layer, the material of which can be selected from any one of a silicon oxide layer, an aluminum oxide layer, a silicon carbide layer, a silicon nitride layer, or a silicon oxynitride layer, or any combination of materials.

[0135] As shown in FIG. 1, the solar cell is taken as an IBC solar cell as an example. The solar cell includes: Figure 4

[0136] a silicon substrate 100;

[0137] a tunneling passivation layer 500, a first semiconductor layer 201, and a first passivation layer 401 arranged in sequence on an N-type conductive region of a back surface of the silicon substrate 100, and a tunneling passivation layer 500, a second semiconductor layer 202, and a second passivation layer 402 arranged in sequence on a P-type conductive region of the back surface of the silicon substrate 100, and the first semiconductor layer 201 has an N-type doping element, and the second semiconductor layer 202 has a P-type doping element;

[0138] a first metal electrode 301 in ohmic contact with the first passivation layer 401 and the first semiconductor layer 201 of the N-type conductive region, so that the first metal electrode 301 and the first semiconductor layer 201 form a first metal-semiconductor contact structure 1;

[0139] a second metal electrode 302 in ohmic contact with the second passivation layer 402 and the second semiconductor layer 202 of the P-type conductive region, so that the second metal electrode 302 and the second semiconductor layer 202 form a second metal-semiconductor contact structure 1.

[0140] ​The silicon substrate 100 has an N-type or P-type conductivity, for example, the silicon substrate 100 is a P-type silicon substrate 100. The light-receiving surface of the silicon substrate 100 has a textured structure, for example, a pyramidal textured structure. By providing the textured structure, the reflectivity of the surface of the silicon substrate 100 is reduced, and the refraction and scattering of light in the silicon substrate 100 are increased. In addition, other structure films can be provided on the light-receiving surface of the silicon substrate 100 according to actual needs. For example, a third passivation layer 403 is provided on the light-receiving surface of the silicon substrate 100.

[0141] In the embodiments of the present application, the solar cell can also be a perovskite-silicon stacked solar cell, wherein the perovskite cell serves as a top cell, any one of the above-mentioned various solar cells, and only the metal-semiconductor contact structure with a conductive structure needs to be provided on the back surface of the crystalline silicon bottom cell.

[0142] In addition, the embodiments of the present application also provide a photovoltaic module, which comprises the above-mentioned solar cell. By connecting and packaging a plurality of the above-mentioned solar cells in series and / or parallel, a photovoltaic module is formed.

[0143] The metal-semiconductor contact structure and its preparation method, solar cell, and photovoltaic module of the present application will be further described below in conjunction with more specific embodiments. In addition, the alkali solution and the like used in the following embodiments can be obtained by commercial purchase. The embodiments of the present application provide a solar cell with a metal-semiconductor contact structure, and the preparation method is as follows:

[0144] (1) Cleaning and texturing: In a tank device, the surface of the silicon wafer is polished and cleaned by using the improved RCA cleaning method to remove metal ions and sawtooth damage on the surface. At the same time, anisotropic etching of n-type silicon wafers is performed by using a low-concentration alkali solution to form a textured structure;

[0145] (2) Boron diffusion: The polished and cleaned silicon wafer is placed in a horizontal boron diffusion furnace tube, and impurity source gas BCl3 and reaction gas oxygen are introduced at 800-1050°C for boron diffusion to form a p+ emitter;

[0146] (3) BSG (borosilicate glass) removal and back etching:

[0147] BSG removal: HF is used to etch the lower surface and the edge of the diffused silicon wafer to remove the BSG on the lower surface and the edge, so that the upper and lower surfaces of the silicon wafer are insulated from each other.

[0148] Backside etching: the structure etching of the backside of the silicon wafer is realized by using alkali solution. Under the action of additives, the front side is protected by BSG and is not etched, the backside directly contacts with the alkali solution to realize surface etching light; then, the process technology is completed after cleaning by using alkali and hydrogen peroxide solution (or ozone solution) and acid pickling (hydrochloric acid, hydrofluoric acid or mixed solution of the two).

[0149] (4) Second dielectric layer and n-type polysilicon growth: the structure obtained after alkali polishing is placed in an LPCVD (Low Pressure Chemical Vapor Deposition), high-purity oxygen is introduced to grow the first dielectric layer at 400-650°C, then high-purity SiH4 is introduced to grow the intrinsic polysilicon layer at 450-700°C, then the above structure is placed in a phosphorus diffusion furnace tube to diffuse POCl3 at 850-1050°C to form an n-type polysilicon layer;

[0150] (5) PSG (phosphosilicate glass) removal and etching cleaning: a chain type HF device is used to remove the boron phosphorus silicon glass (BPSG) on the back light surface of the silicon substrate due to phosphorus diffusion, in a tank type device, sodium hydroxide and an additive with a model number of TS40 are used in a volume ratio of 7:1, the temperature is maintained at 80°C, the time is 7 min, and the silicon wafer is cleaned;

[0151] (6) Deposition of passivation layer: ALD (Atomic layer deposition) equipment is used to deposit aluminum oxide as a passivation layer on the light entering surface and the back light surface, PECVD is used to deposit silicon nitride oxide as a passivation layer on the back light surface, and the back light surface aluminum oxide and silicon nitride oxide constitute a first passivation layer; PECVD is used to deposit a silicon oxide, silicon nitride oxide and silicon nitride stack as a passivation layer and an anti-reflection layer on the light entering surface, and the light entering surface aluminum oxide and the silicon oxide, silicon nitride oxide and silicon nitride stack constitute a second passivation layer;

[0152] (7) Metal semiconductor contact structure (obtained by configuring the following paste formula combined with the sintering curve described below).

[0153] (7.1) Sintering formula:

[0154] Ag: spherical Ag particles (D50=0.3-1.2μm, specific surface area 0.3~0.8m² / g) are selected, the SPAN value is ≤1.5, high conductivity and printing suitability are ensured; glass powder: PbO (40%) -B2O3 (35%) -SiO2 (15%) -TeO2 (10%);

[0155] (7.2) The second electrode is printed on the corresponding n-type polysilicon area on the second passivation layer and is dried in a drying furnace with a temperature of 100-300°C;

[0156] (7.3) p ++ Print the first electrode as the emitter;

[0157] (7.4) high-temperature sintering of the electrode paste, the high-temperature sintering step comprising:

[0158] First heating stage: heating the solidified first electrode and the second electrode, the peak temperature of the first heating stage being 300-400℃, the preset temperature being 250-350℃, and the preset time being 5-10s; wherein the softening temperature of the glass body in the electrode paste is about 300-400℃, the freshly printed electrode paste needs to be first evenly distributed on the surface of the battery and the metal conductive crystalline bodies in the electrode paste need to be evenly distributed in the paste, and the electrode paste needs to be kept in a softened state for a long distance in the furnace body;

[0159] Second heating stage: heating the softened electrode, the peak temperature of the second heating stage being 750-850℃, the preset temperature being 700-800℃, and the preset time being 5-10s, which allows the silver grains to slowly gather on the silver block;

[0160] Third gradient cooling: preset temperature gradient cooling in the second stage, time 3-10s, temperature speed reduction 130-160℃ / s, and slow cooling 50-100℃ / s after reducing to 300-400℃. This stage allows the silver grains to slowly crystallize and grow on the silver block.

[0161] The preset temperature in the above can refer to heating from the preset temperature to the peak temperature within the preset time, and then reducing to the preset temperature.

[0162] (7.5) light injection: once heating the electrode precursor, the peak temperature of the once heating being 180℃-620℃;

[0163] twice heating the electrode precursor and performing light irradiation, the peak temperature of the twice heating being 80℃-320℃, the energy density of the light irradiation being 12 kW / m 2 ~120 kW / m 2 , and the wavelength of the light irradiation being a continuous spectrum wavelength band of 500nm-1100nm.

[0164] Different magnifications of scanning electron microscope (SEM) are taken for the metal-semiconductor contact structure in the solar cell of the embodiment, and the SEM images as shown in Figure 5 are obtained, wherein Figure 5 is the SEM image of the contact interface of the metal-semiconductor contact structure at 50K magnification. From Figure 5It can be seen that the first conductive region includes glass frit and metal particles, which can effectively ablate part of the passivation layer between the metal block and the semiconductor layer, and improve the interface conductive performance. With the etching effect of high fluidity glass frit, the metal block is directly in contact with the glass frit for conduction while maintaining the integrity of the passivation layer. The second conductive region includes the first conductive crystal and the conductive aggregate, which enhances the electron transmission efficiency. Among them, by adjusting the sintering light injection curve and the composition of the glass phase, metal atoms can be preferentially precipitated along the glass phase / metal interface to form conductive aggregates (such as chain-like conductive crystals).

[0165] Further, in some embodiments, the above-mentioned SEM images can be obtained by using the following sampling detection process:

[0166] 1. Selecting a battery piece: A finished battery piece or a battery piece obtained by disassembling the assembly can be selected.

[0167] 2. Preprocessing the battery piece: Sampling the selected battery piece can include the following two methods: ① using a sharp object to apply pressure on the edge of the battery piece to form a hidden crack, ensuring that the hidden crack extends along the cross-sectional direction of the metal grid line. ② Using laser cutting on the back of the metal grid line surface, and then breaking along the cutting line to expose the cross section of the metal grid line.

[0168] 3. Sample fixation: Fix the preprocessed battery piece sample on the scanning electron microscope (SEM) test sample table with conductive glue, and use compressed air or nitrogen to clean the sample surface dust.

[0169] 4. SEM observation: Put the sample table with the sample into the SEM chamber, perform vacuum treatment, then start the observation program, and get the corresponding SEM image.

[0170] It should be understood that although each step in the flowchart involved in each of the above embodiments is displayed in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each of the above embodiments can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0171] The technical features of the above embodiments can be combined in any way. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the application.

[0172] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific manner, but should not be construed as limiting the scope of the patent of the present application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A metal-semiconductor contact structure, characterized by, The metal-semiconductor contact structure comprises a metal electrode and a semiconductor layer in contact with each other, the metal electrode comprises a metal element, and the semiconductor layer comprises a semiconductor element and a doping element for doping the semiconductor layer; An electrically conductive structure is formed at the contact interface between the metal electrode and the semiconductor layer, and the electrically conductive structure comprises an electrically conductive aggregate extending from the metal electrode towards the semiconductor layer.

2. The metal-semiconductor contact structure of claim 1, wherein, The electrically conductive structure further comprises a first electrically conductive crystal, the first electrically conductive crystal is in contact with the metal electrode, and the first electrically conductive crystal comprises a crystal formed by crystallization of the metal element. The electrically conductive aggregate extends from the first electrically conductive crystal towards the semiconductor layer.

3. The metal-semiconductor contact structure of claim 2, wherein, The electrically conductive aggregate comprises an aggregate of the first electrically conductive crystal.

4. The metal-semiconductor contact structure of claim 2, wherein, The metal-semiconductor contact structure further comprises a second electrically conductive crystal, the second electrically conductive crystal is located on the surface of the semiconductor layer, and the first electrically conductive crystal comprises a crystal formed by crystallization of the metal element.

5. The metal-semiconductor contact structure according to any one of claims 1 to 4, wherein: The metal electrode comprises a silver electrode, a copper electrode or a tin electrode; and / or The semiconductor element comprises a silicon element; and / or The semiconductor layer comprises a doped monocrystalline silicon layer, a doped polycrystalline silicon layer or an intrinsic silicon layer.

6. The metal-semiconductor contact structure according to any one of claims 1 to 4, wherein The electrically conductive aggregate comprises a crystalline main chain and a crystalline side chain extending from the crystalline main chain in a direction different from the growth direction of the crystalline main chain.

7. The metal-semiconductor contact structure of any of claims 1 to 4, wherein, The maximum extension width of the electrically conductive aggregate is 5 nm to 200 nm, and the maximum extension length of the electrically conductive aggregate is 10 nm to 500 nm.

8. The metal-semiconductor contact structure of any of claims 1 to 4, wherein, The metal-semiconductor contact structure has a first electrically conductive region and a second electrically conductive region, the second electrically conductive region has the electrically conductive structure, the first electrically conductive region has a glass phase and metal particles, the glass phase is formed by sintering of a glass frit, the glass frit is in contact with the semiconductor layer and ablates part of the passivation layer on the semiconductor layer; The metal particles form a direct electrically conductive contact with the semiconductor layer through the ablated part of the passivation layer; and the metal particles and the electrically conductive aggregate have the same kind of metal element.

9. The metal-semiconductor contact structure of claim 8, wherein, The electrically conductive aggregate is wrapped by the glass phase, and part of the electrically conductive aggregate is in contact with part of the metal particles.

10. A method for fabricating a metal-semiconductor contact structure, characterized in that, The metal-semiconductor contact structure is the metal-semiconductor contact structure according to any one of claims 1 to 9, and the method comprises the following steps: Printing an electrode paste on the semiconductor layer; the electrode paste comprises a glass frit, metal particles and an organic carrier; Sintering the electrode paste at high temperature to form an electrode precursor on the semiconductor layer, the electrode precursor comprises a glass phase, and the metal particles and the electrically conductive aggregate wrapped in the glass phase; Performing photo injection on the electrode precursor to form the metal electrode, so as to form the metal-semiconductor contact structure between the metal electrode and the semiconductor layer.

11. The method of claim 10, wherein, The sintering of the electrode paste at high temperature comprises a first heating stage, a second heating stage and a cooling stage; The peak temperature of the first heating stage is 300°C to 400°C; The peak temperature of the second heating stage is 750-850℃; The cooling stage comprises gradient cooling.

12. The method of claim 11, wherein, The first heating stage comprises the following processes: Heating to a first preset temperature, which is 250-350℃; After heating from the first preset temperature to the peak temperature of the first heating stage within a first preset time, which is 5-10s, the temperature is cooled to the first preset temperature.

13. The method of claim 12, wherein, The second heating stage comprises the following processes: Heating to a second preset temperature, which is 700-800℃; After heating from the second preset temperature to the peak temperature of the second heating stage within a second preset time, which is 5-10s, the temperature is cooled to the second preset temperature.

14. The method of claim 13, wherein, The gradient cooling comprises the following processes: Cooling from the second preset temperature, the cooling time is 3-10s, and the temperature decreasing rate is 130-160℃ / s; After decreasing to 300-400℃, the temperature is slowly decreased, and the decreasing rate of the slow decrease is 50-100℃ / s.

15. The method of claim 10, wherein, The step of light injection comprises: Once heating the electrode precursor, the peak temperature of the once heating is 180-620℃; The electrode precursor is secondarily heated to a peak temperature of 80-320 DEG C and irradiated with light having an energy density of 12-120 kW / m 2 , and a wavelength of 500-1100 nm. 2 , and a wavelength of 500-1100 nm.

16. A solar cell, characterized by The solar cell comprises: A metal-semiconductor contact structure, which comprises a metal electrode and a semiconductor layer in contact with each other, the metal electrode has a metal element, the semiconductor layer has a semiconductor element and a doping element for doping the semiconductor layer; an electrically conductive structure is present at the contact interface between the metal electrode and the semiconductor layer, and the electrically conductive structure comprises an electrically conductive aggregate extending towards the semiconductor layer close to the metal electrode; A silicon substrate, the light-receiving surface of the silicon substrate has a textured structure; The metal-semiconductor contact structure is arranged on the light-receiving surface and / or the back surface of the silicon substrate, and the semiconductor layer is arranged close to the silicon substrate.

17. The solar cell of claim 16, wherein The textured structure is a pyramid structure.

18. The solar cell of claim 16, wherein, The solar cell further comprises a passivation layer arranged on the surface of the semiconductor layer away from the silicon substrate, and the metal electrode penetrates the passivation layer and contacts the semiconductor layer.

19. The solar cell of claim 16, wherein, The solar cell comprises: On the light-receiving surface of the silicon substrate, a PN junction region, a first passivation layer and a first metal electrode are arranged in sequence in the direction away from the light-receiving surface, and the PN junction region is a first semiconductor layer; On the back surface of the silicon substrate, a passivation contact structure, a second passivation layer and a second metal electrode are arranged in sequence in the direction away from the back surface, and the passivation contact structure comprises a tunneling passivation layer arranged close to the silicon substrate and a doped silicon layer arranged away from the silicon substrate, the doped silicon layer has the same conductivity type as the silicon substrate, and the doped silicon layer is a second semiconductor layer; The first metal electrode penetrates the first passivation layer and contacts the first semiconductor layer, so that the first metal electrode and the PN junction region form the metal-semiconductor contact structure, and / or the second metal electrode penetrates the second passivation layer and contacts the doped silicon layer, so that the second metal electrode and the doped silicon layer form the metal-semiconductor contact structure.

20. The solar cell of claim 19, wherein, The first semiconductor layer is formed by thermal diffusion of the doping element to the silicon substrate, or the first semiconductor layer is a doped polysilicon layer or a doped amorphous silicon layer deposited on the light-receiving surface of the silicon substrate; and / or, The first passivation layer is one or more of an aluminum oxide layer, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer deposited on the PN junction region; and / or, The tunneling passivation layer is at least one of a silicon oxide layer, an amorphous silicon layer, a polysilicon layer, or a silicon carbide layer; and / or the second passivation layer is one or more of a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer deposited on the second semiconductor layer.

21. The solar cell of claim 16, wherein, The solar cell comprises: a tunneling passivation layer, a first semiconductor layer, a first passivation layer, and a first metal electrode, which are sequentially arranged on an N-type conductive region on the back surface of the silicon substrate; a tunneling passivation layer, a second semiconductor layer, a second passivation layer, and a second metal electrode, which are sequentially arranged on a P-type conductive region on the back surface of the silicon substrate; one of the first semiconductor layer and the second semiconductor layer has an N-type doping element, and the other has a P-type doping element; The first metal electrode penetrates the first passivation layer and contacts the first semiconductor layer, so that the first metal electrode and the first semiconductor layer form the metal-semiconductor contact structure, and / or the second metal electrode penetrates the second passivation layer and contacts the second semiconductor layer, so that the second metal electrode and the second semiconductor layer form the metal-semiconductor contact structure.

22. A photovoltaic module, characterized by, The photovoltaic module comprises the solar cell according to any one of claims 16 to 21.

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