SELF-LOCKING HETERO TURN TRANSISTOR WITH HIGH ELECTRON MOBILITY

Description

[0001] The invention relates to high electronic mobility transistors based on the presence of heterojunctions, and in particular HEMT transistors of the normally blocked type.

[0002] Many electronic applications now require improved performance, especially in embedded electronics for the automotive and land transport sectors, in aeronautics, in medical systems, and in home automation solutions, for example. Most of these applications require high-power switches operating in frequency ranges frequently exceeding one megahertz.

[0003] Historically, power switches have long relied on semiconductor-channel field-effect transistors, most often made of silicon. For lower frequencies, junction transistors are preferred because they can handle higher current densities. However, due to the relatively limited breakdown voltage of each of these transistors, power applications require the use of a large number of transistors in series, or longer transistors, resulting in higher forward resistance. The losses across these series transistors are considerable. both in steady state and in switching mode.

[0004] An alternative for power switches, particularly at high frequencies, is the use of high electron mobility field-effect transistors, also known as heterostructure field-effect transistors. Such a transistor comprises two superimposed semiconductor layers with different band gaps and a bias that leads to the formation of a two-dimensional gas. of electrons with high mobility and high density. For reasons of high voltage and temperature resistance, these transistors are made using semiconductor materials of type III-N, with a wide band gap.

[0005] For certain applications, particularly security applications in with a view to isolating a circuit in case of a malfunction in a control system, We use normally off HEMT transistors, meaning that their switching threshold voltage is the passing state is positive, so the transistor remains blocked in the absence of a control signal.

[0006] Due to the inherently conductive nature of the electron gas layer formed between a source and a drain, it is technologically easier to fabricate a normally conducting heterojunction transistor. However, several fabrication processes have been developed to create normally open or normally blocked heterojunction transistors.

[0007] It is known to fabricate Schottky-type control gates for normally blocked heterojunction transistors. However, such transistors are unsuitable for power electronics due to the high current leakage levels between the gate and drain and the temperature sensitivity of the current / voltage curve. Various fabrication processes have also been developed to create MIS-type gates for normally blocked heterojunction transistors. This structure also allows for control the grid in positive and negative directions to maintain compatibility with the electronicscontrol used for Silicon power components.

[0008] According to one approach, a binary layer of type III nitride and a ternary layer of type III nitride are superimposed to form a gas layer of electrons at the interface between these nitrides. A recess is created by etching in the ternary nitride layer to locally reduce its thickness. When the local thickness of the ternary nitride layer is sufficiently small, for example 2 to 3 nm for AlGaN, the electron gas disappears at the recess. The grid is then formed at the recess.

[0009] The engraving process of the recess is still insufficiently controlled to guarantee a satisfactory thickness of the ternary nitride layer in the recess.

[0010] According to an alternative described in particular in the document 'over 100A operation normally-off AlGaN / GaN hybrid MOS-HFET on Si substrate with high- breakdown voltage byHiroshi Kambayashi et al., published in 'Solid-State Electronics', Volume 54, number 6, in June 2010, Pages 660-664, etching is carried out down to the binary nitride layer. Such a structure makes it possible to obtain a threshold voltage greater than 3V. Such a structure has the disadvantage of locally operating like a MOSFET with degraded charge density and especially mobility, and therefore a high on-state resistance.

[0011] The US2011 / 068371 document describes a high-electron-mobility field-effect transistor, including: a first layer of GaN; a second layer of GaN with P-type doping formed on the first layer of GaN; a third layer of GaN with N-type doping formed on the second layer of GaN so as to form a depleted p / n junction.

[0012] This document does not guarantee complete depletion of the layerP-type doped GaN does not provide good voltage stability or a sufficient electrical barrier. Furthermore, this document raises concerns about dopant diffusion into the electron gas layer, with a significant electrical effect of these dopants on the electron gas layer.

[0013] The paper 'Normally-Off Al2O3 / GaN MOSFET on Silicon Substrate based on Wet-Etching', published by Mrs. Wang et al. on pages 253-256 of the presentations disclosed at the 26th International Symposium on Power Semiconductor Devices & ICs, held from June 15th to 19th, 2014 in Hawaii, describes a MOSFET fabricated on a silicon substrate. Normally-Off operation is achieved by gate indentation using oxidation and wet etching to remove an AlGaN barrier.

[0014] The invention aims to resolve one or more of these drawbacks. The invention thus relates to a high-electron-mobility heterojunction transistor, as defined in claim 1.

[0015] The invention also relates to variants of the appended claims. Those skilled in the art will understand that each of the features of the variants of the dependent claims can be combined independently with the above features, without thereby constituting an intermediate generalization.

[0016] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying drawings, in which: there figure 1 is a cross-sectional view of an example of a high-electron-mobility heterojunction transistor according to the invention; the figures 2 And 3are conduction band diagrams of a transistor according to the invention and of a transistor according to the prior art; the figure 4 is a diagram illustrating an electron density, a conduction band, and a valence band under the gate of an example of a transistor according to the invention; the figure 5 is a cross-sectional view of a variant of a transistor according to the invention; the figure 6 is a cross-sectional view of a cascode structure including a transistor according to the invention; the figure 7 is an equivalent electrical diagram of the cascode structure of the figure 6 ; THE figures 8 And 9 illustrate the thickness values ​​of certain layers as a function of their dopant concentrations.

[0017] There figure 1is a schematic cross-sectional view of an example of a normally blocked, high-electronic-mobility heterojunction transistor according to an embodiment of the invention. Transistor 1 comprises a substrate 11, a nucleation layer 12 disposed on the substrate 11, a GaN buffer layer 13 disposed on the nucleation layer 12, a P-doped GaN layer 14 disposed on the GaN buffer layer 13, an N-doped GaN layer 15 disposed on the GaN layer 14, and an unintentionally doped GaN layer 16 disposed on the layer 15. Transistor 1 further comprises an AlGaN layer 17 disposed on the layer 16. An electron gas is intrinsically formed by heterojunction at the interface between the layer 17 and the layer 16. For clarity, the electron gas is illustrated as a layer 18 at the interface between the layer 16 and the layer 17.An intermediate layer (not shown) can be interposed between layers 16 and 17, for example, to increase the electron density in the electron gas and improve electron confinement in the GaN. Such an intermediate layer is typically extremely thin (e.g., 1 nm) and can be made of AIN (particularly suitable for the interface between a GaN layer 16 and an AlGaN layer 17).

[0018] According to the invention, layer 14 includes Magnesium forming a P-type dopant, the concentration of activated magnesium in this GaN 14 layer being at least equal to 1 * 10 17< cm -3< and at most equal to 1 * 10 18< cm -3<, this GaN 14 layer having a thickness between 10 and 50 nm.

[0019] With such a configuration according to the invention, a complete depletion of layer 14 can be obtained, and an absence of diffusion of Magnesium to the electron gas layer 18. Such an absence of diffusion of Magnesium to the electron gas layer 18 avoids adverse electrical effects on the latter, in particular for a high value of the diffusion potential of the P / N junction formed at the interface between layers 14 and 15.

[0020] In the example illustrated in the figure 1 Transistor 1 advantageously comprises a GaN layer 19 formed in a manner known per se on layer 17. Layer 19 prevents oxidation of layer 17 to AlGaN in this example. Layer 19 has, for example, a thickness between 1 and 3 nm. Layer 19 is advantageously coated with a passivation layer 20, for example, of silicon oxide or silicon nitride.

[0021] We can also have a Silicon nitride layer 20 on layer 17, replacing layer 19, deposited in-situ in the frame used for the epitaxy steps, in order to have a SiN / AlGaN interface and a SiN layer of very good quality.

[0022] As is known, transistor 1 comprises a source 21, a drain 22, and a control gate 3. The source 21 and the drain 22 are formed on the AlGaN layer 17 and exhibit a linear (ohmic) current-voltage characteristic. The contact resistance between the source 21 and the electron gas layer 18 and the contact resistance between the drain 22 and the electron gas layer 18 are low and typically between 0.5 and 1 Ohm.mm. The source 21, the drain 22, and the control gate 3 are shown schematically only; their dimensions and structures may differ significantly from the illustration. figure 1 .

[0023] A cavity is formed through the AlGaN 17 layer and the GaN 16 layer. The cavity extends into the GaN 15 layer but does not penetrate it. N-doped GaN thus defines the bottom of this cavity. In this example, the cavity also passes through layers 19 and 20.

[0024] The control grid 3 includes a grid insulator layer 32 and a conductive grid material 31 (with a advantageously high work function). The grid insulator 32 electrically isolates the grid conductor 31 from layers 15, 16, and 17, in particular. The grid insulator 32 covers the bottom and side walls of the cavity. The grid insulator 32 is thus in contact with layer 15 at the bottom of the cavity, and with layers 15, 16, and 17 at the side walls of the cavity. The grid insulator 31 can, for example, be made of Al₂O₃.

[0025] The grid material 31 is arranged in the cavity, in a space not occupied by the grid insulator 32. The grid material is separated from the layers 15, 16 and 17 by means of the grid insulator 32. The grid material 31 is in contact with the grid insulator 32. The grid material 31 is for example a metal, including for example TiN, W, or Ni (high work output metals).

[0026] The channel will hereafter be designated as the region of the GaN layer 15 in which conduction is controlled by the gate 3. The access points of transistor 1 include the regions between the control gate 3 and the drain 22, and between the control gate 3 and the source 21, including the electron gas layer 18. The transistor 1 according to the invention aims to ensure gas conduction of electrons to access level and a channel-level accumulating field-effect transistor type operation.

[0027] The superposition of the P-doped GaN layer 14 with the N-doped GaN layer 15 creates a depleted P / N junction, forming a particularly high potential barrier beneath the electron gas layer. Thus, at the access points, the junction confines electrons to layer 16, preventing them from being trapped in lower layers, particularly layer 13, which can contain a large number of traps due to the of a potentially high carbon concentration.

[0028] The P / N junction formed can be completely depleted with appropriate dopant thicknesses and concentrations in layers 14 and 15. Furthermore, such a junction is formed with materials compatible with the unintentionally doped GaN 16 layer intended to form the layer of electron gas. Such a junction can be obtained from a formation by epitaxy of layers 14 and 15.

[0029] The N-doped layer 15 allows for the separation of the access and channel design. Layer 15 absorbs the Vbi potential (detailed later) at the level of the access, and allows the channel to be manufactured independently of the electron gas 18.

[0030] In addition, such a potential barrier prevents the formation of an AlGaN layer under this unintentionally doped GaN layer 16, which helps to limit the mechanical stresses at the interface with this GaN layer 16.

[0031] Furthermore, below gate 3, the depletion of the N-doped GaN in the channel allows for the formation of a normally blocked transistor with a high threshold voltage, easily exceeding 3V. As detailed by the Subsequently, the N-doped GaN in the channel is depleted under the action of the P-doped GaN and the 31. Conductive grid material. To make the channel conductive, it is necessary accumulate enough electrons in the channel below grid 3, via a potential difference between source and grid greater than the Threshold voltage. As detailed later, the threshold voltage Vth of transistor 1 can be adjusted by playing with various technological parameters.

[0032] In the forward state, the electron density and their mobility are greater than those obtained for an inversion channel. Furthermore, by separating the canal and the access points, damage is avoided. the performance of transistor 1 in the on state.

[0033] The substrate 11 can be an insulator or a semiconductor of the intrinsic or doped silicon type, SiC or sapphire (single-crystal Al2O3). The substrate 11 can typically have a thickness on the order of 500 µm to 1 mm.

[0034] The nucleation layer 12 deposited on the substrate 11 serves as an intermediary between this substrate and the GaN buffer layer 13, to promote growth by epitaxy of the buffer layer 13. Such a nucleation layer 12 proves particularly advantageous in cases of significant mesh parameter mismatch and CTE (coefficients thermal expansion or dilation) between layer 13 and substrate 11 could lead to the heterostructure being unable to be fabricated with sufficient quality for component production. For example, nucleation layer 12 is made of AIN. Nucleation layer 12 has a thickness of 100 nm.

[0035] The GaN 13 layer is, for example, enriched with carbon to increase its electrical resistivity. Carbon enrichment can, for instance, be carried out simultaneously with epitaxial growth of layer 13. Layer 13 typically has a thickness of 1 to 15 µm, depending on the target voltage range for the transistor component 1.

[0036] The P-doped GaN layer 14 has a thickness between 10 and 50 nm and a P-dopant concentration of 1 × 10¹⁷ cm⁻³ to 1 × 10¹⁸ cm⁻³. The N-doped GaN layer 15, for example, has a thickness of 80 nm and an N-dopant concentration of 2 × 10¹⁶ to 2 × 10¹⁷ cm⁻³. Layers 14 and 15 have a lower carbon concentration than layer 13. This concentration is, for example, on the order of 10¹⁶ cm⁻³.

[0037] The unintentionally doped GaN layer 16, for example, has a thickness of 50 nm. To promote maximum electron mobility in the electron gas layer 18, the GaN layer 16 has the lowest possible doping level. For example, a layer 16 is considered unintentionally doped if the concentration of N and P dopants is less than 1 * 1016 cm-3. Another criterion for an unintentionally doped layer is that its concentration of N and P dopants is lower than the concentration of N-doped dopants in the layer 15. The AlGaN layer 17, for example, has a thickness of 25 nm.

[0038] In the illustrated example, the barrier layer 17 is formed of AlGaN. According to the invention, any other semiconductor layer can be disposed on the unintentionally doped GaN layer 16, provided it is suitable for generating an electron gas at their interface. Layer 17 can, for example, be another ternary alloy of element III nitride. Layer 17 can also be a binary alloy of element III nitride, for example, AlN.

[0039] In the example, the AlGaN of layer 17 may include a mole fraction of AIN between 15 and 25%, but other proportions can of course be used.

[0040] The doping of layer 14, doped with P, is achieved with Magnesium, a material that can be readily incorporated into layer 14 during eventual formation by epitaxy. Furthermore, Magnesium can be easily activated (i.e., perform its acceptor function). Advantageously, the doping of layer 15, doped with N, is achieved with Silicon, a material that can be readily incorporated into layer 15 during eventual formation by epitaxy.

[0041] There figure 2 is a conduction band diagram of transistor 1 detailed previously as a function of depth, at the access points. For comparison, the figure 3 provides a conduction band diagram of a prior art transistor as a function of access depth. The prior art transistor considered has a 25 nm AlGaN layer formed on an unintentionally doped GaN layer 1.40 µm thick.

[0042] It is observed that the potential barrier for transistor 1 according to the invention is typically at least 1.3 eV and higher, depending on the chosen p and n doping concentrations. Conversely, the potential barrier for the transistor according to the prior art is approximately 0.15 eV. Transistor 1 according to the invention thus makes it possible to obtain a particularly high potential barrier to prevent the injection and consequently the trapping of electrons from the electron gas layer 18 into layer 13, for example. Simulations have determined that the electron density in the respective electron gas layers of these transistors is substantially equivalent, approximately 8.5 × 10¹² cm⁻² for the transistor in the example of the figure 3 compared to approximately 8.2 * 1012 cm-2 for the transistor in the example of the figure 2 . The electron density of the electron gas layer 18 according to the invention therefore remains particularly high.

[0043] The influence of different parameters of layers 14, 15 and 16 on the formation of a potential barrier for the electron gas layer 18 and the GaN layer 16 will be detailed further later.

[0044] To allow for anticipating the influence of different parameters on the performance of transistor 1 according to the invention, the following notations will be used hereafter: Ns: electron density in the electron gas layer (in cm⁻²); µ2DEG: electron mobility in the electron gas layer (in cm² / Vs); ND: donor volume density in the N-doped GaN₁₅ layer (in cm⁻³); NA: acceptor volume density in the P-doped GaN₁₄ layer (in cm⁻³); NA⁻: acceptor volume density in a P-doped GaN layer sufficiently thick to be undepleted (in cm⁻³); ND⁺: donor volume density in an N-doped GaN layer sufficiently thick to be undepleted (in cm⁻³); ni: intrinsic carrier density in a GaN layer at room temperature (in cm⁻³); RT: the ambient temperature taken into account of 298K; T: the substrate temperature in K; Ron: the resistance of transistor 1 in the on state; Nsc: the electron density in the channel of transistor 1 (in cm⁻²); µc: the electron mobility in the channel (in cm² / Vs);Wn: the thickness of the N-doped GaN layer under the control gate; Wnepi: the thickness of the N-doped GaN 15 layer; Wnid: the thickness of the unintentionally doped GaN 16 layer; Wp: the thickness of the P-doped GaN 14 layer; Wt: the thickness of the transition zone between the electron gas layer 18 and the channel-forming portion in the GaN 16 layer; tox: the thickness of the gate insulator; Vbi: the diffusion potential (referred to as the 'built-in' potential) of the P / N junction formed at the interface between layers 14 and 15; Vbbpn: the potential barrier across the depleted P / N junction; Vbbnid: the potential barrier across the unintentionally doped GaN 16 layer; Vbb: the total potential barrier; Lg: the length of the control grid 3; Lgeff: the length of the control grid 3 increased by the source and drain side transition zones (Lgeff = Lg+ 2Wt);Lds: the drain-source distance of transistor 1; ε 0 : the permittivity of a vacuum; ε sc: the permittivity of GaN; ε ox: the permittivity of the oxide or gate insulator used; k: Boltzmann constant = 1.3806488 E -23< J / K q: electronic charge ≈1.6 E -19< C.

[0045] We will model the behavior of the junction between layers 14 and 15 in the absence of a potential difference between the source 21 and the control gate 3. The diffusion potential of the junction between layers 14 and 15 can be defined as follows: V bi T = k ⋅ T q ln N A T − . N D T + n i 2 T

[0046] With phosphorus doping using magnesium, The ionization energy of the Mg acceptor in GaN is approximately 180 meV. Therefore, the ionization is partial. at temperature RT. This must therefore be taken into account by the inequality NA- < NA at temperature RT.

[0047] With ni ≈ 1.9 e⁻¹⁰ cm⁻³ at a temperature of 298 K, Vbi takes values ​​of 3.1 ± 0.1 V for useful values ​​of and NA⁻. Vbi remains relatively insensitive to variations in NA⁻ and ND⁺ due to the logarithm in the relationship. The threshold voltage Vth of transistor 1 (formula detailed later) is therefore relatively insensitive to the dopant concentration in layers 14 and 15.

[0048] To ensure the absence of conduction in the channel when the potential difference Vgs between gate and source is zero, the positive charges developed in the GaN 15 layer are made insufficient to balance the negative charges developed in the GaN 14 layer. This condition can be met in particular by means of a relatively thin GaN 15 layer.

[0049] This condition can for example be expressed by the following inequality, with Wn0, the thickness of N-doped GaN being able to be depleted by the P-doped GaN 14 layer. W n < W n 0 = 2 ε s ⋅ V bi ⋅ N A q ⋅ N D ⋅ N A + N D

[0050] The diagram of the figure 4 The diagram illustrates in solid lines the conduction band of transistor 1, detailed previously, as a function of depth, at the channel level and below gate 3. figure 4 The graph also illustrates, in dotted lines, the valence band as a function of depth under grid 3. figure 4 also illustrated in dashed line electron density depending on the depth under the grid, in the absence of potential difference Vgs. There electron density under the grid 3 is thus extremely reduced (to a maximum of 5.5 e -6< cm -2< ).

[0051] By applying a potential difference Vgs greater than Vth, a conducting channel can be obtained by the appearance of an electron accumulation layer in the 15 layer under the gate insulator 32.

[0052] The threshold voltage Vth can be calculated using the following formula: V th = φ MS ε s ε ox . V bi W n − q . N d . W n 2 ε 0 . ε ox . t ox ≈ φ MS + V bi t ox ε ox W n ε s

[0053] With φ MS the difference in output work between the GaN layer 15 and the gate conductive material 31, with a value of approximately 1eV in this case. This contribution φ MS The threshold voltage can be expressed as depletion. through the gate.

[0054] The second term corresponds to the effect of the diffusion potential Vbi on the P / N junction. The third term corresponds to the positive space charge developed in layer 15 under gate 3.

[0055] It is also understood that the threshold voltage Vth is higher when the value Wn (thickness of layer 15 under grid 3) is small. With Wn << Wn0, the third term becomes almost negligible compared to the second term.

[0056] We also see that in the approximate Vth formula, the weighting coefficient of Vbi is the ratio of the effective thicknesses of the oxide and the n 15 layer.

[0057] In the specific case of Al2O3 chosen as grid insulator 32, with If tox ≥ Wn, we obtain a threshold voltage shift of at least 3.1V. Therefore, Vth ≥ φ MS + 3.1 V Therefore, a Vth value greater than 3V can easily be obtained. The Vth value can be easily adjusted industrially by choosing, for example, appropriate values ​​for Wn and tox.

[0058] The source and drain access zones of the channel are formed by the electron gas layer 18 and exhibit low on-state resistance. The concentration and, especially, the effective mobility of electrons in the channel when Vgs > Vth remain lower than those of electrons in the electron gas layer 18 at the access points. Therefore, to minimize the transistor's on-state resistance Ron, it is desirable to reduce the gate length as much as possible relative to the drain-source distance Lds. For example, in applications where Lds is on the order of 20 µm, a gate length Lg of less than 1 µm is preferable.

[0059] To calculate the on-state resistance of the transistor, we take into account an effective gate length Lgeff, defined approximately as the length Lg of the control gate 3 increased by the transition regions on the source and drain sides, i.e. Lgeff ≈ Lg+ 2Wt.The grid length Lg will be less constrained for high voltage applications (e.g., voltages above 600V).

[0060] To maintain low channel resistance in the on-state, the following relationship should preferably be respected: L g eff ≪ N sc . μ c . L ds N s . μ 2 DEG

[0061] For typical values ​​of Nsc and µc, we can deduce the condition Lgeff < 1µm and therefore Lg < 0.8µm. For example, we could choose an Lg value between 0.25 and 0.5µm. Preferably, we maintain an Lg value of at least 0.25, as tox must be high enough to maintain a Vgs variation range of + / -15V or + / -20V, similar to what is obtained with a gate for a silicon transistor.

[0062] At the access level, the ability to hold the voltage in blocked mode is high, thanks to the high critical electric field of the GaN material.

[0063] The potential barrier formed between the electron gas layer 18 and the buffer layer 13 (preventing the injection and trapping of electrons into thedeep layers of the buffer layer 13) reach a high level and appear thanks to the diffusion potential Vbi, and include: partly a potential barrier at the terminals of the depleted P / N junction formed between layers 14 and 15: V bbpn = q 2 ε s N A . W p 2 + 2 N A . W p . W n − N D . W n 2 partly a potential barrier at the boundaries of the GaN 16 layer: V bbnid = q ε s N A . W p − N D . W n . W nid

[0064] In the space charge zone of the p / n junction, all acceptors and donors are ionized and it is therefore their total concentration that is involved in the calculations (i.e. NA and ND).

[0065] With Wnepi = 80nm and Wp = 50nm and NA = 1e 17< cm -3< , we obtain a potential barrier of about 1.3eV of which 0.9eV across the junction and 0.3eV across layer 16.

[0066] The potential barrier obtained by combining layers 14 and 15 reaches a higher level than that of a possible AlGaN layer which would be placed below the electron gas formation layer 16 (as the example detailed in 'Characteristics of AlGaN / GaN / AlGaN double heterojunction HEMTs with an improved breakdown voltage' cited in the introduction).

[0067] Examples of design rules for such a transistor are then provided.

[0068] When the dopant in layer 14 is Magnesium, the extreme limits for NA are set by: The capabilities of epitaxial technology to incorporate and activate magnesium in layer 14 of GaN (taking into account a solubility limit and passivation by Mg-H type complexes in particular). The maximum usable value for NA is currently a priori 1e19 < cm-3. The value required to have a Vbi > 3V, i.e. NA > 3e16 < cm-3.

[0069] A transistor 1 according to the invention can theoretically be designed within this range of values. In practice, a concentration of 1e17 < cm-3 < NA < 1e18 < cm-3 will advantageously be used. NA > 1e17 < cm-3 allows for a significant buried potential barrier (Back Barrier) (>1.3V) and NA < 1e18 < cm-3 allows for a robust thickness for the p14 layer (Wp>15nm).

[0070] For layer 15, one can select, for example, an ND value between 2e16 < cm-3 (for NA = 1e17 < cm-3) and 2e17 < cm-3 (for NA = 1e18 < cm-3). The maximum value of ND is limited, for example, by the loss of electron mobility in the channel, which would then degrade Ron, particularly if ND > 2e17 < cm-3. The minimum value of ND is determined by the value of NA: the larger NA is, the larger ND must be; otherwise, Wp0 (and therefore Wp) is too small to allow the formation of the p-GaN layer. The Wp0 and Wn0 curves as a function of ND for the extreme values ​​of NA summarize this aspect (as illustrated in Figures 14). figures 8 And 9 ). Once NA is chosen, the dotted area delimits the possibilities for ND. Example 1: If NA = 1 e < 17, we can choose ND between 2 e < 16 and 1 e < 17. We will choose 2 e < 16 if we want to prioritize mobility in the channel. Example 2: If NA = 1 e < 18, we can choose ND = 2 e < 17 to avoid a Wp value that is too small.

[0071] The minimum value of ND is also defined by the ability to achieve low N-type doping in GaN, and by the decrease in the value φ MS (and therefore of the Vth value) if Nd is too low. So, preferably, ND ≥ 2e 16< cm -3< .

[0072] We can then calculate the diffusion potential Vbi according to the relationship detailed previously. We can then calculate a corresponding thickness Wn0 of total depletion in a GaN-n 15 layer of ND doping (for example 375 nm with parameters detailed previously) and a corresponding thickness Wp0 of total depletion in a GaN-p 14 layer (for example 75 nm with parameters detailed previously and the following relationship). W p 0 = 2 ε s . V bi . N D + q . N A . − N A − + N D +

[0073] We can then determine the thicknesses of the channel and the GaN 15 and GaN 14 layers to be made so that they are completely depleted, respecting only the following inequalities: Wn 0 ≥ Wnepi ; Wn 0 > Wn ; And Wp 0 > Wp

[0074] The GaN 14 layer is advantageously completely depleted, to avoid retaining a conductive layer of holes which would prevent the electric field from developing in the thickness of the GaN 13 layer, which would induce a strong degradation of the voltage withstand of the transistor.

[0075] With Vbi = 3V, NA = 1 * 1017 cm-3, and ND = 2 * 1016 cm-3, we obtain a Wp0 value of 75 nm. Advantageously, a Wp value high enough to allow for robust epitaxial growth (e.g., Wp > 15 nm) is used. A decrease in the Wp value lowers the potential barrier level. Conversely, a decrease in the Wp value guarantees the depletion of the GaN14 layer. Advantageously, Wp is between 30 and 50 nm, and preferably equal to 50 nm.

[0076] At the access points, the thickness of the GaN 15 layer is defined as Wnepi. The following design rules aim to completely deplete the GaN 15 layer, both at the access points and in the channel. For simplicity, the thickness of the GaN 15 layer can be considered to correspond to its thickness at the access points.

[0077] Advantageously, Wnepi ≥ 0.2 * Wn0 or Wnepi ≥ 75 nm is used to prevent depletion from impacting the electron gas layer 18. This is because layer 15 must absorb a significant proportion of the diffusion potential Vbi. Furthermore, a sufficiently high Wnepi thickness is used to ensure that the potential barrier generated by the junction is sufficient to prevent the injection of electrons with a sufficiently developed space charge into layer 15. Moreover, to allow for etching of the gate cavity 3 in layer 15 with sufficient margin, the inequality Wnepi > Wn + 20 nm is preferably verified. A Wnepi value of 80 nm, for example, is satisfactory.

[0078] Furthermore, it is desirable to limit the resistance of the transition zones between the electron gas layer 18 and the channel. To avoid increasing the effective gate length, the Wnepi thickness is advantageously minimized.

[0079] Advantageously, Wn is much lower than Wn0 (for example, Wn0 = 4 * Wn), so that the channel in the GaN 15 layer is completely depleted under the electrodes of transistor 1 and so that the threshold voltage Vth detailed previously is not degraded. For example, for a Wn0 value of 373 nm, a Wn value lower than 93 nm can be chosen. Furthermore, if the permittivities of insulator 32 and GaN are close, to obtain a high Vth, it is desirable to respect the relationship 50 nm ≥ tox ≥ Wn. For example, the Wn value can be chosen between 20 and 50 nm. A value of 40 nm is, for example, appropriate. The minimum value of Wn is, for example, defined by manufacturing process constraints. Thus, to etch the 17th layer of AlGaN, the 16th layer of GaN and part of the 15th layer of GaN, an etch of approximately 150nm must be considered to preserve the cavity of the grid 3.In the absence of a stop layer, it is preferable to maintain a channel thickness Wn of at least 20 nm to account for the inaccuracy in the etching depth. The minimum value of Wn is also determined by the maximum value of Vth. Since Vth depends on the tox / Wn ratio, with a maximum Vth value of 6V and a capped tox value, it follows that Wn must, for example, be at least 20 nm.

[0080] The implantation depth Wt of grid 3 in layer 15 is preferably non-zero, advantageously at least 20nm, or even at least 30nm. An implantation depth of 40 nm is, for example, appropriate.

[0081] For a desired value of Vth, having defined the values ​​Wn and φ MS , we can deduce the tox value for the insulating layer 32, from the relationship previously provided for Vth.

[0082] The thickness of layer 16 is advantageously sufficient to prevent any disturbance of the electron gas layer 18 at the electrodes of transistor 1 from the chemical (the deposition of the magnesium-doped layer induces a magnesium memory effect in the layers subsequently deposited by epitaxy) and electrical influence of the dopants in layers 14 and 15. Thus, advantageously, 60 nm ≥ Wnid ≥ 20 nm (for example, obtained with Wnepi = 80 nm and Wnepi + Wnid ≥ 100 nm to limit the influence of magnesium on the electron gas layer 18). To limit the resistivity of the transition regions between the electron gas 18 and the channel, advantageously, the inequality 100 nm > Wnepi - Wn + Wnid is respected. Avantageusement , Wnid = 50 nm .

[0083] Layers 12 to 18 can be formed successively in the same vapor-phase epitaxial deposition (VPD) machine, by changing the epitaxial conditions for each layer. The epitaxial parameters for the formation of each layer are known to those skilled in the art.

[0084] The thickness of the insulation can be limited by the manufacturing process of the insulation. For example, a layer d'AlAl₂O₃⁻ insulators deposited using the ALD (Atomic Layer Deposition) technique are difficult to produce at thicknesses exceeding 50 nm. The minimum tox thickness is dictated by the gate's voltage resistance in both the on and off states. For an Al₂O₃⁻ insulator, a tox thickness of at least 40 nm may be necessary for voltages of at least 600 V and a Vgs variation range of + / -20 V. A tox value of 40 nm is generally suitable for Al₂O₃. Other materials for the gate insulator can be used, for example (but not limited to) SiN, SiO₂, AIN, AlO₂xN, or HfO₂.

[0085] To obtain a maximum Vth value, a metal with a high work function can be used as the conductive material 31, for example Ni. Other metals compatible with CMOS technologies can also be used, including but not limited to W, Ti, P+-doped polysilicon, or TiN. Alternatively, a P+ diamond grid with an ohmic contact on the diamond made from annealed Ti can be considered to obtain a value φ MS particularly high.

[0086] There figure 5 Figure 1 is a schematic cross-sectional view of a transistor variant designed to increase its voltage rating. This variant is particularly suitable when the gate length is reduced, for example less than 0.5 µm. This variant includes a control gate 3 comprising a field electrode or FPG (for Field Plate Gate).

[0087] The gate 3 of transistor 1 here has a lateral overhang 33 above layer 17 (and in this case above layers 19 and 20). This lateral overhang extends by approximately one length fpg from the cavity of gate 3. Thus, the gate conductive material 31 and the gate insulator 32 extend laterally by one length fpg from the cavity of gate 3. The geometry of the field electrode is advantageously optimized (length, height) in a manner known to those skilled in the art in order to reduce the electric field peak at the base of the gate.

[0088] There figure 6 is a schematic cross-sectional view of a cascode 4 structure including a normally blocked transistor according to the invention. figure 7This is an equivalent electrical circuit of this cascode 4 structure. Such a structure is also particularly suitable for a normally blocked transistor with a reduced gate length in the cavity through the electron gas layer, for example, less than 0.2 µm. This cascode 4 structure allows for increased voltage tolerance despite the use of a short-gate normally blocked transistor.

[0089] The cascode 4 structure includes high-electronic-mobility heterojunction transistors 41 and 42 connected in series. Transistor 41 is normally off, while transistor 42 is normally on. The control gate 415 of transistor 41 is driven in a manner known per se by a control circuit 7, via a connection not shown to the figure 6The source 51 of transistor 41 is connected to the control gate 425 of transistor 42. The drain 52 of transistor 42 constitutes an output electrode of the cascode structure 4.

[0090] Layer 20 is covered with an insulating layer 23. This layer 23 is, for example, made of silicon oxide and can, for example, have a thickness of approximately 400 nm.

[0091] The control grid 415 is formed in particular in a cavity passing through layers 16 and 17, and extending into layer 15. The cavity is covered with an insulating layer 412 and filled with a grid conductive material 411. The grid 415 also passes through the insulating layer 23.

[0092] The gate 415 of transistor 41 here has a lateral overhang 413 above layer 17 (and in this case above layers 19 and 20). The control gate 415 thus includes a field plate gate (FPG). This lateral overhang 413 extends approximately one length fpg from the cavity of the gate 415. Thus, the gate conductive material 411 and the gate insulator 412 extend laterally by one length fpg from the cavity of the gate 415. The geometry of the field plate is advantageously optimized (length, height) in a manner known to those skilled in the art in order to reduce the electric field peak at the gate foot. As in the example illustrated in the figure 5 , the grid conductive material 411 and the grid insulator 412 extend laterally relative to the grid cavity 415.

[0093] The grid 415 further includes a lateral overhang 414 above the layer 23. The conductive material 411 and the insulator 412 extend laterally relative to the overhang 413.

[0094] The control grid 425 is formed in a cavity extending through layer 23 and down to layer 20. The cavity is covered with an insulating layer 422 and filled with a conductive grid material 421. The combination of the grid insulator 422 and layer 20 has a bottom in contact with layer 19. The grid 425 has a lateral overhang 424 above layer 23. The conductive material 421 and the insulator 422 extend laterally beyond the cavity of the grid 425. The grids 415 and 425 are covered with an insulating layer 24. This insulating layer 24 has, for example, a thickness of 200 nm and can, for example, be made of silicon dioxide. Interconnecting metal 25 connects the control grid 425 to the source 51 here.

[0095] The 415 and 425 grids are produced without an additional step in the manufacturing process of transistor 1, which is advantageous for its manufacturing cost.

[0096] The drain of transistor 41 and the source of transistor 42 are advantageously combined, their connection being made in the electron gas layer 18. The resulting cascode 4 structure is thus particularly compact and exhibits a relatively low on-state resistance. The drain of transistor 41 and the source of transistor 42 form a node floating.

Claims

1. High-electron-mobility field-effect transistor (1) of normally-off type, characterized in that it comprises: - a first layer of GaN (14) with P-type doping, including magnesium forming a P-type dopant, the concentration of P-type dopants in the first layer of GaN (14) being at least equal to 1*1017 cm-3 and at most equal to 1*1018 cm-3, the concentration of activated magnesium in the first layer of GaN (14) is at least equal to 1*1017 cm-3 and at most equal to 1*1018 cm-3, said first layer of GaN (14) having a thickness of between 10 and 50 nm; - a second layer of GaN (15) with N-type doping formed on the first layer of GaN so as to form a completely depleted p / n junction, the second layer of GaN (15) having a thickness Wnepi<Wn0, with: W n 0 = 2 ε s . V bi . N A q . N D . N A + N D with ND: the volume density of donors in the second layer of GaN; NA: the volume density of acceptors in the first layer of GaN; Vbi: the diffusion potential of the P / N junction formed at the interface between the first and second layers of GaN; εs: the permittivity of the GaN; - a third layer of GaN (16) that is not intentionally doped and is formed on the second layer of GaN; - a semiconductor layer (17) formed above the third layer of GaN that is not intentionally doped, in order to form an electron gas layer (18) at the interface between this semiconductor layer (17) and the third layer of GaN (16); - a cavity formed through said third layer of GaN and through the semiconductor layer (17), and extending to the second layer of GaN (15) without reaching the bottom of this second layer of GaN; - a gate (3) including a conductive gate material (31) and a gate insulation layer (32) arranged in said cavity, said gate insulation layer electrically insulating said conductive gate material (31) relative to said second and third layers of GaN and relative to the semiconductor layer (17).

2. High-electron-mobility field-effect transistor (1) according to Claim 1, in which said first layer of GaN (14) is formed on a fourth layer of GaN (13) having a carbon concentration greater than that of the first and second layers (14, 15) of GaN.

3. Heterojunction transistor according to any one of the preceding claims, in which the second layer of GaN (15) includes silicon forming an N-type dopant.

4. Heterojunction transistor according to Claim 3, in which the silicon concentration in the second layer of GaN (15) is at least equal to 2*1016 cm-3 and / or at most equal to 2*1017 cm-3.

5. Heterojunction transistor according to any one of the preceding claims, in which said second layer of GaN (15) has a thickness of between 50 and 100 nm.

6. Heterojunction transistor according to any one of the preceding claims, in which the concentration of N-type dopants in the second layer of GaN (15) is less than the concentration of P-type dopants in the first layer of GaN (14).

7. Heterojunction transistor according to any one of the preceding claims, in which said third layer (16) comprises a concentration of dopants at least two times smaller than the concentration of dopants of the second layer of GaN (15).

8. Heterojunction transistor according to any one of the preceding claims, in which said third layer (16) has a thickness of between 20 and 60 nm.

9. Heterojunction transistor according to any one of the preceding claims, in which said gate insulation layer (32) has a thickness at least equal to 20 nm.

10. Heterojunction transistor according to any one of the preceding claims, in which said cavity extends into the second layer of GaN (15) to a depth of at least 20 nm.

11. Heterojunction transistor according to Claim 10, in which the thickness of a channel formed in the second layer of GaN (15) between said cavity and the first layer of GaN (14) is at least equal to 20 nm.

12. Heterojunction transistor (1) according to any one of the preceding claims, in which said semiconductor layer (17) includes an alloy of III-N type.

13. Heterojunction transistor according to any one of the preceding claims, in which said gate (3) has a length of at most 0.8 µm.

14. Heterojunction transistor according to Claim 13, in which said gate (3) exhibits an overlap (33) relative to said cavity, the overlap extending directly above said semiconductor layer (17).